LTC3789IUFD#PBF_技术文档

LTC3789

High Efficiency, Synchronous,

4-Switch Buck-Boost Controller

FeaTures

DescripTion

The LTC^®3789 is a high performance buck-boost switch-

ing regulator controller that operates from input volt-

ages above, below or equal to the output voltage. The

constant-frequency, current mode architecture allows

a phase-lockable frequency of up to 600kHz, while an

output current feedback loop provides support for battery

charging.Withawide4Vto38V(40Vmaximum)inputand

outputrangeandseamless, lownoisetransitionsbetween

operating regions, the LTC3789 is ideal for automotive,

telecom and battery-powered systems.

n

Single Inductor Architecture Allows V Above,

IN

OUT

Below or Equal to the Regulated V

n

Programmable Input or Output Current

n

Wide V Range: 4V to 38V

IN

n

1% Output Voltage Accuracy: 0.8V < V

< 38V

OUT

n

Synchronous Rectification: Up to 98% Efficiency

Current Mode Control

Phase-Lockable Fixed Frequency: 200kHz to 600kHz

No Reverse Current During Start-Up

Power Good Output Voltage Monitor

Internal 5.5V LDO

Theoperatingmodeofthecontrollerisdeterminedthrough

the MODE/PLLIN pin. The MODE/PLLIN pin can select

between pulse-skipping mode and forced continuous

mode operation and allows the IC to besynchronized to an

external clock. Pulse-skipping mode offers high efficiency

and low ripple at light loads, while forced continuous

mode operates at a constant frequency for noise-sensitive

applications.

Quad N-Channel MOSFET Synchronous Drive

V

Disconnected from V During Shutdown

OUT

IN

True Soft-Start and V

Short Protection, Even in

OUT

Boost Mode

n

Available in 28-Lead QFN (4mm × 5mm) and

28-Lead SSOP Packages

applicaTions

A PGOOD pin indicates when the output is within 10% of

itsdesignedsetpoint.TheLTC3789isavailableinlowpro-

file 28-pin 4mm × 5mm QFN and narrow SSOP packages.

L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule and Burst Mode are registered

trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks

are the property of their respective owners. Protected by U.S. Patents, including 5408150,

5481178, 5929620, 6580258, 7365525, 7394231.

n

Automotive Systems

n

Distributed DC Power Systems

n

High Power Battery-Operated Devices

Industrial Control

n

Typical applicaTion

+

1µF

CER

4.7µF

100Ω

Efficiency and Power Loss

–

+

I

INTV

I

LIM

CC OSENSE

100Ω

2.2µF

PGOOD

V

I

V

IN

OSENSE

EXTV

0.010Ω

V

12V

5A

100

95

90

85

80

75

70

12

10

8

OUT

4V TO

38V

CC

V

OUTSNS

IN

INSNS

10µF

16V

CER

+

22µF

50V

CER

330µF

16V

D

C

A

B

TG1

TG2

LTC3789

0.1µF

BOOST1

SW1

BOOST2

SW2

6

BG1

I

BG2

MODE/PLLIN

RUN

TH

2200pF

8k

SS

ON/OFF

121k

4

105k, 1%

V

FB

FREQ

0.01µF

1000pF

7.5k

1%

2

SGND

V

LOAD

= 12V

= 5A

OUT

+

–

I

SENSE SENSE PGND

0

5

10 15 20 25 30 35 40

(V)

V

IN

0.010Ω

3789 TA01b

4.7µH

3789 TA01

3789fc

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LTC3789

absoluTe MaxiMuM raTings ^{(Note 1)}

Input Supply Voltage (V )......................... 40V to –0.3V

V

, V

........................................ 40V to –0.3V

IN

INSNS OUTSNS

Topside Driver Voltages

TG1, TG2, BG1, BG2 Voltages ...........................(Note 6)

I , FREQ, I Voltages .......................INTV to –0.3V

(BOOST1, BOOST2)................................... 46V to –0.3V

Switch Voltage (SW1, SW2).......................... 40V to –5V

TH

LIM

CC

V

Voltage ............................................... 2.7V to –0.3V

FB

+

–

Current Sense Voltages (I

, I

).. 40V to –0.3V

RUN, PGOOD Voltage .................................. 6V to –0.3V

Operating Junction Temperature Range

OSENSE OSENSE

BOOST1, BOOST2 – SW1, SW2................... 6V to –0.3V

TG1, TG2 – SW1, SW2................................. 6V to –0.3V

(Notes 2, 3)............................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 125°C

INTV Peak Output Current................................100mA

Lead Temperature (Soldering, 10 sec.)

EXTV Voltage ......................................... 14V to –0.3V

CC

INTV Voltage ............................................ 6V to –0.3V

CC

+

–

SENSE , SENSE Voltages ....................INTV to –0.3V

MODE/PLLIN, SS Voltages ...................INTV to –0.3V

CC

GN Package......................................................300°C

CC

pin conFiguraTion

TOP VIEW

1

2

PGOOD

SW1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

V

FB

SS

+

3

TG1

SENSE

28 27 26 25 24 23

–

SENSE

I

1

2

3

4

5

6

7

8

22

21

20

19

18

17

16

15

BOOST1

PGND

BG1

4

BOOST1

PGND

BG1

SENSE

5

TH

I

TH

SGND

MODE/PLLIN

FREQ

6

SGND

MODE/PLLIN

FREQ

29

SGND

V

IN

7

V

IN

INTV

CC

8

INTV

CC

RUN

EXTV

BG2

CC

9

EXTV

CC

RUN

V

INSNS

10

11

12

13

14

BG2

V

INSNS

V

BOOST2

OUTSNS

BOOST2

TG2

V

OUTSNS

9

10 11 12 13 14

UFD PACKAGE

I

LIM

+

SW2

I

OSENSE

–

TRIM

28-LEAD (4mm × 5mm) PLASTIC QFN

GN PACKAGE

28-LEAD NARROW PLASTIC SSOP

T

JMAX

= 125°C, θ = 34°C/W

JA

EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB

T

JMAX

= 125°C, θ = 80°C/W

JA

orDer inForMaTion

LEAD FREE FINISH

LTC3789EGN#PBF

LTC3789IGN#PBF

LTC3789EUFD#PBF

LTC3789IUFD#PBF

TAPE AND REEL

PART MARKING*

LTC3789

3789

PACKAGE DESCRIPTION

28-Lead Narrow Plastic SSOP

TEMPERATURE RANGE

–40°C to 125°C

LTC3789EGN#TRPBF

LTC3789IGN#TRPBF

LTC3789EUFD#TRPBF

LTC3789IUFD#TRPBF

28-Lead Narrow Plastic SSOP

–40°C to 125°C

28-Lead (4mm × 5mm) Plastic QFN

3789

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3789fc

2

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LTC3789

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 15V, V_RUN= 5V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

4

TYP

MAX

38

UNITS

V

Input Supply Voltage

Output Voltage

V

IN

0.8

38

OUT

FB

l

Regulated Feedback Voltage

I

TH

I

TH

Voltage = 1.2V (Note 4), T = –40°C to 85°C

0.792 0.800 0.808

0.788 0.800 0.812

V

A

= 1.2V, T = 125°C, T = –40°C to 125°C

A

I

Feedback Current

(Note 4)

= 4V to 38V (Note 4)

–15

–50

nA

FB

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

IN

0.002

0.02

%/V

REFLNREG

(Note 4)

Measured in Servo Loop, ∆I Voltage = 1.4V to 2V

Measured in Servo Loop, ∆I Voltage = 2V to 2.5V

LOADREG

l

0.01

–0.01

0.1

–0.1

%

TH

g

Transconductance Amplifier g

I = 1.2V, Sink/Source 5µA (Note 4)

TH

1.5

mmho

m

I

Q

Input DC Supply Current

Normal Mode

Shutdown

(Note 5)

= 0V

3

40

mA

µA

V

60

RUN

UVLO

Undervoltage Lockout

Undervoltage Hysteresis

SENSE Pins Current

INTV Ramping Down

3.4

0.4

0.2

3.6

V

CC

UVLO Hyst

+

–

+

I

V

= V = 0V

SENSE

1

14

4

µA

SENSE

+

–

+

I

Pins Current

= V

= 10V

10

µA

IOSENSE

OSENSE

IOSENSE

I

Soft-Start Charge Current

RUN Pin On-Threshold

RUN Pin On-Hysteresis

RUN Pin Source Current

RUN Pin Hysteresis Current

V = 0V

SS

2

3

1.22

150

1.2

5

µA

V

SS

V

V Rising

RUN

RUN(ON)

RUN(HYS)

RUN

mV

µA

I

RUN(HYS)

V

Maximum Current Sense Threshold

SENSE(MAX)

l

Buck Region, (I Valley)

V

= 0.7V

73

123

90

140

107

157

mV

L

FB

Boost Region, (I Peak)

L

V

Maximum Input/Output Average

Current Sense Threshold

I

= 0V

48

90

130

50

100

145

52.5

106

160

mV

SENSE(IAVG)

LIM

Floating

= INTV

CC

R

Driver Pull-Up On-Resistance

2.6

1.5

Ω

DSPFET(ON)

DSNFET(ON)

Driver Pull-Down On-Resistance

TG t

Top Gate Rise Time

Top Gate Fall Time

25

ns

r

f

BG t

Bottom Gate Rise Time

Bottom Gate Fall Time

25

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On

Delay Synchronous Switch-On

Delay Time

C

= 3300pF Each Driver (Note 6)

60

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On

Delay Top Switch-On Delay Time

60

ns

LOAD

DF

Maximum Duty Factor

% Switch C On

90

9

%

MAX,BOOST

D

Minimum Duty Factor for Main

Switch in Boost Operation

ON(MIN,BOOST)

D

Minimum Duty Factor for

Synchronous Switch in Buck

Operation

% Switch B On

9

%

ON(MIN,BUCK)

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LTC3789

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 15V, V_RUN= 5V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

5.2

4.7

TYP

MAX

UNITS

INTV Linear Regulator

CC

V

Internal V Voltage

6.5V < V < 40V, V = 0V

EXTVCC

5.5

0.2

5.5

0.2

4.8

0.25

5.8

1.0

5.8

1.0

V

%

V

INTVCCVIN

LDOVIN

CC

IN

INTV Load Regulation

I

= 0mA to 20mA, V

= 0V

CC

EXTVCC

Internal V Voltage

6.5V < V

< 14V

EXTVCC

INTVCCEXT

LDOEXT

CC

INTV Load Regulation

I

= 0mA to 20mA, V

= 12V

%

V

CC

EXTVCC

EXTV Switchover Voltage

= 0mA to 20mA, EXTV Ramping Positive

CC

EXTVCC

CC

EXTV Hysteresis

V

LDOHYS

CC

Oscillator and Phase-Locked Loop

f

Nominal Frequency

V

= 1.2V

= 0V

350

175

570

200

400

200

640

440

225

710

600

kHz

kΩ

NOM

LOW

HIGH

SYNC

FREQ

Low Fixed Frequency

High Fixed Frequency

= 2.4V

l

Synchronizable Frequency

MODE/PLLIN Input Resistance

Frequency Setting Current

MODE/PLLIN = External Clock

R

220

10

MODE/PLLIN

FREQ

I

8

12

µA

PGOOD Output

V

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 5V

0.1

0.3

1

V

PGL

PGOOD

I

V

µA

PGOOD

V

with Respect to Set Output Voltage

Ramping Negative

Ramping Positive

PG

FB

V

–10

10

%

FB

V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

D

LTC3789GN: T = T + (P • 80°C/W)

J

A

D

LTC3789UFD: T = T + (P • 34°C/W)

J

A

D

Note 2: The LTC3789 is tested under pulse load conditions such that

Note 4: The LTC3789 is tested in a feedback loop that servos V to a

ITH

T

J

≈ T . The LTC3789E is guaranteed to meet performance specifications

A

specified voltage and measures the resultant V

.

FB

from 0°C to 85°C operating junction temperature. Specifications over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC3789I is guaranteed to meet performance specifications over the

full –40°C to 125°C operating junction temperature range.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See the Applications Information

section.

Note 6: Do not apply a voltage or current to these pins. They must be

connected to capacitive loads only, otherwise permanent damage may

occur.

3789fc

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For more information www.linear.com/LTC3789

LTC3789

Typical perForMance characTerisTics ^T_A^{= 25°C unless otherwise noted.}

Efficiency vs Output Current

(Boost Region)

Efficiency vs Output Current

(Buck Region)

Efficiency vs Output Current

(Buck-Boost Region)

100

90

100

90

100

90

V

= 6V

V

= 12V

V

= 18V

IN

OUT

IN

OUT

IN

OUT

= 12V

80

70

60

50

60

50

60

50

40

30

20

10

0

40

30

20

10

0

40

30

20

10

0

DCM

FCM

DCM

FCM

DCM

FCM

CIRCUIT OF FIGURE 13

100

CIRCUIT OF FIGURE 13

100

CIRCUIT OF FIGURE 13

100

10

1000

10000

10

1000

10000

10

1000

10000

LOAD CURRENT (mA)

3789 G01

3789 G03

3789 G02

Internal 5.5V LDO Line

Regulation

Efficiency vs V_IN

EXTV_CCLDO Line Regulation

99

98

97

96

95

94

93

92

91

6.0

5.5

5.0

4.5

4.0

3.5

6

5

4

3

2

1

0

CIRCUIT OF FIGURE 13

FREQUENCY

200kHz

300kHz

400kHz

520kHz

0

10

20

(V)

30

40

4

14

19

24

29

34

4

5

6

7

8

9

10 11 12 13 14

9

V

IN

INPUT VOLTAGE (V)

EXTV (V)

CC

3789 G05

3789 G06

INTV_CCand EXTV_CCSwitch

Voltage vs Temperature

RUN Pin Threshold

vs Temperature

Supply Current vs Input Voltage

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

6

5

4

3

2

1

0

RISING

FALLING

4

14

19

24

29

34

9

–60 –40

0

20 40 60 80 100

–20

0

20 40 60 80 100

–60 –40

INPUT VOLTAGE (V)

TEMPERATURE (°C)

3789 G08

TEMPERATURE (°C)

3789 G09

3789 G07

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LTC3789

Typical perForMance characTerisTics ^T_A^{= 25°C unless otherwise noted.}

Forced Continuous Mode

SW1

10V/DIV

SW1

10V/DIV

SW1

10V/DIV

SW2

10V/DIV

SW2

10V/DIV

SW2

10V/DIV

I

L

1A/DIV

I

L

1A/DIV

3789 G12

3789 G10

3789 G11

4µs/DIV

V

= 18V

OUT

V

= 6V

OUT

V

= 12V

OUT

IN

= 12V

Pulse-Skipping Mode

SW1

10V/DIV

SW1

10V/DIV

SW1

10V/DIV

SW2

10V/DIV

SW2

10V/DIV

SW2

10V/DIV

I

L

1A/DIV

L

I

L

1A/DIV

3789 G13

3789 G14

3789 G15

4µs/DIV

2µs/DIV

V

= 6V

OUT

V

= 12V

OUT

IN

V

= 18V

OUT

IN

= 12V

Oscillator Frequency

vs Temperature

Undervoltage Threshold at INTV_CC

vs Temperature

Undervoltage Threshold at V_IN

vs Temperature

700

600

500

400

300

200

100

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= 2.4V

FREQ

RISING

FALLING

V

= 1.2V

FREQ

V

= 0V

FREQ

–50

0

50

TEMPERATURE (°C)

100

150

–60 –40

0

20 40 60 80 100

–60 –40 –20

0

20 40 60 80 100

–20

TEMPERATURE (°C)

3789 G18

3789 G17

3789 G16

3789fc

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For more information www.linear.com/LTC3789

LTC3789

Typical perForMance characTerisTics ^T_A^{= 25°C unless otherwise noted.}

Maximum Current Sense

Threshold vs Duty Factor (Boost)

Maximum Current Sense

Threshold vs Duty Factor (Buck)

Maximum Current Limit

vs Temperature

150

140

130

120

110

100

90

150

140

130

120

110

100

90

150

140

130

120

110

100

90

BOOST

BUCK

80

70

60

50

60

50

–10 10 30 50 70

TEMPERATURE (°C)

130

90 110

–50 –30

0

20

60

40

DUTY FACTOR (%)

80

100

0

20

60

40

DUTY FACTOR (%)

80

100

3789 G19

3789 G20

3789 G21

Peak Current Threshold

vs V_ITH(Boost)

Valley Current Threshold

vs V_ITH(Buck)

Current Foldback Limit

200

150

100

50

200

150

100

50

160

140

120

100

80

BOOST

BUCK

0

–50

–100

–150

–200

60

0

40

–50

–100

20

0

0.5

1.5

(V)

2

2.5

3

0

0.5

1.5

(V)

2

2.5

1

0.2 0.3 0.4 0.5 0.6 0.9

0.7 0.8

0

0.1

V

ITH

V

FB

(V)

3789 G23

3789 G22

3789 G24

3789fc

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For more information www.linear.com/LTC3789

LTC3789

Typical perForMance characTerisTics ^T_A^{= 25°C unless otherwise noted.}

Load Step

V

OUT

200mV/DIV

I

L

I

L

I

L

2A/DIV

3789 G25

3789 G26

3789 G27

400µs/DIV

V

= 6V

OUT

V

= 12V

IN

V

= 18V

OUT

IN

= 12V

OUT

= 12V

LOAD STEP = 200mA TO 2A

LOAD STEP = 300mA TO 3A

Line Transient

V

IN

V

ITH

30V TO 5V

V

ITH

V

IN

5V TO 30V

V

(AC)

V

(AC)

OUT

500mV/DIV

I

L

I

L

2A/DIV

3789 G29

3789 G28

1ms/DIV

3789fc

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LTC3789

pin FuncTions ^(SSOP/QFN)

V (Pin1/Pin26):ErrorAmplifierFeedbackPin.Receives

FREQ(Pin8/Pin5):FrequencySetPin.Thereisaprecision

10µA current flowing out of this pin. A resistor to ground

sets a voltage which, in turn, programs the frequency.

Alternatively, this pin can be driven with a DC voltage to

vary the frequency of the internal oscillator.

FB

the feedback voltage for the controller from an external

resistive divider across the output.

SS(Pin2/Pin27):ExternalSoft-StartInput.TheLTC3789

regulatestheV voltagetothesmallerof0.8Vorthevolt-

FB

age on the SS pin. A internal 3µA pull-up current source

is connected to this pin. A capacitor to ground at this

pin sets the ramp time to final regulated output voltage.

RUN (Pin 9/Pin 6): Run Control Input. Forcing the pin

below 0.5V shuts down the controller, reducing quies-

cent current. There are 1.2µA pull-up currents for this

pin. Once the RUN pin rises above 1.22V, the IC is turned

on, and an additional 5µA pull-up current is added to

the pin.

+

SENSE (Pin 3/Pin 28): The (+) Input to the Current Sense

Comparator. The I pin voltage and controlled offsets

TH

–

+

between the SENSE and SENSE pins, in conjunction

with R

, set the current trip threshold.

V

(Pin 10/Pin 7): V Sense Input to the Buck-Boost

SENSE

–

INSNS IN

Transition Comparator. Connect this pin to the drain of the

top N-channel MOSFET on the input side.

SENSE (Pin 4/Pin 1): The (–) Input to the Current Sense

Comparator.

V

(Pin 11/Pin 8): V

Sense Input to the Buck-

OUT

OUTSNS

I

(Pin 5/Pin 2): Error Amplifier Output and Switch-

TH

BoostTransitionComparator.ConnectthispintotheV

.

OUT

ing Regulator Compensation Point. The channel’s

current comparator trip point increases with this control

voltage.

I

(Pin 12/Pin 9): Input/Output Average Current

LIM

Sense Range Input. This pin tied to SGND, INTV or

CC

left floating, sets the maximum average current sense

threshold.

SGND (Pin 6/Pins 3, Exposed Pad Pin 29): Small

Signal Ground. Must be routed separately from high

current grounds to the common (–) terminals of the

+

I

(Pin13/Pin10):The(+)InputtotheInput/Output

OSENSE

C

capacitors. In the QFN package, the exposed pad

Average Current Sense Amplifier.

IN

is SGND. It must be soldered to PCB ground for rated

thermal performance.

–

I

(Pin14/Pin11):The(–)InputtotheInput/Output

OSENSE

Average Current Sense Amplifier.

MODE/PLLIN (Pin 7/Pin 4): Mode Selection or External

Synchronization Input to Phase Detector. This is a dual-

purpose pin. When external frequency synchronization

is not used, this pin selects the operating mode. The

TRIM (Pin 15/Pin 12): Tie this pin to GND for normal

operation. Do not allow this pin to float.

EXTV (Pin 20/Pin 17): External Power Input to an

CC

Internal LDO Connected to INTV . This LDO supplies

pin can be tied to SGND or INTV . SGND or below

CC

INTV power, bypassing the internal LDO powered from

0.8V enables forced continuous mode. INTV enables

CC

V

whenever EXTV is higher than 4.8V. See EXTV

pulse-skipping mode. For external sync, apply a clock

signal to this pin. The internal PLL will synchronize the

internal oscillator to the clock, and forced continuous

mode will be enabled. The PLL composition network is

integrated into the IC.

IN

CC CC

Connection in the Applications Information section. Do

not exceed 14V on this pin.

3789fc

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For more information www.linear.com/LTC3789

LTC3789

pin FuncTions ^(SSOP/QFN)

INTV (Pin 21/Pin 18): Output of the Internal Linear Low

to (V + INTV ). Voltage swing at the BOOST2 pin is

IN CC

CC

Dropout Regulator. The driver and control circuits are

powered from this voltage source. Must be bypassed to

powergroundwithaminimumof4.7µFtantalum,ceramic,

or other low ESR capacitor.

from INTV to (V

+ INTV ).

CC

OUT CC

TG1, TG2 (Pins 26, 17/Pins 23, 14): High Current

Gate Drives for Top N-Channel MOSFETs. These are the

outputs of floating drivers with a voltage swing equal

V (Pin 22/Pin 19): Main Supply Pin. A bypass capacitor

to INTV – 0.5V superimposed on the switch node

IN

CC

should be tied between this pin and the power ground pin.

voltage SW.

BG1, BG2 (Pins 23, 19/Pins 20, 16): High Current

Gate Drives for Bottom (Synchronous) N-Channel

MOSFETs. Voltage swing at these pins is from ground to

SW1, SW2 (Pins 27, 16/Pins 24, 13): Switch Node

Connections to Inductors. Voltage swing at the SW1

pin is from a Schottky diode (external) voltage drop

INTV .

CC

below ground to V . Voltage swing at the SW2 pin is

IN

from a Schottky diode voltage drop below ground to

V .

OUT

PGND (Pin 24/Pin 21): Driver Power Ground. Connects

to C

and R

(–) terminal(s) of C .

OUT

SENSE

IN

PGOOD (Pin 28/Pin 25): Open-Drain Logic Output.

BOOST1,BOOST2(Pins25,18/Pins22,15):Bootstrapped

Supplies to the Top Side Floating Drivers. Capacitors

are connected between the BOOST and SW pins and

PGOOD is pulled to ground when the voltage on the V

FB

pin is not within 10% of its regulation window, after the

internal 20µs power-bad mask timer expires.

Schottky diodes are tied between the BOOST and INTV

pins. Voltage swing at the BOOST1 pin is from INTV

CC

3789fc

10

For more information www.linear.com/LTC3789

LTC3789

block DiagraM

INTV

V

IN

CC

BOOST1

TG1

CHARGE

BOOST1

PUMP

FCB

I

DREV

V

SW1

+

–

IN

BUCK

LOGIC

INTV

CC

CHARGE

BOOST2

PUMP

SW1

BG1

PGND

BG2

I

REV

+

–

R

SENSE

FCB

INTV

CC

BOOST

LOGIC

SW2

TG2

V

FLD

I

CMP

+

–

BOOST2

OV

INTV

+

CC

I

OSENSE

+

R

1.2µA

SHDN

–

SENSE2

I

OSENSE

RUN

V

–

OUT

SLOPE

I

+

LIM

I

OS

EA

–

V

FB

–

+

0.80V

SS

MODE/

PLLIN

3µA

F

IN

PHASE DET

220k

10µA

I

TH

FREQ

+

SENSE

OSCILLATOR

–

SENSE

EXTV

CC

V

IN

V

IN

–

+

0.86V

+

4.8V

OV

PGOOD

EXTV

INTV

CC

5.5V

LDO

REG

5.5V

LDO

REG

–

V

FB

–

+

5.5V

+

CC

INTERNAL

SUPPLY

0.74V

SGND

3789 BD

3789fc

11

For more information www.linear.com/LTC3789

LTC3789

operaTion

MAIN CONTROL LOOP

charges to the external bootstrap capacitor, an internal

UVLO comparator, which constantly monitors the drop

across the capacitor, will sense the (BOOST – SW) voltage

when it is below 3.6V. It will turn off the top MOSFET for

about one-twelfth of the clock period every four cycles to

The LTC3789 is a current mode controller that provides

an output voltage above, equal to or below the input volt-

age.TheLTC proprietarytopologyandcontrolarchitecture

employs a current-sensing resistor. The inductor current

is controlled by the voltage on the I pin, which is the

output of the error amplifier EA. The V pin receives the

voltage feedback signal, which is compared to the internal

reference voltage by the EA. If the input/output current

regulation loop is implemented, the sensed inductor cur-

rent is controlled by either the sensed feedback voltage

or the input/output current.

allow C or C to recharge.

A

B

TH

FB

Shutdown and Start-Up

The controller can be shut down by pulling the RUN

pin low. When the RUN pin voltage is below 0.5V, the

LTC3789 goes into low quiescent current mode. Releas-

ing RUN allows an internal 1.2µA current to pull up the

pin and enable the controller. When RUN is above the

accurate threshold of 1.22V, the internal LDO will power

INTV /EXTV Power

CC

up the INTV . At the same time, a 6µA pull-up current

CC

Power for the top and bottom MOSFET drivers and most

will kick in to provide more RUN pin hysteresis. The RUN

pin may be externally pulled up or driven directly by logic.

Be careful not to exceed the absolute maximum rating of

6V on this pin.

other internal circuitry is derived from the INTV pin.

CC

When the EXTV is left open or tied to a voltage less

CC

than 4.5V, an internal 5.5V low dropout (LDO) regulator

supplies INTV power from V . If EXTV is taken above

CC

IN

CC

4.8V, the 5.5V regulator is turned off, and another LDO

The start-up of the controller’s output voltage V

is

OUT

regulates INTV from EXTV . The EXTV LDO allows

controlled by the voltage on the SS pin. When the voltage

on the SS pin is less than the 0.8V internal reference, the

CC

the INTV power to be derived from a high efficiency

CC

external source such as the LTC3789 regulator output

LTC3789regulatestheV voltagetotheSSvoltageinstead

FB

to reduce IC power dissipation. The absolute maximum

of the 0.8V reference. This allows the SS pin to be used

to program soft-start by connecting an external capacitor

from the SS pin to SGND. An internal 3µA pull-up current

charges this capacitor, creating a voltage ramp on the SS

pin. As the SS voltage rises linearly from 0V to 0.8V (and

voltage on EXTV is 14V.

CC

Internal Charge Pump

Each top MOSFET driver is biased from the floating boot-

strap capacitors C and C , which are normally recharged

beyond),theoutputvoltageV risessmoothlyfromzero

OUT

A

B

to its final value. Alternatively, the SS pin can be used to

byINTV throughanexternaldiodewhenthetopMOSFET

CC

cause the start-up of V

to track that of another supply.

is turned off. When the LTC3789 operates exclusively in

the buck or boost regions, one of the top MOSFETs is

constantly on. An internal charge pump recharges the

bootstrap capacitor to compensate for the small leakage

current through the bootstrap diode so that the MOSFET

can be kept on. However, if a high leakage diode is used

suchthattheinternalchargepumpcannotprovidesufficient

OUT

When RUN is pulled low to disable the controller, or when

INTV is below the undervoltage lockout threshold of

CC

3.4V, the SS pin is pulled low by an internal MOSFET. In

undervoltage lockout, the controller is disabled and the

external MOSFETs are held off.

3789fc

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For more information www.linear.com/LTC3789

LTC3789

operaTion

POWER SWITCH CONTROL

Figure 3 shows typical buck region waveforms. If V

IN

approaches V , the buck-boost region is reached.

OUT

Figure 1 shows a simplified diagram of how the four

power switches are connected to the inductor, V , V

IN OUT

and GND. Figure 2 shows the regions of operation for

the LTC3789 as a function of duty cycle, D. The power

switches are properly controlled so the transfer between

regions is continuous.

CLOCK

SWITCH A

SWITCH B

LOW

HIGH

SWITCH C

SWITCH D

Buck Region (V >> V

)

OUT

IN

Switch D is always on and switch C is always off in this

region. At the start of every cycle, synchronous switch

B is turned on first. Inductor current is sensed when

synchronous switch B is turned on. After the sensed

inductor valley current falls below a reference voltage,

I

L

3780 F03

Figure 3. Buck Region (V_IN>> V_OUT

)

which is proportional to V , synchronous switch B is

ITH

Buck-Boost Region (V

≈

V

OUT

)

IN

turned off and switch A is turned on for the remainder of

the cycle. Switches A and B will alternate, behaving like

a typical synchronous buck regulator. The duty cycle of

switch A increases until the maximum duty cycle of the

When V is close to V , the controller enters buck-

IN

OUT

boostregion. Figure 4showsthetypicalwaveformsinthis

region. At the beginning of a clock cycle, if the controller

starts with B and D on, the controller first operates as a

converter reaches D

, given by:

MAX_BUCK

buck region. When I

trips, switch B is turned off, and

CMP











1

12

switch A is turned on. At 120° clock phase, switch C is

turned on. The LTC3789 starts to operate as a boost until

D_{MAX _BUCK}= 1−

• 100% = 91.67%



I

trips. Then, switch D is turned on for the remainder

CMP

V

OUT

IN

of the clock period. If the controller starts with switches

A and C on, the controller first operates as a boost, until

TG1

BG1

A

D

TG2

BG2

L

SW1

SW2

I

trips and switch D is turned on. At 120°, switch B is

CMP

turned on, making it operate as a buck. Then, I

trips,

CMP

B

C

turning switch B off and switch A on for the remainder of

the clock period.

R

SENSE

3789 F01

Boost Region (V << V

)

IN

OUT

Figure 1. Simplified Diagram of the Output Switches

Switch A is always on and synchronous switch B is always

off in the boost region. In every cycle, switch C is turned

on first. Inductor current is sensed when synchronous

switch C is turned on. After the sensed inductor peak

current exceeds what the reference voltage demands,

90%

MAX

OOST

D

A ON, B OFF

BOOST REGION

BUCK/BOOST REGION

BUCK REGION

PWM C, D SWITCHES

D

MIN

BOOST

which is proportional to V , switch C is turned off and

ITH

FOUR SWITCH PWM

D

MAX

synchronous switch D is turned on for the remainder of

the cycle. Switches C and D will alternate, behaving like a

typical synchronous boost regulator.

BUCK

D ON, C OFF

PWM A, B SWITCHES

D

MIN

3789 F02

BUCK

Figure 2. Operating Region vs Duty Cycle

3789fc

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For more information www.linear.com/LTC3789

LTC3789

operaTion

The duty cycle of switch C decreases until the minimum

duty cycle of the converter reaches D

Light Load Current Operation

, given by:

MIN_BOOST

TheLTC3789canbeenabledtoenterpulse-skippingmode

or forced continuous conduction mode. To select forced

continuous operation, tie the MODE/PLLIN pin to a DC

voltage below 0.8V (e.g., SGND). To select pulse-skipping

 

 

1

12

D_{MIN_BOOST}

=

• 100% = 8.33%

 

Figure 5 shows typical boost region waveforms. If V

mode of operation, tie the MODE/PLLIN pin to INTV .

IN

CC

approaches V , the buck-boost region is reached.

OUT

When the LTC3789 enters pulse-skipping mode, in the

boost region, synchronous switch D is held off whenever

reverse current through switch A is detected. At very

CLOCK

light loads, the current comparator, I

, may remain

CMP

SWITCH A

tripped for several cycles and force switch C to stay off

for the same number of cycles (i.e., skipping pulses). In

the buck region, the inductor current is not allowed to re-

verse. Synchronous switch B is held off whenever reverse

current on the inductor is detected. At very light loads,

SWITCH B

SWITCH C

SWITCH D

I

L

the current comparator, I

, may remain untripped for

CMP

3789 F04a

several cycles, holding switch A off for the same number

of cycles. Synchronous switch B also remains off for the

skipped cycles. In the buck-boost region, the controller

operates alternatively in boost and buck region in one

clock cycle, as in continuous operation. A small amount

of reverse current is allowed, to minimize ripple. For the

samereason,anarrowbandofcontinuousbuckandboost

operation is allowed on the high and low line ends of the

buck-boost region.

(4a) Buck-Boost Region (V_IN≥ V_OUT

)

CLOCK

SWITCH A

SWITCH B

SWITCH C

SWITCH D

Output Overvoltage

I

L

3789 F04b

If the output voltage is higher than the value commanded

by the V resistor divider, the LTC3789 will respond ac-

FB

(4b) Buck-Boost Region (V_IN≤ V_OUT

)

cordingtothemodeandregionofoperation.Incontinuous

conduction mode, the LTC3789 will sink current into the

input. If the input supply is capable of sinking current, the

Figure 4. Buck-Boost Region

LTC3789 will allow up to about 160mV/R

to be sunk

SENSE

into the input. In pulse-skipping mode and in the buck or

boost regions, switching will stop and the output will be

allowedtoremainhigh.Inpulse-skippingmode,andinthe

buck/boost region as well as the narrow band of continu-

ous boost operation that adjoins it, current sunk into the

input through switch A is limited to approximately 40mV/

CLOCK

HIGH

0V

SWITCH A

SWITCH B

SWITCH C

SWITCH D

R

of switch A. If this level is reached, switching will

DS(ON)

stop and the output will rise. In pulse-skipping mode, and

inthenarrowcontinuousbuckregionthatadjoinsthebuck/

I

L

3789 F05

boost region, current sunk into the input through R

SENSE

Figure 5. Boost Region (V_IN<< V_OUT

)

is limited to approximately 40mV/R

.

SENSE

3789fc

14

For more information www.linear.com/LTC3789

LTC3789

operaTion

Constant-Current Regulation

The PLL is capable of locking to any frequency within the

range of 200kHz to 600kHz. The frequency setting resis-

tor should always be present to set the controller’s initial

switching frequency before locking to the external clock.

The LTC3789 provides a constant-current regulation loop

for either input or output current. A sensing resistor close

to the input or output capacitor will sense the input or

outputcurrent.Whenthecurrentexceedstheprogrammed

Power Good (PGOOD) Pins

currentlimit, thevoltage on the I pinwillbe pulled down

TH

ThePGOODpinisconnectedtotheopendrainofaninternal

to maintain the desired maximum input or output current.

The input current limit function prevents overloading the

DC input source, while the output current limit provides

a building block for battery charger or LED driver applica-

tions. It can also serve as an extra current limit protection

for a constant-voltage regulation application. The input/

outputcurrentlimitfunctionhasanoperatingvoltagerange

N-channel MOSFET. When V is not within 10% of the

FB

0.8V reference voltage, the PGOOD pin is pulled low. The

PGOOD pin is also pulled low when RUN is below 1.22V

or when the LTC3789 is in the soft-start phase. There is

an internal 20µs power good or bad mask when V goes

FB

in or out of the 10% window. The PGOOD pin is allowed

to be pulled up by an external resistor to INTV or an

CC

of GND to the absolute maximum V

(V ).

OUT IN

external source of up to 6V.

Frequency Selection and Phase-Locked Loop (FREQ

and MODE/PLLIN Pins)

Short-Circuit Protection, Current Limit and Current

Limit Foldback

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage. The switching

frequency of the LTC3789’s controllers can be selected

using the FREQ pin. If the MODE/PLLIN pin is not being

driven by an external clock source, the FREQ pin can be

usedtoprogramthecontroller’soperatingfrequencyfrom

200kHz to 600kHz.

Themaximumcurrentthresholdofthecontrollerislimited

by a voltage clamp on the I pin. In every boost cycle,

TH

the sensed maximum peak voltage is limited to 140mV.

In every buck cycle, the sensed maximum valley voltage

is limited to 90mV. In the buck-boost region, only peak

sensed voltage is limited by the same threshold as in

the boost region.

The LTC3789 includes current foldback to help limit load

current when the output is shorted to ground. If the out-

put falls below 50% of its nominal output level, then the

maximum sense voltage is progressively lowered from

its maximum value to one-third of the maximum value.

Foldback current limiting is disabled during the soft-start.

Under short-circuit conditions, the LTC3789 will limit the

current by operating as a buck with very low duty cycles,

and by skipping cycles. In this situation, synchronous

switch B will dissipate most of the power (but less than

in normal operation).

Switching frequency is determined by the voltage on the

FREQ pin. Since there is a precision 10µA current flowing

out of the FREQ pin, the user can program the controller’s

switching frequency with a single resistor to SGND. A

curve is provided in the Applications Information section

to show the relationship between the voltage on the FREQ

pin and the switching frequency.

A phase-locked loop (PLL) is integrated on the LTC3789

to synchronize the internal oscillator to an external clock

source driving the MODE/PLLIN pin. The controller oper-

ates in forced continuous mode when it is synchronized.

The PLL filter network is integrated inside the LTC3789.

3789fc

15

For more information www.linear.com/LTC3789

LTC3789

applicaTions inForMaTion

The Typical Application on the first page is a basic

LTC3789 application circuit. External component selec-

tion is driven by the load requirement, and begins with

The maximum current sensing R

region is:

value for the boost

SENSE

R_SENSE(MAX)

=

the selection of R

and the inductor value. Next, the

SENSE

2 • 140mV • V

IN(MIN)

power MOSFETs are selected. Finally, C and C

are

IN

OUT

2 •I_{OUT(MAX,BOOST)}• V_OUT+ ∆I_L,BOOST• V

selected. This circuit can be configured for operation up

to an input voltage of 38V.

IN(MIN)

The maximum current sensing R

region is:

value for the buck

SENSE

R

Selection and Maximum Output Current

SENSE

2 • 90mV

2 •I_{OUT(MAX,BUCK)}– ∆I_L,BUCK

R_SENSE(MAX)

=

R

SENSE

is chosen based on the required output current.

The current comparator threshold sets the peak of the

inductor current in the boost region and the maximum

inductor valley current in the buck region. In the boost

The final R

SENSE(MAX)

to 30% margin is usually recommended.

value should be lower than the calculated

SENSE

R

in both the boost and buck regions. A 20%

region, the maximum average load current at V

is:

IN(MIN)

V





∆I_L

2

140mV

IN(MIN)

Programming Input/Output Current Limit

I_{OUT(MAX,BOOST)}

=

–

•





R

V_OUT





SENSE

As shown in Figures 7 and 8, input/output current sense

resistorR

shouldbeplacedbetweenthebulkcapaci-

and the decoupling capacitor. A lowpass

SENSE2

tor for V /V

where ∆I is peak-to-peak inductor ripple current. In the

buck region, the maximum average load current is:

L

IN OUT

filter formed by R and C is recommended to reduce the

F

∆I_L

2

90mV

R_SENSE

switching noise and stabilize the current loop. The input/

I_{OUT(MAX,BUCK)}

=

+

output current limit is set by the I pin for 50mV, 100mV

LIM

or 140mV with I pulled to the GND, floating, or tied to

LIM

INTV , respectively. If input/output current limit is not

Figure 6 shows how I

• R

varies with in-

SENSE

CC

LOAD(MAX)

put and output voltage.

+

–

desired, the I

to either V

and I

pins should be shorted

OSENSE

or V .

OUT

IN

R

SENSE2

FROM

CONTROLLER

TO

160

150

140

130

120

110

100

SYSTEM

+

R

F

R

C

F

V

OUT

100Ω

2

1

+

–

I

OSENSE

LTC3789

3789 F07

Figure 7. Programming Output Current Limit

R

SENSE2

FROM DC

POWER INPUT

TO DRAIN OF

SWITCH A

90

0.1

1

10

+

R

F

100Ω

C

F

V

/V

(V)

IN OUT

3789 F06

100Ω

Figure 6. Load Current vs V_IN/V_OUT

2

1

+

–

I

OSENSE

LTC3789

3789 F08

Figure 8. Programming Input Current Limit

3789fc

16

For more information www.linear.com/LTC3789

LTC3789

applicaTions inForMaTion

With the typical 100Ω resistors shown here, the value of

Phase-Locked Loop and Frequency Synchronization

capacitor C should be 1µF to 2.2µF. The current loop’s

F

TheLTC3789hasaphase-lockedloop(PLL)comprisedof

aninternalvoltage-controlledoscillator(VCO)andaphase

detector. This allows the turn-on of the top MOSFET of the

controller to be locked to the rising edge of an external

clock signal applied to the MODE/PLLIN pin. The phase

detector is an edge sensitive digital type that provides

zero degrees phase shift between the external and internal

oscillators. This type of phase detector does not exhibit

false locking to harmonics of the external clock.

transfer function should approximate that of the voltage

loop.Crossoverfrequencyshouldbeone-tenththeswitch-

ing frequency, and gain should decrease by 20dB/decade.

Similar current and voltage loop transfer functions will

ensure overall system stability.

When the I

common mode voltage is above ~3.2V,

OSENSE

–

+

theI

pinsources10µA.TheI

pin,however,

OSENSE

sources 18.3µA, 26.6µA and 35µA when the I

pin is

LIM

low, floating, and high, respectively, and when a constant

current is being regulated. The error introduced by this

mismatch can be offset to a first order by scaling the

The output of the phase detector is a pair of comple-

mentary current sources that charge or discharge the

internal filter network. There is a precision 10µA of cur-

rent flowing out of the FREQ pin. This allows a single

resistor to SGND to set the switching frequency when

no external clock is applied to the MODE/PLLIN pin. The

internal switch between FREQ and the integrated PLL filter

network is on, allowing the filter network to be at the same

voltage on the FREQ pin. Operating frequency is shown

in Figure 9 and specified in the Electrical Characteristics

table. If an external clock is detected on the MODE/PLLIN

pin, the internal switch previously mentioned will turn

off and isolate the influence of the FREQ pin. Note that

the LTC3789 can only be synchronized to an external

+

–

I

and I

resistors accordingly. For example,

OSENSE

+

if the I

branch has a 100Ω resistor, the 1.83mV

OSENSE

–

across it can be replicated in the I

a 182Ω resistor.

branch by using

OSENSE

WhentheI

commonmodevoltagefallsbelow~3.2V

OSENSE

by a diode drop, the I

current decreases linearly; it

OSENSE

reaches approximately –300µA at zero volts. The values

of the diode drop and maximum current sinking can vary

by 20% to 30% due to process variation. Ensure that I

SENSE

maximum of 0.3V below ground. Pay special attention to

short-circuit conditions in high power applications.

O-

common mode voltage never exceeds its absolute

700

600

500

400

300

200

100

0

Slope Compensation

Slope compensation provides stability in constant-

frequency architectures by preventing subharmonic

oscillations at high duty cycles in boost operation and at

low duty cycles in buck operation. This is accomplished

internally by adding a compensating ramp to the inductor

current signal at duty cycles in excess of 40% in the boost

region, or subtracting a ramp from the inductor current

signal at lower than 40% duty cycles in the buck region.

Normally, this results in a reduction of maximum inductor

peak current for duty cycles >40% in the boost region, or

an increase of maximum inductor current for duty cycles

<40% in the buck region. However, the LTC3789 uses a

scheme that counteracts this compensating ramp, which

allowsthemaximuminductorcurrenttoremainunaffected

throughout all duty cycles.

0

0.5

1

1.5

2

2.5

FREQ PIN VOLTAGE (V)

3789 F09

Figure 9. Relationship Between Oscillator

Frequency and Voltage at the FREQ Pin

3789fc

17

For more information www.linear.com/LTC3789

LTC3789

applicaTions inForMaTion

clock whose frequency is within range of the LTC3789’s

internal VCO. This is guaranteed to be between 200kHz

and 600kHz. A simplified block diagram is shown in

Figure 10.

For a given ripple the inductance terms in continuous

mode are as follows:

2

V

•(V_OUT– V_IN(MIN)) •100

IN(MIN)

L_BOOST

>

H,

2

f •I_OUT(MAX)• %Ripple • V_OUT

2.4V 5V

R

SET

10µA

V_OUT• V_IN(MAX)– V

•100

(

)

OUT

L_BUCK

where:

>

H

FREQ

f •I_OUT(MAX)• %Ripple • V_IN(MAX)

MODE/

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

SYNC

EXTERNAL

OSCILLATOR

VCO

f is operating frequency, Hz

% Ripple is allowable inductor current ripple

V

is minimum input voltage, V

is maximum input voltage, V

is output voltage, V

IN(MIN)

IN(MAX)

3789 F10

Figure 10. Phase-Locked Loop Block Diagram

OUT

I

is maximum output load current, A

OUT(MAX)

If the external clock frequency is greater than the inter-

For high efficiency, choose an inductor with low core

loss, such as ferrite. Also, the inductor should have low

nal oscillator’s frequency, f , then current is sourced

OSC

2

continuously from the phase detector output, pulling up

DC resistance to reduce the I R losses, and must be able

the filter network. When the external clock frequency is

to handle the peak inductor current without saturating. To

minimize radiated noise, use a toroid, pot core or shielded

bobbin inductor.

less than f , current is sunk continuously, pulling down

OSC

the filter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for the amount of time corresponding to

the phase difference. The voltage on the filter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the filter capacitor holds the voltage.

C and C

IN

Selection

OUT

In the boost region, input current is continuous. In the

buck region, input current is discontinuous. In the buck

region, the selection of input capacitor C is driven by

IN

the need to filter the input square wave current. Use a low

ESR capacitor sized to handle the maximum RMS current.

For buck operation, the input RMS current is given by:

Typically, the external clock (on the MODE/PLLIN pin)

input high threshold is 1.6V, while the input low thresh-

old is 1V.

V_OUT

V

V_OUT

IN

I_RMS≈ I_OUT(MAX)

•

– 1

V

IN

Inductor Selection

This formula has a maximum at V = 2V , where

IN

OUT

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. The inductor

value has a direct effect on ripple current. The inductor

I

= I

/2. This simple worst-case condition

RMS

OUT(MAX)

is commonly used for design because even significant

deviations do not offer much relief. Note that ripple cur-

rentratingsfromcapacitormanufacturersareoftenbased

on only 2000 hours of life which makes it advisable to

derate the capacitor.

current ripple ∆I is typically set to 20% to 40% of the

L

maximum inductor current in the boost region at V

.

IN(MIN)

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In the boost region, the discontinuous current shifts

InordertoselectthepowerMOSFETs,thepowerdissipated

by the device must be known. For switch A, the maximum

power dissipation happens in the boost region, when it

remains on all the time. Its maximum power dissipation

at maximum output current is given by:

from the input to the output, so C

must be capable

OUT

of reducing the output voltage ripple. The effects of ESR

(equivalent series resistance) and the bulk capacitance

must be considered when choosing the right capacitor

for a given output ripple voltage. The steady ripple due to

charginganddischargingthebulkcapacitanceisgivenby:





 ²

V_OUT

P_A,BOOST

=

• I_OUT(MAX)• ρ_t• R_DS(ON)







V

IN

I_OUT(MAX)• V

– V

IN(MIN)

(

)

OUT

Ripple(Boost,Cap) =

V

C_OUT• V_OUT• f

where ρ is a normalization factor (unity at 25°C) ac-

t

counting for the significant variation in on-resistance

with temperature, typically about 0.4%/°C, as shown in

Figure 11. For a maximum junction temperature of 125°C,

where C

is the output filter capacitor.

OUT

The steady ripple due to the voltage drop across the ESR

is given by:

using a value ρ = 1.5 is reasonable.

t

2.0

1.5

1.0

0.5

0

∆V

= I

• ESR

OUT(MAX,BOOST)

BOOST,ESR

In buck mode, V

ripple is given by:

OUT

∆V

≤ ∆I • (ESR + 1 / (8 • f • C

)

OUT

L

OUT

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic

and ceramic capacitors are all available in surface mount

packages. Ceramic capacitors have excellent low ESR

characteristics but can have a high voltage coefficient.

Capacitors are now available with low ESR and high ripple

current ratings, such as OS-CON and POSCAP.

50

100

–50

150

0

JUNCTION TEMPERATURE (°C)

3789 F11

Figure 11. Normalized R_DS(ON)vs Temperature

Power MOSFET Selection and

Efficiency Considerations

Switch B operates in the buck region as the synchronous

rectifier. Its power dissipation at maximum output current

is given by:

TheLTC3789requiresfourexternalN-channelpowerMOS-

FETs, two for the top switches (switches A and D, shown

in Figure 1) and two for the bottom switches (switches

B and C, shown in Figure 1). Important parameters for

V − V

2

IN

OUT

P_B,BUCK

=

• I_OUT(MAX)• ρ_τ• R_DS(ON)

V

IN

the power MOSFETs are the breakdown voltage V

,

BR,DSS

, reverse

SwitchCoperatesintheboostregionasthecontrolswitch.

Its power dissipation at maximum current is given by:

threshold voltage V

, on-resistance R

RSS

GS,TH

DS(ON)

transfercapacitanceC andmaximumcurrentI

.

DS(MAX)

V

– V

V

(

)

IN

2

OUT

2

The drive voltage is set by the 5.5V INTV supply. Con-

P

=

• I_OUT(MAX)• ρ_t

CC

C,BOOST

V

sequently, logic-level threshold MOSFETs must be used

IN

in LTC3789 applications.

I_OUT(MAX)

3

• R_DS(ON)+ k • V_OUT

•

• C_RSS• f

V

IN

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where C

is usually specified by the MOSFET manufac-

gate drivers and much of the LTC3789’s internal circuitry.

ThelinearregulatorregulatesthevoltageattheINTV pin

RSS

turers. The constant k, which accounts for the loss caused

by reverse recovery current, is inversely proportional to

the gate drive current and has an empirical value of 1.7.

CC

to 5.5V when V is greater than 6.5V. EXTV can supply

IN

CC

the needed power when its voltage is higher than 4.8V

through another on-chip PMOS LDO. Each of these can

supply a peak current of 100mA and must be bypassed to

ground with a minimum of 1µF ceramic capacitor or low

ESR electrolytic capacitor. No matter what type of bulk

capacitor is used, an additional 0.1µF ceramic capacitor

For switch D, the maximum power dissipation happens

in the boost region, when its duty cycle is higher than

50%. Its maximum power dissipation at maximum output

current is given by:

2

placed directly adjacent to the INTV and PGND pins is











V_OUT

V

V_OUT

CC

IN

P

=

•

•I_OUT(MAX)• ρ_t•R_DS(ON)

D,BOOST



highlyrecommended.Goodbypassingisneededtosupply

the high transient current required by the MOSFET gate

drivers and to prevent interaction between the channels.

V

IN

For the same output voltage and current, switch A has the

highest power dissipation and switch B has the lowest

power dissipation unless a short occurs at the output.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3789 to be

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

exceeded. The INTV current, which is dominated by the

CC

gate charge current, may be supplied by either the 5.5V

linear regulator from V or the 5.5V LDO from EXTV

.

IN

CC

T = T + P • R

J

A

TH(JA)

When the voltage on the EXTV pin is less than 4.5V, the

CC

linear regulator from V is enabled. Power dissipation for

IN

The R

to be used in the equation normally includes

TH(JA)

theICinthiscaseishighestandisequaltoV • I

.The

IN INTVCC

the R

for the device plus the thermal resistance from

TH(JC)

gate charge current is dependent on operating frequency,

as discussed in the Efficiency Considerations section. The

junction temperature can be estimated by using the equa-

tions given in Note 3 of the Electrical Characteristics. For

the case to the ambient temperature (R

). This value

TH(JC)

of T can then be compared to the original, assumed value

J

used in the iterative calculation process.

example, the LTC3789 INTV current is limited to less

Schottky Diode (D1, D2) Selection

CC

than 24mA from a 24V supply in the SSOP package and

The Schottky diodes, D1 and D2, shown in Figure 13,

conduct during the dead time between the conduction

of the power MOSFET switches. They are intended to

prevent the body diode of synchronous switches B and D

from turning on and storing charge during the dead time.

In particular, D2 significantly reduces reverse recovery

current between switch D turn-off and switch C turn-on,

which improves converter efficiency and reduces switch

C voltage stress. In order for the diode to be effective, the

inductance between it and the synchronous switch must

beassmallaspossible,mandatingthatthesecomponents

be placed adjacently.

not using the EXTV supply:

CC

T = 70°C + (28mA)(24V)(80°C/W) = 125°C

J

To preventthemaximumjunctiontemperaturefrombeing

exceeded,theinputsupplycurrentmustbecheckedwhile

operating in continuous conduction mode (MODE/PLLIN

= SGND) at maximum

EXTV_CCrisesabove4.8V,theINTV_CClinearregulatorfrom

_INis turned off and the linear regulator from EXTV_CCis

V_IN. When the voltage applied to

V

turned on and remains on as long as the voltage applied

to EXTV_CCremains above 4.5V. Using EXTV_CCallows the

MOSFET driver and control power to be derived from the

LTC3789’s switching regulator output during normal

INTV Regulators and EXTV

CC

operation and from the

V

when the output is out of

regulation (e.g., start-up,^INshort-circuit). Do not apply

The LTC3789 features a true PMOS LDO that supplies

power to INTV from the V supply. INTV powers the

more than 14V to EXTV

.

CC

IN

CC

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Significant efficiency and thermal gains can be realized

by powering EXTV_CCfrom the output, since the V_INcur-

the internal precision 0.8V voltage reference by the error

amplifier. The output voltage is given by the equation:

rent resulting from the driver and control currents will be

scaled by a factor of (Duty Cycle)/(Switcher Efficiency).











R2

R1

V_OUT= 0.8V • 1+



Tying the EXTV_CCpin to a 12V output reduces the junction

temperatureinthepreviousexamplefrom125°Cto97°C:

where R1 and R2 are defined in Figure 13.

T_J= 70°C + (28mA)(12V)(80°C/W) = 97°C

Topside MOSFET Driver Supply (C , D , C , D )

A

B

Powering EXTV from the output can also provide

CC

Referring to Figure 13, the external bootstrap capacitors

C and C connected to the BOOST1 and BOOST2 pins

enough gate drive when

V

_INdrops below 5V. This allows

_INafter the controller start

A

B

a wider operating range for

into regulation.

V

supply the gate drive voltage for the topside MOSFET

switches A and D. When the top switch A turns on, the

switch node SW1 rises to V and the BOOST1 pin rises

The following list summarizes the three possible connec-

IN

to approximately V + INTV . When the bottom switch

tions for EXTV :

IN

CC

B turns on, the switch node SW1 drops to low and the

1. EXTV left open (or grounded). This will cause INTV

CC

boost capacitor C is charged through D from INTV .

A

CC

to be powered from the internal 5.5V regulator at the

When the top switch D turns on, the switch node SW2

cost of a small efficiency penalty.

rises to V and the BOOST2 pin rises to approximately

OUT

2. EXTV connecteddirectlytoV

(4.7V<V

<14V).

OUT

V

+ INTV . When the bottom switch C turns on, the

CC

OUT

CC

Thisisthenormalconnectionforthe5.5Vregulatorand

provides the highest efficiency.

switch node SW2 drops to low and the boost capacitor C

B

is charged through D from INTV . The boost capacitors

A

CC

C and C need to store about 100 times the gate charge

A

B

3. EXTV connected to an external supply. If an external

CC

required by the top switches A and D. In most applica-

tions, a 0.1µF to 0.47µF, X5R or X7R dielectric capacitor

is adequate.

supply is available in the 4.7V to 14V range, it may be

used to power EXTV provided it is compatible with

CC

the MOSFET gate drive requirements.

Note that there is an internal body diode from INTV to

Undervoltage Lockout

CC

V . When INTV is powered from EXTV and V drops

IN

CC

IN

The LTC3789 has two functions that help protect the

controller in case of undervoltage conditions. A precision

lower than 4.5V, the diode will create a back-feeding path

from EXTV to V . To limit this back-feeding current, a

CC

IN

UVLOcomparatorconstantlymonitorstheINTV voltage

CC

10Ω ~ 15Ω resistor is recommended between the system

voltage and the chip V pin. To truly eliminate this

to ensure that an adequate gate-drive voltage is present.

V

IN

It locks out the switching action when INTV is below

CC

back-feeding current, a blocking Schottky diode should

be connected between the system V and the chip V .

3.4V. To prevent oscillation when there is a disturbance

IN

on the INTV , the UVLO comparator has 400mV of preci-

CC

sion hysteresis.

Output Voltage

Anotherwaytodetectanundervoltageconditionistomoni-

The LTC3789 output voltage is set by an external feed-

back resistive divider carefully placed across the output

capacitor. The resultant feedback signal is compared with

tor the V supply. Because the RUN pin has a precision

IN

turn-on reference of 1.22V, one can use a resistor divider

to V to turn on the IC when V is high enough. An extra

IN

5µA of current flows out of the RUN pin once its voltage

passes 1.22V. One can program the hysteresis of the run

comparatorbyadjustingthevaluesoftheresistivedivider.

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Soft-Start Function

Efficiency Considerations

When a capacitor is connected to the SS pin, a soft-start

current of 3µA starts to charge the capacitor. A soft-start

function is achieved by controlling the output ramp volt-

age according to the ramp rate on the SS pin. Current

foldback is disabled during this phase to ensure smooth

soft-start. When the chip is in the shutdown state with its

RUN pin voltage below 1.22V, the SS pin is actively pulled

to ground. The soft-start range is defined to be the voltage

range from 0V to 0.8V on the SS pin. The total soft-start

time can be calculated as:

The percent efficiency of a switching regulator is equal

to the output power divided by the input power times

100%. It is often useful to analyze individual losses

to determine what is limiting the efficiency and which

change would produce the most improvement. Although

all dissipative elements in circuit produce losses, four

main sources account for most of the losses in LTC3789

circuits:

2

1. DC I R losses. These arise from the resistances of the

MOSFETs,sensingresistor,inductorandPCboardtraces

and cause the efficiency to drop at high output currents.

C_SS

t_SOFTSTART= 0.8 •

3µA

2. MOSFET Transition loss. This loss arises from the

brief amount of time switch A or switch C spends in

the saturated region during switch node transitions. It

depends upon the input voltage, load current, driver

strengthandMOSFETcapacitance,amongotherfactors.

Regardless of the mode selected by the MODE/PLLIN pin,

the regulator will always start in pulse-skipping mode up

to SS = 0.8V.

Fault Conditions: Current Limit and Current Foldback

3. INTV current. This is the sum of the MOSFET driver

CC

and control currents. This loss can be reduced by sup-

The maximum inductor current is inherently limited in a

currentmodecontrollerbythemaximumsensevoltage.In

the boost region, maximum sense voltage and the sense

resistancedeterminethemaximumallowedinductorpeak

current, which is:

plying INTV current through the EXTV pin from a

CC

high efficiency source, such as the output (if 4.7V <

V

OUT

< 14V) or alternate supply if available.

4. C and C

loss. The input capacitor has the difficult

IN

OUT

joboffilteringthelargeRMSinputcurrenttotheregula-

tor in buck mode. The output capacitor has the more

difficult job of filtering the large RMS output current in

140mV

R_SENSE

I_L(MAX,BOOST)

=

boost mode. Both C and C

are required to have

IN

OUT

In the buck region, maximum sense voltage and the sense

resistancedeterminethemaximumallowedinductorvalley

current, which is:

2

low ESR to minimize the AC I R loss and sufficient

capacitance to prevent the RMS current from causing

additional upstream losses in fuses or batteries.

90mV

R_SENSE

I_L(MAX,BUCK)

=

5. Otherlosses.SchottkydiodesD1andD2areresponsible

for conduction losses during dead time and light load

conduction periods. Inductor core loss should also be

considered. Switch C causes reverse recovery current

loss in boost mode.

To further limit current in the event of a short circuit to

ground, the LTC3789 includes foldback current limiting.

If the output falls by more than 50%, then the maximum

sense voltage is progressively lowered to about one-third

of its full value.

Whenmakingadjustmentstoimproveefficiency,theinput

current is the best indicator of changes in efficiency. If

one makes a change and the input current decreases, then

the efficiency has increased. If there is no change in input

current, then there is no change in efficiency.

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Design Example

Output voltage is 12V. Select R1 as 20k. R2 is:

V_OUT•R1

V = 5V to 18V

IN

R2 =

– R1

0.8

V

I

= 12V

OUT

= 5A

Select R2 as 280k. Both R1 and R2 should have a toler-

ance of no more than 1%.

OUT(MAX)

f = 400kHz

Maximum ambient temperature = 60°C

Selecting MOSFET Switches

Set the frequency at 400kHz by applying 1.2V on the FREQ

pin (see Figure 7). The 10µA current flowing out of the

FREQ pin will give 1.2V across a 120k resistor to GND. The

inductance value is chosen first based on a 30% ripple cur-

rent assumption. In the buck region, the ripple current is:

The MOSFETs are selected based on voltage rating and

DS(ON)

R

value. It is important to ensure that the part is

specified for operation with the available gate voltage am-

plitude. In this case, the amplitude is 5.5V and MOSFETs

with an R

value specified at V = 4.5V can be used.

DS(ON)

GS







V_OUT

f •L

V_OUT

Select QA and QB. With 18V maximum input voltage MOS-

FETs with a rating of at least 30V are used. As we do not yet

knowtheactualthermalresistance(circuitboarddesignand

airflow have a major impact) we assume that the MOSFET

thermal resistance from junction to ambient is 50°C/W.

∆I_L,BUCK

=

• 1–







V

IN

∆I_L,BUCK• 100

I_RIPPLE,BUCK

=

%

I_OUT

Thehighestvalueofripplecurrentoccursatthemaximum

input voltage. In the boost region, the ripple current is:

If we design for a maximum junction temperature, T

J(MAX)

value can be calculated.

= 125°C, the maximum R

DS(ON)

First, calculate the maximum power dissipation:





V

f •L

V

IN

V_OUT

IN

∆I_L,BOOST

=

• 1–











T_J(MAX)− T_A(MAX)



P_D(MAX)

=





R_{(j− a)}





∆I_L,BOOST• 100

I_RIPPLE,BOOST

=

%

(125 − 60)

I_IN

= 1.3W

50

The highest value of ripple current occurs at V = V /2.

IN

OUT

The maximum dissipation in QA occurs at minimum input

voltage when the circuit operates in the boost region and

QA is on continuously. The input current is then:

A6.8µHinductorwillproduce11%rippleintheboostregion

(V = 6V) and 29% ripple in the buck region (V = 18V).

IN

The R

resistor value can be calculated by using the

SENSE

V_OUT•I_OUT(MAX)

maximum current sense voltage specification with some

accommodation for tolerances.

, OR 12A

V

IN(MIN)

2 • 140mV • V_IN(MIN)

We calculate a maximum value for R

:

DS(ON)

R_SENSE

=

2 •I_{OUT(MAX,BOOST)}• V_OUT+ ∆I_L,BOOST• V_IN(MIN)

P

D(MAX)

R_DS(ON)(125°C) <

2

I

IN(MAX)

Select an R of 10mΩ.

SENSE

1.3W

(12A)²

R_DS(ON)(125°C) <

= 0.009Ω

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The Vishay SiR422DP has a typical R

of 0.010Ω at

The dissipation in switch QD is:

DS(ON)



 ²



T = 125°C and V = 4.5V.

J

GS

V_OUT

V

IN

P_D,BOOST

=

•

• I_OUT(MAX)

The maximum dissipation in QB occurs at maximum input

voltage when the circuit is operating in the buck region.

The dissipation is:





V_OUT

• ρ_t• R_DS(ON)

V



IN

Vishay SiR484OY is a possible choice for QC and QD. The

calculated power loss at 5V input voltage is then 1.3W for

QC and 0.84W for QD.

V − V

2

IN

OUT

P_B,BUCK

=

• I_OUT(MAX)• ρ_t• R_DS(ON)

V

IN

1.3W

C ischosentofilterthesquarecurrentinthebuckregion.

R_DS(ON)(125°C) <

= 0.156Ω

IN

18V TO −12V

• (5A)²

In this mode, the maximum input current peak is:

18V

29%

2





I_{IN,PEAK(MAX,BUCK)}= 5A • 1+

= 5.7A







This seems to indicate that a quite small MOSFET can be

used for QB if we only look at power loss. However, with

5Acurrentthevoltagedropacross0.156Ωis0.78V,which

means the MOSFET body diode is conducting. To avoid

body diode current flow we should keep the maximum

voltage drop well below 0.5V, using, for example, Vishay



A low ESR (10mΩ) capacitor is selected. Input voltage

ripple is 57mV (assuming ESR dominates the ripple).

C

is chosen to filter the square current in the boost

OUT

region. In this mode, the maximum output current peak is:

Si4840BDY in the SO-8 package (R

= 0.012Ω).

DSON(MAX)











12

5

11%

2

I_{OUT,PEAK(MAX,BOOST)}

=

• 5 • 1+

= 10.6A



Select QC and QD. With 12V output voltage we need

MOSFETs with 20V or higher rating.

A low ESR (5mΩ) capacitor is suggested. This capacitor

will limit output voltage ripple to 53mV (assuming ESR

dominates the ripple).

The highest dissipation occurs at minimum input voltage

when the inductor current is highest. For switch QC the

dissipation is:

(V_OUT− V )V

IN

2

OUT

PC Board Layout Checklist

P

=

C,BOOST

V

IN

The basic PC board layout requires a dedicated ground

plane layer. Also, for high current, a multilayer board

provides heat sinking for power components.

2

• I_OUT(MAX)• ρ_t• R_DS(ON)

I_OUT(MAX)

3

• The ground plane layer should not have any traces and

should be as close as possible to the layer with power

MOSFETs.

+ k • V_OUT

where C

•

• C_RSS• f

V

IN

is usually specified by the MOSFET manufac-

RSS

turers. The constant k, which accounts for the loss caused

by reverse recovery current, is inversely proportional to

the gate drive current and has an empirical value of 1.7.

•

Place C , switch A, switch B and D1 in one com-

IN

pact area. Place C , switch C, switch D and D2 in

OUT

one compact area. One layout example is shown in

Figure 12.

• Use immediate vias to connect the components (in-

cluding the LTC3789’s SGND and PGND pins) to the

ground plane. Use several large vias for each power

component.

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• Use planes for V and V

to maintain good voltage

• Theoutputcapacitor(–)terminalsshouldbeconnected

as closely as possible to the (–) terminals of the input

capacitor.

IN

OUT

filtering and to keep power losses low.

• Flood all unused areas on all layers with copper. Flood-

ing with copper will reduce the temperature rise of

power components. Connect the copper areas to any

• Connect the top driver boost capacitor C closely to the

A

BOOST1 and SW1 pins. Connect the top driver boost

DC net (V or GND). When laying out the printed circuit

capacitor C closely to the BOOST2 and SW2 pins.

IN

B

board, the following checklist should be used to ensure

proper operation of the LTC3789. These items are also

illustrated in Figure 13.

• Connect the input capacitors C and output capacitors

IN

C

closely to the power MOSFETs. These capacitors

OUT

carry the MOSFET AC current in the boost and buck

region.

• Segregate the signal and power grounds. All small-

signal components should return to the SGND pin at

one point, which is then tied to the PGND pin close to

• Connect V pin resistive dividers to the (+) terminals of

FB

C

OUT

and signal ground. A small V bypass capacitor

FB

the inductor current sense resistor R

.

SENSE

may be connected closely to the LTC3789 SGND pin.

The R2 connection should not be along the high current

or noise paths, such as the input capacitors.

• Place switch B and switch C as close to the controller as

possible, keeping the PGND, BG and SW traces short.

–

+

• Keep the high dV/dT SW1, SW2, BOOST1, BOOST2,

TG1 and TG2 nodes away from sensitive small-signal

nodes.

• Route SENSE and SENSE leads together with mini-

mum PC trace spacing. Avoid having sense lines pass

through noisy areas, such as switch nodes. The filter

+

–

capacitor between SENSE and SENSE should be as

close as possible to the IC. Ensure accurate current

sensing with Kelvin connections at the sense resistor.

One layout example is shown in Figure 14.

• The path formed by switch A, switch B, D1 and the C

IN

capacitor should have shortleadsand PC tracelengths.

The path formed by switch C, switch D, D2 and the

C

capacitor also should have short leads and PC

OUT

trace lengths.

• Connect the I pin compensation network closely to

TH

the IC, between I and the signal ground pins. The

TH

capacitor helps to filter the effects of PCB noise and

output voltage ripple voltage from the compensa-

tion loop.

V

SW2

SW1

V

OUT

IN

L

D2

QD

QA

• Connect the INTV bypass capacitor, C , closely

CC

VCC

to the IC, between the INTV and the power ground

CC

D1

pins.ThiscapacitorcarriestheMOSFETdrivers’current

peaks. An additional 1µF ceramic capacitor placed im-

QB

QC

C

mediately next to the INTV and PGND pins can help

IN

OUT

CC

improve noise performance substantially.

R

SENSE

LTC3789

CKT

GND

3789 F12

Figure 12. Switches Layout

3789fc

25

For more information www.linear.com/LTC3789

LTC3789

applicaTions inForMaTion

R1

20k

R2

280k

V

PULLUP

10Ω

V

IN

V

OUT

5V TO 38V

MAX

C

A

0.22µF

C

IN

47µF

SS

1

2

27

26

25

24

23

22

6.8nF

PGOOD

SW1

TG1

V

FB

Q

A

SS

SiR422DP

C

C2

BOOST1

PGND

BG1

1000pF

3

4

D

+

A

L

SENSE

DFLS160

C

C1

6.8µH

Q

B

SiR422DP

R

68k

–

C

3300pF

C 1µF

5

F

V

IN

I

TH

D1

LTC3789

6

B240A

SGND

C

VCC

4.7µF

21

20

INTV

7

CC

INTV

EXTV

MODE/PLLIN

FREQ

CC

121k

10mΩ

8

V

CC

OUT

D

B

DFLS160

9

RUN

ON/OFF

19

18

10

11

12

13

14

Q

C

V

BG2

V

IN

INSNS

SiR422DP

V

BOOST2

V

OUT

OUTSNS

C

B

0.22µF

I

D2

B240A

LIM

C

OUT

2.2µF

17

16

15

Q

D

SiR422DP

+

TG2

SW2

TRIM

I

OSENSE

2.2µF

–

10mΩ

V

OUT

12V, 5A

+

330µF

100Ω

1k

3789 F13

1k

Figure 13. LTC3789 12V/5A, Buck-Boost Regulator

PGND

C

R

SGND

3789 F14

Figure 14. Sense Lines Layout

3789fc

26

For more information www.linear.com/LTC3789

LTC3789

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 .005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 .004

.0532 – .0688

(1.35 – 1.75)

¥ 45∞

.004 – .0098

(0.102 – 0.249)

(0.38 0.10)

.0075 – .0098

(0.19 – 0.25)

0 – 8 TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

3789fc

27

For more information www.linear.com/LTC3789

LTC3789

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev B)

0.70 0.05

4.50 0.05

3.10 0.05

2.50 REF

2.65 0.05

3.65 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

3.50 REF

4.10 0.05

5.50 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

2.50 REF

R = 0.115

TYP

R = 0.05

TYP

0.75 0.05

4.00 0.10

(2 SIDES)

27

28

0.40 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 0.10

(2 SIDES)

3.50 REF

3.65 0.10

2.65 0.10

(UFD28) QFN 0506 REV B

0.25 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3789fc

28

For more information www.linear.com/LTC3789

LTC3789

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

9/11

Updated Features, Description and Typical Application.

Updated Electrical Characteristics section.

Updated text in MODE/PLLIN, BOOST1, BOOST2, SW1, SW2 in Pin Functions section.

Updated text in Operation section.

1

3

9, 10

12-15

16-25

26

Updated text in Applications Information section.

Updated Figure 13.

Updated Typical Application and Related Parts.

30

B

C

07/14 Updated Application Schematic

Updated Nominal Frequency Resistor

1

4

Updated V

Updated L

and V Sections

9, 10

18

2

OUTSNS

IN

equation

BOOST

11/14 Added TG1, TG2 Absolute Maximum Ratings

Added Note 6

Replaced Figure 9

Added Text

4

17

21

3789fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29

For more information www.linear.com/LTC3789

LTC3789

Typical applicaTion

24V/5A Buck-Boost Regulator

R5

10Ω, 0805

V

IN

J3

V

IN

V

OUT1

V

+

V

OUT

OS

9V TO

35V

C6

C

IN2

J1

+

IN1

INTV

28

CC

V

C15

1µF

50V

1210

OUT

R

232k

3.3µF

50V

1210

270µF

50V

270µF

50V

FB1

24V AT

5A

C1

+

C

R2

R7

100k

OUT2

R8

OPT

2.2µF,

50V

X5R

330µF

34V

0.010Ω

2%

10Ω

R

8.06k

FB2

Q3

+

V

1

2

3

4

5

27

26

25

24

23

22

OS

SiR422DP

PGOOD SW1

V

Q2

SiR422DP

FB

C3

D6

B240A

TG1

SS

2.2µF

50V

C4

R11, 0Ω

R9, 1.24k

R10, 1.24k

0.01µF

+

0.22µF, 16V

BOOST1

PGND1

BG1

SENSE1

L1

5.5µH

X5R

C11, OPT

, 1000pF

–

D4

Q4

SiR422DP

DFLS160

C

C1

R , 15k

I

TH

C

, 0.01µF

C

C2

D5

B240A

V

IN

LTC3789EGN

C18

10µF, 1206

6

7

INTV

CC

SGND

21

20

R21

121k, 1%

INTV

EXTV

MODE/PLLIN

FREQ

CC

D8

BZX84-

C5V1

8

R30

68.1k

CC

+

9

D2

V

IN

D7

RUN

BAS16

DFLS160

19

18

C7, 0.1µF

C8, 0.1µF

10

11

12

13

14

3

1

Q5

SiR422DP

R31

12.1k

BG2

V

INSNS

OUTSNS

LIM

R1, 5.6Ω

BOOST2

C22

0.22µF, 16V

I

R13, 100Ω

C10, 2.2µF

R25

0Ω

17

16

15

+

TG2

SW2

TRIM

I

OSENSE

R14

100Ω

OUT

–

OSENSE

V

IN

R18

8mΩ

2%

R4, 100Ω

R3, 100Ω

3789 TA02

L1: WÜRTH 7443630550

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC3780

High Efficiency (Up to 98%) Synchronous, 4-Switch Buck-Boost

DC/DC Controller

4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 30V, 5mm × 5mm QFN-32 and

IN

OUT

SSOP-24 Packages

LTC3785

LTM4605

LTM4607

LTM4609

LTC3112

LTC3533

High Efficiency (Up to 98%) Synchronous, 4-Switch Buck-Boost

DC/DC Controller

2.7V ≤ V ≤ 10V, 2.7V ≤ V

≤ 10V, 4mm × 4mm

IN

OUT

QFN-24 Package

High Efficiency Buck-Boost DC/DC µModule™ Regulator

Complete Power Supply

4.5V ≤ V ≤ 20V, 0.8V ≤ V

≤ 16V, 15mm × 15mm × 2.8mm

≤ 25V, 15mm × 15mm × 2.8mm

≤ 34V, 15mm × 15mm × 2.8mm

≤ 14V, 4mm × 5mm DFN-16 and

IN

LGA Package

High Efficiency Buck-Boost DC/DC µModule Regulator

Complete Power Supply

4.5V ≤ V ≤ 36V, 0.8V ≤ V

IN

LGA Package

High Efficiency Buck-Boost DC/DC µModule Regulator

Complete Power Supply

4.5V ≤ V ≤ 36V, 0.8V ≤ V

IN

LGA Package

2.5A Synchronous Buck-Boost DC/DC Converter

2.7V ≤ V ≤ 15V, 2.5V ≤ V

IN

TSSOP-20 Packages

2A Synchronous Buck-Boost Monolithic DC/DC Converter

1.8V ≤ V ≤ 5.5V, 1.8V ≤ V

≤ 5.25V, I = 40µA,

OUT Q

IN

I

< 1µA, 3mm × 4mm DFN-14 Package

SD

3789fc

LT 1114 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

30

For more information www.linear.com/LTC3789

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3789

●

 LINEAR TECHNOLOGY CORPORATION 2010


型号：	LTC3789IUFD#PBF
厂家：	Linear
描述：	LTC3789 - High Efficiency, Synchronous, 4-Switch Buck-Boost Controller; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C 开关
文件：	总30页 (文件大小：527K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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