LTC3830ES8#TRPBF [Linear]
LTC3830 - High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC3830ES8#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3830 - High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总24页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3830/LTC3830-1
High Power Step-Down
Synchronous DC/DC Controllers
for Low Voltage Operation
U
FEATURES
DESCRIPTIO
■
High Power Switching Regulator Controller
The LTC®3830/LTC3830-1 are high power, high effi-
ciency switching regulator controllers optimized for
3.3V-5V to 1.xV-3.xV step-down applications. A preci-
sion internal reference and feedback system provide
±1% output regulation over temperature, load current
andlinevoltagevariations. TheLTC3830/LTC3830-1use
a synchronous switching architecture with N-channel
MOSFETs. Additionally, the chip senses output current
through the drain-source resistance of the upper
N-channel FET, providing an adjustable current limit
without a current sense resistor.
for 3.3V-5V to 1.xV-3.xV Step-Down Applications
■
No Current Sense Resistor Required
■
Low Input Supply Voltage Range: 3V to 8V
■
Maximum Duty Cycle >91% Over Temperature
■
All N-Channel External MOSFETs
■
Excellent Output Regulation: ±1% Over Line, Load
and Temperature Variations
High Efficiency: Over 95% Possible
■
■
Adjustable or Fixed 3.3V Output (16-Pin Version)
■
Programmable Fixed Frequency Operation: 100kHz to
500kHz
The LTC3830/LTC3830-1 operate with an input supply
voltage as low as 3V and with a maximum duty cycle of
>91% over temperature. They include a fixed frequency
PWMoscillatorforlowoutputrippleoperation.The200kHz
free-running clock frequency can be externally adjusted or
synchronizedwithanexternalsignalfrom100kHzto500kHz.
In shutdown mode, the LTC3830 supply current drops to
<10µA. The LTC3830-1 differs from the LTC3830 S8 ver-
sion by replacing shutdown with a soft-start function.
■
External Clock Synchronization
■
Soft-Start (16-Pin Version and LTC3830-1)
■
Low Shutdown Current: <10µA
Overtemperature Protection
■
■
Available in S8, S16 and SSOP-16 Packages
U
APPLICATIO S
■
CPU Power Supplies
■
Multiple Logic Supply Generator
For a similar, pin compatible DC/DC converter with an
outputvoltageaslowas0.6V, pleaserefertotheLTC3832.
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Distributed Power Applications
High Efficiency Power Conversion
■
U
TYPICAL APPLICATIO
V
IN
3V TO 6V
4.7µF
Efficiency and Power Loss vs Load Current
5.1Ω
100
90
80
70
60
50
40
30
20
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
+
220µF
10V
0.1µF
LTC3830-1
MBR0520T1
SS
PV
CC2
G1
0.01µF
M1
Si7806DN
COMP
L
0.1µF
15k
3.2µH
1.8V
9A
GND PV
CC1
G2
12.7k 1%
M2
Si7806DN
+
C
FB
B320A
OUT
270µF
2V
5.36k 1%
3.3nF
V
V
= 3.3V
OUT
IN
3830 F01
= 1.8V
L: SUMIDA CDEP105-3R2MC-88
: PANASONIC EEFUEOD271R
0
1
2
3
4
5
6
7
8
9
10
C
OUT
LOAD CURRENT (A)
3830 TA02
Figure 1. High Efficiency 3V-6V to 1.8V Power Converter
3830fa
1
LTC3830/LTC3830-1
W W
U W
ABSOLUTE AXI U RATI GS (Note 1)
Supply Voltage
Junction Temperature (Note 11)........................... 125°C
Operating Temperature Range (Note 9) .. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
VCC ....................................................................... 9V
PVCC1,2 ................................................................ 14V
Input Voltage
IFB, IMAX ............................................... –0.3V to 14V
SENSE+, SENSE–, FB,
SHDN, FREQSET ....................... –0.3V to VCC + 0.3V
U W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
G1
1
2
3
4
8
7
6
5
G2
TOP VIEW
PV
V /PV
CC CC2
CC1
LTC3830ES8
LTC3830EGN
LTC3830ES
G1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
G2
PV
V
GND
FB
COMP
SHDN
PV
CC1
CC2
S8
PGND
GND
PART MARKING
CC
S8 PACKAGE
8-LEAD PLASTIC SO
GN PART
MARKING
I
I
FB
MAX
3830
–
TJMAX = 125°C, θJA = 130°C/ W
SENSE
FB
FREQSET
COMP
SS
3830
+
ORDER PART
NUMBER
TOP VIEW
SENSE
SHDN
G1
1
2
3
4
8
7
6
5
G2
V
PV
/PV
CC2
GN PACKAGE
S PACKAGE
CC1
CC
LTC3830-1ES8
16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO
GND
FB
COMP
SS
TJMAX = 125°C, θJA = 130°C/ W (GN)
TJMAX = 125°C, θJA = 100°C/ W (S)
S8
PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
38301
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
3
TYP
MAX
8
UNITS
V
Supply Voltage
●
●
5
V
V
V
CC
PV
PV , PV Voltage
CC1 CC2
(Note 7)
3
13.2
2.9
CC
UVLO
FB
V
V
Undervoltage Lockout Voltage
Feedback Voltage
2.4
V
V
= 1.25V
= 1.25V
1.255
1.252
1.265
1.265
1.275
1.278
V
V
COMP
COMP
●
●
V
Output Voltage
3.250
3.235
3.3
3.3
3.350
3.365
V
V
OUT
∆V
OUT
Output Load Regulation
Output Line Regulation
I
V
= 0A to 10A (Note 6)
= 4.75V to 5.25V
2
0.1
mV
mV
OUT
CC
3830fa
2
LTC3830/LTC3830-1
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
I
f
Supply Current
Figure 2, V
= V
CC
●
●
0.7
1
1.6
10
mA
µA
VCC
SHDN
V
= 0V
SHDN
PV Supply Current
CC
Figure 2, V
= 0V
= V (Note 3)
●
●
14
0.1
20
10
mA
µA
PVCC
SHDN
CC
V
SHDN
Internal Oscillator Frequency
FREQSET Floating
●
160
200
1.2
2.2
2.85
10
250
780
kHz
OSC
V
V
V
V
V
at Minimum Duty Cycle
at Maximum Duty Cycle
V
SAWL
COMP
COMP
V
V
SAWH
Maximum V
V
= 0V, PV
= 8V
COMPMAX
COMP
FB
CC1
∆f /∆I
Frequency Adjustment
kHz/µA
dB
OSC FREQSET
A
Error Amplifier Open-Loop DC Gain
Measured from FB to COMP,
●
●
46
55
V
+
–
SENSE and SENSE Floating, (Note 4)
g
Error Amplifier Transconductance
Measured from FB to COMP,
520
650
µmho
m
+
–
SENSE and SENSE Floating, (Note 4)
I
I
Error Amplifier Output Sink/Source Current
100
µA
COMP
MAX
I
Sink Current
V
= V
CC
9
4
12
12
15
20
µA
µA
MAX
IMAX
(Note 10)
●
I
Sink Current Tempco
V
= V (Note 6)
3300
ppm/°C
MAX
IMAX
CC
V
V
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
●
●
●
●
2.4
–8
V
V
IH
IL
0.8
1
I
I
I
V
V
= V
CC
0.1
–12
1.6
µA
µA
mA
IN
SHDN
Soft-Start Source Current
= 0V, V
= 0V, V = V
CC
–16
SS
SS
IMAX
IFB
Maximum Soft-Start Sink Current
In Current Limit
V
V
= V , V = 0V,
IMAX CC IFB
SSIL
= V (Note 8), PV = 8V
SS
CC
CC1
R
R
SENSE Input Resistance
SENSE to FB Resistance
Driver Rise/Fall Time
29.2
18
kΩ
kΩ
ns
ns
%
SENSE
SENSEFB
t , t
r
Figure 3, PV
Figure 3, PV
= PV
= PV
= 5V (Note 5)
= 5V (Note 5)
●
●
●
80
250
250
f
CC1
CC2
CC2
t
Driver Nonoverlap Time
Maximum G1 Duty Cycle
25
91
120
95
NOV
CC1
DC
Figure 3, V = 0V (Note 5), PV
= 8V
MAX
FB
CC1
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be
zero.
Note 9: The LTC3830E/LTC3830-1E are guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC3830 operating frequency, operating voltage and the external FETs
used.
Note 10: The minimum and maximum limits for I
over temperature
MAX
includes the intentional temperature coefficient of 3300ppm/°C. This
induced temperature coefficient counteracts the typical temperature
coefficient of the external power MOSFET on-resistance. This results in a
relatively flat current limit over temperature for the application.
+
Note 4: The open-loop DC gain and transconductance from the SENSE
–
and SENSE pins to COMP pin will be (A )(1.265/3.3) and (g )(1.265/3.3)
V
m
respectively.
Note 11: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating temperature
may impair device reliability.
Note 5: Rise and fall times are measured using 10% and 90% levels. Duty
cycle and nonoverlap times are measured using 50% levels.
Note 6: Guaranteed by design, not subject to test.
Note 7: PV
must be higher than V by at least 2.5V for G1 to operate
CC
CC1
at 95% maximum duty cycle and for the current limit protection circuit to
be active.
3830fa
3
LTC3830/LTC3830-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Error Amplifier Transconductance
vs Temperature
Load Regulation
Line Regulation
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
1.275
1.273
1.271
1.269
1.267
1.265
1.263
1.261
1.259
1.257
1.255
10
8
800
750
700
650
T
= 25°C
T
= 25°C
A
A
REFER TO FIGURE 12
6
4
2
0
–2
–4
–6
–8
–10
600
550
500
–10
–5
5
10
15
4
6
50
TEMPERATURE (˚C)
100 125
–15
0
3
5
7
8
–50 –25
0
25
75
OUTPUT CURRENT (A)
SUPPLY VOLTAGE (V)
3830 G02
3830 G03
3830 G05
Error Amplifier Sink/Source
Current vs Temperature
Error Amplifier Open-Loop Gain
vs Temperature
Output Voltage Temperature Drift
60
55
50
45
200
180
160
140
120
100
80
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
40
REFER TO FIGURE 12
OUTPUT = NO LOAD
30
20
10
0
–10
–20
–30
–40
60
40
40
–50 –25
0
25
50
75 100 125
–25
0
50
75 100 125
–50
25
–25
0
50
75 100 125
–50
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2830 G07
3830 G06
3830 G04
Oscillator Frequency
vs Temperature
Oscillator Frequency
Oscillator (VSAWH – VSAWL
)
vs FREQSET Input Current
vs External Sync Frequency
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
600
500
400
300
200
100
0
250
240
230
220
210
200
190
180
170
T
A
= 25°C
T
= 25°C
FREQSET FLOATING
A
160
–40
–20
–10
0
10
20
100
200
300
400
500
–30
–50 –25
0
25
125
50
75 100
FREQSET INPUT CURRENT (µA)
EXTERNAL SYNC FREQUENCY (kHz)
TEMPERATURE (°C)
3830 G09
3830 G10
3831 G08
3830fa
4
LTC3830/LTC3830-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum G1 Duty Cycle
vs Temperature
IMAX Sink Current
vs Temperature
Output Overcurrent Protection
100
99
98
97
96
95
94
93
92
4.0
20
18
16
14
12
10
8
V
= 0V
FB
REFER TO FIGURE 3
3.5
3.0
2.5
2.0
1.5
1.0
T
= 25°C
A
6
0.5
0
REFER TO FIGURE 12
= 5k
R
IMAX
91
4
–50 –25
0
25
125
–50 –25
0
25
50
75 100 125
0
2
4
6
8
10
12
14
50
75 100
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT (A)
3830 G11
3830 G12
3830 G13
Output Current Limit Threshold
vs Temperature
Soft-Start Source Current
vs Temperature
Soft-Start Sink Current
vs (VIFB – VIMAX
)
16
14
12
10
8
–8
–9
2.00
1.75
1.50
1.25
T
= 25°C
A
–10
–11
–12
–13
–14
–15
–16
1.00
0.75
6
4
0.50
0.25
0
REFER TO FIGURE 12 AND NOTE 10 OF
THE ELECTRICAL CHARACTERISTICS
2
R
IMAX
= 5k
0
–50
0
25
50
75 100 125
–25
–25
0
50
75 100 125
–125 –100
–50
–50
25
–150
–25
0
–75
– V
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(mV)
IFB
IMAX
3830 G14
3830 G15
3830 G16
Undervoltage Lockout Threshold
Voltage vs Temperature
VCC Operating Supply Current
vs Temperature
PVCC Supply Current
vs Oscillator Frequency
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
90
80
70
60
50
40
30
20
10
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
T
= 25°C
FREQSET FLOATING
A
G1 AND G2 LOADED
WITH 6800pF,
PV
CC1,2
= 12V
G1 AND G2
LOADED
G1 AND G2
LOADED
WITH 6800pF,
PV
WITH 1000pF,
= 5V
CC1,2
PV
= 5V
CC1,2
0
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
0
400
500
–25
100
200
300
TEMPERATURE (°C)
TEMPERATURE (°C)
OSCILLATOR FREQUENCY (kHz)
3830 G17
3830 G18
3830 G19
3830fa
5
LTC3830/LTC3830-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
PVCC Supply Current
vs Gate Capacitance
G1 Rise/Fall Time
vs Gate Capacitance
Transient Response
50
40
30
200
180
160
140
120
100
80
T
= 25°C
T
= 25°C
A
A
VOUT
50mV/DIV
PV
= 12V
CC1,2
t AT PV
= 5V
CC1,2
f
ILOAD
2AV/DIV
t AT PV
r
= 5V
CC1,2
20
10
0
PV
= 5V
CC1,2
60
40
50µs/DIV
3830 G22.tif
t AT PV
f
= 12V
CC1,2
20
t AT PV
r
= 12V
CC1,2
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
GATE CAPACITANCE AT G1 AND G2 (nF)
GATE CAPACITANCE AT G1 AND G2 (nF)
3830 G20
3830 G21
U
U
U
PI FU CTIO S (16-Lead LTC3830/8-Lead LTC3830/LTC3830-1)
G1 (Pin 1/Pin 1/Pin 1): Top Gate Driver Output. Connect
this pin to the gate of the upper N-channel MOSFET, Q1.
This output swings from PGND to PVCC1. It remains low if
G2 is high or during shutdown mode.
resistor divider to set the output voltage, float SENSE+ and
SENSE– and connect the external resistor divider to FB.
TheinternalresistordividerisnotincludedintheLTC3830-1
and the 8-lead LTC3830.
PVCC1 (Pin 2/Pin 2/Pin 2): Power Supply Input for G1.
SHDN (Pin 8/Pin 5/NA): Shutdown. A TTL compatible low
levelatSHDNforlongerthan100µsputstheLTC3830into
shutdown mode. In shutdown, G1 and G2 go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allows the part to operate normally. This pin also doubles
as an external clock input to synchronize the internal
oscillator with an external clock. The shutdown function is
disabled in the LTC3830-1.
Connect this pin to a potential of at least VIN + VGS(ON)(Q1)
.
Thispotentialcanbegeneratedusinganexternalsupplyor
charge pump.
PGND (Pin 3/Pin 3/Pin 3): Power Ground. Both drivers
return to this pin. Connect this pin to a low impedance
ground in close proximity to the source of Q2. Refer to the
Layout Consideration section for more details on PCB
layouttechniques.TheLTC3830-1andthe8-leadLTC3830
have PGND and GND tied together internally at Pin 3.
SS (Pin 9/NA/Pin 5): Soft-Start. Connect this pin to an
externalcapacitor, CSS, toimplementasoft-startfunction.
If the LTC3830 goes into current limit, CSS is discharged
to reduce the duty cycle. CSS must be selected such that
during power-up, the current through Q1 will not exceed
the current limit level. The soft-start function is disabled in
the 8-lead LTC3830.
GND (Pin 4/Pin 3/Pin 3): Signal Ground. All low power
internal circuitry returns to this pin. To minimize regula-
tion errors due to ground currents, connect GND to PGND
right at the LTC3830.
SENSE–, FB, SENSE+ (Pins 5, 6, 7/Pin 4/Pin 4): These
threepinsconnecttotheinternalresistordividerandinput
of the error amplifier. To use the internal divider to set the
output voltage to 3.3V, connect SENSE+ to the positive
terminal of the output capacitor and SENSE– to the nega-
tive terminal. FB should be left floating. To use an external
COMP (Pin 10/Pin 6/Pin 6): External Compensation. This
pin internally connects to the output of the error amplifier
and input of the PWM comparator. Use a RC + C network
at this pin to compensate the feedback loop to provide
optimum transient response.
3830fa
6
LTC3830/LTC3830-1
U
U
U
PI FU CTIO S
VCC (Pin 14/Pin 7/Pin 7): Power Supply Input. All low
power internal circuits draw their supply from this pin.
Connect this pin to a clean power supply, separate from
the main VIN supply at the drain of Q1. This pin requires a
4.7µF bypass capacitor. The LTC3830-1 and the 8-lead
LTC3830 have VCC and PVCC2 tied together at Pin 7 and
require a 10µF bypass capacitor to GND.
FREQSET (Pin 11/NA/NA): Frequency Set. Use this pin to
adjustthefree-runningfrequencyoftheinternaloscillator.
With the pin floating, the oscillator runs at about 200kHz.
A resistor from FREQSET to ground speeds up the oscil-
lator; a resistor to VCC slows it down.
IMAX (Pin 12/NA/NA): Current Limit Threshold Set. IMAX
sets the threshold for the internal current limit compara-
tor. If IFB drops below IMAX with G1 on, the LTC3830 goes
into current limit. IMAX has an internal 12µA pull-down to
GND. Connect this pin to the main VIN supply at the drain
of Q1, through an external resistor to set the current limit
threshold. Connect a 0.1µF decoupling capacitor across
this resistor to filter switching noise.
PVCC2 (Pin 15/Pin 7/Pin 7): Power Supply Input for G2.
Connect this pin to the main high power supply.
G2 (Pin 16/Pin 8/Pin 8): Bottom Gate Driver Output.
Connect this pin to the gate of the lower N-channel
MOSFET, Q2. This output swings from PGND to PVCC2. It
remains low when G1 is high or during shutdown mode.
Topreventoutputundershootduringasoft-startcycle, G2
is held low until G1 first goes high. (FFBG in Block
Diagram.)
IFB (Pin 13/NA/NA): Current Limit Sense. Connect this pin
to the switching node at the source of Q1 and the drain of
Q2 through a 1k resistor. The 1k resistor is required to
prevent voltage transients from damaging IFB.This pin is
used for sensing the voltage drop across the upper
N-channel MOSFET, Q1.
W
BLOCK DIAGRA
DISDR
LOGIC AND
THERMAL SHUTDOWN
SHDN
100ms DELAY
POWER DOWN
INTERNAL
OSCILLATOR
PV
G1
CC1
–
FREQSET
COMP
S
R
Q
Q
PWM
+
PV
CC2
12µA
FFBG
QSS
G2
SS
S
Q
ENABLE
G2
PGND
POR
R
ERR
MIN
MAX
+
+
+
–
–
–
FB
18k
V
REF
V
REF
– 3%
V
+ 3%
REF
+
–
SENSE
I
I
–
FB
CC
11.2k
SENSE
+
MAX
V
REF
V
REF
V
REF
– 3%
+ 3%
BG
12µA
3830 BD
2.2V
1.2V
QC
DISABLE
ILIM
+
–
PV
V
CC1
V
+ 2.5V
CC1
3830fa
7
LTC3830/LTC3830-1
TEST CIRCUITS
5V
PV
CC
V
V
V
+
SHDN
CC
CC
0.1µF
10µF
SHDN
PV
PV
I
I
V
PV
PV
CC1 CC2
CC2
CC1
FB
FB
CC
G1 RISE/FALL
NC
NC
NC
NC
FB
SS
FREQSET
COMP
G1
V
COMP
G1
G2
COMP
6800pF
6800pF
6800pF
LTC3830
LTC3830
GND
G2 RISE/FALL
I
G2
+
V
FB
I
MAX
FB
–
PGND
6800pF
MAX
GND
PGND SENSE
SENSE
3830 F03
3830 F02
Figure 2
Figure 3
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APPLICATIO S I FOR ATIO
OVERVIEW
THEORY OF OPERATION
The LTC3830 is a voltage mode feedback, synchronous
switching regulator controller (see Block Diagram) de-
signed for use in high power, low voltage step-down
(buck)converters.ItincludesanonboardPWMgenerator,
a precision reference trimmed to ±0.8%, two high power
MOSFET gate drivers and all necessary feedback and
control circuitry to form a complete switching regulator
circuit. The PWM loop nominally runs at 200kHz.
Primary Feedback Loop
The LTC3830/LTC3830-1 sense the output voltage of the
circuit at the output capacitor and feeds this voltage back
to the internal transconductance error amplifier, ERR,
through a resistor divider network. The error amplifier
compares the resistor-divided output voltage to the inter-
nal 1.265V reference and outputs an error signal to the
PWM comparator. This error signal is compared with a
fixed frequency ramp waveform, from the internal oscil-
lator, to generate a pulse width modulated signal. This
PWM signal drives the external MOSFETs through the G1
andG2pins.Theresultingchoppedwaveformisfilteredby
LO and COUT which closes the loop. Loop compensation is
achieved with an external compensation network at the
COMP pin, the output node of the error amplifier.
The 16-lead versions of the LTC3830 include a current
limitsensingcircuitthatusesthetopsideexternalN-channel
power MOSFET as a current sensing element, eliminating
the need for an external sense resistor.
Also included in the 16-lead version and the LTC3830-1
is an internal soft-start feature that requires only a single
external capacitor to operate. In addition, 16-lead parts
feature an adjustable oscillator that can free run or
synchronize to external signal with frequencies from
100kHz to 500kHz, allowing added flexibility in external
component selection. The 8-lead version does not in-
clude current limit, internal soft-start and frequency
adjustability. The LTC3830-1 does not include current
limit, frequency adjustability, external synchronization
and the shutdown function.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MIN
comparesthefeedbacksignaltoavoltage40mVbelowthe
internal reference. If the signal is below the comparator
threshold, the MIN comparator overrides the error ampli-
fier and forces the loop to maximum duty cycle, >91%.
3830fa
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Similarly, the MAX comparator forces the output to 0%
duty cycle if the feedback signal is greater than 40mV
above the internal reference. To prevent these two com-
parators from triggering due to noise, the MIN and MAX
comparators’ response times are deliberately delayed by
two to three microseconds. These two comparators help
prevent extreme output perturbations with fast output
load current transients, while allowing the main feedback
loop to be optimally compensated for stability.
the voltage at IFB to the voltage at the IMAX pin. As the peak
current rises, the measured voltage across Q1 increases
duetothedropacrosstheRDS(ON) ofQ1.Whenthevoltage
at IFB drops below IMAX, indicating that Q1’s drain current
has exceeded the maximum level, CC starts to pull current
outofCSS,cuttingthedutycycleandcontrollingtheoutput
current level. The CC comparator pulls current out of the
SS pin in proportion to the voltage difference between IFB
and IMAX. Under minor overload conditions, the SS pin
falls gradually, creating a time delay before current limit
takes effect. Very short, mild overloads may not affect the
output voltage at all. More significant overload conditions
allow the SS pin to reach a steady state, and the output
remains at a reduced voltage until the overload is re-
moved. Serious overloads generate a large overdrive at
CC, allowing it to pull SS down quickly and preventing
damage to the output components. By using the RDS(ON)
of Q1 to measure the output current, the current limiting
circuiteliminatesanexpensivediscretesenseresistorthat
would otherwise be required. This helps minimize the
number of components in the high current path.
Thermal Shutdown
The LTC3830/LTC3830-1 have a thermal protection cir-
cuit that disables both gate drivers if activated. If the chip
junction temperature reaches 150°C, both G1 and G2 are
pulled low. G1 and G2 remain low until the junction
temperature drops below 125°C, after which, the chip
resumes normal operation.
Soft-Start and Current Limit
The 16-lead LTC3830 devices include a soft-start circuit
that is used for start-up and current limit operation. The
LTC3830-1 only has the soft-start function; the current
limitfunctionisdisabled.The8-leadLTC3830hasboththe
soft-start and current limit function disabled. The SS pin
requires an external capacitor, CSS, to GND with the value
determined by the required soft-start time. An internal
12µA current source is included to charge CSS. During
power-up, the COMP pin is clamped to a diode drop (B-E
junction of QSS in the Block Diagram) above the voltage at
the SS pin. This prevents the error amplifier from forcing
thelooptomaximumdutycycle.TheLTC3830/LTC3830-1
operate at low duty cycle as the SS pin rises above 0.6V
(VCOMP ≈1.2V). AsSScontinuestorise, QSSturnsoffand
the error amplifier takes over to regulate the output. The
MIN comparator is disabled during soft-start to prevent it
from overriding the soft-start function.
The current limit threshold can be set by connecting an
external resistor RIMAX from the IMAX pin to the main VIN
supply at the drain of Q1. The value of RIMAX is determined
by:
RIMAX = (ILMAX)(RDS(ON)Q1)/IIMAX
where:
ILMAX = ILOAD + (IRIPPLE/2)
ILOAD = Maximum load current
IRIPPLE = Inductor ripple current
V – V
V
OUT
(
OUT)(
L
)
IN
=
f
V
( )(
)
OSC
O IN
fOSC = LTC3830 oscillator frequency = 200kHz
The 16-lead LTC3830 devices include yet another feed-
back loop to control operation in current limit. Just before
every falling edge of G1, the current comparator, CC,
samples and holds the voltage drop measured across the
external upper MOSFET, Q1, at the IFB pin. CC compares
LO = Inductor value
RDS(ON)Q1 = On-resistance of Q1 at ILMAX
IIMAX= Internal 12µA sink current at IMAX
3830fa
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APPLICATIO S I FOR ATIO
The RDS(ON) of Q1 usually increases with temperature. To
keep the current limit threshold constant, the internal
12µA sink current at IMAX is designed with a positive
temperature coefficient to provide first order correction
operation of the current limit circuit, PVCC1 must be at
least 2.5V above VCC when G1 is high. PVCC1 can go low
when G1 is low, allowing the use of an external charge
pump to power PVCC1
.
for the temperature coefficient of RDS(ON)Q1
.
Oscillator Frequency
Inorderforthecurrentlimitcircuittooperateproperlyand
toobtainareasonablyaccuratecurrentlimitthreshold,the
The LTC3830 includes an onboard current controlled
oscillator that typically free-runs at 200kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin floating, the oscillator runs
at about 200kHz. Every additional 1µA of current into/out
of the FREQSET pin decreases/increases the frequency by
10kHz. Thepinisinternallyservoedto1.265V, connecting
a 50k resistor from FREQSET to ground forces 25µA out
of the pin, causing the internal oscillator to run at approxi-
mately 450kHz. Forcing an external 10µA current into
FREQSET cuts the internal frequency to 100kHz. An inter-
nalclamppreventstheoscillatorfromrunningslowerthan
about 50kHz. Tying FREQSET to VCC forces the chip to run
at this minimum speed. The LTC3830-1 and the 8-lead
LTC3830 do not have this frequency adjustment function.
IIMAX and IFB pins must be Kelvin sensed at Q1’s drain and
source pins. In addition, connect a 0.1µF decoupling
capacitor across RIMAX to filter switching noise. Other-
wise, noise spikes or ringing at Q1’s source can cause the
actual current limit to be greater than the desired current
limit set point. Due to switching noise and variation of
RDS(ON), the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuitbeginstotakeeffectwillvaryfromunittounitasthe
RDS(ON) of Q1 varies. Typically, RDS(ON) varies as much as
±40% and with ±25% variation on the LTC3830’s IMAX
current, this can give a ±65% variation on the current limit
threshold.
Shutdown
The RDS(ON) is high if the VGS applied to the MOSFET is
low. This occurs during power up, when PVCC1 is ramping
up.TopreventthehighRDS(ON) fromactivatingthecurrent
limit, the LTC3830 disables the current limit circuit if
PVCC1 is less than 2.5V above VCC. To ensure proper
The LTC3830 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allowstheparttooperatenormally.AlowlevelatSHDNfor
more than 100µs forces the LTC3830 into shutdown
mode.Inthismode,allinternalswitchingstops,theCOMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3830 supply current drops to <10µA, although off-
state leakage in the external MOSFETs may cause the total
VIN current to be some what higher, especially at elevated
temperatures. If SHDN returns high, the LTC3830 reruns
a soft-start cycle and resumes normal operation. The
LTC3830-1 does not have this shutdown function.
V
IN
LTC3830
+
R
IMAX
0.1µF
C
IN
+
–
12
I
MAX
12µA
CC
G1
G2
Q1
I
FB
L
O
1k
V
13
OUT
+
Q2
C
OUT
3830 F04
Figure 4. Current Limit Setting
3830fa
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LTC3830/LTC3830-1
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APPLICATIO S I FOR ATIO
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External Clock Synchronization
2.5V converters. The low period of this clock signal must
not be >100µs, or else the LTC3830 enters shutdown
mode.
The LTC3830 SHDN pin doubles as an external clock input
for applications that require a synchronized clock. An
internal circuit forces the LTC3830 into external synchro-
nization mode if a negative transition at the SHDN pin is
detected. In this mode, every negative transition on the
SHDN pin resets the internal oscillator and pulls the ramp
signal low, this forces the LTC3830 internal oscillator to
lock to the external clock frequency. The LTC3830-1 does
not have this external synchronization function.
Figure 5 describes the operation of the external synchro-
nization function. A negative transition at the SHDN pin
forces the internal ramp signal low to restart a new PWM
cycle. Notice that with the traditional sync method, the
ramp amplitude is lowered as the external clock frequency
goes higher. The effect of this decrease in ramp amplitude
increases the open-loop gain of the controller feedback
loop. As a result, the loop crossover frequency increases
and it may cause the feedback loop to be unstable if the
phase margin is insufficient.
TheLTC3830internaloscillatorcanbeexternallysynchro-
nized from 100kHz to 500kHz. Frequencies above 300kHz
can cause a decrease in the maximum obtainable duty
cycle as rise/fall time and propagation delay take up a
larger percentage of the switch cycle. Circuits using these
frequencies should be checked carefully in applications
where operation near dropout is important—like 3.3V to
To overcome this problem, the LTC3830 monitors the
peak voltage of the ramp signal and adjusts the oscillator
charging current to maintain a constant ramp peak.
V
CC
PV
CC2
PV
CC1
V
IN
G1
G2
Q1
L
O
SHDN
INTERNAL
CIRCUITRY
V
OUT
+
C
Q2
OUT
200kHz
FREE RUNNING
RAMP SIGNAL
RAMP SIGNAL
WITH EXT SYNC
3830 F6
LTC3830 (16-LEAD)
TRADITIONAL
SYNC METHOD
WITH EARLY
RAMP
Figure 6. 16-Lead Power Supplies
TERMINATION
V /PV
CC CC2
PV
CC1
V
IN
G1
G2
RAMP AMPLITUDE
ADJUSTED
Q1
L
O
LTC3830
KEEPS RAMP
AMPLITUDE
CONSTANT
INTERNAL
CIRCUITRY
V
OUT
+
C
Q2
OUT
UNDER SYNC
3830 F7
LTC3830 (8-LEAD)
3830 F05
Figure 7. 8-Lead Power Supplies
Figure 5. External Synchronization Operation
3830fa
11
LTC3830/LTC3830-1
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APPLICATIO S I FOR ATIO
Input Supply Considerations/Charge Pump
needs to be above the power MOSFET VGS(ON) for efficient
operation. PVCC2 canalsobedrivenfromthesamesupply/
charge pump for the PVCC1, or it can be connected to a
lower supply to improve efficiency.
The 16-lead LTC3830 requires four supply voltages to
operate:VIN forthemainpowerinput,PVCC1 andPVCC2 for
MOSFET gate drive and a clean, low ripple VCC for the
LTC3830 internal circuitry (Figure 6). The LTC3830-1 and Figure 8 shows a tripling charge pump circuit that can be
the 8-lead LTC3830 have the PVCC2 and VCC pins tied used to provide 2VIN and 3VIN gate drive for the external
together inside the package (Figure 7). This pin, brought top and bottom MOSFETs respectively. These should fully
out as VCC/PVCC2 , has the same low ripple requirements enhance MOSFETs with 5V logic level thresholds. This
asthe16-leadpart,butmustalsobeabletosupplythegate circuit provides 3VIN – 3VF to PVCC1 while Q1 is ON and
drive current to Q2.
2VIN – 2VF to PVCC2 where VF is the forward voltage of the
Schottky diodes. The circuit requires the use of Schottky
diodes to minimize forward drop across the diodes at
start-up. The tripling charge pump circuit can rectify any
ringing at the drain of Q2 and provide more than 3VIN at
PVCC1; a 12V zener diode should be included from PVCC1
to PGND to prevent transients from damaging the circuitry
at PVCC1 or the gate of Q1.
In many applications, VCC can be powered from VIN
through an RC filter. This supply can be as low as 3V. The
low quiescent current (typically 800µA) allows the use of
relatively large filter resistors and correspondingly small
filter capacitors. 100Ω and 4.7µF usually provide ad-
equatefilteringforVCC. Forbestperformance, connectthe
4.7µFbypasscapacitorasclosetotheLTC3830VCC pinas
possible.
The charge pump capacitors refresh when the G2 pin goes
high and the switch node is pulled low by Q2. The G2 on-
time becomes narrow when LTC3830 operates at maxi-
mumdutycycle(95%typical), whichcanoccuriftheinput
supply rises more slowly than the soft-start capacitor or
the input voltage droops during load transients. If the G2
on-time gets so narrow that the switch node fails to pull
completely to ground, the charge pump voltage may
collapse or fail to start, causing excessive dissipation in
external MOSFET Q1. This is most likely with low VCC
voltages and high switching frequencies, coupled with
large external MOSFETs which slow the G2 and switch
node slew rates.
Gate drive for the top N-channel MOSFET Q1 is supplied
from PVCC1. This supply must be above VIN (the main
powersupplyinput)byatleastonepowerMOSFETVGS(ON)
forefficientoperation.AninternallevelshifterallowsPVCC1
to operate at voltages above VCC and VIN, up to 14V maxi-
mum. This higher voltage can be supplied with a separate
supply, or it can be generated using a charge pump.
Gate drive for the bottom MOSFET Q2 is provided through
PVCC2 for the 16-lead LTC3830 or VCC/PVCC2 for the
LTC3830-1 and the 8-lead LTC3830. This supply only
D
1N5817
Z
V
IN
12V
1N5242
1N5817
1N5817
0.1µF
10µF
PV
PV
CC1
CC2
0.1µF
G1
Q1
L
O
V
OUT
+
G2
Q2
C
OUT
3830 F08
LTC3830
Figure 8. Tripling Charge Pump
3830fa
12
LTC3830/LTC3830-1
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APPLICATIO S I FOR ATIO
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The LTC3830/LTC3830-1 overcomes this problem by
sensingthePVCC1 voltagewhenG1ishigh. IfPVCC1 isless
than (VCC + 2.5V), the maximum G1 duty cycle is reduced
to 70% by clamping the COMP pin at 1.8V (QC in BLOCK
DIAGRAM). This increases the G2 on time and allows the
charge pump capacitor to be refreshed.
an auxiliary 12V supply is available to power PVCC1 and
PVCC2, standard MOSFETs with RDS(ON) specified at VGS
= 5V or 6V can be used with good results. The current
drawn from this supply varies with the MOSFETs used
and the LTC3830’s operating frequency, but is generally
less than 50mA.
For Applications using an external supply to power PVCC1
,
LTC3830applicationsthatuse5VorlowerVIN voltageand
this supply must also be higher than VCC by at least 2.5V a doubling/tripling charge pump to generate PVCC1 and
to insure normal operation.
PVCC2, do not provide enough gate drive voltage to fully
enhance standard power MOSFETs. Under this condition,
the effective MOSFET RDS(ON) may be quite high, raising
the dissipation in the FETs and reducing efficiency. Logic
level FETs are the recommended choice for 5V or lower
voltage systems. Logic level FETs can be fully enhanced
with a doubler/tripling charge pump and will operate at
maximum efficiency.
For applications with a 5V or higher VIN supply, PVCC2 can
be tied to VIN if a logic level MOSFET is used. PVCC1 can be
suppliedusingadoublingchargepumpasshowninFigure
9. This circuit provides 2VIN – VF to PVCC1 while Q1 is ON.
Figure 12 shows a typical 5V to 3.3V application using a
doubling charge pump to generate PVCC1
.
Power MOSFETs
AftertheMOSFETthresholdvoltageisselected,choosethe
RDS(ON) based on the input voltage, the output voltage,
allowablepowerdissipationandmaximumoutputcurrent.
InatypicalLTC3830circuit,operatingincontinuousmode,
the average inductor current is equal to the output load
current.ThiscurrentflowsthrougheitherQ1orQ2withthe
power dissipation split up according to the duty cycle:
Two N-channel power MOSFETs are required for most
LTC3830 circuits. These should be selected based
primarilyonthresholdvoltageandon-resistanceconsid-
erations. Thermal dissipation is often a secondary con-
cern in high efficiency designs. The required MOSFET
threshold should be determined based on the available
power supply voltages and/or the complexity of the gate
drive charge pump scheme. In 3.3V input designs where
VOUT
V
IN
DC(Q1) =
V
IN
VOUT V – VOUT
IN
DC(Q2) = 1–
=
OPTIONAL
USE FOR V ≥ 7V
MBR0530T1
V
V
IN
IN
IN
D
Z
PV
PV
CC1
12V
CC2
The RDS(ON) required for a given conduction loss can now
be calculated by rearranging the relation P = I2R.
0.1µF
1N5242
G1
Q1
L
O
PMAX(Q1)
DC(Q1)•(ILOAD
PMAX(Q2)
V •PMAX(Q1)
IN
V
OUT
RDS(ON)Q1
RDS(ON)Q2
=
=
=
2
2
+
G2
)
VOUT •(ILOAD
)
Q2
C
OUT
V •PMAX(Q2)
IN
3830 F09
=
LTC3830
2
2
DC(Q2)•(ILOAD
)
(V – VOUT)•(ILOAD)
IN
Figure 9. Doubling Charge Pump
3830fa
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APPLICATIO S I FOR ATIO
PMAX should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed for 5V input and 3.3V at 10A
output might allow no more than 3% efficiency loss at full
load for each MOSFET. Assuming roughly 90% efficiency
at this current level, this gives a PMAX value of:
orInternationalRectifierIRF7413(bothinSO-8)orSiliconix
SUD50N03-10 (TO-252) or ON Semiconductor
MTD20N03HDL(DPAK)aresmallfootprintsurfacemount
devices with RDS(ON) values below 0.03Ω at 5V of VGS that
work well in LTC3830 circuits. Using a higher PMAX value
intheRDS(ON) calculationsgenerallydecreasestheMOSFET
cost and the circuit efficiency and increases the MOSFET
heat sink requirements.
(3.3V)(10A/0.9)(0.03) = 1.1W per FET
and a required RDS(ON) of:
Table 1 highlights a variety of power MOSFETs for use in
LTC3830 applications.
(5V)•(1.1W)
RDS(ON)Q1
RDS(ON)Q2
=
=
= 0.017Ω
(3.3V)(10A)2
Inductor Selection
(5V)•(1.1W)
(5V – 3.3V)(10A)2
= 0.032Ω
TheinductorisoftenthelargestcomponentinanLTC3830
design and must be chosen carefully. Choose the inductor
valueandtypebasedonoutputslewraterequirements.The
maximum rate of rise of inductor current is set by the
inductor’svalue,theinput-to-outputvoltagedifferentialand
the LTC3830’s maximum duty cycle. In a typical 5V input,
3.3V output application, the maximum rise time will be:
Note that the required RDS(ON) for Q2 is roughly twice that
of Q1 in this example. This application might specify a
single 0.03Ω device for Q2 and parallel two more of the
same devices to form Q1. Note also that while the required
RDS(ON) values suggest large MOSFETs, the power dissi-
pation numbers are only 1.1W per device or less; large
TO-220 packages and heat sinks are not necessarily
requiredinhighefficiencyapplications.SiliconixSi4410DY
DCMAX •(V – VOUT
)
1.615 A
LO µs
IN
=
LO
Table 1. Recommended MOSFETs for LTC3830 Applications
TYPICAL INPUT
CAPACITANCE
R
DS(ON)
PARTS
AT 25°C (mΩ)
RATED CURRENT (A)
C
(pF)
θ
JC
(°C/W)
T
(°C)
JMAX
ISS
Siliconix SUD50N03-10
TO-252
19
15 at 25°C
3200
2700
880
1.8
175
10 at 100°C
Siliconix Si4410DY
SO-8
20
35
8
10 at 25°C
8 at 70°C
150
150
150
150
150
175
175
150
ON Semiconductor MTD20N03HDL
DPAK
20 at 25°C
16 at 100°C
1.67
25
Fairchild FDS6670A
S0-8
13 at 25°C
3200
2070
4025
1600
3300
1750
Fairchild FDS6680
SO-8
10
9
11.5 at 25°C
25
ON Semiconductor MTB75N03HDL
DD PAK
75 at 25°C
59 at 100°C
1
IR IRL3103S
DD PAK
19
28
37
64 at 25°C
45 at 100°C
1.4
1
IR IRLZ44
TO-220
50 at 25°C
36 at 100°C
Fuji 2SK1388
TO-220
35 at 25°C
2.08
Note: Please refer to the manufacturer’s data sheet for testing conditions and detailed information.
3830fa
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Peak inductor current at 10A load:
10A + (2.8A/2) = 11.4A
where LO is the inductor value in µH. With proper fre-
quency compensation, the combination of the inductor
andoutputcapacitorvaluesdeterminethetransientrecov-
ery time. In general, a smaller value inductor improves
transient response at the expense of ripple and inductor
core saturation rating. A 2µH inductor has a 0.81A/µs rise
time in this application, resulting in a 6.2µs delay in
responding to a 5A load current step. During this 6.2µs,
thedifferencebetweentheinductorcurrentandtheoutput
current is made up by the output capacitor. This action
causes a temporary voltage droop at the output. To
minimize this effect, the inductor value should usually be
in the 1µH to 5µH range for most 5V input LTC3830
circuits. To optimize performance, different combinations
of input and output voltages and expected loads may
require different inductor values.
The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
undershort-circuitorfaultconditions;theinductorshould
be sized accordingly to withstand this additional current.
Inductorswithgradualsaturationcharacteristicsareoften
the best choice.
Input and Output Capacitors
A typical LTC3830 design places significant demands on
both the input and the output capacitors. During normal
steady load operation, a buck converter like the LTC3830
drawssquarewavesofcurrentfromtheinputsupplyatthe
switchingfrequency. Thepeakcurrentvalueisequaltothe
output load current plus 1/2 the peak-to-peak ripple cur-
rent. Most of this current is supplied by the input bypass
capacitor. The resulting RMS current flow in the input
capacitor heats it and causes premature capacitor failure
in extreme cases. Maximum RMS current occurs with
50% PWM duty cycle, giving an RMS current value equal
to IOUT/2. A low ESR input capacitor with an adequate
ripple current rating must be used to ensure reliable
operation. Note that capacitor manufacturers’ ripple cur-
rentratingsareoftenbasedononly2000hours(3months)
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer’s speci-
fication is recommended to extend the useful life of the
circuit. Loweroperatingtemperaturehasthelargesteffect
on capacitor longevity.
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-to-
peak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:
(V − VOUT)•(VOUT
)
IN
IRIPPLE
=
fOSC •LO • V
IN
fOSC = LTC3830 oscillator frequency = 200kHz
LO = Inductor value
Solving this equation with our typical 5V to 3.3V applica-
tion with a 2µH inductor, we get:
(5V – 3.3V)• 3.3V
= 2.8AP-P
200kHz • 2µH • 5V
3830fa
15
LTC3830/LTC3830-1
W U U
U
APPLICATIO S I FOR ATIO
The output capacitor in a buck converter under steady-
state conditions sees much less ripple current than the
input capacitor. Peak-to-peak current is equal to inductor
ripple current, usually 10% to 40% of the total load
current. Output capacitor duty places a premium not on
power dissipation but on ESR. During an output load
transient, the output capacitor must supply all of the
additional load current demanded by the load until the
LTC3830 adjusts the inductor current to the new value.
ESR in the output capacitor results in a step in the output
voltage equal to the ESR value multiplied by the change in
load current. An 5A load step with a 0.05Ω ESR output
capacitor results in a 250mV output voltage shift; this is
7.6% of the output voltage for a 3.3V supply! Because of
the strong relationship between output capacitor ESR and
output load transient response, choose the output capaci-
tor for ESR, not for capacitance value. A capacitor with
suitable ESR will usually have a larger capacitance value
than is needed to control steady-state output ripple.
a maximum rated ESR of 0.04Ω; three in parallel lower
the net output capacitor ESR to 0.013Ω.
Feedback Loop Compensation
TheLTC3830voltagefeedbackloopiscompensatedatthe
COMP pin, which is the output node of the error amplifier.
The feedback loop is generally compensated with an RC +
C network from COMP to GND as shown in Figure 10a.
Loop stability is affected by the values of the inductor, the
output capacitor, the output capacitor ESR, the error
amplifier transconductance and the error amplifier com-
pensation network. The inductor and the output capacitor
create a double pole at the frequency:
fLC = 1/ 2π (LO)(COUT
)
The ESR of the output capacitor and the output capacitor
value form a zero at the frequency:
fESR = 1/ 2π(ESR)(C
)
[
]
OUT
Electrolytic capacitors rated for use in switching power
supplies with specified ripple current ratings and ESR can
be used effectively in LTC3830 applications. OS-CON
electrolytic capacitors from Sanyo and other manufactur-
ers give excellent performance and have a very high
performance/size ratio for electrolytic capacitors. Surface
mount applications can use either electrolytic or dry
tantalum capacitors. Tantalum capacitors must be surge
tested and specified for use in switching power supplies.
Low cost, generic tantalums are known to have very short
lives followed by explosive deaths in switching power
supply applications. Other capacitors that can be used
include the Sanyo POSCAP and MV-WX series.
The compensation network used with the error amplifier
must provide enough phase margin at the 0dB crossover
frequency for the overall open-loop transfer function. The
zero and pole from the compensation network are:
fZ = 1/[2π(RC)(CC)] and
fP = 1/[2π(RC)(C1)] respectively
+
SENSE
7
C2
LTC3830
R2
V
FB
–
+
6
COMP
10
A common way to lower ESR and raise ripple current
capability is to parallel several capacitors. A typical
LTC3830 application might exhibit 5A input ripple cur-
rent.SanyoOS-CONcapacitors,partnumber10SA220M
(220µF/10V), feature 2.3A allowable ripple current at
85°C; three in parallel at the input (to withstand the input
ripple current) meet the above requirements. Similarly,
Sanyo POSCAP 4TPB470M (470µF/4V) capacitors have
ERR
R1
–
SENSE
5
R
C
V
REF
C1
C
C
3830 F10a
Figure 10a. Compensation Pin Hook-Up
3830fa
16
LTC3830/LTC3830-1
W U U
APPLICATIO S I FOR ATIO
U
Figure 10b shows the Bode plot of the overall transfer
Although a mathematical approach to frequency compen-
sationcanbeused, theaddedcomplicationofinputand/or
output filters, unknown capacitor ESR, and gross operat-
ing point changes with input voltage, load current varia-
tions, all suggest a more practical empirical method. This
can be done by injecting a transient current at the load and
using an RC network box to iterate toward the final values,
or by obtaining the optimum loop response using a
network analyzer to find the actual loop poles and zeros.
function.
When low ESR output capacitors (Sanyo OS-CON) are
used, the ESR zero can be high enough in frequency that
it provides little phase boost at the loop crossover fre-
quency. As a result, the phase margin becomes inad-
equate and the load transient is not optimized. To resolve
this problem, a small capacitor can be connected between
the top of the resistor divider network and the VFB pin to
create a pole-zero pair in the loop compensation. The zero
location is prior to the pole location and thus, phase lead
can be added to boost the phase margin at the loop
crossover frequency. The pole and zero locations are
located at:
Table 2 shows the suggested compensation component
value for 5V to 3.3V applications based on Sanyo OS-CON
4SP820M low ESR output capacitors.
Table 2. Recommended Compensation Network for 5V to 3.3V
Applications Using Multiple Paralleled 820µF Sanyo OS-CON
4SP820M Output Capacitors
fZC2 = 1/[2π(R2)(C2)] and
fPC2 = 1/[2π(R1||R2)(C2)]
L1 (µH)
1.2
C
OUT
(µF)
R (kΩ)
C (nF)
C1 (pF)
470
470
220
330
220
220
330
180
180
C2 (pF)
1000
1000
1000
1000
1000
1000
1000
1000
1000
C
C
1640
6.2
12
12
15
20
36
30
36
82
3.3
3.3
1.8
2.7
1.0
1.0
1.8
1.0
1.0
1.2
2460
4100
1640
2460
4100
1640
2460
4100
whereR1||R2istheparallelcombinationresistanceofR1
and R2. Choose C2 so that the zero is located at a lower
frequency compared to fCO and the pole location is high
enoughthattheclosedloophasenoughphasemarginfor
stability. Figure 10c shows the Bode plot using phase
lead compensation around the LTC3830 resistor divider
network. Note: This technique is effective only when
R1 >> R2 i.e., at high output voltages only so that the pole
and zero are sufficiently separated.
1.2
2.4
2.4
2.4
4.7
4.7
4.7
f
f
= LTC3830 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
f
f
= LTC3830 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
SW
SW
f
Z
CO
CO
f
Z
20dB/DECADE
20dB/DECADE
f
CO
f
f
f
PC2
P
P
FREQUENCY
FREQUENCY
f
f
f
f
ZC2
LC
ESR
LC
f
CO
f
ESR
3830 F10b
3830 F10c
Figure 10b. Bode Plot of the LTC3830 Overall Transfer Function
Figure 10c. Bode Plot of the LTC3830 Overall
Transfer Function Using a Low ESR Output Capacitor
3830fa
17
LTC3830/LTC3830-1
W U U
U
APPLICATIO S I FOR ATIO
Table 3 shows the suggested compensation component
values for 5V to 3.3V applications based on 470µF Sanyo
POSCAP 4TPB470M output capacitors.
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the LTC3830.
These items are also illustrated graphically in the layout
diagram of Figure 11. The thicker lines show the high
current paths. Note that at 10A current levels or above,
current density in the PC board itself is a serious concern.
Traces carrying high current should be as wide as pos-
sible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15" to carry 10A.
Table 3. Recommended Compensation Network for 5V to 3.3V
Applications Using Multiple Paralleled 470µF Sanyo POSCAP
4TPB470M Output Capacitors
L1 (µH)
1.2
C
(µF)
R (kΩ)
C (nF)
C1 (pF)
33
OUT
C
C
1410
6.8
15
22
18
43
62
43
91
150
4.7
2.2
2.2
10
1.2
2820
4700
1410
2820
4700
1410
2820
4700
33
1.2
33
2.4
33
2.4
2.2
2.2
10
33
1. In general, layout should begin with the location of the
powerdevices. Besuretoorientthepowercircuitrysothat
a clean power flow path is achieved. Conductor widths
shouldbemaximizedandlengthsminimized. Afteryouare
satisfied with the power path, the control circuitry should
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
2.4
10
4.7
10
4.7
33
10
4.7
10
10
Table 4 shows the suggested compensation component
valuesfor5Vto3.3Vapplicationsbasedon1500µFSanyo
MV-WX output capacitors.
2. The GND and PGND pins should be shorted directly at
the LTC3830. This helps to minimize internal ground dis-
turbancesintheLTC3830andpreventdifferencesinground
potential from disrupting internal circuit operation. This
connectionshouldthentieintothegroundplaneatasingle
point, preferably at a fairly quiet point in the circuit such as
close to the output capacitors. This is not always practical,
however, due to physical constraints. Another reasonably
good point to make this connection is between the output
capacitors and the source connection of the bottom
MOSFETQ2. Donottiethissinglepointgroundinthetrace
runbetweentheQ2sourceandtheinputcapacitorground,
as this area of the ground plane will be very noisy.
Table 4. Recommended Compensation Network for 5V to 3.3V
Applications Using Multiple Paralleled 1500µF Sanyo MV-WX
Output Capacitors
L1 (µH)
1.2
C
(µF)
R (kΩ)
C (nF)
C1 (pF)
120
82
OUT
C
C
4500
22
30
1.5
1
1.2
6000
9000
4500
6000
9000
4500
6000
9000
1.2
39
0.47
1
56
2.4
51
56
2.4
62
1
33
2.4
82
0.47
3.3
0.47
0.47
27
4.7
100
150
200
15
4.7
15
4.7
15
3830fa
18
LTC3830/LTC3830-1
W U U
APPLICATIO S I FOR ATIO
U
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
5. The (+) plate of CIN should be connected as close as
possible to the drain of the upper MOSFET, Q1. An addi-
tional1µFceramiccapacitorbetweenVINandpowerground
is recommended.
6.TheSENSEandVFBpinsareverysensitivetopickupfrom
the switching node. Care should be taken to isolate SENSE
and VFB from possible capacitive coupling to the inductor
switchingsignal.ConnectingtheSENSE+andSENSE–close
to the load can significantly improve load regulation.
4.TheVCC,PVCC1 andPVCC2 decouplingcapacitorsshould
be as close to the LTC3830 as possible. The 4.7µF and 1µF
bypasscapacitorsshownatVCC,PVCC1 andPVCC2 willhelp
provide optimum regulation performance.
7. Kelvin sense IMAX and IFB at Q1’s drain and source pins.
PV
CC
V
IN
100Ω
+
+
1µF
C
IN
4.7µF
V
PV
CC
CC2
0.1µF
1µF
PV
PGND
CC1
Q1A
Q1B
G1
LTC3830
GND
I
MAX
L
O
1k
FREQSET
SHDN
COMP
SS
I
V
OUT
NC
FB
+
SENSE
Q2
G2
NC
FB
–
C1
R
+
C
SENSE
OUT
C
GND
PGND
PGND
C
C
C
SS
GND
3830 F11
Figure 11. Typical Schematic Showing Layout Considerations
3830fa
19
LTC3830/LTC3830-1
W U U
U
APPLICATIO S I FOR ATIO
5V
100
90
80
70
60
50
40
3.0
2.5
2.0
1.5
1.0
0.5
0
+
C
IN
MBR0530T1
330µF
×2
+
100Ω 1µF
0.1µF
5k
PV
CC2
PV
Q1
CC1
G1
0.1µF
0.1µF
V
+
CC
L
4.7µF
O
SS
I
MAX
2.5µH
1k
0.01µF
3.3V
10A
I
LTC3830
FB
+
C
OUT
NC
Q2
FREQSET
SHDN
G2
PGND
GND
470µF
×3
SHUTDOWN
V
IN
V
OUT
= 5V
COMP
C1
33pF
= 3.3V
R
+
C
SENSE
18k
0
2
4
6
8
10 12
C
C
: SANYO 6TPB330M
FB
–
IN
C
C
LOAD CURRENT (A)
SENSE
: SANYO 4TPB470M
OUT
0.01µF
3830 F012
L : SUMIDA CDEP105-2R5
O
Q1, Q2: VISHAY Si7892DP
Figure 12. 5V to 3.3V, 10A Application
3830fa
20
LTC3830/LTC3830-1
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3830fa
21
LTC3830/LTC3830-1
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 ±.005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
3830fa
22
LTC3830/LTC3830-1
U
PACKAGE DESCRIPTIO
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.386 – .394
(9.804 – 10.008)
.045 ±.005
NOTE 3
.050 BSC
N
16
N
15
14
13
12
11
10
9
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
2
3
N/2
N/2
8
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0° – 8° TYP
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
.016 – .050
(0.406 – 1.270)
S16 0502
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
3830fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
23
LTC3830/LTC3830-1
U
TYPICAL APPLICATIO
Typical 3.3V to 2.5V, 14A Application
12V
3.3V
+
+
C
IN
330µF
×2
0.1µF
10µF
6.8k
100Ω
PV
PV
CC2
CC1
G1
Q1
V
CC
0.1µF
L
4.7µF
O
SS
I
MAX
1.3µH
1k
2.5V
14A
0.01µF
I
LTC3830
FB
C
OUT
Q2
D1
FREQSET
SHDN
G2
PGND
GND
470µF
×3
16.5k
1%
130k
SHDN
COMP
C1
33pF
16.9k
1%
R
+
C
SENSE
NC
18k
C
C
: SANYO POSCAP 6TPB330M
IN
FB
–
: SANYO POSCAP 4TPB470M
C
OUT
C
SENSE
NC
D1: MBRS330T3
1500pF
L : SUMIDA CDEP105-1R3
O
3830 TA01
Q1, Q2: VISHAY Si7892DP
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1530
High Power Synchronous Switching Regulator Controller
SO-8 with Current Limit. No R
TM Required
SENSE
LTC1628/LTC3728 Dual High Efficiency 2-Phase Synchronous Step-Down Controller Constant Frequency, Standby 5V and 3.3V LDOs,
3.5V ≤ V ≤ 36V
IN
LTC1702
LTC1709
LTC1736
LTC1773
Dual High Efficiency 2-Phase Synchronous Step-Down Controller 550kHz, 25MHz GBW Voltage Mode, V ≤ 7V, No R
IN SENSE
2-Phase, 5-Bit Desktop VID Synchronous Step-Down Controller
Current Mode, V to 36V, I
Up to 42A
OUT
IN
Synchronous Step-Down Controller with 5-Bit Mobile VID Control Fault Protection, Power Good, 3.5V to 36V Input, Current Mode
Synchronous Step-Down Controller in MS10
Up to 95% Efficiency, 550kHz, 2.65V ≤ V ≤ 8.5V,
IN
0.8V ≤ V
≤ V , Synchronizable to 750kHz
OUT
IN
LTC1778
LTC1873
LTC1876
Wide Operating Range/Step-Down Controller, No R
V Up to 36V, Current Mode, Power Good
IN
SENSE
Dual Synchronous Switching Regulator with 5-Bit Desktop VID
1.3V to 3.5V Programmable Core Output Plus I/O Output
2-Phase, Dual Step-Down Synchronous Controller with
Integrated Step-Up DC/DC Regulator
Step-Down DC/DC Conversion from 3V , Minimum C and
IN
IN
C
, Uses Logic-Level N-Channel MOSFETs
OUT
LTC1929/LTC3729 2-Phase, Synchronous High Efficiency Converter
with Mobile VID
Current Mode Ensures Accurate Current Sensing V Up to 36V,
IN
I
Up to 40A
OUT
LTC3713
LTC3770
LTC3831
LTC3832
Low Input Voltage, High Power, No R
Synchronous Controller
, Step-Down
Minimum V : 1.5V, Uses Standard Logic-Level N-Channel
MOSFETs
SENSE
IN
Fast DC/DC Step-Down Synchronous Controller with Margining,
Tracking and PLL
4V ≤ V ≤ 32V, 0.6V ≤ V
≤ 28V, Powerful Gate Drivers
OUT
IN
High Power Synchronous Switching Regulator Controller for
DDR Memory Termination
V
Tracks 1/2 of V or External Reference
OUT
IN
Synchronous Step-Down Controller
0.6V ≤ V
≤ 5V, Pin-for-Pin Compatible with the LTC3830
OUT
No R
is a trademark of Linear Technology Corporation.
SENSE
3830fa
LT/LT 0305 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2001
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