LTC3831EGN#TR [Linear]
LTC3831 - High Power Synchronous Switching Regulator Controller for DDR Memory Termination; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC3831EGN#TR |
| 厂家： | 
Linear |
| 描述： | LTC3831 - High Power Synchronous Switching Regulator Controller for DDR Memory Termination; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 双倍数据速率 开关 光电二极管 |
| 文件： | 总20页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3831
High Power Synchronous
Switching Regulator Controller
for DDR Memory Termination
U
FEATURES
DESCRIPTIO
The LTC®3831 is a high power, high efficiency switching
regulator controller designed for DDR memory termina-
tion. The LTC3831 generates an output voltage equal to
1/2ofanexternalsupplyorreferencevoltage.TheLTC3831
uses a synchronous switching architecture with N-chan-
nel MOSFETs. Additionally, the chip senses output cur-
rent through the drain-source resistance of the upper
N-channel FET, providing an adjustable current limit
without a current sense resistor.
■
High Power Switching Regulator Controller
for DDR Memory Termination
■
VOUT Tracks 1/2 of VIN or External VREF
■
No Current Sense Resistor Required
■
Low Input Supply Voltage Range: 3V to 8V
■
Maximum Duty Cycle >91% Over Temperature
■
Drives All N-Channel External MOSFETs
■
High Efficiency: Over 95% Possible
■
Programmable Fixed Frequency Operation:
100kHz to 500kHz
The LTC3831 operates with input supply voltage as low as
3V and with a maximum duty cycle of >91%. It includes a
fixed frequency PWM oscillator for low output ripple
operation. The 200kHz free-running clock frequency can
be externally adjusted or synchronized with an external
signal from 100kHz to above 500kHz. In shutdown mode,
the LTC3831 supply current drops to <10µA.
■
External Clock Synchronization Operation
■
Programmable Soft-Start
■
Low Shutdown Current: <10µA
■
Overtemperature Protection
■
Available in 16-PUin Narrow SSOP Package
APPLICATIO S
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
DDR SDRAM Termination
SSTL_2 Interface
SSTL_3 Interface
■
■
U
TYPICAL APPLICATIO
V
DDQ
5V
2.5V
Efficiency vs Load Current
100
+
C
IN
MBR0530T1
330µF
×2
90
80
70
60
50
40
30
20
10
0
0.1µF
1µF
PV
CC2
PV
CC1
Q1
MBRS340T3
10k
V
TG
CC
0.1µF
L
O
0.1µF
SS
I
MAX
1.2µH
V
1k
TT
0.01µF
130k
+
1.25V
LTC3831
I
FB
4.7µF
±6A
Q2
MBRS340T3
FREQSET
SHDN
BG
PGND
GND
+
C
OUT
470µF
×3
SHDN
T
V
V
= 25°C
A
COMP
= 2.5V
C
: SANYO POSCAP 6TPB330M
C : SANYO POSCAP 4TPB470M
OUT
Q1, Q2: SILICONIX Si4410DY
IN
IN
C1
33pF
= 1.25V
R
+
OUT
C
R
15k
3831 F01
FB
C
0
1
3
4
5
6
2
C
–
R
1500pF
LOAD CURRENT (A)
2831 G01
Figure 1. Typical DDR Memory Termination Application
3831f
1
LTC3831
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage
ORDER PART
TOP VIEW
V
CC ....................................................................... 9V
NUMBER
TG
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BG
PV
V
PVCC1,2 ................................................................ 14V
Input Voltage
PV
CC1
CC2
LTC3831EGN
PGND
GND
CC
IFB, IMAX ............................................... –0.3V to 14V
R+, R–, FB, SHDN, FREQSET ..... –0.3V to VCC + 0.3V
Junction Temperature (Note 9)............................. 125°C
Operating Temperature Range (Note 4) .. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
I
I
FB
MAX
–
R
FB
FREQSET
COMP
SS
GN PART MARKING
3831
+
R
SHDN
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, VR+ = 2.5V, VR– = GND, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
3
TYP
MAX
8
UNITS
V
Supply Voltage
●
●
5
V
V
V
V
CC
PV
PV , PV Voltage
CC1 CC2
(Note 7)
3
13.2
2.9
CC
UVLO
FB
V
V
Undervoltage Lockout Voltage
Feedback Voltage
2.4
V + = 2.5V, V – = 0V, V
R
= 1.25V
●
1.231
1.25
1.269
R
COMP
∆V
Output Load Regulation
Output Line Regulation
I
V
= 0A to 10A (Note 6)
= 4.75V to 5.25V
2
0.1
mV
mV
OUT
OUT
CC
I
I
Supply Current
Figure 2, V
= V
CC
●
●
0.7
1
1.6
10
mA
µA
VCC
SHDN
V
= 0V
SHDN
PV Supply Current
CC
Figure 2, V
= 0V
= V (Note 3)
●
●
14
0.1
20
10
mA
µA
PVCC
SHDN
CC
V
SHDN
∆f
Internal Oscillator Frequency
FREQSET Floating
●
160
200
1.2
2.2
2.85
10
240
kHz
V
OSC
V
V
V
V
V
at Minimum Duty Cycle
at Maximum Duty Cycle
SAWL
COMP
COMP
V
SAWH
Maximum V
V
= 0V, PV = 8V
CC1
V
COMPMAX
COMP
FB
∆f /∆I
Frequency Adjustment
kHz/µA
dB
OSC FREQSET
A
Error Amplifier Open-Loop DC Gain
Error Amplifier Transconductance
Error Amplifier Output Sink/Source Current
●
●
46
55
V
g
520
650
100
780
µmho
µA
m
I
I
COMP
MAX
I
Sink Current
V
V
= V
CC
9
4
12
12
15
20
µA
µA
MAX
IMAX
IMAX
●
I
Sink Current Tempco
= V (Note 6)
3300
ppm/°C
MAX
CC
3831f
2
LTC3831
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, VR+ = 2.5V, VR– = GND, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
Soft-Start Source Current
●
●
●
●
2.4
IH
IL
0.8
1
V
I
I
I
V
V
V
= V
CC
0.1
–12
1.6
µA
IN
SHDN
= 0V, V
= 0V, V = V
CC
–8
–16
µA
SS
SS
IMAX
IFB
Maximum Soft-Start Sink Current
Undercurrent Limit
= V , V = 0V, V = V (Note 8),
mA
SSIL
IMAX
CC IFB
SS
CC
PV
CC1
= 8V
+
+
R
R Input Resistance
49.5
80
kΩ
ns
ns
%
t , t
Driver Rise/Fall Time
Figure 2, PV
Figure 2, PV
= PV
= PV
= 5V (Note 5)
= 5V (Note 5)
●
●
●
250
250
r
f
CC1
CC2
CC2
t
Driver Nonoverlap Time
Maximum TG Duty Cycle
25
91
120
95
NOV
CC1
DC
Figure 2, V = 0V (Note 5), PV
= 8V
MAX
FB
CC1
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: Rise and fall times are measured using 10% and 90% levels. Duty
cycle and nonoverlap times are measured using 50% levels.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC3831 operating frequency, operating voltage and the external FETs
used.
Note 6: Guaranteed by design, not subject to test.
Note 7: PV
must be higher than V by at least 2.5V for TG to operate
CC1
CC
at 95% maximum duty cycle and for the current limit protection circuit to
be active.
Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be
zero.
Note 4: The LTC3831EGN is guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note9:ThisICincludesovertemperatureprotectionthatisintendedtoprotect
the device during momentary overload conditions. Junction temperature will
exceed 125°C when overtemperature protection is active. Continuous opera-
tionabovethespecifiedmaximumoperatingjunctiontemperaturemayimpair
device reliability.
3831f
3
LTC3831
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Error Amplifier Transconductance
vs Temperature
Load Regulation
Line Regulation
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.260
1.258
1.256
1.254
1.252
1.250
1.248
1.246
1.244
1.242
1.240
10
8
800
750
700
650
T
= 25°C
T
= 25°C
A
A
REFER TO FIGURE 1
NEGATIVE OUTPUT CURRENT
INDICATES CURRENT SINKING
6
4
2
0
–2
–4
–6
–8
–10
600
550
500
–4
–2
2
4
6
4
6
50
TEMPERATURE (˚C)
100 125
–6
0
3
5
7
8
–50 –25
0
25
75
OUTPUT CURRENT (A)
SUPPLY VOLTAGE (V)
3831 G02
3831 G03
3831 G05
Error Amplifier Sink/Source
Current vs Temperature
Error Amplifier Open-Loop Gain
vs Temperature
Output Temperature Drift
60
55
50
45
200
180
160
140
120
100
80
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
20
15
10
5
REFER TO FIGURE 1
OUTPUT = NO LOAD
0
–5
–10
–15
–20
60
40
40
–50 –25
0
25
50
75 100 125
–25
0
50
75 100 125
–50
25
–25
0
50
75
100
–50
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3831 G07
3831 G06
3831 G04
Oscillator Frequency
vs Temperature
Oscillator Frequency
Oscillator (VSAWH – VSAWL
)
vs FREQSET Input Current
vs External Sync Frequency
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
600
500
400
300
200
100
0
250
240
230
220
210
200
190
180
170
T
A
= 25°C
FREQSET FLOATING
T = 25°C
A
160
100
200
300
400
500
–40
–20
–10
0
10
20
–30
–50 –25
0
25
125
50
75 100
EXTERNAL SYNC FREQUENCY (kHz)
FREQSET INPUT CURRENT (µA)
TEMPERATURE (°C)
3831 G10
3831 G09
3831 G08
3831f
4
LTC3831
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum TG Duty Cycle
vs Temperature
IMAX Sink Current
vs Temperature
Output Overcurrent Protection
100
99
98
97
96
95
94
93
92
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
20
18
16
14
12
10
8
V
FB
= 0V
REFER TO FIGURE 3
6
T
= 25°C
A
REFER TO FIGURE 1
91
4
–50 –25
0
25
125
–50 –25
0
25
50
75 100 125
0
2
4
6
8
10
50
75 100
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT (A)
3831 G11
3831 G12
3831 G13
Output Current Limit Threshold
vs Temperature
Soft-Start Source Current
vs Temperature
Soft-Start Sink Current
vs (VIFB – VIMAX
)
10
9
8
7
6
5
4
3
2
1
0
–8
–9
2.00
1.75
1.50
1.25
REFER TO FIGURE 1
T
= 25°C
A
–10
–11
–12
–13
–14
–15
–16
1.00
0.75
0.50
0.25
0
–50
0
25
50
75 100 125
–25
–25
0
50
75 100 125
–125 –100
–50
–50
25
–150
–25
0
–75
– V
TEMPERATURE (°C)
TEMPERATURE (°C)
V
IFB
(mV)
IMAX
3831 G14
3831 G15
3831 G16
Undervoltage Lockout Threshold
Voltage vs Temperature
VCC Operating Supply Current
vs Temperature
PVCC Supply Current
vs Oscillator Frequency
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
90
80
70
60
50
40
30
20
10
T
= 25°C
FREQSET FLOATING
A
TG AND BG LOADED
WITH 6800pF,
PV
= 12V
CC1,2
TG AND BG
LOADED
TG AND BG
LOADED
WITH 6800pF,
PV
WITH 1000pF,
= 5V
CC1,2
PV
= 5V
CC1,2
0
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
125
–50
0
25
75 100
–25
0
400
500
100
200
300
TEMPERATURE (°C)
OSCILLATOR FREQUENCY (kHz)
3831 G17
3831 G18
3831 G19
3831f
5
LTC3831
TYPICAL PERFOR A CE CHARACTERISTICS
U W
PVCC Supply Current
vs Gate Capacitance
TG Rise/Fall Time
vs Gate Capacitance
Transient Response
50
40
30
200
180
160
140
120
100
80
T
A
= 25°C
T
= 25°C
A
VOUT
50mV/DIV
PV
= 12V
CC1,2
t AT PV
= 5V
CC1,2
f
ILOAD
2A/DIV
t AT PV
r
= 5V
CC1,2
20
10
0
PV
= 5V
CC1,2
60
40
50µs/DIV
3831 G22.tif
t AT PV
f
= 12V
CC1,2
20
t AT PV
r
= 12V
CC1,2
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
GATE CAPACITANCE AT TG AND BG (nF)
GATE CAPACITANCE AT TG AND BG (nF)
3831 G20
3831 G21
U
U
U
PI FU CTIO S
TG ( Pin 1): Top Driver Output. Connect this pin to the gate
of the upper N-channel MOSFET, Q1. This output swings
from PGND to PVCC1. It remains low if BG is high or during
shutdown mode.
referenceunderclosed-loopconditions.TheLTC3831can
operate with a minimum VFB of 1.1V and maximum VFB of
(VCC – 1.75V).
SHDN (Pin 8): Shutdown. A TTL compatible low level at
SHDN for longer than 100µs puts the LTC3831 into
shutdown mode. In shutdown, TG and BG go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allowstheparttooperatenormally.Thispinalsodoubleas
an external clock input to synchronize the internal oscilla-
tor with an external clock.
PVCC1 (Pin2):PowerSupplyInputforTG.Connectthispin
to a potential of at least VIN + VGS(ON)(Q1). This potential
can be generated using an external supply or a simple
charge pump connected to the switching node between
the upper MOSFET and the lower MOSFET.
PGND (Pin 3): Power Ground. Both drivers return to this
pin. Connect this pin to a low impedance ground in close
proximity to the source of Q2. Refer to the Layout Consid-
eration section for more details on PCB layout techniques.
SS (Pin 9): Soft-Start. Connect this pin to an external
capacitor, CSS, to implement a soft-start function. If the
LTC3831 goes into current limit, CSS is discharged to
reduce the duty cycle. CSS must be selected such that
during power-up, the current through Q1 will not exceed
the current limit level.
GND (Pin 4): Signal Ground. All low power internal cir-
cuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at the
LTC3831.
COMP (Pin 10): External Compensation. This pin inter-
nallyconnectstotheoutputoftheerroramplifierandinput
of the PWM comparator. Use a RC + C network at this pin
to compensate the feedback loop to provide optimum
transient response.
R–, R+ (Pins 5, 7): These two pins connect to the internal
resistor divider that generate the internal ratiometric ref-
erence for the error amplifier. The reference voltage is set
at 0.5 • (VR+ – VR–).
FB (Pin 6): Feedback Voltage. FB senses the regulated
output voltage either directly or through an external resis-
tor divider. The FB pin is servoed to the ratiometric
3831f
6
LTC3831
U
U
U
PI FU CTIO S
FREQSET (Pin 11): Frequency Set. Use this pin to adjust
the free-running frequency of the internal oscillator. With
the pin floating, the oscillator runs at about 200kHz. A
resistorfromFREQSETtogroundspeedsuptheoscillator;
a resistor to VCC slows it down.
voltage transients from damaging IFB.This pin is used for
sensing the voltage drop across the upper N-channel
MOSFET, Q1.
V
CC (Pin 14): Power Supply Input. All low power internal
circuits draw their supply from this pin. This pin requires
IMAX (Pin 12): Current Limit Threshold Set. IMAX sets the
a 4.7µF bypass capacitor to GND.
threshold for the internal current limit comparator. If IFB
drops below IMAX with TG on, the LTC3831 goes into
current limit. IMAX has an internal 12µA pull-down to GND.
Connect this pin to the main VIN supply at the drain of Q1,
through an external resistor to set the current limit thresh-
old. Connect a 0.1µF decoupling capacitor across this
resistor to filter switching noise.
PVCC2 (Pin 15): Power Supply Input for BG. Connect this
pin to the main high power supply.
BG(Pin16):BottomDriverOutput. Connectthispintothe
gate of the lower N-channel MOSFET, Q2. This output
swings from PGND to PVCC2. It remains low when TG is
high or during shutdown mode. To prevent output under-
shoot during a soft-start cycle, BG is held low until TG first
goes high (FFBG in the Block Diagram).
IFB (Pin 13): Current Limit Sense. Connect this pin to the
switching node at the source of Q1 and the drain of Q2
througha1kresistor.The1kresistorisrequiredtoprevent
W
BLOCK DIAGRA
DISABLE GATE DRIVE
LOGIC AND
THERMAL SHUTDOWN
V
SHDN
100µs DELAY
CC
POWER DOWN
INTERNAL
OSCILLATOR
PV
TG
PV
BG
CC1
–
FREQSET
COMP
S
R
Q
Q
PWM
+
CC2
FFBG
12µA
PGND
FB
S
Q
ENABLE
BG
QSS
SS
POR
R
+
R
ERR
MIN
MAX
24k
+
+
+
–
–
–
V
V
+ 3%
REF
750Ω
750Ω
24k
V
V
REF
V
– 3%
V
I
+ 3%
REF
REF
REF
–
FB
CC
– 3%
REF
+
I
MAX
–
R
DISABLE
12µA
2.2V
1.2V
I
LIM
Q
C
GND
+
PV
V
CC1
3830 BD
V
+ 2.5V
–
CC1
3831f
7
LTC3831
TEST CIRCUITS
PV
CC
+
V
V
V
SHDN
CC
CC
0.1µF
10µF
SHDN
PV
PV
I
FB
CC2
CC1
TG RISE/FALL
6800pF
NC
NC
SS
FREQSET
FB
TG
BG
V
LTC3831
FB
V
COMP
COMP
2.5V
+
BG RISE/FALL
6800pF
R
–
R
I
GND
PGND
MAX
3831 F02
Figure 2
W U U
U
APPLICATIO S I FOR ATIO
OVERVIEW
THEORY OF OPERATION
The LTC3831 is a voltage mode feedback, synchronous
switching regulator controller (see Block Diagram) de-
signed for use in high to medium power, DDR memory
termination. It includes an onboard PWM generator, a
ratiometric reference, two high power MOSFET gate driv-
ers and all necessary feedback and control circuitry to
form a complete switching regulator circuit. The PWM
loop nominally runs at 200kHz.
Primary Feedback Loop
The LTC3831 senses the output voltage of the circuit
through the FB pin and feeds this voltage back to the
internal transconductance error amplifier, ERR. The error
amplifier compares the output voltage to the internal
ratiometric reference, VREF, and outputs an error signal to
the PWM comparator. VREF is set to 0.5 multiplied by the
voltage difference between the R+ and R– pins, using an
internal resistor divider.
TheLTC3831isdesignedtogenerateanoutputvoltagethat
tracksat1/2oftheexternalvoltageconnectedbetweenthe
R+ and R– pins. The LTC3831 can be used to generate the
terminationvoltage,VTT,forinterfaceliketheSSTL_2where
VTT is a ratio of the interface supply voltage, VDDQ. It is a
requirement in the SSTL_2 interface standard for VTT to
track the interface supply voltage to improve noise immu-
nity. Using the LTC3831 to supply the interface termina-
tion voltage allows large current sourcing and sinking
through the termination resistors during bus transitions.
This error signal is compared with a fixed frequency ramp
waveform, from the internal oscillator, to generate a pulse
width modulated signal. This PWM signal drives the
external MOSFETs through the TG and BG pins. The
resulting chopped waveform is filtered by LO and COUT
which closes the loop. Loop compensation is achieved
with an external compensation network at the COMP pin,
the output node of the error amplifier.
The LTC3831 includes a current limit sensing circuit that
uses the topside external N-channel power MOSFET as a
current sensing element, eliminating the need for an
external sense resistor. Also included is an internal soft-
start feature that requires only a single external capacitor
to operate. In addition, the part features an adjustable
oscillator which can free run or synchronize to an external
signal with frequencies from 100kHz to 500kHz, allowing
added flexibility in external component selection.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MIN
compares the feedback signal to a voltage 3% below VREF
.
If the signal is below the comparator threshold, the MIN
comparator overrides the error amplifier and forces the
loop to maximum duty cycle, >91%. Similarly, the MAX
3831f
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LTC3831
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APPLICATIO S I FOR ATIO
U
comparator forces the output to 0% duty cycle if the
feedback signal is greater than 3% above VREF. To prevent
these two comparators from triggering due to noise, the
MIN and MAX comparators’ response times are deliber-
ately delayed by two to three microseconds. These two
comparators help prevent extreme output perturbations
with fast output load current transients, while allowing the
main feedback loop to be optimally compensated for
stability.
current level. The CC comparator pulls current out of the
SS pin in proportion to the voltage difference between IFB
and IMAX. Under minor overload conditions, the SS pin
falls gradually, creating a time delay before current limit
takes effect. Very short, mild overloads may not affect the
output voltage at all. More significant overload conditions
allow the SS pin to reach a steady state, and the output
remains at a reduced voltage until the overload is re-
moved. Serious overloads generate a large overdrive at
CC, allowing it to pull SS down quickly and preventing
damage to the output components. By using the RDS(ON)
of Q1 to measure the output current, the current limiting
circuiteliminatesanexpensivediscretesenseresistorthat
would otherwise be required. This helps minimize the
number of components in the high current path.
Thermal Shutdown
TheLTC3831hasathermalprotectioncircuitthatdisables
both gate drivers if activated. If the chip junction tempera-
turereaches150°C,bothTGandBGarepulledlow.TGand
BG remain low until the junction temperature drops below
125°C, after which, the chip resumes normal operation.
The current limit threshold can be set by connecting an
external resistor RIMAX from the IMAX pin to the main VIN
supply at the drain of Q1. The value of RIMAX is determined
by:
Soft-Start and Current Limit
The LTC3831 includes a soft-start circuit that is used for
start-up and current limit operation. The SS pin requires
an external capacitor, CSS, to GND with the value deter-
mined by the required soft-start time. An internal 12µA
current source is included to charge CSS. During power-
up, the COMP pin is clamped to a diode drop (B-E junction
of QSS in the Block Diagram) above the voltage at the SS
pin. This prevents the error amplifier from forcing the loop
tomaximumdutycycle.TheLTC3831operatesatlowduty
cycleastheSSpinrisesabove0.6V(VCOMP ≈1.2V). AsSS
continues to rise, QSS turns off and the error amplifier
takes over to regulate the output. The MIN comparator is
disabled during soft-start to prevent it from overriding the
soft-start function.
RIMAX = (ILMAX)(RDS(ON)Q1)/IIMAX
where:
ILMAX = ILOAD + (IRIPPLE/2)
ILOAD= Maximum load current
IRIPPLE = Inductor ripple current
V – V
V
OUT
(
OUT)(
)
IN
=
f
L
V
( )(
)
OSC
O IN
fOSC = LTC3831 oscillator frequency = 200kHz
LO = Inductor value
The LTC3831 includes yet another feedback loop to con-
trol operation in current limit. Just before every falling
edge of TG, the current comparator, CC, samples and
holds the voltage drop measured across the external
upperMOSFET,Q1,attheIFB pin.CCcomparesthevoltage
at IFB to the voltage at the IMAX pin. As the peak current
rises,themeasuredvoltageacrossQ1increasesduetothe
drop across the RDS(ON) of Q1. When the voltage at IFB
drops below IMAX, indicating that Q1’s drain current has
exceeded the maximum level, CC starts to pull current out
of CSS, cutting the duty cycle and controlling the output
RDS(ON)Q1 = On-resistance of Q1 at ILMAX
IIMAX = Internal 12µA sink current at IMAX
The RDS(ON) of Q1 usually increases with temperature. To
keep the current limit threshold constant, the internal
12µA sink current at IMAX is designed with a positive
temperature coefficient to provide first order correction
for the temperature coefficient of RDS(ON)Q1
.
Inorderforthecurrentlimitcircuittooperateproperlyand
toobtainareasonablyaccuratecurrentlimitthreshold,the
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LTC3831
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APPLICATIO S I FOR ATIO
IIMAX and IFB pins must be Kelvin sensed at Q1’s drain and
source pins. In addition, connect a 0.1µF decoupling
capacitor across RIMAX to filter switching noise. Other-
wise, noise spikes or ringing at Q1’s source can cause the
actual current limit to be greater than the desired current
limit set point. Due to switching noise and variation of
10kHz. The pin is internally servoed to 1.265V, connecting
a50kresistorfromFREQSETtogroundforces25µAoutof
the pin, causing the internal oscillator to run at approxi-
mately 450kHz. Forcing an external 10µA current into
FREQSET cuts the internal frequency to 100kHz. An inter-
nalclamppreventstheoscillatorfromrunningslowerthan
about 50kHz. Tying FREQSET to VCC forces the chip to run
at this minimum speed.
RDS(ON), the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuitbeginstotakeeffectwillvaryfromunittounitasthe
Shutdown
The LTC3831 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allowstheparttooperatenormally.AlowlevelatSHDNfor
more than 100µs forces the LTC3831 into shutdown
mode.Inthismode,allinternalswitchingstops,theCOMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3831 supply current drops to <10µA, although off-
state leakage in the external MOSFETs may cause the total
VIN current to be somewhat higher, especially at elevated
temperatures. If SHDN returns high, the LTC3831 reruns
a soft-start cycle and resumes normal operation.
RDS(ON) of Q1 varies. Typically, RDS(ON) varies as much as
±40% and with ±25% variation on the LTC3831’s IMAX
current, this can give a ±65% variation on the current limit
threshold.
The RDS(ON) is high if the VGS applied to the MOSFET is
low. This occurs during power up, when PVCC1 is ramping
up.TopreventthehighRDS(ON) fromactivatingthecurrent
limit, the LTC3831 disables the current limit circuit if
PVCC1 is less than 2.5V above VCC. To ensure proper
operation of the current limit circuit, PVCC1 must be at
least 2.5V above VCC when TG is high. PVCC1 can go low
when TG is low, allowing the use of an external charge
External Clock Synchronization
pump to power PVCC1
.
The LTC3831 SHDN pin doubles as an external clock input
for applications that require a synchronized clock. An
internal circuit forces the LTC3831 into external synchro-
nization mode if a negative transition at the SHDN pin is
detected. In this mode, every negative transition on the
SHDN pin resets the internal oscillator and pulls the ramp
signal low. This forces the LTC3831 internal oscillator to
lock to the external clock frequency.
V
IN
LTC3831
+
+
R
0.1µF
IMAX
C
IN
+
12
I
MAX
12µA
CC
TG
BG
Q1
I
FB
L
O
1k
V
OUT
13
–
Q2
TheLTC3831internaloscillatorcanbeexternallysynchro-
nized from 100kHz to 500kHz. Frequencies above 300kHz
can cause a decrease in the maximum obtainable duty
cycle as rise/fall time and propagation delay take up a
larger percentage of the switch cycle. The low period of
this clock signal must not be >100µs or else the LTC3831
enters into the shutdown mode.
C
OUT
3831 F03
Figure 3. Current Limit Setting
Oscillator Frequency
The LTC3831 includes an onboard current controlled
oscillator that typically free-runs at 200kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin floating, the oscillator runs
at about 200kHz. Every additional 1µA of current into/out
of the FREQSET pin decreases/increases the frequency by
Figure 4 describes the operation of the external synchro-
nization function. A negative transition at the SHDN pin
forces the internal ramp signal low to restart a new PWM
cycle. Notice that the ramp amplitude is lowered as the
external clock frequency goes higher. The effect of this
3831f
10
LTC3831
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APPLICATIO S I FOR ATIO
U
Gate drive for the top N-channel MOSFET Q1 is supplied
from PVCC1. This supply must be above VIN (the main
power supply input) by at least one power MOSFET
VGS(ON) for efficient operation. An internal level shifter
allows PVCC1 to operate at voltages above VCC and VIN, up
to14Vmaximum. Thishighervoltagecanbesuppliedwith
a separate supply, or it can be generated using a charge
pump.
SHDN
200kHz
RAMP SIGNAL
WITH EXT SYNC
FREE RUNNING
RAMP SIGNAL
TRADITIONAL
SYNC METHOD
WITH EARLY
RAMP
Gate drive for the bottom MOSFET Q2 is provided through
PVCC2. This supply only need to be above the power
MOSFETVGS(ON) forefficientoperation. PVCC2 canalsobe
TERMINATION
driven from the same supply/charge pump for the PVCC1
,
RAMP AMPLITUDE
ADJUSTED
or it can be connected to a lower supply to improve
efficiency.
LTC3831
KEEPS RAMP
AMPLITUDE
CONSTANT
Figure 6 shows a doubling charge pump circuit that can be
used to provide 2VIN gate drive for Q1. The charge pump
consistsofaSchottkydiodefromVIN toPVCC1 anda0.1µF
capacitor from PVCC1 to the switching node at the drain of
UNDER SYNC
3831 F04
Figure 4. External Synchronization Operation
V
CC
PV
CC2
PV
CC1
V
IN
TG
BG
decrease in ramp amplitude increases the open-loop gain
of the controller feedback loop. As a result, the loop
crossover frequency increases and it may cause the feed-
backlooptobeunstableifthephasemarginisinsufficient.
Q1
L
O
INTERNAL
CIRCUITRY
V
OUT
+
C
Q2
OUT
To overcome this problem, the LTC3831 monitors the
peak voltage of the ramp signal and adjust the oscillator
charging current to maintain a constant ramp peak.
3831 F05
LTC3831
Figure 5. Supplies Input
Input Supply Considerations/Charge Pump
V
IN
TheLTC3831requiresfoursupplyvoltagestooperate:VIN
for the main power input, PVCC1 and PVCC2 for MOSFET
gate drive and a clean, low ripple VCC for the LTC3831
internal circuitry (Figure 5).
OPTIONAL
USE FOR V ≥ 7V
MBR0530T1
IN
D
Z
PV
CC2
PV
CC1
12V
0.1µF
1N5242
TG
In many applications, VCC can be powered from VIN
through an RC filter. This supply can be as low as 3V. The
low quiescent current (typically 800µA) allows the use of
relatively large filter resistors and correspondingly small
filter capacitors. 100Ω and 4.7µF usually provide ad-
equatefilteringforVCC. Forbestperformance, connectthe
4.7µFbypasscapacitorasclosetotheLTC3831VCC pinas
possible.
Q1
L
O
V
OUT
+
BG
Q2
C
OUT
3831 F06a
LTC3831
Figure 6. Doubling Charge Pump
3831f
11
LTC3831
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APPLICATIO S I FOR ATIO
Q2. This circuit provides 2VIN – VF to PVCC1 while Q1 is ON
andVIN –VF whileQ1isOFFwhereVFistheforwardvoltage
of the Schottky diode. Ringing at the drain of Q2 can cause
transients above 2VIN at PVCC1; if VIN is higher than 7V, a
12V zener diode should be included from PVCC1 to PGND
to prevent transients from damaging the circuitry at PVCC1
or the gate of Q1.
D
Z
1N5817
V
IN
12V
1N5242
1N5817
1N5817
0.1µF
10µF
PV
PV
CC1
CC2
0.1µF
TG
Q1
L
O
V
OUT
For applications with a lower VIN supply, a tripling charge
pumpcircuitshowninFigure7canbeusedtoprovide2VIN
and 3VIN gate drive for the external top and bottom
MOSFETs respectively. This circuit provides 3VIN – 3VF to
PVCC1 while Q1 is ON and 2VIN – 2VF to PVCC2 where VF is
the forward voltage of the Schottky diode. The circuit
requires the use of Schottky diodes to minimize forward
drop across the diodes at start-up. The tripling charge
pump circuit can rectify any ringing at the drain of Q2 and
providemorethan3VIN atPVCC1;a12Vzenerdiodeshould
be included from PVCC1 to PGND to prevent transients
from damaging the circuitry at PVCC1 or the gate of Q1.
+
BG
Q2
C
OUT
3831 F07
LTC3831
Figure 7. Tripling Charge Pump
For applications using an external supply to power PVCC1
this supply must also be higher than VCC by at least 2.5V
to ensure normal operation.
,
Connecting the Ratiometric Reference Input
The charge pump capacitors for PVCC1 refresh when the
BG pin goes high and the switch node is pulled low by Q2.
The BG on time becomes narrow when the LTC3831
operates at maximum duty cycle (95% typical) which can
occur if the input supply rises more slowly than the soft-
start capacitor or the input voltage droops during load
transients. If the BG on time gets so narrow that the switch
node fails to pull completely to ground, the charge pump
voltage may collapse or fail to start causing excessive
dissipationinexternalMOSFETQ1. Thisismostlikelywith
low VCC voltages and high switching frequencies, coupled
with large external MOSFETs that slow the BG and switch
node slew rates.
The LTC3831 derives its ratiometric reference, VREF
,
using an internal resistor divider. The top and bottom of
the resistor divider is connected to the R+ and R– pins
respectively. This permits the output voltage to track at a
ratio of the differential voltage at R+ and R–.
The LTC3831 can operate with a minimum VFB of 1.1V and
maximum VFB of (VCC – 1.75V). With R– connected to
+
GND, this gives a VR input range of 2.2V to (2 • VCC
–
+
3.5V). If VR is higher than the permitted input voltage,
increase the VCC voltage to raise the input range.
InatypicalDDRmemoryterminationapplicationasshown
in Figure 1, R+ is connected to VDDQ, the supply voltage of
the interface, and R– to GND. The output voltage VTT is
The LTC3831 overcomes this problem by sensing the
PVCC1 voltage when TG is high. If PVCC1 is less than 2.5V
above VCC, the maximum TG duty cycle is reduced to 70%
by clamping the COMP pin at 1.8V (QC in the Block
Diagram). This increases the BG on time and allows the
charge pump capacitors to be refreshed.
connected to the FB pin, so VTT = 0.5 • VDDQ
.
If a ratio greater than 0.5 is desired, it can be achieved
using an external resistor divider connected to VTT and FB
pin. Figure 8 shows an application that generates a VTT of
0.6 • VDDQ
.
3831f
12
LTC3831
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APPLICATIO S I FOR ATIO
U
V
DDQ
2.5V
5V
+
C
IN
MBR0530T1
330µF
×2
1µF
10k
0.1µF
PV
PV
CC1
Q1
Q2
MBRS340T3
CC2
V
TG
CC
0.1µF
L
O
0.1µF
SS
I
MAX
1.2µH
V
TT
1k
0.01µF
130k
+
1.5V
I
FB
LTC3831
4.7µF
±6A
MBRS340T3
FREQSET
SHDN
BG
PGND
GND
+
C
OUT
SHDN
470µF
×3
COMP
C
: SANYO POSCAP 6TPB330M
: SANYO POSCAP 4TPB470M
IN
OUT
C1
33pF
2k
1%
R
C
+
C
R
15k
Q1, Q2: SILICONIX Si4410DY
FB
C
C
–
R
1500pF
10k
1%
3831 F08
Figure 8. Typical Application with VTT = 0.6 • VDDQ
Power MOSFETs
After the MOSFET threshold voltage is selected, choose
theRDS(ON) basedontheinputvoltage, theoutputvoltage,
allowable power dissipation and maximum output cur-
rent. In a typical LTC3831 circuit operating in continuous
mode, the average inductor current is equal to the output
load current. This current flows through either Q1 or Q2
with the power dissipation split up according to the duty
cycle:
Two N-channel power MOSFETs are required for most
LTC3831 circuits. These should be selected based prima-
rilyonthresholdvoltageandon-resistanceconsiderations.
Thermal dissipation is often a secondary concern in high
efficiencydesigns.TherequiredMOSFETthresholdshould
be determined based on the available power supply volt-
ages and/or the complexity of the gate drive charge pump
scheme. In 3.3V input designs where an auxiliary 12V
supply is available to power PVCC1 and PVCC2, standard
MOSFETs with RDS(ON) specified at VGS = 5V or 6V can be
used with good results. The current drawn from this sup-
ply varies with the MOSFETs used and the LTC3831’s
operating frequency, but is generally less than 50mA.
VOUT
V
IN
DC(Q1) =
VOUT V – VOUT
IN
DC(Q2) = 1–
=
V
V
IN
IN
The RDS(ON) required for a given conduction loss can now
be calculated by rearranging the relation P = I2R.
LTC3831applicationsthatuse5VorlowerVIN voltageand
doubling/tripling charge pumps to generate PVCC1 and
PVCC2, do not provide enough gate drive voltage to fully
enhance standard power MOSFETs. Under this condition,
the effective MOSFET RDS(ON) may be quite high, raising
the dissipation in the FETs and reducing efficiency. Logic-
level FETs are the recommended choice for 5V or lower
voltage systems. Logic-level FETs can be fully enhanced
with a doubler/tripling charge pump and will operate at
maximum efficiency.
PMAX(Q1)
DC(Q1)•(ILOAD
PMAX(Q2)
V •PMAX(Q1)
IN
RDS(ON)Q1
RDS(ON)Q2
=
=
=
2
2
)
VOUT •(ILOAD
)
V •PMAX(Q2)
IN
=
2
2
DC(Q2)•(ILOAD
)
(V – VOUT)•(ILOAD)
IN
PMAX should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
3831f
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LTC3831
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APPLICATIO S I FOR ATIO
efficiency circuit designed for 2.5V input and 1.25V at 5A
output might allow no more than 3% efficiency loss at full
load for each MOSFET. Assuming roughly 90% efficiency
at this current level, this gives a PMAX value of:
decreases the MOSFET cost and the circuit efficiency and
increases the MOSFET heat sink requirements.
Table 1 highlights a variety of power MOSFETs that are for
use in LTC3831 applications.
(1.25V)(5A/0.9)(0.03) = 0.21W per FET
and a required RDS(ON) of:
Inductor Selection
TheinductorisoftenthelargestcomponentinanLTC3831
design and must be chosen carefully. Choose the inductor
valueandtypebasedonoutputslewraterequirements.The
maximum rate of rise of inductor current is set by the
inductor’svalue,theinput-to-outputvoltagedifferentialand
theLTC3831’smaximumdutycycle.Inatypical2.5Vinput
1.25V output application, the maximum rise time will be:
(2.5V)•(0.21W)
RDS(ON)Q1
RDS(ON)Q2
=
=
= 0.017Ω
(1.25V)(5A)2
(2.5V)•(0.21W)
(2.5V – 1.25V)(5A)2
= 0.017Ω
Note that while the required RDS(ON) values suggest large
MOSFETs, the power dissipation numbers are only 0.21W
per device or less; large TO-220 packages and heat sinks
arenotnecessarilyrequiredinhighefficiencyapplications.
SiliconixSi4410DYorInternationalRectifierIRF7413(both
in SO-8) or Siliconix SUD50N03-10 (TO-252) or ON Semi-
conductor MTD20N03HDL (DPAK) are small footprint
surfacemountdeviceswithRDS(ON) valuesbelow0.03Ωat
5V of VGS that work well in LTC3831 circuits. Using a
higher PMAX value in the RDS(ON) calculations generally
DCMAX •(V – VOUT
)
1.138 A
LO µs
IN
=
LO
where LO is the inductor value in µH. With proper fre-
quency compensation, the combination of the inductor
andoutputcapacitorvaluesdeterminethetransientrecov-
ery time. In general, a smaller value inductor improves
transient response at the expense of ripple and inductor
core saturation rating. A 2µH inductor has a 0.57A/µs rise
Table 1. Recommended MOSFETs for LTC3831 Applications
TYPICAL INPUT
CAPACITANCE
R
DS(ON)
PARTS
AT 25°C (mΩ)
RATED CURRENT (A)
C
(pF)
θ
(°C/W)
T
(°C)
JMAX
ISS
JC
Siliconix SUD50N03-10
TO-252
19
15 at 25°C
3200
2700
880
1.8
175
10 at 100°C
Siliconix Si4410DY
SO-8
20
35
8
10 at 25°C
8 at 70°C
150
150
150
150
150
175
175
150
ON Semiconductor MTD20N03HDL
D PAK
20 at 25°C
16 at 100°C
1.67
25
Fairchild FDS6670A
S0-8
13 at 25°C
3200
2070
4025
1600
3300
1750
Fairchild FDS6680
SO-8
10
9
11.5 at 25°C
25
ON Semiconductor MTB75N03HDL
DD PAK
75 at 25°C
59 at 100°C
1
IR IRL3103S
DD PAK
19
28
37
64 at 25°C
45 at 100°C
1.4
1
IR IRLZ44
TO-220
50 at 25°C
36 at 100°C
Fuji 2SK1388
TO-220
35 at 25°C
2.08
Note: Please refer to the manufacturer’s data sheet for testing conditions and detailed information.
3831f
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U
time in this application, resulting in a 8.8µs delay in
responding to a 5A load current step. During this 8.8µs,
thedifferencebetweentheinductorcurrentandtheoutput
current is made up by the output capacitor. This action
causes a temporary voltage droop at the output. To
minimize this effect, the inductor value should usually be
in the 1µH to 5µH range for most LTC3831 circuits. To
optimize performance, different combinations of input
and output voltages and expected loads may require
different inductor values.
Input and Output Capacitors
A typical LTC3831 design places significant demands on
both the input and the output capacitors. During normal
steady load operation, a buck converter like the LTC3831
drawssquarewavesofcurrentfromtheinputsupplyatthe
switchingfrequency. Thepeakcurrentvalueisequaltothe
output load current plus 1/2 the peak-to-peak ripple cur-
rent. Most of this current is supplied by the input bypass
capacitor. The resulting RMS current flow in the input
capacitor heats it and causes premature capacitor failure
in extreme cases. Maximum RMS current occurs with
50% PWM duty cycle, giving an RMS current value equal
to IOUT/2. A low ESR input capacitor with an adequate
ripple current rating must be used to ensure reliable
operation. Note that capacitor manufacturers’ ripple cur-
rentratingsareoftenbasedononly2000hours(3months)
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer’s speci-
fication is recommended to extend the useful life of the
circuit. Loweroperatingtemperaturehasthelargesteffect
on capacitor longevity.
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-to-
peak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:
(V − VOUT)•(VOUT
)
IN
IRIPPLE
=
fOSC •LO • V
IN
fOSC = LTC3831 oscillator frequency = 200kHz
LO = Inductor value
The output capacitor in a buck converter under steady-
state conditions sees much less ripple current than the
input capacitor. Peak-to-peak current is equal to inductor
ripple current, usually 10% to 40% of the total load
current. Output capacitor duty places a premium not on
power dissipation but on ESR. During an output load
transient, the output capacitor must supply all of the
additional load current demanded by the load until the
LTC3831 adjusts the inductor current to the new value.
ESR in the output capacitor results in a step in the output
voltage equal to the ESR value multiplied by the change in
load current. A 5A load step with a 0.05Ω ESR output
capacitor results in a 250mV output voltage shift; this is
20% of the output voltage for a 1.25V supply! Because of
the strong relationship between output capacitor ESR and
output load transient response, choose the output capaci-
tor for ESR, not for capacitance value. A capacitor with
suitable ESR will usually have a larger capacitance value
than is needed to control steady-state output ripple.
Solving this equation with our typical 2.5V to 1.25V
application with 2µH inductor, we get:
(2.5V – 1.25V)•1.25V
= 1.56AP-P
200kHz • 2µH • 2.5V
Peak inductor current at 5A load:
5A + (1.56A/2) = 5.78A
The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
under short circuit or fault conditions; the inductor should
be sized accordingly to withstand this additional current.
Inductorswithgradualsaturationcharacteristicsareoften
the best choice.
Electrolytic capacitors, such as the Sanyo MV-WX series,
rated for use in switching power supplies with specified
ripple current ratings and ESR, can be used effectively in
3831f
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APPLICATIO S I FOR ATIO
LTC3831 applications. OS-CON electrolytic capacitors
from Sanyo and other manufacturers give excellent per-
formance and have a very high performance/size ratio for
electrolytic capacitors. Surface mount applications can
use either electrolytic or dry tantalum capacitors. Tanta-
lum capacitors must be surge tested and specified for use
in switching power supplies. Low cost, generic tantalums
are known to have very short lives followed by explosive
deaths in switching power supply applications. Other
capacitor series that can be used include Sanyo POSCAPs
and the Panasonic SP line.
frequency for the overall open-loop transfer function. The
zero and pole from the compensation network are:
fZ = 1/[2π(RC)(CC)] and
fP = 1/[2π(RC)(C1)] respectively.
Figure 9b shows the Bode plot of the overall transfer
function.
Although a mathematical approach to frequency compen-
sationcanbeused, theaddedcomplicationofinputand/or
output filters, unknown capacitor ESR, and gross operat-
ing point changes with input voltage, load current varia-
tions, all suggest a more practical empirical method. This
can be done by injecting a transient current at the load and
using an RC network box to iterate toward the final values,
or by obtaining the optimum loop response using a
network analyzer to find the actual loop poles and zeros.
A common way to lower ESR and raise ripple current
capabilityistoparallelseveralcapacitors.AtypicalLTC3831
application might exhibit 5A input ripple current. Sanyo
OS-CONcapacitors,partnumber10SA220M(220µF/10V),
feature 2.3A allowable ripple current at 85°C; three in
parallel at the input (to withstand the input ripple current)
meet the above requirements. Similarly, Sanyo POSCAP
4TPB470M (470µF/4V) capacitors have a maximum rated
ESR of 0.04Ω, three in parallel lower the net output
capacitor ESR to 0.013Ω.
LTC3831
V
FB
–
V
TT
6
COMP
10
ERR
+
R
C
Feedback Loop Compensation
V
C1
REF
C
C
3831 F09a
TheLTC3831voltagefeedbackloopiscompensatedatthe
COMP pin, which is the output node of the error amplifier.
The feedback loop is generally compensated with an RC +
C network from COMP to GND as shown in Figure 9a.
Figure 9a. Compensation Pin Hook-Up
Loop stability is affected by the values of the inductor, the
output capacitor, the output capacitor ESR, the error
amplifier transconductance and the error amplifier com-
pensation network. The inductor and the output capacitor
create a double pole at the frequency:
f
f
= LTC3831 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
SW
f
Z
CO
fLC = 1/ 2π (LO)(COUT
)
20dB/DECADE
[
]
The ESR of the output capacitor and the output capacitor
value form a zero at the frequency:
f
P
FREQUENCY
f
LC
f
ESR
f
CO
fESR = 1/ 2π(ESR)(C
)
]
[
OUT
3830 F10b
The compensation network used with the error amplifier
must provide enough phase margin at the 0dB crossover
Figure 9b. Bode Plot of the LTC3831 Overall Transfer Function
3831f
16
LTC3831
W U U
APPLICATIO S I FOR ATIO
U
Table 2 shows the suggested compensation component
value for 2.5V to 1.25V applications based on the 470µF
Sanyo POSCAP 4TPB470M output capacitors.
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3831. These items are also illustrated graphically in
the layout diagram of Figure 10. The thicker lines show the
high current paths. Note that at 5A current levels or above,
Table 3 shows the suggested compensation component
values for 2.5V to 1.25V applications based on 1500µF
Sanyo MV-WX output capacitors.
Table 2. Recommended Compensation Network for 2.5V to
1.25V Applications Using Multiple Paralleled 470µF Sanyo
POSCAP 4TPB470M Output Capacitors
Table 3. Recommended Compensation Network for 2.5V to
1.25V Applications Using Multiple Paralleled 1500µF Sanyo
MV-WX Output Capacitors
L1 (µH)
1.2
C
(µF)
R (kΩ)
C (nF)
C1 (pF)
33
L1 (µH)
1.2
C
(µF)
R (kΩ)
C (nF)
C1 (pF)
120
82
OUT
C
C
OUT
C
C
1410
6.8
15
22
15
36
47
33
68
120
3.3
3.3
1.5
10
4500
20
27
1.5
1
1.2
2820
4700
1410
2820
4700
1410
2820
4700
33
1.2
6000
9000
4500
6000
9000
4500
6000
9000
1.2
33
1.2
43
0.47
1
56
2.4
33
2.4
51
56
2.4
3.3
4.7
10
10
2.4
62
1
33
2.4
10
2.4
82
0.47
3.3
1
27
4.7
10
4.7
82
33
4.7
22
10
4.7
100
150
15
4.7
10
10
4.7
1
15
PV
V
IN
CC
100Ω
1µF
10k
+
4.7µF
+
V
PV
CC2
CC
C
IN
0.1µF
1µF
PV
PGND
CC1
OPTIONAL
Q1
TG
LTC3831
GND
MBRS340T3
MBRS340T3
I
MAX
L
O
1k
FREQSET
SHDN
COMP
SS
I
V
OUT
NC
FB
+
R
Q2
BG
FB
C1
R
+
–
C
OUT
R
C
GND
PGND
PGND
C
C
C
SS
3830 F11
GND
Figure 10. Typical Schematic Showing Layout Considerations
3831f
17
LTC3831
W U U
U
APPLICATIO S I FOR ATIO
current density in the PC board itself is a serious concern.
Traces carrying high current should be as wide as pos-
sible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15" to carry 5A.
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
1. In general, layout should begin with the location of the
powerdevices.Besuretoorientthepowercircuitrysothat
a clean power flow path is achieved. Conductor widths
shouldbemaximizedandlengthsminimized.Afteryouare
satisfied with the power path, the control circuitry should
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
4.TheVCC,PVCC1 andPVCC2 decouplingcapacitorsshould
be as close to the LTC3831 as possible. The 4.7µF and 1µF
bypasscapacitorsshownatVCC,PVCC1 andPVCC2 willhelp
provide optimum regulation performance.
5. The (+) plate of CIN should be connected as close as
possible to the drain of the upper MOSFET, Q1. An addi-
tional1µFceramiccapacitorbetweenVINandpowerground
is recommended.
2. The GND and PGND pins should be shorted directly at
the LTC3831. This helps to minimize internal ground dis-
turbances in the LTC3831 and prevents differences in
groundpotentialfromdisruptinginternalcircuitoperation.
This connection should then tie into the ground plane at
a single point, preferably at a fairly quiet point in the circuit
such as close to the output capacitors. This is not always
practical, however, due to physical constraints. Another
reasonably good point to make this connection is between
the output capacitors and the source connection of the
bottom MOSFET Q2. Do not tie this single point ground in
the trace run between the Q2 source and the input capaci-
tor ground, as this area of the ground plane will be very
noisy.
6. The VFB pin is very sensitive to pickup from the switch-
ingnode.CareshouldbetakentoisolateVFB frompossible
capacitive coupling to the inductor switching signal.
7. In a typical SSTL application, if the R+ pin is to be con-
nected to VDDQ, which is also the main supply voltage for
the switching regulator, do not connect R+ along the high
current flow path; it should be connected to the SSTL in-
terfacesupplyoutput. R– shouldbeconnectedtotheinter-
face supply GND.
8. Kelvin sense IMAX and IFB at Q1’s drain and source pins.
3831f
18
LTC3831
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3831f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
19
LTC3831
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Current Mode Ensures Accurate Current Sensing V Up to 36V,
2-Phase, Synchronous High Efficiency Converter
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I
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LTC3413
LTC3713
LTC3778
LTC3717
3A, Monolithic Synchronous Regulator for DDR/QDR
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Low R
(Sink and Source), V
Internal Switch: 85mΩ, ±3A Output Current
DS(ON)
= V /2
REF
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Low Input Voltage, High Power, No R
Synchronous Controller
, Step-Down
SENSE
Minimum V : 1.5V, Uses Standard Logic-Level N-Channel
MOSFETs
IN
Wide Operating Range, No R
, Step-Down Controller
SENSE
V Up to 36V, Current Mode, Power Good, Stable with
IN
Ceramic C
OUT
Wide V Step-Down Controller for DDR Memory Termination
Current Mode Operation, V
Tracks V (V ), No R
= 1/2 V , V
(V )
IN
OUT
IN OUT TT
, Symmetrical Sink and Source
SENSE
IN DDQ
Output Current Limit
LTC3718
LTC3832
Bus termination Supply for Low Votlage V
1.5V ≤ V , Generates 5V Gate Drive for Standard N-Ch MOSFETs,
IN
IN
2A ≤ I
≤ 25A
OUT
High Power Synchronous Switching Regulator Controller
is a trademark of Linear Technology Corporation.
V
as low as 0.6V
OUT
No R
SENSE
3831f
LT/TP 0503 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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