LTC3851AEUD#PBF_技术文档

LTC3851A

Synchronous

Step-Down Switching

Regulator Controller

FeaTures

DescripTion

The LTC^®3851A is a high performance synchronous

step-down switching regulator controller that drives

an all N-channel synchronous power MOSFET stage. A

n

Wide V Range: 4V to 38V Operation

SENSE

±±1 Output Voltage Accuracy

Phase-Lockable Fixed Frequency: 250kHz to 750kHz constant frequency current mode architecture allows a

IN

n

R

or DCR Current Sensing

n

Dual N-Channel MOSFET Synchronous Drive

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Output Voltage Soft-Start or Tracking

Output Current Foldback Limiting

phase-lockable frequency of up to 750kHz.

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capacitance

and ESR values. The LTC3851A features a precision 0.8V

reference that is compatible with a wide 4V to 38V input

supply range.

Output Overvoltage Protection

5V Internal Regulator

OPTI-LOOP^®Compensation Minimizes C

OUT

The TK/SS pin ramps the output voltage during start-up.

Current foldback limits MOSFET heat dissipation during

short-circuit conditions. The MODE/PLLIN pin selects

among Burst Mode operation, pulse-skipping mode or

continuous inductor current mode at light loads and al-

lows the IC to be synchronized to an external clock. The

LTC3851A contains an improved PLL compared to the

LTC3851.

Selectable Continuous, Pulse-Skipping or

Burst Mode^®Operation at Light Loads

n

Low Shutdown I : 20µA

Q

V

Range: 0.8V to 5.5V

OUT

Thermally Enhanced 16-Lead MSOP, 16-Lead Narrow

SSOP or 3mm × 3mm QFN Package

applicaTions

n

Automotive Systems

The LTC3851A-1 is a version with a power good output

signal instead of adjustable current limit.

n

Telecom Systems

n

Industrial Equipment

Distributed DC Power Systems

L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are registered

trademarks and No R , UltraFast are trademarks of Linear Technology Corporation. All other

SENSE

n

trademarks are the property of their respective owners. Protected by U.S. Patents including

5408150, 5481178, 5705919, 5929620, 6304066, 6498466, 6580258, 6611131.

Typical applicaTion

High Efficiency Synchronous Step-Down Converter

Efficiency and Power Loss

vs Load Current

V

IN

4.5V TO 36V

I

V

LIM

IN

100

95

10000

1000

100

22µF

V

= 12V

IN

OUT

FREQ/PLLFLTR TG

= 3.3V

0.68µH

3.01k

V

3.3V

15A

OUT

0.1µF

82.5k

RUN

LTC3851A

SW

90

EFFICIENCY

0.1µF

85

TK/SS

BOOST

330µF

×2

0.1µF

80

75

POWER LOSS

INTV

CC

2200pF

4.7µF

70

65

60

55

50

BG

I

TH

GND

330pF

15k

+

SENSE

MODE/PLLIN

SENSE

0.047µF

30.1k

–

154k

10

100

1000

10000

100000

V

FB

LOAD CURRENT (mA)

48.7k

3851A TA01b

3851A TA01a

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1

LTC3851A

absoluTe MaxiMuM raTings ^{(Note ±)}

Input Supply Voltage (V )......................... 40V to –0.3V

INTV Peak Output Current..................................50mA

IN

CC

Topside Driver Voltage (BOOST)................ 46V to –0.3V

Switch Voltage (SW).....................................40V to –5V

Operating Junction Temperature Range (Notes 2, 3)

E-Grade, I-Grade................................–40°C to 125°C

H-Grade ............................................. –40°C to 150°C

MP-Grade .......................................... –55°C to 150°C

Storage Temperature Range ..................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

INTV , (BOOST – SW), RUN ...................... 6V to –0.3V

CC

TK/SS, I ...........................................INTV to –0.3V

LIM

CC

+

–

SENSE , SENSE .......................................... 6V to –0.3V

MODE/PLLIN, FREQ/PLLFLTR ..............INTV to –0.3V

CC

I , V Voltages.......................................... 3V to –0.3V

GN/MSE............................................................300°C

TH FB

pin conFiguraTion

TOP VIEW

MODE/PLLIN

FREQ/PLLFLTR

RUN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SW

1

2

3

4

5

6

7

8

MODE/PLLIN

FREQ/PLLFLTR

RUN

16 SW

TG

16 15 14 13

15 TG

BOOST

14 BOOST

RUN

1

2

3

4

12 BOOST

TK/SS

17

GND

13 V

IN

TK/SS

V

TK/SS

11

10

9

V

IN

12 INTV

11 BG

17

GND

I

TH

CC

FB

I

INTV

BG

I

TH

INTV

CC

TH

CC

–

+

SENSE

10 GND

FB

9

I

LIM

FB

BG

–

5

6

7

8

MSE PACKAGE

16-LEAD PLASTIC MSOP

SENSE

GND

+

SENSE

I

LIM

T

JMAX

= 125°C, θ = 35°C/W TO 40°C/W

JA

EXPOSED PAD (PIN 17) IS GND,

MUST BE SOLDERED TO PCB

GN PACKAGE

16-LEAD PLASTIC SSOP NARROW

UD PACKAGE

16-LEAD (3mm × 3mm) PLASTIC QFN

T

JMAX

= 125°C, θ = 110°C/W

JA

T

= 125°C, θ = 68°C/W, θ = 4.2°C/W

JA JC

JMAX

EXPOSED PAD (PIN 17) IS GND,

MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LTC3851AEGN#PBF

LTC3851AIGN#PBF

LTC3851AEMSE#PBF

LTC3851AIMSE#PBF

LTC3851AHMSE#PBF

LTC3851AMPMSE#PBF

LTC3851AEUD#PBF

LTC3851AIUD#PBF

TAPE AND REEL

PART MARKING*

3851A

PACKAGE DESCRIPTION

16-Lead Plastic SSOP

16-Lead Plastic MSOP

TEMPERATURE RANGE

LTC3851AEGN#TRPBF

LTC3851AIGN#TRPBF

LTC3851AEMSE#TRPBF

LTC3851AIMSE#TRPBF

LTC3851AHMSE#TRPBF

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

–40°C to 125°C

3851A

LTC3851AMPMSE#TRPBF 3851A

LTC3851AEUD#TRPBF

LTC3851AIUD#TRPBF

LFPZ

16-Lead (3mm × 3mm) Plastic QFN

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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2

LTC3851A

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= ±5V, V_RUN= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Main Control Loops

l

V

Operating Input Voltage Range

Regulated Feedback Voltage

4

38

V

IN

l

I

= 1.2V (Note 4) 0°C to 85°C

0.792 0.800 0.808

V

FB

TH

= 1.2V (Note 4) –40°C to 125°C

= 1.2V (Note 4) –40°C to 150°C

= 1.2V (Note 4) –55°C to 150°C

0.788

0.812

I

Feedback Current

(Note 4)

= 6V to 38V (Note 4)

–10

–50

nA

FB

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

0.002 0.02

%/V

REFLNREG

LOADREG

IN

(Note 4) Measured in Servo Loop,

l

∆I = 1.2V to 0.7V

0.01

0.1

0.2

%

TH

(Note 4) Measured in Servo Loop,

∆I = 1.2V to 0.7V (H-Grade, MP-Grade)

TH

(Note 4) Measured in Servo Loop,

l

∆I = 1.2V to 1.6V

–0.01 –0.1

%

TH

(Note 4) Measured in Servo Loop,

∆I = 1.2V to 1.6V (H-Grade, MP-Grade)

–0.2

%

mmho

MHz

TH

g

Transconductance Amplifier g

I

TH

I

TH

= 1.2V, Sink/Source = 5µA (Note 4)

= 1.2V (Note 8)

2

3

m

GBW

Transconductance Amp Gain Bandwidth

m

I

Input DC Supply Current

Normal Mode

(Note 5)

Q

V

= 5V

= 0V

1.2

mA

µA

RUN

Shutdown

25

3.25

0.4

10

50

UVLO

Undervoltage Lockout on INTV

V

Ramping Down

INTVCC

V

CC

UVLO Hys UVLO Hysteresis

V

Feedback Overvoltage Lockout

with Respect to Set Regulated Voltage V Ramping

7.5

12.5

%

OVL

FB

Positive (OV)

I

SENSE Pins Current

1

2

µA

V

SENSE

Soft-Start Charge Current

RUN Pin On—Threshold

RUN Pin On—Hysteresis

V

= 0V

0.6

TK/SS

l

V

Rising

RUN

1.10

1.22

120

30

1.35

RUN

mV

RUNHYS

SENSE(MAX)

l

Maximum Current Sense Threshold

V

= 0.7V, V

= 3.3V, I = 0V

20

15

40

35

65

60

40

45

mV

FB

SENSE

LIM

= 3.3V, I = 0V (H-/MP-Grade)

LIM

= 3.3V, I = Float

53

80

65

LIM

= 3.3V, I = Float (H-/MP-Grade)

70

LIM

= 3.3V, I = INTV

95

LIM

CC

= 3.3V, I = INTV (H-/MP-Grade)

100

LIM

TG R

BG R

TG Driver Pull-Up On-Resistance

TG Driver Pull-Down On-Resistance

BG Driver Pull-Up On-Resistance

BG Driver Pull-Down On-Resistance

TG High

TG Low

BG High

BG Low

(Note 6)

2.2

1.2

2.1

1.1

Ω

UP

DOWN

UP

DOWN

TG Transition Time

Rise Time

Fall Time

TG t

C

= 3300pF

25

ns

r

f

LOAD

BG Transition Time

Rise Time

Fall Time

(Note 6)

BG tr

BG tf

C

= 3300pF

25

ns

LOAD

TG/BG t

Top Gate Off to Bottom Gate On Delay

Bottom Switch-On Delay Time

C

= 3300pF Each Driver

30

90

ns

1D

2D

LOAD

(Note 6)

BG/TG t

Bottom Gate Off to Top Gate On Delay Top

Switch-On Delay Time

C

= 3300pF Each Driver

LOAD

ns

(Note 6)

t

Minimum On-Time

(Note 7)

ns

ON(MIN)

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3

LTC3851A

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= ±5V, V_RUN= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

INTV Linear Regulator

CC

INTVCC

V

Internal V Voltage

6V < V < 38V

4.8

5

5.2

2

V

CC

IN

INT

INTV Load Regulation

I = 0mA to 50mA

CC

0.5

%

LDO

CC

Oscillator and Phase-Locked Loop

f

Nominal Frequency

R

= 60k

= 160k

= 36k

460

205

690

500

235

750

100

540

265

810

kHz

kΩ

NOM

LOW

HIGH

FREQ

Lowest Frequency

Highest Frequency

R

MODE/PLLIN Input Resistance

MODE/PLLIN

MODE

f

I

MODE/PLLIN Minimum Input Frequency

MODE/PLLIN Maximum Input Frequency

V

= External Clock

250

750

kHz

MODE

Phase Detector Output Current

Sinking Capability

Sourcing Capability

FREQ

f

> f

< f

–90

75

µA

MODE

OSC

Note ±: Stresses beyond those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to any Absolute Maximum

Rating condition for extended periods may affect device reliability and lifetime.

Note 3: T is calculated from the ambient temperature T and power

J A

dissipation P according to the following formulas:

D

LTC3851AGN: T = T + (P • 110°C/W)

J

A

D

Note 2: The LTC3851A is tested under pulsed load conditions such that

LTC3851AUD: T = T + (P • 68°C/W)

J

A

D

T ≈ T . The LTC3851AE is guaranteed to meet performance speciﬁcations

A

J

LTC3851AMSE: T = T + (P • 40°C/W)

J

A

D

from 0°C to 85°C junction temperature. Speciﬁcations over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3851AI is guaranteed to meet specifications over the –40°C to 125°C

operating junction temperature range, the LTC3851AH is guaranteed

over the –40°C to 150°C operating junction temperature range and the

LTC3851AMP is tested and guaranteed over the –55°C to 150°C operating

junction temperature range. High junction temperatures degrade operating

lifetimes; operating lifetime is derated for junction temperatures greater

than 125°C. Note that the maximum ambient temperature consistent with

these specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal impedance and

other environmental factors.

Note 4: The LTC3851A is tested in a feedback loop that servos V to a

ITH

speciﬁed voltage and measures the resultant V

.

FB

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels. Rise and fall times are assured by

design, characterization and correlation with statistical process controls.

Note 7: The minimum on-time condition is speciﬁed for an inductor

peak-to-peak ripple current ~40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).

Note 8: Guaranteed by design; not tested in production.

Typical perForMance characTerisTics

Efficiency vs Output Current

and Mode

Efficiency vs Output Current

and Mode

Efficiency vs Output Current

and Mode

100

90

100

90

100

90

V

= 12V

IN

OUT

= 1.5V

BURST

80

BURST

70

PULSE

SKIP

PULSE

SKIP

60

50

60

50

60

50

PULSE

SKIP

CCM

40

30

20

10

0

40

30

20

10

0

40

30

20

10

0

CCM

V

= 12V

IN

OUT

V

OUT

= 12V

= 5V

= 3.3V

IN

V

FIGURE 11 CIRCUIT

10000 100000

LOAD CURRENT (mA)

10

100

1000

10000

100000

10

100

1000

10

100

1000

10000

100000

LOAD CURRENT (mA)

3851A G01

3851A G02

3851A G03

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4

LTC3851A

Typical perForMance characTerisTics

Efficiency and Power Loss

vs Input Voltage

Load Step

(Burst Mode Operation)

100

95

10000

1000

100

I

LOAD

EFFICIENCY,

= 5A

5A/DIV

I

POWER LOSS,

= 5A

OUT

0.2A TO 7.5A

I

OUT

I

L

90

5A/DIV

85

80

EFFICIENCY,

= 0.5A

V

OUT

I

OUT

100mV/DIV

AC-COUPLED

POWER LOSS,

I

= 0.5A

OUT

3851A G05

V

= 1.5V

OUT

= 12V

IN

100µs/DIV

V

= 12V

75

70

IN

OUT

= 3.3V

FIGURE 11 CIRCUIT

4

8

12

16

20 28

24 32

INPUT VOLTAGE (V)

3851A G04

Load Step

(Forced Continuous Mode)

Load Step

(Pulse-Skipping Mode)

I

LOAD

5A/DIV

0.2A TO 7.5A

I

L

5A/DIV

V

OUT

100mV/DIV

AC-COUPLED

3851A G07

3851A G06

V

= 1.5V

100µs/DIV

V

= 1.5V

100µs/DIV

OUT

IN

OUT

IN

= 12V

FIGURE 11 CIRCUIT

Coincident Tracking with Master

Supply

Start-Up with Prebiased Output

at 2V

Inductor Current at Light Load

FORCED

CONTINOUS

MODE

V

MASTER

V

OUT

0.5V/DIV

V

2V/DIV

OUT

5A/DIV

TK/SS

0.5V/DIV

2A LOAD

0.5V/DIV

Burst Mode

OPERATION

5A/DIV

V

FB

PULSE-SKIPPING

MODE

0.5V/DIV

5A/DIV

3851A G08

3851A G09

3851A G10

V

LOAD

= 1.5V

= 1mA

1µs/DIV

OUT

IN

20ms/DIV

10ms/DIV

= 12V

I

FIGURE 11 CIRCUIT

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5

LTC3851A

Typical perForMance characTerisTics

Ratiometric Tracking with Master

Supply

Input DC Supply Current

vs Input Voltage

INTV_CCLine Regulation

3.0

2.5

2.0

1.5

1.0

0.5

0

5.3

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

I

= 0mA

LOAD

V

MASTER

I

= 25mA

LOAD

0.5V/DIV

V

OUT

2A LOAD

0.5V/DIV

3851A G11

10ms/DIV

3.5

4

8

12 16 20 24 28 32 36 40

INPUT VOLTAGE (V)

4

8

12 16 20 24

INPUT VOLTAGE (V)

40

28 32 36

3851A G12

3851A G13

Burst Mode Peak Current Sense

Threshold vs I_THVoltage

Maximum Current Sense Threshold

vs Common Mode Voltage

Maximum Peak Current Sense

Threshold vs I_THVoltage

90

80

70

60

50

40

30

20

10

0

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

DUTY CYCLE RANGE: 0% TO 100%

MAXIMUIM

I

= INTV

CC

LIM

I

= INTV

CC

LIM

I

= FLOAT

I

= FLOAT

LIM

I

= GND

LIM

I

= GND

LIM

MINIMUIM

I

= FLOAT

LIM

BURST COMPARATOR FALLING THESHOLD:

= 0.4V

–10

–20

V

ITH

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

(V)

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

(V)

0

0.5

1

1.5

2

2.5

5

3

3.5 4 4.5

V

ITH

V

COMMON MODE VOLTAGE (V)

SENSE

3851A G16

3851A G15

3851A G14

Maximum Current Sense

Threshold vs Feedback Voltage

(Current Foldback)

TK/SS Pull-Up Current

vs Temperature

Maximum Current Sense

Threshold vs Duty Cycle

90

80

70

60

50

40

30

20

10

0

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

90

80

70

60

50

40

30

20

10

I

= INTV

CC

I

= INTV

CC

LIM

I

= FLOAT

= GND

I

= FLOAT

= GND

LIM

I

LIM

I

LIM

0

0.4 0.5

FEEDBACK VOLTAGE (V)

0

0.1 0.2 0.3

0.6 0.7 0.8

0

80

100

20

40

60

–75

0

25 50 75 100 125 150

–50 –25

DUTY CYCLE (%)

TEMPERATURE (°C)

3851A G18

3851A G17

3851A G19

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LTC3851A

Typical perForMance characTerisTics

Oscillator Frequency

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

Regulated Feedback Voltage

vs Temperature

1.4

1.3

1.2

1.1

1.0

0.9

806

804

802

800

900

800

R

= 36k

PLLLPF

RUN RISING THRESHOLD (ON)

RUN FALLING THRESHOLD (OFF)

700

600

500

400

300

R

= 60k

PLLLPF

798

796

794

R

= 160k

PLLLPF

200

50

TEMPERATURE (°C)

100 125 150

50

100 125 150

75

–75 –50 –25

0

25

75

–75 –50 –25

0

25

–75 –50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3851A G21

3851A G22

3851A G20

Oscillator Frequency

vs Input Voltage

Undervoltage Lockout Threshold

(INTV_CC) vs Temperature

Shutdown Input DC Supply

Current vs Input Voltage

420

5

4

3

2

1

0

40

35

30

25

20

15

10

5

R

= 80k

FREQ

415

410

INTV RAMPING UP

CC

405

400

395

390

385

INTV RAMPING DOWN

CC

380

0

10

15

25

30

35

40

5

20

20 25

INPUT VOLTAGE (V)

0

5

10 15

30 35 40

–75 –50 –25

0

25 50 75 100 125 150

INPUT VOLTAGE (V)

TEMPERATURE (°C)

3851A G23

3851A G25

3851A G24

Shutdown Input DC Supply

Current vs Temperature

Input DC Supply Current

vs Temperature

Maximum Current Sense

Threshold vs INTV_CCVoltage

3.0

2.5

2.0

1.5

40

90

80

70

60

50

40

30

20

10

I

= INTV

CC

SET

35

30

I

= FLOAT

25

20

15

10

5

SET

I

= GND

SET

1.0

0.5

0

50

100 125 150

75

–75 –50 –25

0

25

–25

0

50 75 100 125 150

–75 –50

25

3.2 3.4 3.6 3.8 4.0 4.2

5.0

4.4 4.6 4.8

TEMPERATURE (°C)

INTV VOLTAGE(V)

CC

3851A G27

3851A G26

3851A G28

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7

LTC3851A

pin FuncTions ^{(GN and MSE/UD)}

MODE/PLLIN (Pin ±/Pin ±5): Forced Continuous Mode,

BurstModeorPulse-SkippingModeSelectionPinandEx-

ternalSynchronizationInputtoPhaseDetectorPin.Connect

I

(Pin 9/Pin 7): Current Comparator Sense Voltage

LIM

Range Input. Tying this pin to GND, FLOAT or INTV

CC

selects the maximum current sense threshold from three

different levels.

this pin to INTV to force continuous conduction mode

CC

of operation. Connect to GND to enable pulse-skipping

GND (Pin ±0/Pin 8, Exposed Pad Pin ±7): Ground. All

small-signalcomponentsandcompensationcomponents

shouldbeKelvinconnectedtothisground.The(–)terminal

mode of operation. To select Burst Mode operation, tie

this pin to INTV through a resistor no less than 50k,

CC

but no greater than 250k. A clock on the pin will cause

the controller to operate in forced continuous mode of

operation and synchronize the internal oscillator.

of CV and the (–) terminal of C should be closely con-

CC

IN

nected to this pin. The exposed pad should be soldered

to ground for good thermal conductivity.

FREQ/PLLFLTR (Pin 2/Pin ±6): The phase-locked loop’s

lowpass filter is tied to this pin. Alternatively, a resistor

can be connected between this pin and GND to vary the

frequency of the internal oscillator.

BG (Pin ±±/Pin 9): Bottom Gate Driver Output. This pin

drives the gate of the bottom N-channel MOSFET between

GND and INTV .

CC

INTV (Pin±2/Pin±0):Internal5VRegulatorOutput. The

CC

RUN (Pin 3/Pin ±): Run Control Input. A voltage above

1.22V on this pin turns on the IC. However, forcing this

pin below 1.1V causes the IC to shut down the IC. There

is a 2μA pull-up current on this pin.

control circuit is powered from this voltage. Decouple this

pin to GND with a minimum 2.2μF low ESR tantalum or

ceramic capacitor.

V (Pin ±3/Pin ±±): Main Input Supply. Decouple this pin

IN

TK/SS(Pin4/Pin2):OutputVoltageTrackingandSoft-Start

Input. A capacitor to ground at this pin sets the ramp rate

for the output voltage. An internal soft-start current of of

1μA charges this capacitor.

to GND with a capacitor.

BOOST (Pin ±4/Pin ±2): Boosted Floating Driver Supply.

The (+) terminal of the boost-strap capacitor is connected

to this pin. This pin swings from a diode voltage drop

I

(Pin 5/Pin 3): Current Control Threshold and Error

TH

below INTV up to V + INTV .

CC

IN

CC

Amplifier Compensation Point. The current comparator

TG (Pin ±5/Pin ±3): Top Gate Driver Output. This is the

tripping threshold increases with its I control voltage.

TH

output of a floating driver with a voltage swing equal to

FB (Pin 6/Pin 4): Error Amplifier Feedback Input. This pin

receives the remotely sensed feedback voltage from an

external resistive divider across the output.

INTV superimposed on the switch node voltage.

CC

SW (Pin ±6/Pin ±4): Switch Node Connection to the In-

ductor. Voltage swing at this pin is from a Schottky diode

–

SENSE (Pin7/Pin5):CurrentSenseComparatorInverting

(external) voltage drop below ground to V .

IN

Input.The(–)inputtothecurrentcomparatorisconnected

to the output.

+

SENSE (Pin 8/Pin 6): Current Sense Comparator Non-

inverting Input. The (+) input to the current comparator

is normally connected to the DCR sensing network or

current sensing resistor.

3851afa

8

LTC3851A

FuncTional DiagraM

V

IN

FREQ/PLLFLTR

MODE/PLLIN

V

IN

+

C

IN

100k

5V REG

0.8V

MODE/SYNC

DETECT

PLL-SYNC

–

+

BOOST

BURSTEN

C

B

TG

OSC

S

R

PULSE SKIP

ON

M1

Q

SW

SWITCH

LOGIC

AND

ANTI-

SHOOT

THROUGH

5k

+

SENSE

D

B

+

–

I

L1

I

REV

V

CMP

OUT

–

SENSE

+

–

RUN

OV

INTV

BG

CC

+

I

LIM

C

OUT

M2

C

VCC

SLOPE COMPENSATION

GND

INTV

CC

UVLO

1

100k

R2

R1

V

FB

I

THB

+

–

OV

0.88V

V

SLEEP

IN

RUN

SS

–

+

0.8V

REF

1µA

EA

+ –

–

+

0.64V

1.22V

2µA

0.4V

3851A FD

I

TH

RUN

TK/SS

C

SS

R

C

C1

3851afa

9

LTC3851A

operaTion

Main Control Loop

pull up the pin and enable that controller. Alternatively,

the RUN pin may be externally pulled up or driven directly

by logic. Be careful not to exceed the absolute maximum

rating of 6V on this pin.

The LTC3851A is a constant frequency, current mode

step-down controller. During normal operation, the top

MOSFET is turned on when the clock sets the RS latch,

and is turned off when the main current comparator, I

,

The start-up of the controller’s output voltage, V , is

CMP

OUT

resets the RS latch. The peak inductor current at which

resets the RS latch is controlled by the voltage on

controlled by the voltage on the TK/SS pin. When the

I

voltage on the TK/SS pin is less than the 0.8V internal

CMP

the I pin, which is the output of the error amplifier, EA.

reference, the LTC3851A regulates the V voltage to the

TH

FB

The V pin receives the voltage feedback signal, which is

TK/SS pin voltage instead of the 0.8V reference. This al-

lows the TK/SS pin to be used to program a soft-start by

connecting an external capacitor from the TK/SS pin to

GND.Aninternal1µApull-upcurrentchargesthiscapacitor

creating a voltage ramp on the TK/SS pin. As the TK/SS

voltage rises linearly from 0V to 0.8V (and beyond), the

FB

comparedtotheinternalreferencevoltagebytheEA.When

the load current increases, it causes a slight decrease in

V relative to the 0.8V reference, which in turn causes the

FB

TH

I

voltage to increase until the average inductor current

matches the new load current. After the top MOSFET has

turned off, the bottom MOSFET is turned on until either

the inductor current starts to reverse, as indicated by the

reverse current comparator, I , or the beginning of the

next cycle.

output voltage V

rises smoothly from zero to its final

OUT

value. Alternatively, the TK/SS pin can be used to cause

the start-up of V to track another supply. Typically,

REV

OUT

this requires connecting to the TK/SS pin an external

resistor divider from the other supply to ground (see the

Applications Information section). When the RUN pin

INTV Power

CC

is pulled low to disable the controller, or when INTV

CC

Power for the top and bottom MOSFET drivers and most

drops below its undervoltage lockout threshold of 3.2V,

the TK/SS pin is pulled low by an internal MOSFET. When

in undervoltage lockout, the controller is disabled and the

external MOSFETs are held off.

other internal circuitry is derived from the INTV pin. An

CC

internal 5V low dropout linear regulator supplies INTV

CC

power from V .

IN

The top MOSFET driver is biased from the floating boot-

strapcapacitor, C , whichnormallyrechargesduringeach

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping or Continuous Conduction)

B

off cycle through an external diode when the top MOSFET

turns off. If the input voltage, V , decreases to a voltage

IN

The LTC3851A can be enabled to enter high efficiency

BurstMode operation, constantfrequency pulse-skipping

mode or forced continuous conduction mode. To select

forced continuous operation, tie the MODE/PLLIN pin to

close to V , the loop may enter dropout and attempt

OUT

to turn on the top MOSFET continuously. The dropout

detector detects this and forces the top MOSFET off for

about 1/10 of the clock period every tenth cycle to allow

INTV . To select pulse-skipping mode of operation, float

CC

C to recharge. However, it is recommended that there is

B

the MODE/PLLIN pin or tie it to GND. To select Burst Mode

always a load present during the drop-out transition to

operation, tie MODE/PLLIN to INTV through a resistor

CC

ensure C is recharged.

B

no less than 50k, but no greater than 250k.

Shutdown and Start-Up (RUN and TK/SS)

When the controller is enabled for Burst Mode operation,

the peak current in the inductor is set to approximately

one-forth of the maximum sense voltage even though

The LTC3851A can be shut down using the RUN pin. Pull-

ing this pin below 1.1V disables the controller and most

of the internal circuitry, including the INTV regulator.

Releasing the RUN pin allows an internal 2µA current to

the voltage on the I pin indicates a lower value. If the

TH

CC

average inductor current is higher than the load current,

3851afa

10

LTC3851A

operaTion

Frequency Selection and Phase-Locked Loop

the error amplifier, EA, will decrease the voltage on the I

TH

(FREQ/PLLFLTR and MODE/PLLIN Pins)

pin. When the I voltage drops below 0.4V, the internal

TH

sleep signal goes high (enabling sleep mode) and both

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage. The switching fre-

quency of the LTC3851A can be selected using the FREQ/

PLLFLTR pin. If the MODE/PLLIN pin is not being driven

by an external clock source, the FREQ/PLLFLTR pin can

be used to program the controller’s operating frequency

from 250kHz to 750kHz.

external MOSFETs are turned off.

In sleep mode, the load current is supplied by the output

capacitor. Astheoutputvoltagedecreases, theEA’soutput

begins to rise. When the output voltage drops enough, the

sleep signal goes low, and the controller resumes normal

operation by turning on the top external MOSFET on the

next cycle of the internal oscillator. When a controller is

enabled for Burst Mode operation, the inductor current is

not allowed to reverse. The reverse current comparator,

I

, turnsoffthebottomexternalMOSFETjustbeforethe

REV

A phase-locked loop (PLL) is available on the LTC3851A

to synchronize the internal oscillator to an external clock

source that is connected to the MODE/PLLIN pin. The

controlleroperatesinforcedcontinuousmodeofoperation

when it is synchronized. A series RC should be connected

between the FREQ/PLLFLTR pin and GND to serve as the

PLL’s loop filter. It is suggested that the external clock be

applied before enabling the controller unless a second

resistorisconnectedinparallelwiththeseriesRCnetwork.

Thesecondresistorpreventsverylowswitchingfrequency

operation if the controller is enabled before the clock.

inductor current reaches zero, preventing it from revers-

ing and going negative. Thus, the controller operates in

discontinuous operation. In forced continuous operation,

the inductor current is allowed to reverse at light loads or

under large transient conditions. The peak inductor cur-

rent is determined by the voltage on the I pin, just as in

TH

normal operation. In this mode the efficiency at light loads

is lower than in Burst Mode operation. However, continu-

ous mode has the advantages of lower output ripple and

less interference to audio circuitry.

When the MODE/PLLIN pin is connected to GND, the

LTC3851A operates in PWM pulse-skipping mode at light

Output Overvoltage Protection

loads.Atverylightloadsthecurrentcomparator,I

,may

CMP

An overvoltage comparator, OV, guards against transient

overshoots (>10%) as well as other more serious con-

ditions that may overvoltage the output. In such cases,

the top MOSFET is turned off and the bottom MOSFET is

turned on until the overvoltage condition is cleared.

remaintrippedforseveralcyclesandforcetheexternaltop

MOSFET to stay off for the same number of cycles (i.e.,

skipping pulses). The inductor current is not allowed to

reverse (discontinuous operation). This mode, like forced

continuousoperation, exhibitslowoutputrippleaswellas

low audio noise and reduced RF interference as compared

to Burst Mode operation. It provides higher low current

efficiency than forced continuous mode, but not nearly as

high as Burst Mode operation.

3851afa

11

LTC3851A

applicaTions inForMaTion

The Typical Application on the first page of this data sheet

is a basic LTC3851A application circuit. The LTC3851A

can be configured to use either DCR (inductor resistance)

sensing or low value resistor sensing. The choice of the

two current sensing schemes is largely a design trade-off

between cost, power consumption and accuracy. DCR

sensing is becoming popular because it saves expensive

current sensing resistors and is more power efficient,

especially in high current applications. However, current

sensing resistors provide the most accurate current limits

for the controller. Other external component selection

is driven by the load requirement, and begins with the

V

IN

INTV

CC

BOOST

TG

R

LTC3851A

SENSE

V

OUT

SW

BG

GND

+

SENSE

–

SENSE

3851A F01

FILTER COMPONENTS

PLACED NEAR SENSE PINS

selection of R

(if R

is used) and the inductor

SENSE

value. Next, the power MOSFETs and Schottky diodes are

selected. Finally, input and output capacitors are selected.

The circuit shown on the first page can be configured for

Figure ±. Using a Resistor to Sense Current with the LTC385±A

The current comparator has a maximum threshold, V

,

MAX

operation up to 38V at V .

IN

determined by the I

setting. The current comparator

LIM

threshold sets the maximum peak of the inductor current,

Current Limit Programming

yieldingamaximumaverageoutputcurrent,I

,equalto

MAX

The I

pin is a tri-level logic input to set the maximum

the maximum peak value less half the peak-to-peak ripple

LIM

current limit of the controller. When I is grounded, the

current, ∆I . Allowing a margin of 20% for variations in

LIM

L

maximum current limit threshold of the current compara-

the IC and external component values yields:

tor is programmed to be 30mV. When I is floated, the

LIM

V_MAX

I_MAX+ ∆I_L/2

R_SENSE= 0.8 •

maximum current limit threshold is 50mV. When I

is

LIM

tied to INTV , the maximum current limit threshold is

CC

set to 75mV.

Inductor DCR Sensing

+

–

SENSE and SENSE Pins

Forapplicationsrequiringthehighestpossibleefficiency,

the LTC3851A is capable of sensing the voltage drop

across the inductor DCR, as shown in Figure 2. The

DCR of the inductor represents the small amount of

DC winding resistance of the copper, which can be less

than 1mΩ for today’s low value, high current inductors.

If the external R1||R2 • C1 time constant is chosen to

be exactly equal to the L/DCR time constant, the voltage

drop across the external capacitor is equal to the voltage

dropacrosstheinductorDCRmultipliedbyR2/(R1+R2).

Therefore,R2maybeusedtoscalethevoltageacrossthe

sense terminals when the DCR is greater than the target

sense resistance. Check the manufacturer’s data sheet

for specifications regarding the inductor DCR, in order

to properly dimension the external filter components.

The DCR of the inductor can also be measured using a

+

–

The SENSE and SENSE pins are the inputs to the current

comparators. The common mode input voltage range of

the current comparators is 0V to 5.5V. Both SENSE pins

are high impedance inputs with small base currents of

less than 1μA. When the SENSE pins ramp up from 0V

to 1.4V, the small base currents flow out of the SENSE

pins. When the SENSE pins ramp down from 5V to 1.1V,

the small base currents flow into the SENSE pins. The

high impedance inputs to the current comparators allow

accurate DCR sensing. However, care must be taken not

to float these pins during normal operation.

Low Value Resistors Current Sensing

A typical sensing circuit using a discrete resistor is shown

in Figure 1. R

current.

is chosen based on the required output

SENSE

good RLC meter.

3851afa

12

LTC3851A

applicaTions inForMaTion

Accepting larger values of ∆I allows the use of low

L

V

IN

V

IN

inductances, but results in higher output voltage ripple

INTV

CC

and greater core losses. A reasonable starting point for

BOOST

TG

setting ripple current is ∆I = 0.3(I

). The maximum

MAX

L

INDUCTOR

∆I occurs at the maximum input voltage.

L

LTC3851A

L

DCR

SW

V

OUT

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

BG

GND

R1

R2

+

SENSE

≈10% of the current limit determined by R

. Lower

SENSE

C1*

inductor values (higher ∆I ) will cause this to occur at

L

–

SENSE

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to increase.

L

+

–

3851A F02

R1||R2 • C1 =

*PLACE C1 NEAR SENSE , SENSE PINS

DCR

R2

R1 + R2

R

= DCR

SENSE(EQ)

Figure 2. Current Mode Control Using the Inductor DCR

Inductor Core Selection

Slope Compensation and Inductor Peak Current

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

fixedinductorvalue,butitisverydependentoninductance

selected. As inductance increases, core losses go down.

Unfortunately, increased inductance requires more turns

of wire and therefore copper losses will increase.

Slope compensation provides stability in constant fre-

quency architectures by preventing sub-harmonic oscil-

lations at high duty cycles. It is accomplished internally

by adding a compensating ramp to the inductor current

signal. Normally, this results in a reduction of maximum

inductor peak current for duty cycles > 40%. However, the

LTC3851A uses a novel scheme that allows the maximum

inductor peak current to remain unaffected throughout all

duty cycles.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates hard, which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Inductor Value Calculation

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smaller inductor and capacitor values. A higher frequency

generally results in lower efficiency because of MOSFET

gate charge losses. In addition to this basic trade-off, the

effect of inductor value on ripple current and low current

operation must also be considered.

Power MOSFET and Schottky Diode (Optional)

Selection

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆I decreases with higher

L

Two external power MOSFETs must be selected for the

LTC3851A controller: one N-channel MOSFET for the top

(main) switch, and one N-channel MOSFET for the bottom

(synchronous) switch.

inductance or frequency and increases with higher V :

IN









V_OUT

1

f •L

ΔI_L

=

V

1–

_OUT

V



IN

3851afa

13

LTC3851A

applicaTions inForMaTion

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.

CC

equation includes an additional term for transition losses,

This voltage is typically 5V during start-up. Consequently,

logic-level threshold MOSFETs must be used in most

applications. The only exception is if low input voltage

which are highest at high input voltages. For V < 20V,

IN

the high current efficiency generally improves with larger

MOSFETs, while for V > 20V, the transition losses rapidly

is expected (V < 5V); then, sub-logic level threshold

IN

GS(TH)

DSS

increasetothepointthattheuseofahigherR

device

MOSFETs (V

< 3V) should be used. Pay close atten-

specification for the MOSFETs as well;

DS(ON)

withlowerC

actuallyprovideshigherefficiency.The

tion to the BV

MILLER

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

short-circuit when the synchronous switch is on close to

100% of the period.

mostofthelogic-levelMOSFETsarelimitedto30Vorless.

Selection criteria for the power MOSFETs include the on-

resistance, R , Miller capacitance, C , input

DS(ON) MILLER

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

The term (1 + δ) is generally given for a MOSFET in the

C

MILLER

form of a normalized R

vs Temperature curve, but

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

DS(ON)

δ = 0.005/°C can be used as an approximation for low

MILLER

voltage MOSFETs.

along the horizontal axis while the curve is approximately

flat divided by the specified change in V . This result is

DS

TheoptionalSchottkydiodeconductsduringthedeadtime

between the conduction of the two power MOSFETs. This

preventsthebodydiodeofthebottomMOSFETfromturn-

ing on, storing charge during the dead time and requiring

a reverse recovery period that could cost as much as 3%

then multiplied by the ratio of the application applied V

DS

to the gate charge curve specified V . When the IC is

DS

operating in continuous mode, the duty cycles for the top

and bottom MOSFETs are given by:

in efficiency at high V . A 1A to 3A Schottky is generally

V_OUT

IN

Main Switch Duty Cycle =

a good size due to the relatively small average current.

Larger diodes result in additional transition losses due to

their larger junction capacitance.

V

IN

V – V

IN

OUT

Synchronous Switch Duty Cycle =

V

IN

Soft-Start and Tracking

The MOSFET power dissipations at maximum output

current are given by:

The LTC3851A has the ability to either soft-start by itself

with a capacitor or track the output of another channel

or external supply. When the LTC3851A is configured to

soft-start by itself, a capacitor should be connected to

the TK/SS pin. The LTC3851A is in the shutdown state if

the RUN pin voltage is below 1.10V. TK/SS pin is actively

pulled to ground in this shutdown state.

V_OUT

2

P_MAIN

=

I

1+ δ R

+

)

(

_MAX) (

)

DS(ON)

V

IN











I_MAX

2

V

R

C

)

(

•

(

)

²

(

IN

DR

MILLER







1

Once the RUN pin voltage is above 1.22V, the LTC3851A

powersup.Asoft-startcurrentof1μAthenstartstocharge

its soft-start capacitor. Note that soft-start or tracking is

achieved not by limiting the maximum output current of

the controller but by controlling the output ramp voltage

according to the ramp rate on the TK/SS pin. Current

foldback is disabled during this phase to ensure smooth

soft-start or tracking. The soft-start or tracking range is



(f)

+

V

– V_TH(MIN)

V

_TH(MIN)



 ^INTVCC



V – V

2

IN

OUT

P

=

I

1+ δ R

DS(ON)

(

_MAX) (

)

SYNC

V

IN

where δ is the temperature dependency of R

DR

and

DS(ON)

R

(approximately 2Ω) is the effective driver resistance

at the MOSFET’s Miller threshold voltage. V

is the

TH(MIN)

typical MOSFET minimum threshold voltage.

3851afa

14

LTC3851A

applicaTions inForMaTion

0V to 0.8V on the TK/SS pin. The total soft-start time can

be calculated as:

Output Voltage Tracking

The LTC3851A allows the user to program how its output

ramps up and down by means of the TK/SS pins. Through

this pin, the output can be set up to either coincidentally or

ratiometricallytrackwithanothersupply’soutput,asshown

C_SS

1.0µA

t_SOFT-START= 0.8 •

inFigure3. Inthefollowingdiscussions, V

refersto

Regardless of the mode selected by the MODE/PLLIN pin,

the regulator will always start in pulse-skipping mode up

to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.72V, it

will operate in forced continuous mode and revert to the

selected mode once TK/SS > 0.72V. The output ripple

is minimized during the 80mV forced continuous mode

window.

MASTER

a master supply and V

refers to the LTC3851A’s output

OUT

as a slave supply. To implement the coincident tracking

in Figure 3a, connect a resistor divider to V and

MASTER

connect its midpoint to the TK/SS pin of the LTC3851A.

The ratio of this divider should be selected the same as

thatoftheLTC3851A’sfeedbackdividerasshowninFigure

4a. In this tracking mode, V

must be higher than

MASTER

When the regulator is configured to track another supply,

the feedback voltage of the other supply is duplicated by a

resistordividerandappliedtotheTK/SSpin.Therefore,the

voltageramprateonthispinisdeterminedbytheramprate

of the other supply’s voltage. Note that the small soft-start

capacitor charging current is always flowing, producing

a small offset error. To minimize this error, one can select

the tracking resistive divider value to be small enough to

make this error negligible.

V

. To implement ratiometric tracking, the ratio of the

OUT

resistor divider connected to V

is determined by:

MASTER









V_OUT

R2 R3+ R4

=





V_MASTERR4 R1+ R2

So which mode should be programmed? While either

mode in Figure 4 satisfies most practical applications,

the coincident mode offers better output regulation.

This concept can be better understood with the help of

Figure 5. At the input stage of the error amplifier, two

common anode diodes are used to clamp the equivalent

reference voltage and an additional diode is used to match

the shifted common mode voltage. The top two current

sources are of the same amplitude. In the coincident

In order to track down another supply after the soft-start

phase expires, the LTC3851A must be configured for

forced continuous operation by connecting MODE/PLLIN

to INTV .

CC

V

MASTER

OUT

MASTER

V

OUT

3851A F03

TIME

(3a) Coincident Tracking

(3b) Ratiometric Tracking

Figure 3. Two Different Modes of Output Voltage Tracking

3851afa

15

LTC3851A

applicaTions inForMaTion

V

OUT

V

OUT

MASTER

R3

R1

R2

R3

R4

TO

TK/SS

TO

FB

TO

TK/SS

TO

FB

V

R4

3851A F04

(4a) Coincident Tracking Setup

(4b) Ratiometric Tracking Setup

Figure 4. Setup for Coincident and Ratiometric Tracking

what type of bulk capacitor is used, an additional 0.1μF

ceramic capacitor placed directly adjacent to the INTV

I

CC

and GND pins is highly recommended. Good bypassing

is needed to supply the high transient currents required

by the MOSFET gate drivers.

+

–

D1

D2

EA

TK/SS

0.8V

D3

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3851A to be

3851A F05

V

FB

Figure 5. Equivalent Input Circuit of Error Amplifier

exceeded. The INTV current, which is dominated by the

CC

gate charge current, is supplied by the 5V LDO.

mode, the TK/SS voltage is substantially higher than

0.8V at steady state and effectively turns off D1. D2 and

D3 will therefore conduct the same current and offer

Power dissipation for the IC in this case is highest and

is approximately equal to V • I

. The gate charge

IN INTVCC

current is dependent on operating frequency as discussed

intheEfficiencyConsiderationssection. Thejunctiontem-

perature can be estimated by using the equations given in

Note 3 of the Electrical Characteristics. For example, the

tight matching between V and the internal precision

FB

0.8V reference. In the ratiometric mode, however, TK/SS

equals 0.8V at steady state. D1 will divert part of the bias

current to make V slightly lower than 0.8V.

FB

LTC3851A INTV current is limited to less than 14mA

CC

Although this error is minimized by the exponential I-V

characteristic of the diode, it does impose a finite amount

ofoutputvoltagedeviation.Furthermore,whenthemaster

supply’s output experiences dynamic excursion (under

load transient, for example), the slave channel output will

be affected as well. For better output regulation, use the

coincident tracking mode instead of ratiometric.

from a 36V supply in the GN package:

T = 70°C + (14mA)(36V)(110°C/W) = 125°C

J

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (MODE/PLLIN

= INTV ) at maximum V .

CC

IN

INTV Regulator

CC

Topside MOSFET Driver Supply (C , D )

B

TheLTC3851AfeaturesaPMOSlowdropoutlinearregulator

An external bootstrap capacitor, C , connected to the

B

(LDO) that supplies power to INTV from the V supply.

CC

IN

BOOST pin supplies the gate drive voltage for the topside

INTV powersthegatedriversandmuchoftheLTC3851A’s

CC

MOSFET.CapacitorC intheFunctionalDiagramischarged

B

internal circuitry. The LDO regulates the voltage at the

though external diode D from INTV when the SW pin

B

CC

INTV pin to 5V.

CC

is low. When the topside MOSFET is to be turned on, the

driver places the C voltage across the gate source of the

The LDO can supply a peak current of 50mA and must

be bypassed to ground with a minimum of 2.2μF ceramic

capacitor or low ESR electrolytic capacitor. No matter

B

MOSFET. This enhances the MOSFET and turns on the

topside switch. The switch node voltage, SW, rises to V

IN

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16

LTC3851A

applicaTions inForMaTion

and the BOOST pin follows. With the topside MOSFET on,

the boost voltage is above the input supply:

C

Selection

OUT

The selection of C

is primarily determined by the effec-

OUT

tiveseriesresistance, ESR, tominimizevoltageripple. The

V

= V + V

IN INTVCC

BOOST

outputripple,ΔV ,incontinuousmodeisdeterminedby:

OUT

The value of the boost capacitor C needs to be 100 times

B







that of the total input capacitance of the topside MOSFET.

1

ΔV_OUT≈ ΔI ESR+

_L

The reverse breakdown of the external Schottky diode

8fC



_OUT

must be greater than V

.

IN(MAX)

where f = operating frequency, C

= output capacitance

Undervoltage Lockout

OUT

and ΔI = ripple current in the inductor. The output ripple

L

The LTC3851A has two functions that help protect the

controller in case of undervoltage conditions. A precision

is highest at maximum input voltage since ΔI increases

with input voltage. Typically, once the ESR require-

L

UVLOcomparatorconstantlymonitorstheINTV voltage

CC

ment for C

has been met, the RMS current rating

OUT

to ensure that an adequate gate-drive voltage is present.

generally far exceeds the I

requirement. With

RIPPLE(P-P)

and allowing 2/3 of the ripple to be

It locks out the switching action when INTV is below

CC

ΔI = 0.3I

L

OUT(MAX)

3.2V. To prevent oscillation when there is a disturbance

due to ESR, the output ripple will be less than 50mV at

maximum V if the I pin is configured to float and:

on the INTV , the UVLO comparator has 400mV of preci-

CC

IN

LIM

sion hysteresis.

C_OUTRequired ESR < 2.2R_SENSE

1

Another way to detect an undervoltage condition is to

monitor the V supply. Because the RUN pin has a preci-

IN

C_OUT

>

sion turn-on reference of 1.22V, one can use a resistor

8fR_SENSE

divider to V to turn on the IC when V is high enough.

IN

ThefirstconditionrelatestotheripplecurrentintotheESR

oftheoutputcapacitancewhilethesecondtermguarantees

thattheoutputcapacitancedoesnotsignificantlydischarge

duringtheoperatingfrequencyperiodduetoripplecurrent.

The choice of using smaller output capacitance increases

the ripple voltage due to the discharging term but can be

compensated for by using capacitors of very low ESR to

C Selection

IN

In continuous mode, the source current of the top N-

channel MOSFET is a square wave of duty cycle V

/

OUT

V . To prevent large voltage transients, a low ESR input

IN

capacitor sized for the maximum RMS current must be

used. The maximum RMS capacitor current is given by:

maintain the ripple voltage at or below 50mV. The I pin

TH







^1/2

OPTI-LOOP compensation components can be optimized

to provide stable, high performance transient response

regardless of the output capacitors selected.

V_OUT

V

OUT

IN

I_RMS≅ I_O(MAX)

– 1





V

IN

This formula has a maximum at V = 2V , where

The selection of output capacitors for applications with

largeloadcurrenttransientsisprimarilydeterminedbythe

voltage tolerance specifications of the load. The resistive

component of the capacitor, ESR, multiplied by the load

current change, plus any output voltage ripple must be

within the voltage tolerance of the load.

IN

OUT

I

= I

/2. This simple worst-case condition is

RMS

O(MAX)

commonly used for design because even significant

deviations do not offer much relief. Note that capacitor

manufacturers’ ripple current ratings are often based on

only 2000 hours of life. This makes it advisable to further

derate the capacitor or to choose a capacitor rated at a

higher temperature than required. Several capacitors may

also be paralleled to meet size or height requirements in

the design. Always consult the manufacturer if there is

any question.

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17

LTC3851A

applicaTions inForMaTion

The required ESR due to a load current step is:

ΔV

AVX TPSV or the KEMET T510 series of surface mount

tantalums, available in case heights ranging from 1.5mm

to 4.1mm. Aluminum electrolytic capacitors can be used

in cost-driven applications, provided that consideration is

given to ripple current ratings, temperature and long-term

reliability. Atypicalapplicationwillrequireseveraltomany

aluminum electrolytic capacitors in parallel. A combina-

tion of the above mentioned capacitors will often result

in maximizing performance and minimizing overall cost.

Other capacitor types include Nichicon PL series, NEC

Neocap, Panasonic SP and Sprague 595D series. Consult

manufacturers for other specific recommendations.

R_ESR

≤

ΔI

where∆Iisthechangeincurrentfromfullloadtozeroload

(or minimum load) and ∆V is the allowed voltage devia-

tion (not including any droop due to finite capacitance).

The amount of capacitance needed is determined by the

maximum energy stored in the inductor. The capacitance

must be sufficient to absorb the change in inductor

current when a high current to low current transition

occurs. The opposite load current transition is generally

determinedby thecontrolloop OPTI-LOOPcomponents,

so make sure not to over compensate and slow down

the response. The minimum capacitance to assure the

inductors’ energy is adequately absorbed is:

Like all components, capacitors are not ideal. Each ca-

pacitorhasitsownbenefitsandlimitations. Combinations

of different capacitor types have proven to be a very cost

effectivesolution.Rememberalsotoincludehighfrequency

decoupling capacitors. They should be placed as close as

possible to the power pins of the load. Any inductance

presentinthecircuitboardtracesnegatestheirusefulness.

2

L ΔI

(

)

C

>

OUT

2 ΔV V

(

)

OUT

Setting Output Voltage

where ∆I is the change in load current.

The LTC3851A output voltage is set by an external feed-

back resistive divider carefully placed across the output,

as shown in Figure 6. The regulated output voltage is

determined by:

Manufacturers such as Nichicon, United Chemi-Con and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor electrolyte

capacitor available from Sanyo has the lowest (ESR)

(size) product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

V

L

IN

ΔI_L(SC)= t_ON(MIN)

•

To improve the transient response, a feed-forward ca-

Insurfacemountapplications,ESR,RMScurrenthandling

and load step specifications may require multiple capaci-

tors in parallel. Aluminum electrolytic, dry tantalum and

special polymer capacitors are available in surface mount

packages.Specialpolymersurfacemountcapacitorsoffer

very low ESR but have much lower capacitive density per

unit volume than other capacitor types. These capacitors

offeraverycost-effectiveoutputcapacitorsolutionandare

an ideal choice when combined with a controller having

highloopbandwidth.Tantalumcapacitorsofferthehighest

capacitance density and are often used as output capaci-

tors for switching regulators having controlled soft-start.

Several excellent surge-tested choices are the AVX TPS,

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

V

OUT

R

B

C

FF

LTC3851A

V

FB

R

A

3851A F06

Figure 6. Settling Output Voltage

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18

LTC3851A

applicaTions inForMaTion

Fault Conditions: Current Limit and Current Foldback

Phase-Locked Loop and Frequency Synchronization

The LTC3851A includes current foldback to help limit

load current when the output is shorted to ground. If the

output falls below 40% of its nominal output level, the

maximum sense voltage is progressively lowered from

its maximum programmed value to about 25% of the that

value. Foldback current limiting is disabled during soft-

start or tracking. Under short-circuit conditions with very

low duty cycles, the LTC3851A will begin cycle skipping

in order to limit the short-circuit current. In this situation

the bottom MOSFET will be dissipating most of the power

but less than in normal operation. The short-circuit ripple

current is determined by the minimum on-time t_ON(MIN)

of the LTC3851A (≈90ns), the input voltage and inductor

value:

The LTC3851A has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (V ) and a

CO

phase detector. This allows the turn-on of the top MOSFET

to be locked to the rising edge of an external clock signal

applied to the MODE/PLLIN pin. This phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

The output of the phase detector is a pair of complemen-

tary current sources that charge or discharge the external

filter network connected to the FREQ/PLLFLTR pin. Note

that the LTC3851A can only besynchronized to an external

clock whose frequency is within range of the LTC3851A’s

internal V .This is guaranteed to be between 250kHz and









CO

R_B

R_A

V_OUT= 0.8V 1+



750kHz. A simplified block diagram is shown in Figure 8.



If the external clock frequency is greater than the internal

The resulting short-circuit current is:

oscillator’s frequency, f

, then current is sunk con-

OSC

tinuously from the phase detector output, pulling down

theFREQ/PLLFLTRpin.Whentheexternalclockfrequency

1/4MaxV_SENSE

R_SENSE

1

2

I_SC

=

– ΔI_L(SC)

is less than f , current is sourced continuously, pull-

OSC

ing up the FREQ/PLLFLTR pin. If the external and internal

frequencies are the same but exhibit a phase difference,

the current sources turn on for an amount of time corre-

spondingtothephasedifference.ThevoltageontheFREQ/

PLLFLTR pin is adjusted until the phase and frequency of

the internal and external oscillators are identical. At the

stable operating point, the phase detector output is high

Programming Switching Frequency

To set the switching frequency of the LTC3851A, connect

a resistor, R , between FREQ/PLLFLTR and GND. The

FREQ

relationship between the oscillator frequency and R

is shown in Figure 7. A 0.1µF bypass capacitor should be

FREQ

connected in parallel with R

.

FREQ

impedance and the filter capacitor C holds the voltage.

750

700

650

600

550

500

450

400

350

300

250

LP

R

LP

2.7V

C

LP

FREQ/PLLFLTR

VCO

MODE/

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

EXTERNAL

OSCILLATOR

20

40

60

80 100 120 140 160

(k)

R

FREQ

3851 F07

3851A F08

Figure 7. Relationship Between Oscillator Frequency

and Resistor Connected Between FREQ/PLLFLTR and GND

Figure 8. Phase-Locked Loop Block Diagram

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19

LTC3851A

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The minimum on-time for the LTC3851A is approximately

90ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases. This is of particu-

lar concern in forced continuous applications with low

ripple current at light loads. If the duty cycle drops below

the minimum on-time limit in this situation, a significant

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

The loop filter components, C and R , smooth out

LP

the current pulses from the phase detector and provide

a stable input to the voltage-controlled oscillator. The

filter components C and R determine how fast the

LP

loop acquires lock. Typically R is 1k to 10k and C is

LP

2200pF to 0.01μF.

When the external oscillator is active before the LTC3851A

is enabled, the internal oscillator frequency will track the

externaloscillatorfrequencyasdescribedinthepreceding

paragraphs. In situations where the LTC3851A is enabled

before the external oscillator is active, a low free-running

oscillatorfrequencyofapproximately50kHzwillresult.Itis

possibletoincreasethefree-running,pre-synchronization

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

frequency by adding a second resistor, R

, in parallel

FREQ

with R and C . R

will also cause a phase difference

LP

LP FREQ

between the internal and external oscillator signals. The

magnitudeofthephasedifferenceisinverselyproportional

%Efficiency = 100% – (L1 + L2 + L3 + ...)

to the value of R

. The free-running frequency may be

FREQ

where L1, L2, etc. are the individual losses as a percent-

age of input power.

programmed by using Figure 7 to determine the appropri-

ate value of R

. In order to maintain adequate phase

FREQ

margin for the PLL, the typical value for C is 0.01µF

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

LP

and for R is 1k.

LP

losses in LTC3851A circuits: 1) IC V current, 2) INTV

IN

CC

The external clock (on MODE/PLLIN pin) input high

threshold is nominally 1.6V, while the input low threshold

is nominally 1.2V.

2

regulator current, 3) I R losses, 4) topside MOSFET

transition losses.

1. The V current is the DC supply current given in the

IN

Minimum On-Time Considerations

ElectricalCharacteristicstable,whichexcludesMOSFET

driver current. V current typically results in a small

Minimum on-time, t

, is the smallest time dura-

ON(MIN)

IN

(<0.1%) loss.

tion that the LTC3851A is capable of turning on the top

MOSFET. Itisdeterminedbyinternaltimingdelaysandthe

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

2. INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

fromINTV_CCtoground. TheresultingdQ/dtisacurrent

out of INTV_CCthat is typically much larger than the

control circuit current. In continuous mode, I_GATECHG

= f(Q_T+ Q_B), where Q_Tand Q_Bare the gate charges of

the topside and bottom side MOSFETs.

V_OUT

t_ON(MIN)

<

V (f)

IN

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

3851afa

20

LTC3851A

applicaTions inForMaTion

2

3. I R losses are predicted from the DC resistances of

series resistance of C . ∆I

also begins to charge or

OUT

LOAD

the fuse (if used), MOSFET, inductor and current sense

resistor.Incontinuousmode,theaverageoutputcurrent

discharge C

generating the feedback error signal that

OUT

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recovery

flows through L and R

, but is chopped between

SENSE

OUT

the topside MOSFET and the synchronous MOSFET. If

time V

can be monitored for excessive overshoot or

OUT

thetwoMOSFETshaveapproximatelythesameR

,

ringing, which would indicate a stability problem. The

DS(ON)

then the resistance of one MOSFET can simply be

availability of the I pin not only allows optimization of

TH

summed with the resistances of L and R

to obtain

control loop behavior but also provides a DC coupled and

AC filtered closed-loop response test point. The DC step,

rise time and settling at this test point truly reflects the

closed-loop response. Assuming apredominantly second

ordersystem, phasemarginand/ordampingfactorcanbe

estimated using the percentage of overshoot seen at this

pin.Thebandwidthcanalsobeestimatedbyexaminingthe

SENSE

= 10mΩ, DCR

2

I R losses. For example, if each R

DS(ON)

= 10mΩ and R

= 5mΩ, then the total resistance

SENSE

is 25mΩ. This results in losses ranging from 2% to

8% as the output current increases from 3A to 15A for

a 5V output, or a 3% to 12% loss for a 3.3V output.

Efficiency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

rise time at the pin. The I external components shown

TH

in the Typical Application circuit will provide an adequate

starting point for most applications.

The I series R -C filter sets the dominant pole-zero

TH

C

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

2

Transition Loss = (1.7)V • I

• C

• f

IN

O(MAX)

RSS

Other hidden losses such as copper trace and the battery

internal resistance can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these system level losses during the

design phase. The internal battery and fuse resistance

produce output voltage and I pin waveforms that will

TH

give a sense of the overall loop stability without break-

ing the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This is

losses can be minimized by making sure that C has ad-

IN

equate charge storage and very low ESR at the switching

frequency.A25Wsupplywilltypicallyrequireaminimumof

20μF to 40μF of capacitance having a maximum of 20mΩ

to 50mΩ of ESR. Other losses including Schottky con-

duction losses during dead time and inductor core losses

generally account for less than 2% total additional loss.

why it is better to look at the I pin signal which is in the

TH

feedback loop and is the filtered and compensated control

loop response. The midband gain of the loop will be in-

Checking Transient Response

creased by increasing R and the bandwidth of the loop

C

will be increased by decreasing C . If R is increased by

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V

amount equal to ∆I

C

the same factor that C is decreased, the zero frequency

C

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

3851afa

shifts by an

OUT

(ESR), where ESR is the effective

LOAD

21

LTC3851A

applicaTions inForMaTion

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3851A. These items are also illustrated graphically

in the layout diagram of Figure 9. Check the following in

your layout:

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

1. Are the board signal and power grounds segregated?

The LTC3851A GND pin should tie to the ground plane

closetotheinputcapacitor(s).Thelowcurrentorsignal

ground lines should make a single point tie directly to

the GND pin. The synchronous MOSFET source pins

should connect to the input capacitor(s) ground.

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10μF capacitor would

LOAD

require a 250μs rise time, limiting the charging current

to about 200mA.

+

0.1µF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

MODE/PLLIN

SW

TG

R

FREQ

C

IN

M1

FREQ/PLLFLTR

C

D

B

RUN

BOOST

V

IN

LTC3851A

C

SS

TK/SS

V

IN

B

C

C2

C

R

C

I

TH

INTV

CC

47pF

+

M2

V

BG

4.7µF

FB

–

+

SENSE

GND

–

1000pF

10Ω

I

LIM

L1

10Ω

–

R1

C

OUT

V

OUT

+

R

SENSE

R2

3851A F09

Figure 9. LTC385±A Layout Diagram

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22

LTC3851A

applicaTions inForMaTion

2. Does the V pin connect directly to the feedback resis-

PC Board Layout Debugging

FB

tors? The resistive divider R1, R2 must be connected

It is helpful to use a DC-50MHz current probe to monitor

thecurrentintheinductorwhiletestingthecircuit.Monitor

the output switching node (SW pin) to synchronize the

oscilloscope to the internal oscillator and probe the actual

outputvoltageaswell. Checkforproperperformanceover

the operating voltage and current range expected in the

application. The frequency of operation should be main-

tained over the input voltage range down to dropout and

until the output load drops below the low current opera-

tion threshold—typically 10% of the maximum designed

current level in Burst Mode operation.

between the (+) plate of C

and signal ground. The

OUT

47pF to 100pF capacitor should be as close as pos-

sible to the LTC3851A. Be careful locating the feedback

resistors too far away from the LTC3851A. The V line

FB

should not be routed close to any other nodes with high

slew rates.

–

+

3. Are the SENSE and SENSE leads routed together

with minimum PC trace spacing? The filter capacitor

+

–

between SENSE and SENSE should be as close as

possible to the LTC3851A. Ensure accurate current

sensingwithKelvinconnectionsasshowninFigure 10.

Series resistance can be added to the SENSE lines to

increase noise rejection and to compensate for the ESL

The duty cycle percentage should be maintained from

cycle to cycle in a well designed, low noise PCB imple-

mentation. Variation in the duty cycle at a subharmonic

rate can suggest noise pick-up at the current or voltage

sensing inputs or inadequate loop compensation. Over-

compensation of the loop can be used to tame a poor PC

layout if regulator bandwidth optimization is not required.

of R

.

SENSE

4. Does the (+) terminal of C connect to the drain of

IN

the topside MOSFET(s) as closely as possible? This

capacitor provides the AC current to the MOSFET(s).

5. Is the INTV decoupling capacitor connected closely

Reduce V from its nominal level to verify operation

CC

IN

between INTV and GND? This capacitor carries the

of the regulator in dropout. Check the operation of the

CC

MOSFETdriverpeakcurrents.Anadditional1μFceramic

undervoltage lockout circuit by further lowering V while

IN

capacitor placed immediately next to the INTV and

monitoring the outputs to verify operation.

CC

GND pins can help improve noise performance.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

6. Keep the switching node (SW), top gate node (TG) and

boost node (BOOST) away from sensitive small-signal

nodes, especially from the voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on

the output side (Pin 9 to Pin 16) of the LTC3851AEGN

and occupy minimum PC trace area.

HIGH CURRENT PATH

for inductive coupling between C , the Schottky and the

IN

top MOSFET to the sensitive current and voltage sens-

ing traces. In addition, investigate common ground path

voltage pickup between these components and the GND

pin of the IC.

3851A F10

CURRENT SENSE

RESISTOR

(R

)

SENSE

+

–

SENSE SENSE

Figure ±0. Kelvin Sensing R_SENSE

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23

LTC3851A

applicaTions inForMaTion

Design Example

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

As a design example, assume V = 12V (nominal), V =

IN

MAX

IN

results in: R

= 0.035Ω/0.022Ω, C

= 215pF. At

DS(ON)

MILLER

22V (maximum), V

Refer to Figure 13.

= 1.8V, I

= 5A, and f = 250kHz.

OUT

maximum input voltage with T (estimated) = 50°C:

1.8V

22V

²



1+ 0.005 50°C − 25°C •



The inductance value is chosen first based on a 30%

ripple current assumption. The highest value of ripple

current occurs at the maximum input voltage. Connect a

160k resistor between the FREQ/PLLFLTR and GND pins,

generating 250kHz operation. The minimum inductance

for 30% ripple current is:

P_MAIN

=

5

( )

(

)

(

)





²









5A

2

0.035Ω + 22V

) (

2Ω 215pF •

) (

(

)

(

)





1

+

250kHz = 185mW

(

)









5− 2.3 2.3









V_OUT

1

ΔI_L=

V

1−

_OUT

A short circuit to ground will result in a folded back cur-

rent of:

f L

( ) ( )

V



IN

A 4.7µH inductor will produce 28% ripple current and a

3.3µH will result in 40%. The peak inductor current will be

the maximum DC value plus one-half the ripple current, or

6A, for the 3.3µH value. Increasing the ripple current will

also help ensure that the minimum on-time of 90ns is not













90ns 22V

29mV

0.0125Ω 2

1

(

)

I_SC=

–

= 2.02A

3.3µH

with a typical value of R

= 0.125. The resulting power dissipated in the bottom

and δ = (0.005/°C)(25°C)

DS(ON)

violated. The minimum on-time occurs at maximum V :

IN

MOSFET is:

V_OUT

1.8V

22V

= 101.0mW

2

t_ON(MIN)

=

= 327ns

P

=

2.02A 1.125 0.022Ω

(

) (

)

SYNC

V

f

22V 250kHz

_IN(MAX)( )

(

)

The R

resistor value can be calculated by connect-

SENSE

ing I to INTV and using the maximum current sense

which is less than under full-load conditions.

C is chosen for an RMS current rating of at least 3A at

LIM

CC

voltage specification with some accommodation for toler-

IN

ances. Tie I to INTV .

LIM

CC

temperature. C

is chosen with an ESR of 0.02Ω for

OUT

75mV

6A

low output ripple. The output ripple in continuous mode

will be highest at the maximum input voltage. The output

voltage ripple due to ESR is approximately:

R_SENSE

≤

= 0.0125Ω, so 0.01Ω is selected

Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

V

= R

(∆I ) = 0.02Ω (2A) = 40mV

ORIPPLE

ESR L P-P

3851afa

24

LTC3851A

Typical applicaTions

V

IN

4.5V TO 32V

MODE/PLLIN

V

IN

+

C

R

IN

FREQ

22µF

82.5k

M1

FREQ/PLLFLTR

TG

BOOST

SW

HAT2170H

L1

C

B

0.1µF

RUN

C20

0.1µF

C

SS

LTC3851A

0.1µF

0.68µH

V

3.3V

15A

OUT

TK/SS

C

D

R

C2

B

R2

154k

1%

C

2200pF

R27

C15

47pF

330pF

CMDSH05-4

15k

3.01k

I

INTV

CC

TH

+

C

OUT

4.7µF

330µF

M2

HAT2170H

×2

R1

48.7k

1%

V

BG

FB

–

+

SENSE

GND

C5

0.047µF

30.1k

C

: SANYO 6TPE330MIL

OUT

IN

I

LIM

: SANYO 63HVH22M

L1: VISHAY IHLP5050-EZERR68MO1

3851A F11

Figure ±±. High Efficiency 3.3V/±5A Step-Down Converter

V

IN

6V TO 14V

PLLIN

350kHz

MODE/PLLIN

V

IN

C2

+

R5

1k

C

IN

180µF

0.01µF

M1

FREQ/PLLFLTR

TG

BOOST

SW

RJK0305DPB

C

B

0.1µF

RUN

C

SS

0.1µF

L1

0.68µH

C1

R

SENSE

0.002Ω

LTC3851A

1000pF

V

1.5V

15A

OUT

TK/SS

C

D

B

R

C

R2

43.2k

1%

C

C2

1000pF

CMDSH-3

C10

33pF

7.5k

100pF

I

TH

INTV

CC

+

C

OUT

4.7µF

330µF

M2

RJK0301DPB

R1

20k

1%

×2

V

FB

BG

–

+

SENSE

GND

1000pF

SENSE

I

C

: SANYO 2R5TPE330M9

OUT

LIM

L1: SUMIDA CEP125-OR6MC

R22 10Ω

R20 10Ω

3851A F12

Figure ±2. ±.5V/±5A Synchronized at 350kHz

3851afa

25

LTC3851A

package DescripTion

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 ±.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ±.0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 ± .004

(0.38 ± 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

3851afa

26

LTC3851A

package DescripTion

UD Package

16-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1691)

0.70 ±0.05

3.50 ± 0.05

2.10 ± 0.05

1.45 ± 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 × 45° CHAMFER

R = 0.115

TYP

0.75 ± 0.05

3.00 ± 0.10

(4 SIDES)

15 16

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

1

2

1.45 ± 0.10

(4-SIDES)

(UD16) QFN 0904

0.200 REF

0.25 ± 0.05

0.00 – 0.05

0.50 BSC

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3851afa

27

LTC3851A

package DescripTion

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev C)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 ± 0.102

(.112 ± .004)

2.845 ± 0.102

(.112 ± .004)

0.889 ± 0.127

(.035 ± .005)

1

8

0.35

REF

5.23

(.206)

MIN

1.651 ± 0.102

(.065 ± .004)

1.651 ± 0.102

(.065 ± .004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

16

9

0.305 ± 0.038

0.50

(.0197)

BSC

NO MEASUREMENT PURPOSE

4.039 ± 0.102

(.159 ± .004)

(NOTE 3)

(.0120 ± .0015)

TYP

0.280 ± 0.076

(.011 ± .003)

RECOMMENDED SOLDER PAD LAYOUT

16151413121110

9

REF

DETAIL “A”

0° – 6° TYP

0.254

(.010)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

GAUGE PLANE

0.53 ± 0.152

(.021 ± .006)

1 2 3 4 5 6 7 8

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ± 0.0508

(.004 ± .002)

MSOP (MSE16) 0910 REV C

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3851afa

28

LTC3851A

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

6/11

Added H-Grade and MP-Grade parts. Reflected throughout the data sheet.

1-30

3851afa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29

LTC3851A

Typical applicaTion

V

IN

4.5V TO 22V

MODE/PLLIN

V

IN

+

C

22µF

25V

IN

R

FREQ

160k

M1A

FREQ/PLLFLTR

TG

BOOST

SW

FDS6982S

L1

C

B

0.1µF

RUN

0.1µF

C

SS

R

SENSE

LTC3851A

0.1µF

3.3µH

V

1.8V

5A

0.01Ω

OUT

TK/SS

C

D

C

B

R

C

470pF

C2

CMDSH-3

R2

33k

220pF

32.4k

1%

C

I

INTV

CC

OUT

TH

+

150µF

6.3V

×2

4.7µF

M1B

FDS6982S

R1

25.5k

1%

V

BG

FB

PANASONIC SP

–

+

SENSE

GND

1000pF

I

LIM

C

: PANASONIC EEFUEOG151R

10Ω 10Ω

OUT

IN

: MARCON THCR70LE1H226ZT

L1: PANASONIC ETQP6F3R3HFA

: IRC LR 2010-01-R010F

R

SENSE

3851A F13

Figure ±3. ±.8V/5A Converter from Design Example with Pulse-Skipping Operation

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC3854

Small Footprint Wide V Range Synchronous Step-Down DC/ Fixed 400kHz Operating Frequency, 4.5V≤ V ≤ 38V,

IN

DC Controller

0.8V ≤ V

≤ 5.25V, 2mm × 3mm QFN-12

OUT

LTC3878

LTC3879

No R ™ Constant On-Time Synchronous Step-Down DC/

Very Fast Transient Response, t

= 43ns, 4V≤ V ≤ 38V,

IN

SENSE

ON(MIN)

DC Controller

0.8V ≤ V

≤ 0.9V , SSOP-16

OUT IN

No R Constant On-Time Synchronous Step-Down DC/DC Very Fast Transient Response, t

= 43ns, 4V≤ V ≤ 38V,

SENSE

ON(MIN)

IN

Controller

0.6V ≤ V

≤ 0.9V , MSOP-16E, 3mm × 3mm QFN-16

OUT IN

LTC3850/LTC3850-1 Dual 2-Phase, High Efficiency Synchronous Step-Down DC/DC Phase-Lockable Fixed Operating Frequency 250kHz to 780kHz,

LTC3850-2

LTC3853

Controllers, R

or DCR Current Sensing and Tracking

4V≤ V ≤ 30V, 0.8V ≤ V

≤ 5.25V

SENSE

IN

OUT

Triple Output, Multiphase Synchronous Step-Down DC/DC

Controller, R or DCR Current Sensing and Tracking

Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz,

4V≤ V ≤ 24V, V Up to 13.5V

SENSE

IN

OUT

LTC3610

LTC3611

LTC3775

12A, 1MHz, Monolithic Synchronous Step-Down DC/DC

Converter

High Efficiency, Adjustable Constant On-Time, 4V≤ V ≤ 24V,

IN

OUT(MIN)

V

= 0.6V, 9mm × 9mm QFN-64

10A, 1MHz, Monolithic Synchronous Step-Down DC/DC

Converter

High Efficiency, Adjustable Constant On-Time, 4V≤ V ≤ 32V,

IN

V

= 0.6V, 9mm × 9mm QFN-64

OUT(MIN)

High Frequency Synchronous Voltage Mode Step-Down DC/DC Synchronizable Fixed Frequency 250kHz to 1MHz,

Controller

t

= 30ns, 4V ≤ V ≤ 38V, 0.6V ≤ V

≤ 0.8V ,

OUT IN

ON(MIN)

IN

MSOP-16E, 3mm × 3mm QFN-16

3851afa

LT 0611 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

30

●

 LINEAR TECHNOLOGY CORPORATION 2010

(408)432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3851AEUD#PBF
厂家：	Linear
描述：	LTC3851A - Synchronous Step-Down Switching Regulator Controller; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C 开关
文件：	总30页 (文件大小：429K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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