LTC3851AIMSE-1#PBF [Linear]
LTC3851A-1 - Synchronous Step-Down Switching Regulator Controller; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C;型号: | LTC3851AIMSE-1#PBF |
厂家: | Linear |
描述: | LTC3851A-1 - Synchronous Step-Down Switching Regulator Controller; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
文件: | 总30页 (文件大小:424K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3851A-1
Synchronous
Step-Down Switching
Regulator Controller
FeaTures
DescripTion
The LTC®3851A-1 is a high performance synchronous
step-down switching regulator controller that drives
an all N-channel synchronous power MOSFET stage. A
constant frequency current mode architecture allows a
n
Wide V Range: 4V to 38V Operation
SENSE
±±1 Output Voltage Accuracy
Power Good Output Voltage Monitor
IN
n
R
or DCR Current Sensing
n
n
n
n
n
n
n
n
n
n
Phase-Lockable Fixed Frequency: 250kHz to 750kHz phase-lockable frequency of up to 750kHz.
Dual N-Channel MOSFET Synchronous Drive
OPTI-LOOP compensation allows the transient response
Very Low Dropout Operation: 99% Duty Cycle
to be optimized over a wide range of output capacitance
Adjustable Output Voltage Soft-Start or Tracking
andESRvalues.TheLTC3851A-1featuresaprecision0.8V
Output Current Foldback Limiting
reference and a power good indicator. A wide 4V to 38V
Output Overvoltage Protection
(40Vabsolutemaximum)inputsupplyrangeencompasses
OPTI-LOOP® Compensation Minimizes C
OUT
mostbatteryconfigurationsandintermediatebusvoltages.
Selectable Continuous, Pulse-Skipping or
Burst Mode® Operation at Light Loads
TheTK/SSpinrampstheoutputvoltageduringstart-upand
n
n
n
shutdown with coincident or ratiometric tracking. Current
foldback limits MOSFET heat dissipation during short-
circuit conditions. The MODE/PLLIN pin selects among
Burst Mode operation, pulse-skipping mode or continu-
ous inductor current mode at light loads and allows the IC
to be synchronized to an external clock. The LTC3851A-1
contains an improved PLL compared to the LTC3851-1.
Low Shutdown I : 20µA
Q
V
Range: 0.8V to 5.5V
OUT
Thermally Enhanced 16-Lead MSOP
or 3mm × 3mm QFN Package
applicaTions
n
Automotive Systems
The LTC3851A-1 is identical to the LTC3851A except that
the I pin is replaced by PGOOD.
n
Telecom Systems
LIM
n
Industrial Equipment
Distributed DC Power Systems
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are registered
n
trademarks and No R , UltraFast are trademarks of Linear Technology Corporation. All other
SENSE
trademarks are the property of their respective owners. Protected by U.S. Patents including
5408150, 5481178, 5705919, 5929620, 6304066, 6498466, 6580258, 6611131.
Typical applicaTion
Efficiency and Power Loss
vs Load Current
High Efficiency Synchronous Step-Down Converter
100k
V
IN
4.5V TO 38V
100
95
10000
1000
100
PGO0D
FREQ/PLLFLTR TG
INTV
V
CC
IN
V
V
= 12V
IN
OUT
22µF
= 3.3V
0.68µH
3.01k
V
3.3V
15A
EFFICIENCY
OUT
0.1µF
90
82.5k
RUN
SW
LTC3851A-1
0.1µF
85
TK/SS
BOOST
330µF
×2
80
75
0.1µF
POWER LOSS
INTV
CC
2200pF
70
65
60
55
50
4.7µF
BG
I
TH
GND
15k
330pF
+
SENSE
MODE/PLLIN
SENSE
0.047µF
30.1k
10
–
154k
10
100
1000
10000
100000
V
FB
LOAD CURRENT (mA)
3851A1 TA01b
48.7k
3851A1 TA01a
3851a1fa
1
LTC3851A-1
absoluTe MaxiMuM raTings (Note ±)
Input Supply Voltage (V )......................... 40V to –0.3V
INTV Peak Output Current..................................50mA
IN
CC
Topside Driver Voltage (BOOST)................ 46V to –0.3V
Switch Voltage (SW).....................................40V to –5V
Operating Junction Temperature Range (Notes 2, 3)
E-Grade, I-Grade................................–40°C to 125°C
H-Grade ............................................. –40°C to 150°C
MP-Grade .......................................... –55°C to 150°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
INTV , (BOOST – SW), RUN, PGOOD........ 6V to –0.3V
CC
TK/SS ...................................................INTV to –0.3V
CC
+
–
SENSE , SENSE .......................................... 6V to –0.3V
MODE/PLLIN, FREQ/PLLFLTR ..............INTV to –0.3V
CC
I , V Voltages ......................................... 3V to –0.3V
MSE..................................................................300°C
TH FB
pin conFiguraTion
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
MODE/PLLIN
FREQ/PLLFLTR
RUN
16 SW
16 15 14 13
15 TG
14 BOOST
RUN
1
2
3
4
12 BOOST
17
GND
TK/SS
13 V
IN
TK/SS
11
10
9
V
IN
I
12 INTV
11 BG
TH
CC
17
GND
FB
–
I
INTV
BG
TH
CC
SENSE
10 GND
+
SENSE
9
PGOOD
FB
MSE PACKAGE
16-LEAD PLASTIC MSOP
5
6
7
8
T
= 125°C, θ = 35°C/W TO 40°C/W
JA
JMAX
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
= 125°C, θ = 68°C/W, θ = 4.2°C/W
T
JMAX
JA
JC
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
3851A1
3851A1
3851A1
3851A1
LFQB
PACKAGE DESCRIPTION
16-Lead Plastic MSOP
TEMPERATURE RANGE
LTC3851AEMSE-1#PBF
LTC3851AIMSE-1#PBF
LTC3851AHMSE-1#PBF
LTC3851AEMSE-1#TRPBF
LTC3851AIMSE-1#TRPBF
LTC3851AHMSE-1#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
16-Lead Plastic MSOP
16-Lead Plastic MSOP
LTC3851AMPMSE-1#PBF LTC3851AMPMSE-1#TRPBF
16-Lead Plastic MSOP
LTC3851AEUD-1#PBF
LTC3851AIUD-1#PBF
LTC3851AEUD-1#TRPBF
LTC3851AIUD-1#TRPBF
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
LFQB
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3851a1fa
2
LTC3851A-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = ±5V, VRUN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
V
V
Input Operating Voltage Range
Regulated Feedback Voltage
4
38
V
IN
l
l
l
l
I
TH
I
TH
I
TH
I
TH
= 1.2V (Note 4) 0°C to 85°C
0.792
0.788
0.788
0.788
0.800
0.808
0.812
0.812
0.812
V
V
V
V
FB
= 1.2V (Note 4) –40°C to 125°C
= 1.2V (Note 4) –40°C to 150°C
= 1.2V (Note 4) –55°C to 150°C
I
Feedback Current
(Note 4)
= 6V to 38V (Note 4)
–10
–50
nA
FB
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
IN
0.002
0.02
%/V
REFLNREG
(Note 4) Measured in Servo Loop,
LOADREG
l
l
∆I = 1.2V to 0.7V
0.01
0.1
0.2
%
%
TH
(Note 4) Measured in Servo Loop,
∆I = 1.2V to 0.7V (H-Grade, MP-Grade)
TH
(Note 4) Measured in Servo Loop,
l
l
∆I = 1.2V to 1.6V
–0.01
–0.1
–0.2
%
TH
(Note 4) Measured in Servo Loop,
∆I = 1.2V to 1.6V (H-Grade, MP-Grade)
%
mmho
MHz
TH
g
g
Transconductance Amplifier g
I
TH
I
TH
= 1.2V, Sink/Source = 5µA (Note 4)
= 1.2V (Note 8)
2
3
m
m
GBW
Transconductance Amp Gain Bandwidth
m
I
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
Q
V
V
= 5V
= 0V
1
25
mA
µA
RUN
RUN
50
UVLO
Undervoltage Lockout on INTV
UVLO Hysteresis
V
Ramping Down
INTVCC
3.25
0.4
1
V
V
CC
UVLO Hys
I
I
SENSE Pins Current
2
2
µA
µA
V
SENSE
TK/SS
Soft-Start Charge Current
RUN Pin On—Threshold
RUN Pin On—Hysteresis
V
V
= 0V
0.6
1
TK/SS
l
V
V
V
Rising
RUN
1.10
1.22
120
53
1.35
RUN
mV
RUNHYS
SENSE(MAX)
l
l
Maximum Current Sense Threshold
V
V
= 0.7V, V
= 0.7V, V
= 3.3V
40
35
65
70
mV
mV
FB
FB
SENSE
SENSE
= 3.3V (H-Grade, MP-Grade)
TG R
TG R
BG R
BG R
TG Driver Pull-Up On-Resistance
TG Driver Pull-Down On-Resistance
BG Driver Pull-Up On-Resistance
BG Driver Pull-Down On-Resistance
TG High
TG Low
BG High
BG Low
(Note 6)
2.2
1.2
2.1
1.1
Ω
Ω
Ω
Ω
UP
DOWN
UP
DOWN
TG Transition Time
Rise Time
Fall Time
TG t
TG t
C
C
= 3300pF
= 3300pF
25
25
ns
ns
r
f
LOAD
LOAD
BG Transition Time
Rise Time
Fall Time
(Note 6)
BG tr
BG tf
C
C
= 3300pF
= 3300pF
25
25
ns
ns
LOAD
LOAD
TG/BG t
Top Gate Off to Bottom Gate On Delay
Bottom Switch-On Delay Time
C
= 3300pF Each Driver
30
30
90
ns
ns
ns
1D
2D
LOAD
(Note 6)
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
C
= 3300pF Each Driver
LOAD
(Note 6)
t
Minimum On-Time
(Note 7)
ON(MIN)
INTV Linear Regulator
CC
V
V
Internal V Voltage
6V < V < 38V
4.8
5
5.2
V
INTVCC
CC
IN
INT
INTV Load Regulation
I = 0mA to 50mA
CC
0.5
%
LDO
CC
3851a1fa
3
LTC3851A-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = ±5V, VRUN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
f
f
f
Nominal Frequency
R
R
R
= 60k
= 160k
= 36k
460
205
690
500
235
750
100
540
265
810
kHz
kHz
kHz
kΩ
NOM
LOW
HIGH
FREQ
FREQ
FREQ
Lowest Frequency
Highest Frequency
R
MODE/PLLIN Input Resistance
MODE/PLLIN
MODE
f
I
MODE/PLLIN Minimum Input Frequency
MODE/PLLIN Maximum Input Frequency V
V
MODE
MODE
= External Clock
= External Clock
250
750
kHz
kHz
Phase Detector Output Current
Sinking Capability
Sourcing Capability
FREQ
f
f
> f
< f
–90
75
µA
µA
MODE
MODE
OSC
OSC
PGOOD Output
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.1
0.3
1
V
PGL
PGOOD
I
V
V
µA
PGOOD
PGOOD
V
PG
with Respect to Set Regulated Voltage
Ramping Negative (UV)
Ramping Positive (OV)
FB
V
V
–12.5
7.5
–10
10
–7.5
12.5
%
%
FB
FB
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: T is calculated from the ambient temperature T and power
J A
dissipation P according to the following formulas:
D
LTC3851AMSE-1: T = T + (P • 40°C/W)
J
A
D
LTC3851AUD-1: T = T + (P • 68°C/W)
J
A
D
Note 2: The LTC3851A-1 is tested under pulsed load conditions such that
Note 4: The LTC3851A-1 is tested in a feedback loop that servos V to a
ITH
T ≈ T . The LTC3851AE-1 is guaranteed to meet performance
A
J
specified voltage and measures the resultant V
.
FB
specifications from 0°C to 85°C junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3851AI-1 is guaranteed to meet specifications over the –40°C
to 125°C operating junction temperature range, the LTC3851AH-1 is
guaranteed over the –40°C to 150°C operating junction temperature range
and the LTC3851AMP-1 is tested and guaranteed over the –55°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes; operating lifetime is derated for junction temperatures
greater than 125°C. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels. Rise and fall times are assured by
design, characterization and correlation with statistical process controls.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ~40% of I
(see Minimum On-Time
MAX
Considerations in the Applications Information section).
Note 8: Guaranteed by design; not tested in production.
3851a1fa
4
LTC3851A-1
Typical perForMance characTerisTics
Efficiency vs Output Current
and Mode
Efficiency vs Output Current
and Mode
100
90
100
90
V
V
= 12V
IN
OUT
= 1.5V
BURST
80
80
BURST
70
70
PULSE
SKIP
60
50
60
50
PULSE
SKIP
CCM
40
30
20
10
0
40
30
20
10
0
CCM
V
V
= 12V
IN
OUT
= 3.3V
FIGURE 11 CIRCUIT
10
100
1000
10000 100000
10
100
1000
10000
100000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3851A1 G02
3851A1 G01
Efficiency vs Output Current
and Mode
Efficiency and Power Loss
vs Input Voltage
100
90
100
95
10000
1000
100
EFFICIENCY,
OUT
I
= 5A
POWER LOSS,
= 5A
80
I
BURST
OUT
70
90
PULSE
SKIP
60
50
85
80
EFFICIENCY,
= 0.5A
CCM
I
40
30
20
10
0
OUT
POWER LOSS,
I
= 0.5A
OUT
V
V
= 12V
75
70
IN
OUT
V
V
= 12V
OUT
= 3.3V
IN
= 5V
FIGURE 11 CIRCUIT
10
100
1000
10000
100000
4
8
12
16
20 28
24 32
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
3851A1 G03
3851A1 G04
Load Step
(Forced Continuous Mode)
Load Step
(Burst Mode Operation)
I
I
LOAD
LOAD
5A/DIV
5A/DIV
0.2A TO 7.5A
0.2A TO 7.5A
I
L
I
L
5A/DIV
5A/DIV
V
OUT
V
OUT
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
3851A1 G05
3851A1 G06
V
V
= 1.5V
100µs/DIV
V
V
= 1.5V
OUT
100µs/DIV
OUT
IN
= 12V
= 12V
IN
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
3851a1fa
5
LTC3851A-1
Typical perForMance characTerisTics
Load Step
(Pulse-Skipping Mode)
Inductor Current at Light Load
I
LOAD
FORCED
CONTINOUS
MODE
5A/DIV
0.2A TO 7.5A
5A/DIV
I
L
Burst Mode
OPERATION
5A/DIV
5A/DIV
V
OUT
PULSE SKIP
MODE
100mV/DIV
AC-COUPLED
5A/DIV
3851A1 G08
3851A1 G07
V
V
I
= 1.5V
= 1mA
1µs/DIV
V
V
= 1.5V
100µs/DIV
OUT
IN
LOAD
OUT
IN
= 12V
= 12V
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
Coincident Tracking with Master
Supply
Start-Up with Prebiased Output
at 2V
V
MASTER
V
OUT
0.5V/DIV
V
OUT
2V/DIV
TK/SS
0.5V/DIV
2A LOAD
0.5V/DIV
V
FB
0.5V/DIV
3851A1 G09
3851A1 G10
20ms/DIV
10ms/DIV
Input DC Supply Current
vs Input Voltage
Ratiometric Tracking with Master
Supply
3.0
2.5
2.0
1.5
1.0
0.5
0
V
MASTER
0.5V/DIV
V
OUT
2A LOAD
0.5V/DIV
3851A1 G11
10ms/DIV
4
8
12 16 20 24 28 32 36 40
INPUT VOLTAGE (V)
3851A1 G12
3851a1fa
6
LTC3851A-1
Typical perForMance characTerisTics
Maximum Current Sense Threshold
vs Common Mode Voltage
Maximum Peak Current Sense
Threshold vs ITH Voltage
INTVCC Line Regulation
5.3
5.1
4.9
4.7
4.5
4.3
4.1
3.9
3.7
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
DUTY CYCLE RANGE: 0% TO 100%
I
= 0mA
LOAD
I
= 25mA
LOAD
–10
–20
3.5
4
8
12 16 20 24
INPUT VOLTAGE (V)
40
28 32 36
0
0.5
V
1
1.5
2
2.5
5
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
(V)
3
3.5 4 4.5
V
COMMON MODE VOLTAGE (V)
ITH
SENSE
3851A1 G13
3851A1 G14
3851A1 G15
Maximum Current Sense
Threshold vs Feedback Voltage
(Current Foldback)
Burst Mode Peak Current Sense
Threshold vs ITH Voltage
Maximum Current Sense
Threshold vs Duty Cycle
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
MAXIMUIM
MINIMUIM
BURST COMPARATOR FALLING THESHOLD:
V
= 0.4V
ITH
0
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
(V)
0.4 0.5
FEEDBACK VOLTAGE (V)
0
0.1 0.2 0.3
0.6 0.7 0.8
0
80
100
20
40
60
V
ITH
DUTY CYCLE (%)
3851A1 G16
3851A1 G18
3851A1 G17
TK/SS Pull-Up Current
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
Regulated Feedback Voltage
vs Temperature
1.4
1.3
1.2
1.1
1.0
0.9
806
804
802
800
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
RUN RISING THRESHOLD (ON)
RUN FALLING THRESHOLD (OFF)
798
796
794
50
TEMPERATURE (°C)
100 125 150
3851A1 G21
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25
75
–75 –50
0
25 50 75 100 125 150
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
3851A1 G20
3851A1 G19
3851a1fa
7
LTC3851A-1
Typical perForMance characTerisTics
Oscillator Frequency
vs Temperature
Oscillator Frequency
vs Input Voltage
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
900
800
5
4
3
2
1
0
420
R
= 80k
FREQ
415
410
R
= 36k
= 60k
PLLLPF
INTV RAMPING UP
CC
700
600
500
400
300
405
400
395
390
385
INTV RAMPING DOWN
CC
R
PLLLPF
R
= 160k
PLLLPF
200
380
50
100 125 150
75
–75 –50 –25
0
25
10
15
25
30
35
40
5
20
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3851A1 G22
3851A1 G23
3851A1 G24
Shutdown Input DC Supply
Current vs Input Voltage
Shutdown Input DC Supply
Current vs Temperature
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
–25
0
50 75 100 125 150
–75 –50
25
20 25
10 15
INPUT VOLTAGE (V)
0
5
30 35 40
TEMPERATURE (°C)
3851A1 G26
3851A1 G25
Input DC Supply Current
vs Temperature
Maximum Current Sense
Threshold vs INTVCC Voltage
90
80
70
60
50
40
30
20
10
3.0
2.5
2.0
1.5
1.0
0.5
0
0
50
100 125 150
75
–75 –50 –25
0
25
3.2 3.4 3.6 3.8 4.0 4.2
5.0
4.4 4.6 4.8
TEMPERATURE (°C)
INTV VOLTAGE(V)
CC
3851A1 G27
3851A1 G28
3851a1fa
8
LTC3851A-1
pin FuncTions (MSE/UD)
MODE/PLLIN (Pin ±/Pin ±5): Forced Continuous Mode,
Burst Mode or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
PGOOD(Pin9/Pin7):PowerGoodIndicatorOutput.Open-
drain logic out that is pulled to ground when the output
voltage exceeds the 10% regulation window, after the
internal 17µs power bad mask timer expires.
ConnectthispintoINTV toforcecontinuousconduction
CC
mode of operation. Connect to GND to enable pulse-skip-
GND (Pin ±0/Pin 8, Exposed Pad Pin ±7): Ground. All
small-signalcomponentsandcompensationcomponents
shouldbeKelvinconnectedtothisground.The(–)terminal
ping mode of operation. To select Burst Mode operation,
tie this pin to INTV through a resistor no less than 50k,
CC
but no greater than 250k. A clock on the pin will force the
controller into forced continuous mode of operation and
synchronize the internal oscillator.
of CV and the (–) terminal of C should be closely con-
CC
IN
nected to this pin. The exposed pad should be soldered
to ground for good thermal conductivity.
FREQ/PLLFLTR (Pin 2/Pin ±6): The phase-locked loop’s
lowpass filter is tied to this pin. Alternatively, a resistor
can be connected between this pin and GND to vary the
frequency of the internal oscillator.
BG (Pin ±±/Pin 9): Bottom Gate Driver Output. This pin
drives the gate of the bottom N-channel MOSFET between
GND and INTV .
CC
INTV (Pin±2/Pin±0):Internal5VRegulatorOutput. The
CC
RUN (Pin 3/Pin ±): Run Control Input. A voltage above
1.22V on this pin turns on the IC. However, forcing this
pin below 1.1V causes the IC to shut down the IC. There
is a 2μA pull-up current on this pin.
control circuit is powered from this voltage. Decouple this
pin to GND with a minimum 2.2μF low ESR tantalum or
ceramic capacitor.
V (Pin ±3/Pin ±±): Main Input Supply. Decouple this pin
IN
TK/SS(Pin4/Pin2):OutputVoltageTrackingandSoft-Start
Input. A capacitor to ground at this pin sets the ramp rate
for the output voltage. An internal soft-start current of of
1μA charges this capacitor.
to GND with a capacitor.
BOOST (Pin ±4/Pin ±2): Boosted Floating Driver Supply.
The (+) terminal of the boost-strap capacitor is connected
to this pin. This pin swings from a diode voltage drop
I
(Pin 5/Pin 3): Current Control Threshold and Error
TH
below INTV up to V + INTV .
CC
IN
CC
Amplifier Compensation Point. The current comparator
TG (Pin ±5/Pin ±3): Top Gate Driver Output. This is the
tripping threshold increases with its I control voltage.
TH
output of a floating driver with a voltage swing equal to
FB (Pin 6/Pin 4): Error Amplifier Feedback Input. This pin
receives the remotely sensed feedback voltage from an
external resistive divider across the output.
INTV superimposed on the switch node voltage.
CC
SW (Pin ±6/Pin ±4): Switch Node Connection to the In-
ductor. Voltage swing at this pin is from a Schottky diode
–
SENSE (Pin7/Pin5):CurrentSenseComparatorInverting
(external) voltage drop below ground to V .
IN
Input.The(–)inputtothecurrentcomparatorisconnected
to the output.
+
SENSE (Pin 8/Pin 6): Current Sense Comparator Non-
inverting Input. The (+) input to the current comparator
is normally connected to the DCR sensing network or
current sensing resistor.
3851a1fa
9
LTC3851A-1
FuncTional DiagraM
V
IN
FREQ/PLLFLTR
MODE/PLLIN
V
IN
+
C
IN
100k
5V REG
0.8V
MODE/SYNC
DETECT
PLL-SYNC
–
+
BOOST
BURSTEN
C
B
TG
OSC
S
R
PULSE SKIP
ON
M1
Q
I
SW
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
5k
+
SENSE
D
+
–
+
B
L1
I
V
CMP
REV
OUT
–
SENSE
–
RUN
OV
+
INTV
BG
CC
C
OUT
M2
C
VCC
SLOPE COMPENSATION
GND
PGOOD
INTV
CC
UVLO
1
+
–
0.72V
100k
R2
UV
OV
I
V
THB
FB
R1
+
–
V
IN
SLEEP
0.88V
RUN
SS
–
–
+
+
0.8V
REF
1µA
EA
+ –
–
+
+
0.64V
1.22V
2µA
0.4V
3851A1 FD
I
TH
RUN
TK/SS
C
SS
R
C
C
C1
3851a1fa
10
LTC3851A-1
operaTion
Main Control Loop
by logic. Be careful not to exceed the absolute maximum
rating of 6V on this pin.
The LTC3851A-1 is a constant frequency, current mode
step-down controller. During normal operation, the top
MOSFET is turned on when the clock sets the RS latch,
The start-up of the controller’s output voltage, V , is
OUT
controlled by the voltage on the TK/SS pin. When the
and is turned off when the main current comparator, I
,
voltage on the TK/SS pin is less than the 0.8V internal
CMP
resets the RS latch. The peak inductor current at which
resets the RS latch is controlled by the voltage on
reference, the LTC3851A-1 regulates the V voltage to
FB
I
the TK/SS pin voltage instead of the 0.8V reference. This
allows the TK/SS pin to be used to program a soft-start
by connecting an external capacitor from the TK/SS pin to
GND.Aninternal1µApull-upcurrentchargesthiscapacitor
creating a voltage ramp on the TK/SS pin. As the TK/SS
voltage rises linearly from 0V to 0.8V (and beyond), the
CMP
the I pin, which is the output of the error amplifier, EA.
TH
The V pin receives the voltage feedback signal, which is
FB
comparedtotheinternalreferencevoltagebytheEA.When
the load current increases, it causes a slight decrease in
V relative to the 0.8V reference, which in turn causes the
FB
TH
I
voltage to increase until the average inductor current
output voltage V
rises smoothly from zero to its final
OUT
matches the new load current. After the top MOSFET has
turned off, the bottom MOSFET is turned on until either
the inductor current starts to reverse, as indicated by the
value. Alternatively, the TK/SS pin can be used to cause
the start-up of V to track another supply. Typically,
OUT
this requires connecting to the TK/SS pin an external
resistor divider from the other supply to ground (see the
Applications Information section). When the RUN pin
reverse current comparator, I , or the beginning of the
REV
next cycle.
is pulled low to disable the controller, or when INTV
CC
INTV Power
drops below its undervoltage lockout threshold of 3.2V,
the TK/SS pin is pulled low by an internal MOSFET. When
in undervoltage lockout, the controller is disabled and the
external MOSFETs are held off.
CC
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV pin. An
CC
internal 5V low dropout linear regulator supplies INTV
CC
power from V .
IN
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Continuous Conduction)
The top MOSFET driver is biased from the floating boot-
strapcapacitor, C , whichnormallyrechargesduringeach
B
The LTC3851A-1 can be enabled to enter high efficiency
BurstMode operation, constantfrequency pulse-skipping
mode or forced continuous conduction mode. To select
forced continuous operation, tie the MODE/PLLIN pin to
off cycle through an external diode when the top MOSFET
turns off. If the input voltage, V , decreases to a voltage
IN
close to V , the loop may enter dropout and attempt
OUT
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about 1/10 of the clock period every tenth cycle to allow
INTV . To select pulse-skipping mode of operation, float
CC
the MODE/PLLIN pin or tie it to GND. To select Burst Mode
operation, tie MODE/PLLIN to INTV through a resistor
CC
C to recharge. However, it is recommended that there is
B
no less than 50k, but no greater than 250k.
always a load present during the drop-out transition to
ensure C is recharged.
When the controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-forth of the maximum sense voltage even though
B
Shutdown and Start-Up (RUN and TK/SS)
the voltage on the I pin indicates a lower value. If the
TH
The LTC3851A-1 can be shut down using the RUN pin.
Pulling this pin below 1.1V disables the controller and
average inductor current is higher than the load current,
the error amplifier, EA, will decrease the voltage on the I
TH
most of the internal circuitry, including the INTV regula-
CC
pin. When the I voltage drops below 0.4V, the internal
TH
tor. Releasing the RUN pin allows an internal 2µA current
to pull up the pin and enable that controller. Alternatively,
the RUN pin may be externally pulled up or driven directly
sleep signal goes high (enabling “sleep” mode) and both
external MOSFETs are turned off.
3851a1fa
11
LTC3851A-1
operaTion
pin. If the MODE/PLLIN pin is not being driven by an ex-
ternal clock source, the FREQ/PLLFLTR pin can be used
to program the controller’s operating frequency from
250kHz to 750kHz.
In sleep mode, the load current is supplied by the output
capacitor. Astheoutputvoltagedecreases, theEA’soutput
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator,
A phase-locked loop (PLL) is available on the LTC3851A-1
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controlleroperatesinforcedcontinuousmodeofoperation
when it is synchronized. A series RC should be connected
between the FREQ/PLLFLTR pin and GND to serve as the
PLL’s loop filter.
I
, turns off the bottom external MOSFET just before the
REV
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
It is suggested that the external clock be applied before
enabling the controller unless a second resistor is con-
nected in parallel with the series RC loop filter network.
The second resistor prevents low switching frequency
operation if the controller is enabled before the clock.
rent is determined by the voltage on the I pin, just as in
TH
normal operation. In this mode the efficiency at light loads
is lower than in Burst Mode operation. However, continu-
ous mode has the advantages of lower output ripple and
less interference to audio circuitry.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious con-
ditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
When the MODE/PLLIN pin is connected to GND, the
LTC3851A-1 operates in PWM pulse-skipping mode at
light loads. At very light loads the current comparator,
I
, may remain tripped for several cycles and force the
CMP
external top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
likeforcedcontinuousoperation,exhibitslowoutputripple
as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
low current efficiency than forced continuous mode, but
not nearly as high as Burst Mode operation.
Power Good (PGOOD) Pin
ThePGOODpinisconnectedtoanopendrainofaninternal
N-channel MOSFET. The MOSFET turns on and pulls the
pin voltage is not within
PGOOD pin low when the V
FB
10% of the 0.8V reference voltage. The PGOOD pin is
also pulled low when the RUN pin is low (shut down) or
whentheLTC3851A-1isinthesoft-startortrackingphase.
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
When the V pin voltage is within the 10% requirement,
FB
the MOSFET is turned off and the pin is allowed to be
pulled up by an external resistor to a source of up to 6V.
The PGOOD pin will flag power good immediately when
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage. The switching frequency of
the LTC3851A-1 can be selected using the FREQ/PLLFLTR
the V pin is within the 10% window. However, there is
FB
an internal 17µs power bad mask when V goes out of
FB
the 10% window.
3851a1fa
12
LTC3851A-1
applicaTions inForMaTion
The Typical Application on the first page of this data sheet
isabasicLTC3851A-1applicationcircuit.TheLTC3851A-1
can be configured to use either DCR (inductor resistance)
sensing or low value resistor sensing. The choice of the
two current sensing schemes is largely a design trade-off
between cost, power consumption and accuracy. DCR
sensing is becoming popular because it saves expensive
current sensing resistors and is more power efficient,
especially in high current applications. However, current
sensing resistors provide the most accurate current limits
for the controller. Other external component selection
is driven by the load requirement, and begins with the
V
V
IN
IN
INTV
CC
BOOST
TG
R
SENSE
V
SW
OUT
LTC3851A-1
BG
GND
+
SENSE
–
SENSE
3851A1 F01
FILTER COMPONENTS
PLACED NEAR SENSE PINS
selection of R
(if R
is used) and the inductor
SENSE
SENSE
value. Next, the power MOSFETs and Schottky diodes are
selected. Finally, input and output capacitors are selected.
The circuit shown on the first page can be configured for
Figure ±. Using a Resistor to Sense Current with the LTC385±A-±
of 20% for variations in the IC and external component
values yields:
operation up to 38V at V .
IN
+
–
SENSE and SENSE Pins
VMAX
MAX + ∆IL/2
RSENSE = 0.8 •
+
–
I
The SENSE and SENSE pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5.5V. Both SENSE pins
are high impedance inputs with small base currents of
less than 1μA. When the SENSE pins ramp up from 0V
to 1.4V, the small base currents flow out of the SENSE
pins. When the SENSE pins ramp down from 5V to 1.1V,
the small base currents flow into the SENSE pins. The
high impedance inputs to the current comparators allow
accurate DCR sensing. However, care must be taken not
to float these pins during normal operation.
Inductor DCR Sensing
Forapplicationsrequiringthehighestpossibleefficiency,
the LTC3851A-1 is capable of sensing the voltage drop
across the inductor DCR, as shown in Figure 2. The
DCR of the inductor represents the small amount of
DC winding resistance of the copper, which can be less
than 1mΩ for today’s low value, high current inductors.
If the external R1||R2 • C1 time constant is chosen to
be exactly equal to the L/DCR time constant, the voltage
drop across the external capacitor is equal to the voltage
dropacrosstheinductorDCRmultipliedbyR2/(R1+R2).
Therefore,R2maybeusedtoscalethevoltageacrossthe
sense terminals when the DCR is greater than the target
sense resistance. Check the manufacturer’s data sheet
for specifications regarding the inductor DCR, in order
to properly dimension the external filter components.
The DCR of the inductor can also be measured using a
good RLC meter.
Low Value Resistors Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 1. R
current.
is chosen based on the required output
SENSE
The current comparator has a maximum threshold,
= 53mV. The current comparator threshold sets the
maximumpeakoftheinductorcurrent,yieldingamaximum
average output current, I , equal to the peak value less
halfthepeak-to-peakripplecurrent,∆I .Allowingamargin
V
MAX
MAX
L
3851a1fa
13
LTC3851A-1
applicaTions inForMaTion
Accepting larger values of ∆I allows the use of low
L
V
IN
V
IN
inductances, but results in higher output voltage ripple
INTV
CC
and greater core losses. A reasonable starting point for
setting ripple current is ∆I = 0.3(I
). The maximum
MAX
BOOST
TG
L
INDUCTOR
∆I occurs at the maximum input voltage.
L
L
DCR
SW
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
V
OUT
LTC3851A-1
BG
GND
R1
R2
+
≈10% of the current limit determined by R
. Lower
SENSE
SENSE
inductor values (higher ∆I ) will cause this to occur at
C1*
L
–
SENSE
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to increase.
L
DCR
+
–
3851A1 F02
R1||R2 • C1 =
*PLACE C1 NEAR SENSE , SENSE PINS
R2
R1 + R2
R
= DCR
SENSE(EQ)
Figure 2. Current Mode Control Using the Inductor DCR
Inductor Core Selection
Slope Compensation and Inductor Peak Current
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcingtheuseofmoreexpensiveferriteormolypermalloy
cores. Actual core loss is independent of core size for a
fixedinductorvalue,butitisverydependentoninductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Slope compensation provides stability in constant fre-
quency architectures by preventing sub-harmonic oscil-
lations at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal. Normally, this results in a reduction of maximum
inductor peak current for duty cycles >40%. However, the
LTC3851A-1usesanovelschemethatallowsthemaximum
inductor peak current to remain unaffected throughout all
duty cycles.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Inductor Value Calculation
The operating frequency and inductor selection are inter-
relatedinthathigheroperatingfrequenciesallowtheuseof
smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge losses. In addition to this basic trade-off, the
effect of inductor value on ripple current and low current
operation must also be considered.
Power MOSFET and Schottky Diode (Optional)
Selection
The inductor value has a direct effect on ripple current.
Two external power MOSFETs must be selected for the
LTC3851A-1 controller: one N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The inductor ripple current ∆I decreases with higher
L
inductance or frequency and increases with higher V :
IN
⎛
⎞
⎟
⎠
VOUT
1
f •L
∆IL =
VOUT 1–
⎜
V
⎝
IN
3851a1fa
14
LTC3851A-1
applicaTions inForMaTion
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.
CC
This voltage is typically 5V during start-up. Consequently,
logic-level threshold MOSFETs must be used in most ap-
plications. The only exception is if low input voltage is ex-
which are highest at high input voltages. For V < 20V,
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V, the transition losses rapidly
pected(V <5V);then,sub-logiclevelthresholdMOSFETs
IN
IN
increasetothepointthattheuseofahigherR
device
(V
< 3V) should be used. Pay close attention to the
DS(ON)
GS(TH)
withlowerC
actuallyprovideshigherefficiency.The
BV
specification for the MOSFETs as well; most of the
MILLER
DSS
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the on-
resistance, R , Miller capacitance, C
DS(ON)
, input
MILLER
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge curve
The term (1 + δ) is generally given for a MOSFET in the
C
MILLER
form of a normalized R
vs Temperature curve, but
usually provided on the MOSFET manufacturers’ data
sheet. C is equal to the increase in gate charge
DS(ON)
δ = 0.005/°C can be used as an approximation for low
MILLER
voltage MOSFETs.
along the horizontal axis while the curve is approximately
flat divided by the specified change in V . This result is
DS
TheoptionalSchottkydiodeconductsduringthedeadtime
between the conduction of the two power MOSFETs. This
preventsthebodydiodeofthebottomMOSFETfromturn-
ing on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
then multiplied by the ratio of the application applied V
DS
to the gate charge curve specified V . When the IC is
DS
operating in continuous mode, the duty cycles for the top
and bottom MOSFETs are given by:
in efficiency at high V . A 1A to 3A Schottky is generally
VOUT
IN
Main Switch Duty Cycle =
a good size due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.
V
IN
V – V
IN
OUT
Synchronous Switch Duty Cycle =
V
IN
Soft-Start and Tracking
The MOSFET power dissipations at maximum output
current are given by:
The LTC3851A-1 has the ability to either soft-start by itself
with a capacitor or track the output of another channel
or external supply. When the LTC3851A-1 is configured
to soft-start by itself, a capacitor should be connected to
the TK/SS pin. The LTC3851A-1 is in the shutdown state if
the RUN pin voltage is below 1.10V. TK/SS pin is actively
pulled to ground in this shutdown state.
VOUT
2
PMAIN
=
I
1+ δ R
+
)
(
MAX ) (
)
DS(ON)
V
IN
⎛
⎞
⎟
⎠
IMAX
2
2
V
R
C
)
(
•
(
)
⎜
(
IN
DR
MILLER
⎝
⎡
⎢
⎤
1
1
Once the RUN pin voltage is above 1.22V, the LTC3851A-1
powersup.Asoft-startcurrentof1μAthenstartstocharge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
⎥
+
(f)
V
– VTH(MIN) VTH(MIN)
⎢
⎥
⎦
⎣ INTVCC
V – V
2
IN
OUT
P
=
I
1+ δ R
DS(ON)
(
MAX ) (
)
SYNC
V
IN
where δ is the temperature dependency of R
DR
and
DS(ON)
R
(approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V
is the
TH(MIN)
typical MOSFET minimum threshold voltage.
3851a1fa
15
LTC3851A-1
applicaTions inForMaTion
0V to 0.8V on the TK/SS pin. The total soft-start time can
be calculated as:
Output Voltage Tracking
The LTC3851A-1 allows the user to program how its
output ramps up and down by means of the TK/SS pins.
Through this pin, the output can be set up to either co-
incidentally or ratiometrically track with another supply’s
output, as shown in Figure 3. In the following discussions,
CSS
1.0µA
tSOFT-START = 0.8 •
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode up
to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.72V, it
will operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.72V. The output ripple
is minimized during the 80mV forced continuous mode
window.
V
refers to a master supply and V
refers to the
MASTER
OUT
LTC3851A-1’s output as a slave supply. To implement the
coincident tracking in Figure 3a, connect a resistor divider
to V
and connect its midpoint to the TK/SS pin of
MASTER
theLTC3851A-1.Theratioofthisdividershouldbeselected
the same as that of the LTC3851A-1’s feedback divider as
shown in Figure 4a. In this tracking mode, V
must
MASTER
When the regulator is configured to track another supply,
the feedback voltage of the other supply is duplicated by a
resistordividerandappliedtotheTK/SSpin.Therefore,the
voltageramprateonthispinisdeterminedbytheramprate
of the other supply’s voltage. Note that the small soft-start
capacitor charging current is always flowing, producing a
small offset error. To minimize this error, one can select
the tracking resistive divider value to be small enough to
make this error negligible.
be higher than V . To implement ratiometric tracking,
OUT
the ratio of the resistor divider connected to V
determined by:
is
MASTER
⎛
⎞
⎟
⎠
VOUT
R2 R3+R4
=
⎜
⎝
VMASTER R4 R1+R2
So which mode should be programmed? While either
mode in Figure 4 satisfies most practical applications,
the coincident mode offers better output regulation.
This concept can be better understood with the help of
Figure 5. At the input stage of the LTC3851A-1’s error
amplifier, two common anode diodes are used to clamp
In order to track down another supply after the soft-start
phase expires, the LTC3851A-1 must be configured for
forced continuous operation by connecting MODE/PLLIN
to INTV .
CC
V
V
V
MASTER
OUT
MASTER
V
OUT
3851A1
3851A1 F03
TIME
TIME
(3a) Coincident Tracking
(3b) Ratiometric Tracking
Figure 3. Two Different Modes of Output Voltage Tracking
3851a1fa
16
LTC3851A-1
applicaTions inForMaTion
V
V
V
OUT
V
OUT
MASTER
MASTER
R3
R3
R1
R2
R3
R4
TO
TK/SS
PIN
TO
FB
PIN
TO
TK/SS
PIN
TO
FB
PIN
V
V
R4
R4
3851A1 F04
(4a) Coincident Tracking Setup
(4b) Ratiometric Tracking Setup
Figure 4. Setup for Coincident and Ratiometric Tracking
The LDO can supply a peak current of 50mA and must
be bypassed to ground with a minimum of 2.2μF ceramic
capacitor or low ESR electrolytic capacitor. No matter
what type of bulk capacitor is used, an additional 0.1μF
I
I
+
–
D1
D2
EA
ceramic capacitor placed directly adjacent to the INTV
CC
TK/SS
0.8V
and GND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers.
D3
3851A1 F05
V
FB
Figure 5. Equivalent Input Circuit of Error Amplifier
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3851A-1 to
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincidentmode, theTK/SSvoltageissubstantiallyhigher
than 0.8V at steady state and effectively turns off D1. D2
and D3 will therefore conduct the same current and offer
be exceeded. The INTV current, which is dominated by
CC
the gate charge current, is supplied by the 5V LDO.
Power dissipation for the IC in this case is highest and
is approximately equal to V • I
. The gate charge
IN
INTVCC
current is dependent on operating frequency as discussed
intheEfficiencyConsiderationssection. Thejunctiontem-
perature can be estimated by using the equations given in
Note 3 of the Electrical Characteristics. For example, the
tight matching between V and the internal precision
FB
0.8V reference. In the ratiometric mode, however, TK/SS
equals 0.8V at steady state. D1 will divert part of the bias
current to make V slightly lower than 0.8V.
FB
LTC3851A-1 INTV current is limited to less than 17mA
CC
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
ofoutputvoltagedeviation.Furthermore,whenthemaster
supply’s output experiences dynamic excursion (under
load transient, for example), the slave channel output will
be affected as well. For better output regulation, use the
coincident tracking mode instead of ratiometric.
from a 36V supply in the GN package:
T = 70°C + (17mA)(36V)(90°C/W) = 125°C
J
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE/PLLIN
= INTV ) at maximum V .
CC
IN
INTV Regulator
CC
Topside MOSFET Driver Supply (C , D )
B
B
The LTC3851A-1 features a PMOS low dropout linear
An external bootstrap capacitor, C , connected to the
B
regulator (LDO) that supplies power to INTV from the
CC
BOOST pin supplies the gate drive voltage for the topside
V supply. INTV powers the gate drivers and much of
IN
CC
MOSFET.CapacitorC intheFunctionalDiagramischarged
B
the LTC3851A-1 ’s internal circuitry. The LDO regulates
the voltage at the INTV pin to 5V.
though external diode D from INTV when the SW pin
B
CC
CC
3851a1fa
17
LTC3851A-1
applicaTions inForMaTion
required.Severalcapacitorsmayalsobeparalleledtomeet
size or height requirements in the design. Always consult
the manufacturer if there is any question.
is low. When the topside MOSFET is to be turned on, the
driver places the C voltage across the gate source of the
B
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage, SW, rises to V
IN
C
OUT
Selection
and the BOOST pin follows. With the topside MOSFET on,
The selection of C
is primarily determined by the effec-
OUT
the boost voltage is above the input supply:
tiveseriesresistance, ESR, tominimizevoltageripple. The
outputripple,∆V ,incontinuousmodeisdeterminedby:
V
= V + V
IN INTVCC
BOOST
OUT
The value of the boost capacitor, C , needs to be 100 times
B
⎛
⎞
⎟
⎠
1
that of the total input capacitance of the topside MOSFET.
∆VOUT ≈ ∆I ESR+
⎜
⎝
L
8fCOUT
The reverse breakdown of the external Schottky diode
must be greater than V
.
IN(MAX)
where f = operating frequency, C
= output capacitance
OUT
Undervoltage Lockout
and ∆I = ripple current in the inductor. The output ripple
L
is highest at maximum input voltage since ∆I increases
The LTC3851A-1 has two functions that help protect the
controller in case of undervoltage conditions. A precision
L
with input voltage. Typically, once the ESR requirement
for C
has been met, the RMS current rating gener-
UVLOcomparatorconstantlymonitorstheINTV voltage
OUT
CC
ally far exceeds the I
requirement. With ∆I =
to ensure that an adequate gate-drive voltage is present.
RIPPLE(P-P)
L
0.3I
and allowing 2/3 of the ripple to be due to
It locks out the switching action when INTV is below
OUT(MAX)
CC
ESR, the output ripple will be less than 50mV at maximum
3.2V. To prevent oscillation when there is a disturbance
V and:
IN
on the INTV , the UVLO comparator has 400mV of preci-
CC
sion hysteresis.
COUT Required ESR < 2.2RSENSE
1
Anotherwaytodetectanundervoltageconditionistomoni-
COUT
>
tor the V supply. Because the RUN pin has a precision
IN
8fRSENSE
turn-on reference of 1.22V, one can use a resistor divider
to V to turn on the IC when V is high enough.
IN
IN
ThefirstconditionrelatestotheripplecurrentintotheESR
oftheoutputcapacitancewhilethesecondtermguarantees
thattheoutputcapacitancedoesnotsignificantlydischarge
duringtheoperatingfrequencyperiodduetoripplecurrent.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
C Selection
IN
Incontinuousmode, thesourcecurrentofthetopN-chan-
nel MOSFET is a square wave of duty cycle V /V . To
OUT IN
preventlargevoltagetransients, alowESRinputcapacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
maintain the ripple voltage at or below 50mV. The I pin
TH
OPTI-LOOP compensation components can be optimized
to provide stable, high performance transient response
regardless of the output capacitors selected.
1/2
⎛
⎜
⎝
⎞
VOUT
V
V
OUT
IN
IRMS ≅IO(MAX)
– 1
⎟
⎠
V
IN
The selection of output capacitors for applications with
largeloadcurrenttransientsisprimarilydeterminedbythe
voltage tolerance specifications of the load. The resistive
component of the capacitor, ESR, multiplied by the load
current change, plus any output voltage ripple must be
within the voltage tolerance of the load.
This formula has a maximum at V = 2V , where I =
RMS
O(MAX)
IN
OUT
I
/2. This simple worst-case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
3851a1fa
18
LTC3851A-1
applicaTions inForMaTion
The required ESR due to a load current step is:
∆V
AVX TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights ranging from 1.5mm
to 4.1mm. Aluminum electrolytic capacitors can be used
in cost-driven applications, provided that consideration is
given to ripple current ratings, temperature and long-term
reliability. Atypicalapplicationwillrequireseveraltomany
aluminum electrolytic capacitors in parallel. A combina-
tion of the above mentioned capacitors will often result
in maximizing performance and minimizing overall cost.
Other capacitor types include Nichicon PL series, NEC
Neocap, Panasonic SP and Sprague 595D series. Consult
manufacturers for other specific recommendations.
RESR
≤
∆I
where
(or minimum load) and
∆Iisthechangeincurrentfromfullloadtozeroload
∆
V is the allowed voltage devia-
tion (not including any droop due to finite capacitance).
The amount of capacitance needed is determined by the
maximum energy stored in the inductor. The capacitance
must be sufficient to absorb the change in inductor
current when a high current to low current transition
occurs. The opposite load current transition is generally
determined by thecontrolloop OPTI-LOOPcomponents,
so make sure not to over compensate and slow down
the response. The minimum capacitance to assure the
inductors’ energy is adequately absorbed is:
Like all components, capacitors are not ideal. Each
capacitor has its own benefits and limitations. Combina-
tions of different capacitor types have proven to be a very
cost effective solution. Remember also to include high
frequency decoupling capacitors. They should be placed
as close as possible to the power pins of the load. Any
inductance present in the circuit board traces negates
their usefulness.
2
L ∆I
( )
C
>
OUT
2 ∆V V
(
)
OUT
where ∆I is the change in load current.
Setting Output Voltage
Manufacturers such as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor electrolyte
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
The LTC3851A-1 output voltage is set by an external feed-
back resistive divider carefully placed across the output,
as shown in Figure 6. The regulated output voltage is
determined by:
⎛
⎞
⎟
⎠
RB
RA
VOUT = 0.8V 1+
⎜
⎝
Insurfacemountapplications,ESR,RMScurrenthandling
and load step specifications may require multiple capaci-
tors in parallel. Aluminum electrolytic, dry tantalum and
special polymer capacitors are available in surface mount
packages.Specialpolymersurfacemountcapacitorsoffer
very low ESR but have much lower capacitive density per
unit volume than other capacitor types. These capacitors
offeraverycost-effectiveoutputcapacitorsolutionandare
an ideal choice when combined with a controller having
highloopbandwidth.Tantalumcapacitorsofferthehighest
capacitance density and are often used as output capaci-
tors for switching regulators having controlled soft-start.
Several excellent surge-tested choices are the AVX TPS,
To improve the transient response, a feed-forward
capacitor, C , may be used. Great care should be taken
FF
to route the V line away from noise sources, such as
FB
the inductor or the SW line.
V
OUT
R
B
C
FF
LTC3851A-1
V
FB
R
A
3851A1 F06
Figure 6. Settling Output Voltage
3851a1fa
19
LTC3851A-1
applicaTions inForMaTion
Fault Conditions: Current Limit and Current Foldback
Phase-Locked Loop and Frequency Synchronization
The LTC3851A-1 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 40% of its nominal output level, the
maximum sense voltage is progressively lowered from
its maximum programmed value to about 25% of the
that value. Foldback current limiting is disabled during
soft-start or tracking. Under short-circuit conditions
with very low duty cycles, the LTC3851A-1 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuitripplecurrentisdeterminedbytheminimum
on-time, tON(MIN), of the LTC3851A-1 (≈90ns), the input
voltage and inductor value:
TheLTC3851A-1hasaphase-lockedloop(PLL)comprised
of an internal voltage-controlled oscillator (V ) and a
CO
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. This phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the FREQ/PLLFLTR pin. Note
that the LTC3851A-1 can only be synchronized to an
external clock whose frequency is within range of the
V
L
LTC3851A-1’s internal V .This is guaranteed to be be-
CO
IN
∆IL(SC) = tON(MIN)
•
tween 250kHz and 750kHz. A simplified block diagram is
shown in Figure 8.
The resulting short-circuit current is:
If the external clock frequency is greater than the internal
1/4MaxVSENSE
RSENSE
1
2
oscillator’s frequency, f , then current is sunk con-
ISC =
– ∆IL(SC)
OSC
tinuouslyfromthephasedetectoroutput,pullingdownthe
FREQ/PLLFLTR pin. When the external clock frequency is
Programming Switching Frequency
less than f
, current is sourced continuously, pulling up
OSC
theFREQ/PLLFLTRpin.Iftheexternalandinternalfrequen-
ciesarethesamebutexhibitaphasedifference,thecurrent
sourcesturnonforanamountoftimecorrespondingtothe
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
TosettheswitchingfrequencyoftheLTC3851A-1,connect
a resistor, R
, between FREQ/PLLFLTR and GND. The
FREQ
relationship between the oscillator frequency and R
FREQ
is shown in Figure 7. A 0.1µF bypass capacitor should be
connected in parallel with R
.
FREQ
750
700
650
600
550
500
450
400
350
300
250
the filter capacitor C holds the voltage.
LP
R
LP
2.7V
C
LP
FREQ/PLLFLTR
VCO
MODE/
PLLIN
DIGITAL
PHASE/
FREQUENCY
DETECTOR
EXTERNAL
OSCILLATOR
20
60
80 100 120 140 160
(kΩ)
40
R
FREQ
3851A1 F07
3851A1 F08
Figure 7. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND
Figure 8. Phase-Locked Loop Block Diagram
3851a1fa
20
LTC3851A-1
applicaTions inForMaTion
minimum on-time gradually increases. This is of particu-
lar concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
The loop filter components, C and R , smooth out
LP
LP
the current pulses from the phase detector and provide
a stable input to the voltage-controlled oscillator. The
filter components C and R determine how fast the
LP
LP
loop acquires lock. Typically R is 1k to 10k and C is
LP
LP
2200pF to 0.01μF.
When the external oscillator is active before the LTC3851
is enabled, the internal oscillator frequency will track the
externaloscillatorfrequencyasdescribedinthepreceding
paragraphs. In situations where the LTC3851 is enabled
before the external oscillator is active, a low free-running
oscillatorfrequencyofapproximately50kHzwillresult.Itis
possibletoincreasethefree-running,pre-synchronization
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
frequency by adding a second resistor, R
, in parallel
FREQ
with R and C . R
will also cause a phase difference
LP
LP FREQ
%Efficiency = 100% – (L1 + L2 + L3 + ...)
between the internal and external oscillator signals. The
where L1, L2, etc. are the individual losses as a percent-
age of input power.
magnitudeofthephasedifferenceisinverselyproportional
to the value R
. The free-running frequency may be
FREQ
programmed by using Figure 7 to determine the appropri-
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
ate value of R
. In order to maintain adequate phase
FREQ
margin for the PLL, the typical value for C is 0.01µF and
the losses in LTC3851A-1 circuits: 1) IC V current, 2)
LP
IN
2
the typical value for R is 1k.
INTV regulatorcurrent,3)I Rlosses,4)topsideMOSFET
LP
CC
transition losses.
The external clock (on MODE/PLLIN pin) input high
threshold is nominally 1.6V, while the input low threshold
is nominally 1.2V.
1. The V current is the DC supply current given in the
IN
ElectricalCharacteristicstable,whichexcludesMOSFET
driver current. V current typically results in a small
IN
Minimum On-Time Considerations
(<0.1%) loss.
Minimum on-time, t
, is the smallest time dura-
ON(MIN)
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
fromINTVCC toground. TheresultingdQ/dtisacurrent
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
tion that the LTC3851A-1 is capable of turning on the top
MOSFET. It isdetermined by internaltiming delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
VOUT
tON(MIN)
<
V (f)
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
2
3. I R losses are predicted from the DC resistances of
the fuse (if used), MOSFET, inductor and current sense
resistor.Incontinuousmode,theaverageoutputcurrent
flows through L and R
, but is chopped between
SENSE
Theminimumon-timefortheLTC3851A-1isapproximately
90ns. However, as the peak sense voltage decreases the
the topside MOSFET and the synchronous MOSFET.
3851a1fa
21
LTC3851A-1
applicaTions inForMaTion
time V
can be monitored for excessive overshoot or
If the two MOSFETs have approximately the same
OUT
ringing, which would indicate a stability problem. The
R
, then theresistance ofoneMOSFETcan simply
DS(ON)
availability of the I pin not only allows optimization of
be summed with the resistances of L and R
to
TH
SENSE
=10mΩ,
2
control loop behavior but also provides a DC-coupled and
AC-filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loop response. Assuming apredominantly second
ordersystem, phasemarginand/ordampingfactorcanbe
estimated using the percentage of overshoot seen at this
pin.Thebandwidthcanalsobeestimatedbyexaminingthe
obtainI Rlosses.Forexample,ifeachR
DS(ON)
DCR = 10mΩ and R
= 5mΩ, then the total resis-
SENSE
tance is 25mΩ. This results in losses ranging from 2%
to 8% as the output current increases from 3A to 15A
for a 5V output, or a 3% to 12% loss for a 3.3V output.
Efficiency varies as the inverse square of V
for the
OUT
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
rise time at the pin. The I external components shown
TH
in the Typical Application circuit will provide an adequate
starting point for most applications.
The I series R -C filter sets the dominant pole-zero
TH
C
C
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
2
Transition Loss = (1.7)V • I
• C
• f
IN
O(MAX)
RSS
Other hidden losses such as copper trace and the battery
internal resistance can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
produce output voltage and I pin waveforms that will
TH
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
losses can be minimized by making sure that C has ad-
IN
equate charge storage and very low ESR at the switching
frequency.A25Wsupplywilltypicallyrequireaminimumof
20μF to 40μF of capacitance having a maximum of 20mΩ
to 50mΩ of ESR. Other losses including Schottky con-
duction losses during dead time and inductor core losses
generally account for less than 2% total additional loss.
is why it is better to look at the I pin signal which is in
TH
the feedback loop and is the filtered and compensated
Checking Transient Response
control loop response. The midband gain of the loop will
be increased by increasing R and the bandwidth of the
C
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
loop will be increased by decreasing C . If R is increased
C
C
bythesamefactorthatC isdecreased,thezerofrequency
C
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
load current. When a load step occurs, V
shifts by an
OUT
amount equal to ∆I
(ESR), where ESR is the effective
LOAD
series resistance of C . ∆I
also begins to charge or
generating the feedback error signal that
OUT
LOAD
discharge C
OUT
forces the regulator to adapt to the current change and
return V
to its steady-state value. During this recovery
OUT
3851a1fa
22
LTC3851A-1
applicaTions inForMaTion
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3851A-1. These items are also illustrated graphically
in the layout diagram of Figure 9. Check the following in
your layout:
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
1. Are the board signal and power grounds segregated?
TheLTC3851A-1GNDpinshouldtietothegroundplane
closetotheinputcapacitor(s).Thelowcurrentorsignal
ground lines should make a single point tie directly to
the GND pin. The synchronous MOSFET source pins
should connect to the input capacitor(s) ground.
C
LOAD
to C
is greater than 1:50, the switch rise time
OUT
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10μF capacitor would
LOAD
require a 250μs rise time, limiting the charging current
to about 200mA.
+
0.1mF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE/PLLIN
SW
TG
R
FREQ
C
IN
M1
FREQ/PLLFLTR
RUN
BOOST
V
IN
LTC3851A-1
C
SS
D1
TK/SS
V
IN
C
C2
C
C
D
B
B
C
R
C
M2
I
TH
INTV
CC
47pF
+
V
BG
GND
4.7µF
FB
–
+
SENSE
SENSE
–
1000pF
R
PGOOD
PGOOD
V
PULL-UP
L1
–
R1
R2
C
OUT
V
OUT
+
+
R
SENSE
3851A1 F09
Figure 9. LTC385±A-± Layout Diagram
3851a1fa
23
LTC3851A-1
applicaTions inForMaTion
2. Does the V pin connect directly to the feedback resis-
PC Board Layout Debugging
FB
tors? The resistive divider R1, R2 must be connected
It is helpful to use a DC-50MHz current probe to monitor
thecurrentintheinductorwhiletestingthecircuit.Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
outputvoltageaswell. Checkforproperperformanceover
the operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold—typically 10% of the maximum designed
current level in Burst Mode operation.
between the (+) plate of C
and signal ground. The
OUT
47pF to 100pF capacitor should be as close as possible
to the LTC3851A-1. Be careful locating the feedback
resistors too far away from the LTC3851A-1. The V
FB
line should not be routed close to any other nodes with
high slew rates.
–
+
3. Are the SENSE and SENSE leads routed together
with minimum PC trace spacing? The filter capacitor
+
–
between SENSE and SENSE should be as close as
possible to the LTC3851A-1. Ensure accurate current
sensingwithKelvinconnectionsasshowninFigure 10.
Series resistance can be added to the SENSE lines to
increase noise rejection and to compensate for the ESL
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawelldesigned, lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pick-up at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
of R
.
SENSE
4. Does the (+) terminal of C connect to the drain of
IN
the topside MOSFET(s) as closely as possible? This
capacitor provides the AC current to the MOSFET(s).
5. Is the INTV decoupling capacitor connected closely
Reduce V from its nominal level to verify operation
CC
IN
between INTV and GND? This capacitor carries the
of the regulator in dropout. Check the operation of the
CC
MOSFETdriverpeakcurrents.Anadditional1μFceramic
undervoltage lockout circuit by further lowering V while
IN
capacitor placed immediately next to the INTV and
monitoring the outputs to verify operation.
CC
GND pins can help improve noise performance.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
6. Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the “output side” (Pin 9 to Pin 16) of the LTC3851A-1
and occupy minimum PC trace area.
HIGH CURRENT PATH
for inductive coupling between C , the Schottky and the
IN
top MOSFET to the sensitive current and voltage sens-
ing traces. In addition, investigate common ground path
voltage pickup between these components and the GND
pin of the IC.
3851A1 F10
CURRENT SENSE
RESISTOR
(R
)
SENSE
+
–
SENSE SENSE
Figure ±0. Kelvin Sensing RSENSE
3851a1fa
24
LTC3851A-1
applicaTions inForMaTion
ThepowerdissipationonthetopsideMOSFETcanbeeasily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
Design Example
As a design example, assume V = 12V (nominal), V =
22V (maximum), V
(refer to Figure 12).
IN
MAX
IN
results in: R
= 0.035Ω/0.022Ω, C
= 215pF.
DS(ON)
MILLER
= 1.8V, I
= 5A, and f = 250kHz
OUT
At maximum input voltage with T (estimated) = 50°C:
1.8V
22V
2
⎡
⎤
The inductance value is chosen first based on a 30%
ripple current assumption. The highest value of ripple
current occurs at the maximum input voltage. Connect a
160k resistor between the FREQ/PLLFLTR and GND pins,
generating 250kHz operation. The minimum inductance
for 30% ripple current is:
PMAIN
=
5
( )
1+ 0.005 50°C − 25°C •
(
)
(
)
⎣ ⎦
⎛
⎜
⎝
⎞
⎟
⎠
5A
2
2
0.035Ω + 22V
) (
2Ω 215pF •
)(
(
)
(
)
⎡
⎤
1
1
+
250kHz = 185mW
(
)
⎢
⎥
⎣
⎦
5− 2.3 2.3
⎛
⎞
⎟
⎠
VOUT
1
∆IL =
VOUT 1−
⎜
A short-circuit to ground will result in a folded back cur-
rent of:
f L
( )( )
V
⎝
IN
A 4.7µH inductor will produce 28% ripple current and
a 3.3µH will result in 40%. The peak inductor current
will be the maximum DC value plus one-half the ripple
current, or 6A, for the 3.3µH value. Increasing the ripple
current will also help ensure that the minimum on-time
of 90ns is not violated. The minimum on-time occurs at
⎛
⎜
⎝
⎞
⎟
⎠
90ns 22V
29mV
0.0125Ω 2
1
(
)
ISC =
–
= 2.02A
3.3µH
with a typical value of R
= 0.125. The resulting power dissipated in the bottom
and δ = (0.005/°C)(25°C)
DS(ON)
MOSFET is:
maximum V :
IN
22V
22V
2
P
=
2.02A 1.125 0.022Ω = 101.0mW
VOUT
1.8V
22V 250kHz
(
) (
)(
)
SYNC
tON(MIN)
=
=
= 327ns
V
f
IN(MAX)( )
(
)
which is less than under full-load conditions.
C is chosen for an RMS current rating of at least 3A at
The R
resistor value can be calculated by using the
SENSE
IN
maximum current sense voltage specification with some
accommodation for tolerances.
temperature. C
is chosen with an ESR of 0.02Ω for
OUT
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage. The output
voltage ripple due to ESR is approximately:
50mV
6A
RSENSE
≤
= 0.0083Ω
V
= R (∆I ) = 0.02Ω (2A) = 40mV
ESR L P-P
ORIPPLE
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
3851a1fa
25
LTC3851A-1
Typical applicaTions
V
IN
4.5V TO 32V
MODE/PLLIN
V
IN
+
C
R
IN
FREQ
22µF
82.5k
M1
FREQ/PLLFLTR
TG
BOOST
SW
HAT2170H
C
B
0.1µF
RUN
C20
0.1µF
C
SS
L1
0.68µH
LTC3851A-1
0.1µF
V
3.3V
15A
OUT
TK/SS
C
C
D
C
B
R
C2
R2
154k
1%
C
C15
47pF
2200pF
R27
3.01k
CMDSH05-4
330pF
15k
I
INTV
CC
+
C
TH
OUT
330µF
4.7µF
×2
R1
48.7k
1%
M2
HAT2170H
V
BG
GND
FB
–
+
SENSE
SENSE
C5
0.047µF
R
PG
30.1k
C
C
: SANYO 6TPE330MIL
OUT
IN
V
PGOOD
PULL-UP
: SANYO 63HVH22M
L1: VISHAY IHLP5050-EZERR68M01
3851A1 F11
Figure ±±. High Efficiency 3.3V/±5A Step-Down Converter
V
IN
4.5V TO 22V
MODE/PLLIN
V
IN
C
22µF
25V
+
IN
R
FREQ
160k
M1
FREQ/PLLFLTR
TG
BOOST
SW
FDS6982S
C
B
0.1µF
0.1µF
RUN
C
SS
L1
3.3µH
R
SENSE
0.01Ω
LTC3851A-1
0.1µF
V
1.8V
5A
OUT
TK/SS
C
C
R2
32.4k
1%
D
B
R
C
C
470pF
C2
CMDSH-3
C
OUT
33k
220pF
+
150µF
I
TH
INTV
CC
6.3V
×2
PANASONIC SP
R1
25.5k
1%
4.7µF
M2
FDS6982S
V
BG
GND
FB
–
+
SENSE
SENSE
1000pF
R
PG
PGOOD
V
PULL-UP
C
C
: PANASONIC EEFUEOG151R
OUT
IN
: MARCON THCR70LE1H226ZT
L1: PANASONIC ETQP6F3R3HFA
: IRC LR 2010-01-R010F
R
SENSE
3851A1 F12
Figure ±2. ±.8V/5A Converter from Design Example with Pulse Skip Operation
3851a1fa
26
LTC3851A-1
package DescripTion
UD Package
±6-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
1.45 ± 0.05
(4 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ± 0.05
3.00 ± 0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
1.45 ± 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 ± 0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3851a1fa
27
LTC3851A-1
package DescripTion
MSE Package
±6-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev C)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ± 0.102
(.112 ± .004)
2.845 ± 0.102
(.112 ± .004)
0.889 ± 0.127
(.035 ± .005)
1
8
0.35
REF
5.23
(.206)
MIN
1.651 ± 0.102
(.065 ± .004)
1.651 ± 0.102
(.065 ± .004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ± 0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
(.0120 ± .0015)
TYP
0.280 ± 0.076
(.011 ± .003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0° – 6° TYP
0.254
(.010)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MSE16) 0910 REV C
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3851a1fa
28
LTC3851A-1
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
5/11
Added H-Grade and MP-Grade parts. Reflected througout the data sheet.
1-30
3851a1fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
29
LTC3851A-1
Typical applicaTion
±.5V/±5A Synchronized at 350kHz
V
IN
6V TO 14V
PLLIN
350kHz
MODE/PLLIN
V
IN
C2
+
R5
1k
C
0.01µF
IN
180µF
M1
FREQ/PLLFLTR
TG
BOOST
SW
RJK0305DPB
C
B
C1
1000pF
0.1µF
RUN
C
SS
L1
0.68µH
R
SENSE
0.002Ω
LTC3851A-1
0.1µF
V
1.5V
15A
OUT
TK/SS
C
C
R2
43.2k
1%
D
R
B
C
7.5k
C10
33pF
C
1000pF
C2
CMDSH-3
100pF
+
C
OUT
I
INTV
CC
TH
330µF
R1
20k
1%
×2
4.7µF
M2
RJK0301DPB
V
BG
GND
FB
–
+
SENSE
SENSE
C
: SANYO 2R5TPE330M9
1000pF
OUT
R
PG
L1: SUMIDA CEP125-OR6MC
PGOOD
V
PULL-UP
R22 10Ω
R20 10Ω
3851A1 TA03
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTC3854
Small Footprint Wide V Range Synchronous Step-Down Fixed 400kHz Operating Frequency, 4.5V≤ V ≤ 38V,
IN
IN
DC/DC Controller
0.8V ≤ V
≤ 5.25V, 2mm × 3mm QFN-12
OUT
LTC3878
LTC3879
No R ™ Constant On-Time Synchronous Step-Down
Very Fast Transient Response, t
= 43ns, 4V≤ V ≤ 38V,
IN
SENSE
ON(MIN)
DC/DC Controller
0.8V ≤ V
≤ 0.9V , SSOP-16
OUT IN
No R Constant On-Time Synchronous Step-Down
Very Fast Transient Response, t
0.6V ≤ V
= 43ns, 4V≤ V ≤ 38V,
IN
SENSE
ON(MIN)
DC/DC Controller
≤ 0.9V , MSOP-16E, 3mm × 3mm QFN-16
IN
OUT
LTC3850/LTC3850-1 Dual 2-Phase, High Efficiency Synchronous Step-Down
Phase-Lockable Fixed Operating Frequency 250kHz to 780kHz,
4V≤ V ≤ 30V, 0.8V ≤ V ≤ 5.25V
LTC3850-2
DC/DC Controllers, R
Tracking
or DCR Current Sensing and
SENSE
IN
OUT
LTC3853
Triple Output, Multiphase Synchronous Step-Down DC/DC Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz,
Controller, R or DCR Current Sensing and Tracking 4V≤ V ≤ 24V, V Up to 13.5V
SENSE
IN
OUT
LTC3834/LTC3834-1 Low I , Synchronous Step-Down DC/DC Controller
Phase-Lockable Fixed Operating Frequency 140kHz to 650kHz,
4V≤ V ≤ 36V, 0.8V ≤ V ≤ 10V, I = 30µA,
Q
IN
OUT
Q
LT®3845A
LTC3775
Low I , High Voltage Synchronous Step-Down DC/DC
Adjustable Fixed Operating Frequency 100kHz to 500kHz,
4V≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, I = 30µA, TSSOP-16
Q
Controller
IN
OUT
Q
High Frequency Synchronous Voltage Mode Step-Down
DC/DC Controller
Synchronizable Fixed Frequency 250kHz to 1MHz, t
= 30ns,
ON(MIN)
4V ≤ V ≤ 38V, 0.6V ≤ V
≤ 0.8V , MSOP-16E, 3mm × 3mm
IN
IN
OUT
QFN-16
3851a1fa
LT 0511 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
30
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408)432-1900 FAX: (408) 434-0507 www.linear.com
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