LTC3876_技术文档

LTC3839

Fast, Accurate, 2-Phase,

Single-Output Step-Down DC/DC

Controller with Differential Output Sensing

DESCRIPTION

FEATURES

The LTC^®3839 is a 2-phase, single-output PolyPhase^®

synchronous step-down switching regulator controller

that drives all N-channel power MOSFETs. The controlled

on-time,valleycurrentmodecontrolarchitectureallowsfor

fast transient response and constant frequency switching

n

Wide V Range: 4.5V to 38V, V : 0.6V to 5.5V

IN

OUT

n

0.6ꢀ7 Output Voltage Accuracy Over Temperature,

Differential Output Voltage Sensing, Allowing Up to

500mV ꢁine ꢁoss at Remote ꢂround

n

Controlled On-Time, Valley Current Mode Control

FastꢁoadTransientResponse

in steady-state operation, independent of V , V

and

IN OUT

DetectTransient(DTR)ReducesV

Overshoot

load current. Its load-release transient detection feature

significantly reduces overshoot at low output voltages.

OUT

Frequency Programmable from 200kHz to 2MHz,

Synchronizable to External Clock

Differential output voltage sensing, along with a preci-

sion internal reference, offers an accurate ±±.ꢀ67 output

regulation,eveniftheremoteoutputgrounddeviatesfrom

local ground by ±ꢁ±±mV.

n

t

= 30ns, t

= 90ns

ON(MIN)

OFF(MIN)

Up to 12-Phase Operation

R

or Inductor DCR Current Sensing

SENSE

Overvoltage Protection and Current Limit Foldback

Power Good Output Voltage Monitor

Output Voltage Tracking and Adjustable Soft Start-Up

Thermally Enhanced 32-Pin (ꢁmm × ꢁmm) QFN

Package

Theswitchingfrequencycanbeprogrammedfrom2±±kHz

to2MHzwithanexternalresistorandcanbesynchronized

to an external clock. Very low t and t times allow for

ON

OFF

near ±7 and near 1±±7 duty cycles, respectively. Volt-

age tracking soft start-up and multiple safety features are

provided.

APPLICATIONS

L, LT, LTC, LTM, PolyPhase, OPTI-LOOP, Linear Technology and the Linear logo are

registered trademarks and Hot Swap and Stage Shedding are trademarks of Linear Technology

Corporation. All other trademarks are the property of their respective owners. Protected by U.S.

Patents, including ꢁ481168, ꢁ846ꢁꢁ4, ꢀꢁ8±2ꢁ8, ꢀ3±4±ꢀꢀ, ꢀ46ꢀꢁ89, ꢀ664ꢀ11.

n

Distributed Power Systems

Point-of-Load Converters

n

Computing Systems

n

Data Communication Systems

TYPICAL APPLICATION

3.3V/25A Output, 2MHz Step-Down Converter (Refer to Figure 20 for Full Design)

V

IN

Efficiency/Power ꢁoss

4.ꢁV TO 14V

–

+

–

+

1±

8

1±±

9±

8±

6±

ꢀ±

ꢁ±

SENSE1

SENSE2

INTV

V

IN

= ꢁV

DISCONTINUOUS

MODE

V

IN

CC

TG1

TG2

LTC3839

SW1

SW2

FORCED

±.3μH

V

ꢀ

OUT

CONTINUOUS

BOOST1

BOOST2

3.3V

2ꢁA

MODE

±.1μF

4ꢁ.3k

1±k

4

+

DRV

CC2

DRV

CC1

1±±μF

wꢀ

BG1

BG2

4.6μF

2

PGND

LOSS

FORCED CM

MODE/PLLIN

CLKOUT

PHASMD

RUN

LOSS

DCM

+

–

V

OUTSENSE

±

1±±

±.1

1

1±

TRACK/SS

ITH

LOAD CURRENT (A)

3839 TA±1b

18.6k

DTR

RT

SGND

3839 TA±1a

3839fa

1

LTC3839

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

V Voltage................................................. –±.3V to 4±V

IN

BOOST1, BOOST2 Voltages ....................... –±.3V to 4ꢀV

SW1, SW2 Voltages...................................... –ꢁV to 4±V

32 31 3± 29 28 26 2ꢀ 2ꢁ

INTV , DRV , DRV , EXTV , PGOOD, RUN,

CC

CC1

CC2

CC

PHASMD

MODE/PLLIN

CLKOUT

SGND

1

2

3

4

ꢁ

ꢀ

6

8

24 BG2

23 DRV

(BOOST1-SW1), (BOOST2-SW2), MODE/PLLIN

CC2

Voltages....................................................... –±.3V to ꢀV

EXTV

22

21

CC

+

–

+

V

, V

, SENSE1 , SENSE2 ,

INTV

OUTSENSE

CC

33

PGND

–

SENSE1 , SENSE2 Voltages ....................... –±.ꢀV to ꢀV

TRACK/SS Voltage....................................... –±.3V to ꢁV

RT

2± PGND

ITH

V

IN

19

TRACK/SS

+

18 DRV

16 BG1

CC1

DTR, PHASMD, RT, V

,

RNG

V

OUTSENSE

ITH Voltages ...........................–±.3V to (INTV + ±.3V)

CC

9

1± 11 12 13 14 1ꢁ 1ꢀ

Operating Junction Temperature Range

(Notes 2, 3, 4)........................................ –4±°C to 12ꢁ°C

Storage Temperature Range .................. –ꢀꢁ°C to 1ꢁ±°C

UH PACKAGE

32-LEAD (ꢁmm × ꢁmm) PLASTIC QFN

T

= 12ꢁ°C, θ = 44°C/W

JA

JMAX

EXPOSED PAD (PIN 33) IS PGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

ꢁEAD FREE FINISH

LTC3839EUH#PBF

LTC3839IUH#PBF

TAPE AND REEꢁ

PART MARKINꢂ*

3839

PACKAꢂE DESCRIPTION

TEMPERATURE RANꢂE

–4±°C to 12ꢁ°C

LTC3839EUH#TRPBF

LTC3839IUH#TRPBF

32-Lead (ꢁmm × ꢁmm) Plastic QFN

3839

–4±°C to 12ꢁ°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V unless otherwise noted (Note 3).

SYMBOꢁ

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control ꢁoops

V

Input Voltage Operating Range

4.ꢁ

±.ꢀ

38

V

IN

Regulated Output Voltage Operating Range

V

Regulated Differentially with Respect to

OUTSENSE

ꢁ.ꢁ

OUT(REG)

OUT

–

I

Q

Input DC Supply Current

RUN Enabled

Shutdown Supply Current

MODE/PLLIN = ±V, No Load

RUN = ±V

3

1ꢁ

mA

μA

V

Regulated Differential Feedback Voltage

ITH1 = 1.2V (Note ꢁ)

OUTSENSE(REG)

+

–

(V

– V

)

T = 2ꢁ°C

±.ꢁ98ꢁ

±.ꢁ9ꢀ

±.ꢁ94

±.ꢀ

±.ꢀ±1ꢁ

±.ꢀ±4

±.ꢀ±ꢀ

V

OUTSENSE

A

l

T = ±°C to 8ꢁ°C

A

T = –4±°C to 12ꢁ°C

A

l

Regulated Differential Feedback Voltage

Over Line, Load and Common Mode

V

= 4.ꢁV to 38V, ITH1 = ±.ꢁV to 1.9V

±.ꢁ91

±.ꢀ

±.ꢀ±9

V

IN

–

–±.ꢁV < V

< ±.ꢁV (Notes ꢁ, 6)

OUTSENSE

3839fa

2

LTC3839

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V unless otherwise noted (Note 3).

SYMBOꢁ

PARAMETER

CONDITIONS

MIN

TYP

±ꢁ

MAX

±2ꢁ

–ꢁ±

UNITS

nA

+

–

+

–

I

V

Input Bias Current

V

– V

= ±.ꢀV

VOUTSENSE

OUTSENSE

–

+

–2ꢁ

1.6

3±

μA

g

Error Amplifier Transconductance

Minimum Top Gate On-Time

Minimum Top Gate Off-Time

ITH = 1.2V (Note ꢁ)

mS

ns

m(EA)

t

V

IN

= 38V, V

= ±.ꢀV, R = 2±k (Note ꢀ)

ON(MIN)1,2

OUT

T

(Note ꢀ)

9±

ns

OFF(MIN)1,2

Current Sensing

–

l

V

Maximum Valley Current Sense Threshold

V

= 2V, V = ±.ꢁ6V, V

= 2.ꢁV

8±

21

39

1±±

3±

ꢁ±

12±

4±

ꢀ1

mV

SENSE(MAX)1,2

RNG

FB

SENSE

+

–

(V

– V

)

= ±V, V = ±.ꢁ6V, V

= 2.ꢁV

SENSE1,2

FB

–

= INTV , V = ±.ꢁ6V, V

= 2.ꢁV

CC FB

SENSE

–

Minimum Valley Current Sense Threshold

V

= 2V, V = ±.ꢀ3V, V

= 2.ꢁV

–ꢁ±

–1ꢁ

–2ꢁ

mV

SENSE(MIN)1,2

RNG

FB

SENSE

+

–

(V

– V

)

= ±V, V = ±.ꢀ3V, V

= 2.ꢁV

SENSE1,2

FB

–

(Forced Continuous Mode)

= INTV , V = ±.ꢀ3V, V

= 2.ꢁV

CC FB

SENSE

+

I

SENSE1,2 Pins Input Bias Current

V

SENSE

V

SENSE

= ±.ꢀV

= ꢁV

±ꢁ

1

±ꢁ±

±2

nA

μA

SENSE1,2

–

SENSE1,2 Pins Input Bias Current

V

= ±.ꢀV

= ꢁV

1.2

1±

μA

SENSE1,2

SENSE

(Internal ꢁ±±k Resistor to SGND)

Start-Up and Shutdown

l

V

RUN Pin On Threshold

V

Rising

1.1

3.3

1.2

1±±

2.ꢁ

1±

1.3

V

mV

μA

RUN

RUN Pin On Hysteresis

Falling from On Threshold

RUN

I

RUN Pin Pull-Up Current when Off

RUN Pin Pull-Up Current Hysteresis

RUN = SGND

(I – I

RUN

)

RUN(OFF)

μA

RUN(ON)

l

UVLO

INTV Undervoltage Lockout

INTV Falling

INTV Rising

3.6

4.2

V

CC

4.ꢁ

I

Soft-Start Pull-Up Current

±V < TRACK/SS < ±.ꢀV

1

μA

TRACK/SS

Frequency and Clock Synchronization

f

Clock Output Frequency

(Steady-State Switching Frequency)

R = 2±ꢁk

2±±

ꢁ±±

2±±±

kHz

T

R = 8±.ꢀk

4ꢁ±

ꢁꢁ±

T

R = 18.2k

T

Channel 2 Phase (Relative to Channel 1)

CLKOUT Phase (Relative to Channel 1)

PHASMD = SGND

18±

24±

Deg

PHASMD = Floating

PHASMD = INTV

CC

PHASMD = SGND

ꢀ±

9±

12±

Deg

PHASMD = Floating

PHASMD = INTV

CC

V

Clock Input High Level Into MODE/PLLIN

Clock Input Low Level Into MODE/PLLIN

MODE/PLLIN Input Resistance

2

V

PLLIN(H)

±.ꢁ

PLLIN(L)

R

With Respect to SGND

ꢀ±±

kΩ

MODE/PLLIN

ꢂate Drivers

R

TG Driver Pull-Up On Resistance

TG Driver Pull-Down On Resistance

BG Driver Pull-Up On Resistance

BG Driver Pull-Down On Resistance

TG High

TG Low

BG High

BG Low

2.ꢁ

1.2

2.ꢁ

±.8

2±

Ω

TG(UP)1,2

TG(DOWN)1,2

BG(UP)1,2

Ω

BG(DOWN)1,2

D(TG/BG)1,2

D(BG/TG)1,2

t

Top Gate Off to Bottom Gate On Delay Time (Note ꢀ)

Bottom Gate Off to Top Gate On Delay Time (Note ꢀ)

ns

1ꢁ

3839fa

3

LTC3839

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V unless otherwise noted (Note 3).

SYMBOꢁ

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Internal V Regulator

CC

V

Internally Regulated DRV

Voltage

ꢀV < V < 38V

ꢁ.±

ꢁ.3

–1.ꢁ

4.ꢀ

ꢁ.ꢀ

–3.ꢁ

4.8

V

7

DRVCC1

EXTVCC

CC1

IN

DRV

Load Regulation

I

= ±mA to –1±±mA

CC1

DRVCC1

EXTV Switchover Voltage

EXTV Rising

4.4

V

CC

EXTV Switchover Hysteresis

EXTV Falling from Switchover Voltage

2±±

mV

CC

EXTV to DRV

Voltage Drop

V

= ꢁV, I

= –1±±mA

CC

CC2

EXTVCC

DRVCC2

Pꢂood Output

OV

UV

PGOOD Overvoltage Threshold

PGOOD Undervoltage Threshold

PGOOD Threshold Hysteresis

PGOOD Low Voltage

V

Rising, with Respect to Regulated Voltage

Falling, with Respect to Regulated Voltage

Returning to Reference Voltage

ꢁ

6.ꢁ

–6.ꢁ

2

1±

7

V

OUT

–ꢁ

–1±

OUT

V

I

= 2mA

±.1

ꢁ±

±.3

PGOOD(L)

PGOOD

t

Delay from V Fault (OV/UV) to PGOOD

μs

D(PGOOD)

FB

Falling

Delay from V Good to PGOOD Rising

2±

μs

FB

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 2: The junction temperature (T , in °C) is calculated from the ambient

J

temperature (T , in °C) and power dissipation (P , in Watts) according to

A

D

the formula:

T = T + (P • θ )

JA

Note 5: The LTC3839 is tested in a feedback loop that adjusts the

+

–

differential feedback voltage (V

– V

) to

OUTSENSE

J

A

D

achieve specified error amplifier output voltages (ITH).

Note 6: Delay times are measured with top gate (TG) and bottom gate

(BG) driving minimum load, and using ꢁ±7 levels.

where θ (in °C/W) is the package thermal impedance.

JA

Note 3: The LTC3839 is tested under pulsed loading conditions such that

T ≈ T . The LTC3839E is guaranteed to meet specifications over the ±°C

J

A

Note ꢀ: In order to simplify the total system error computation, the

regulated voltage is defined in one combined specification which includes

the effects of line, load and common mode variation. The combined

regulated voltage specification is tested by independently varying line,

load, and common mode, which by design do not significantly affect one

another. For any combination of line, load, and common mode variation,

the regulated voltage should be within the limits specified that are tested in

production to the following conditions:

to 8ꢁ°C operating junction temperature range. Specifications over the

–4±°C to 12ꢁ°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC3839I is guaranteed to meet specifications over the –4±°C to

12ꢁ°C operating junction temperature range . Note that the maximum

ambient temperature consistent with these specifications is determined by

specific operating conditions in conjunction with board layout, the rated

package thermal impedance and other environmental factors.

–

Line: V = 4.ꢁV to 38V, ITH = 1.2V, V

= ±V

•

IN

OUTSENSE

–

Load: V = 1ꢁV, ITH = ±.ꢁV to 1.9V, V

IN

OUTSENSE

–

Common mode: V = 1ꢁV, ITH = 1.2V, to V

= ±ꢁ±±mV

IN

OUTSENSE

3839fa

4

LTC3839

TYPICAL PERFORMANCE CHARACTERISTICS

Transient Response

(Forced Continuous Mode)

ꢁoad Step

(Forced Continuous Mode)

ꢁoad Release

(Forced Continuous Mode)

I

LOAD

I

LOAD

2±A/DIV

V

OUT

V

OUT

ꢁ±mV/DIV

I

L1

1±A/DIV

I

L1

I

L1

I

L2

1±A/DIV

I

L2

I

L2

1±A/DIV

3839 G±1

3839 G±2

3839 G±3

ꢁ±μs/DIV

ꢁμs/DIV

LOAD TRANSIENT = ±A TO 3±A

LOAD STEP = ±A TO 3±A

LOAD RELEASE = 3±A TO ±A

V

= 12V

V

= 12V

V

= 12V

IN

OUT

IN

OUT

IN

OUT

= 1.2V

FIGURE 16 CIRCUIT

Transient Response

(Discontinuous Mode)

ꢁoad Step

(Discontinuous Mode)

ꢁoad Release

(Discontinuous Mode)

I

LOAD

2±A/DIV

V

OUT

V

OUT

ꢁ±mV/DIV

I

L1

I

L1

I

L1

1±A/DIV

I

L2

I

L2

I

L2

1±A/DIV

3839 G±ꢀ

3839 G±4

3839 G±ꢁ

ꢁμs/DIV

ꢁ±μs/DIV

ꢁμs/DIV

LOAD RELEASE = 3±A TO 6ꢁ±mA

LOAD TRANSIENT = 6ꢁ±mA TO 3±A

LOAD STEP = 6ꢁ±mA TO 3±A

V

= 12V

V

= 12V

V

= 12V

IN

OUT

IN

OUT

IN

OUT

= 1.2V

FIGURE 16 CIRCUIT

ꢁoad Release with Detect Transient (DTR)

Feature Enabled

ꢁoad Release with Detect Transient (DTR)

Feature Disabled

SW1

ꢁV/DIV

SW1

ꢁV/DIV

SW2

ꢁV/DIV

SW2

ꢁV/DIV

I

LOAD

2±A/DIV

V

OUT

V

OUT

2±mV/DIV

AC-COUPLED

2±mV/DIV

AC-COUPLED

3839 G±6

3839 G±8

2μs/DIV

BACK PAGE APPLICATION CIRCUIT

LOAD RELEASE = 3±A TO 1±A

BACK PAGE APPLICATION CIRCUIT,

MODIFIED: R = 1ꢀ.ꢁk (≈3ꢀ.ꢁk/3±.1k)

LOAD RELEASE = 3±A TO 1±A

ITH

V

IN

V

OUT

= ꢁV

V

= ꢁV

= ±.ꢀV

IN

OUT

= ±.ꢀV

SHADING OBTAINED WITH INFINITE PERSISTENCE ON

OSCILLOSCOPE WAVEFORMS

3839fa

5

LTC3839

TYPICAL PERFORMANCE CHARACTERISTICS

Soft Start-Up Into

Pre-Biased Output

Regular Soft Start-Up

Output Tracking

RUN

ꢁV/DIV

RUN

ꢁV/DIV

TRACK/SS

2±±mV/DIV

TRACK/SS

2±±mV/DIV

V

OUT

ꢁ±±mV/DIV

V

OUT

TRACK/SS

2±±mV/DIV

ꢁ±±mV/DIV

V

OUT

ꢁ±±mV/DIV

3839 G1±

3839 G±9

3839 G11

C

V

= 1±nF

= 12V

1ms/DIV

C

V

= 1±nF

= 12V

OUT

1ms/DIV

V

= 12V

1±ms/DIV

SS

IN

SS

IN

OUT

= 1.2V

FORCED CONTINUOUS MODE

OUT

PRE-BIASED TO ±.6ꢁV

FORCED CONTINUOUS MODE

Overcurrent Protection

Short-Circuit Protection

Overvoltage Protection

SHORT-

CIRCUIT

TRIGGER

I

L

1±A/DIV

I

L

ꢁA/DIV

OVERVOLTAGE CREATED BY APPLYING

V

OUT

A CHARGED CAPACITOR TO V

OUT

V

OUT

FULL CURRENT LIMIT

1V/DIV

1±±mV/DIV

WHEN V

HIGHER

CURRENT LIMIT STARTS TO FOLD BACK AS

OUT

AC-COUPLED

V

OUT

DROPS BELOW HALF OF REGULATED

THAN HALF OF REGULATED

I

C

L

OUT

BG1

ꢁV/DIV

V

OUT

1±A/DIV

RECHARGE

1±±mV/DIV

AC-COUPLED

3839 G14

3839 G13

3839 G12

V

= 12V

2±μs/DIV

BG STAYS ON UNTIL

IS PULLED

IN

OUT

V

LOAD

= 12V

ꢁ±±μs/DIV

V

= 12V

ꢁms/DIV

IN

OUT

= 1.2V

= ±A

= 1.2V

OUT

FORCED CONTINUOUS

MODE

V

OUT

I

FORCED CONTINUOUS MODE

BELOW OVERVOLTAGE

THRESHOLD

I

= ±A

LOAD

Phase Relationship:

PHASMD = ꢂround

Phase Relationship:

PHASMD = Float

Phase Relationship:

PHASMD = INTV_CC

PLLIN

ꢁV/DIV

PLLIN

ꢁV/DIV

PLLIN

ꢁV/DIV

SW1

1±V/DIV

SW1

1±V/DIV

SW1

1±V/DIV

±°

SW2

24±°

12±°

18±°

9±°

1±V/DIV

CLKOUT

ꢁV/DIV

CLKOUT

ꢁV/DIV

CLKOUT

ꢁV/DIV

ꢀ±°

3839 G16

3839 G1ꢁ

3839 G1ꢀ

ꢁ±±ns/DIV

FIGURE 13 CIRCUIT

V

= 12V

V

= 12V

V

= 12V

IN

LOAD = ±A

MODE/PLLIN = 333kHz EXTERNAL CLOCK

3839fa

6

LTC3839

TYPICAL PERFORMANCE CHARACTERISTICS

Output Regulation

vs Input Voltage

Output Regulation

vs ꢁoad Current

Output Regulation

vs Temperature

±.2

±.1

±.2

±.1

±

±.ꢀ

±.4

V

= 1ꢁV

V

I

= 1ꢁV

= ±.ꢀV

= ±A

V

I

= ±.ꢀV

= ꢁA

IN

OUT

= ±.ꢀV

OUT

LOAD

NORMALIZED AT I

= 8A

V

NORMALIZED AT V = 1ꢁV

LOAD

OUT

IN

V

NORMALIZED AT T = 2ꢁ°C

OUT

A

±.2

±

–±.2

–±.4

–±.ꢀ

–±.1

–±.2

±

4

8

12

1ꢀ

2±

6ꢁ 1±±

12ꢁ 1ꢁ±

–ꢁ± –2ꢁ

±

2ꢁ ꢁ±

±

ꢁ

1± 1ꢁ 2± 2ꢁ 3± 3ꢁ 4±

TEMPERATURE (°C)

V

(V)

I

(A)

IN

LOAD

3839 G19

3839 G2±

3839 G18

Error Amplifier Transconductance

vs Temperature

CꢁKOUT/Switching Frequency

vs Input Voltage

CꢁKOUT/Switching Frequency

vs Temperature

1.8±

1.6ꢁ

1.6±

1.ꢀꢁ

1.ꢀ±

1.ꢁꢁ

1.ꢁ±

2

1

2

1

V

= 1ꢁV, V

= ±.ꢀV

OUT

IN

I

= ±A

LOAD

f = ꢁ±±kHz

FREQUENCY NORMALIZED AT T = 2ꢁ°C

A

±

–1

V

= ±.ꢀV

= ꢁA

OUT

I

LOAD

f = ꢁ±±kHz

FREQUENCY NORMALIZED AT V = 1ꢁV

IN

–2

6ꢁ 1±±

TEMPERATURE (°C)

–ꢁ± –2ꢁ

±

2ꢁ ꢁ±

12ꢁ 1ꢁ±

±

ꢁ

1± 1ꢁ 2± 2ꢁ 3± 3ꢁ 4±

(V)

–ꢁ± –2ꢁ

±

2ꢁ ꢁ± 6ꢁ 1±± 12ꢁ 1ꢁ±

TEMPERATURE (°C)

V

IN

3839 G26

3839 G21

3839 G23

t_ON(MIN)and t_OFF(MIN)

vs Voltage on V_INPin

t_ON(MIN)and t_OFF(MIN)

vs Switching Frequency

vs V_OUT(Voltage on SENSE^–Pin)

1±±

9±

8±

6±

ꢀ±

ꢁ±

4±

3±

2±

1±

±

1±±

9±

8±

6±

ꢀ±

ꢁ±

4±

3±

2±

1±

±

1±±

9±

8±

6±

ꢀ±

ꢁ±

4±

3±

2±

1±

±

t

OFF(MIN)

t

ON(MIN)

t

ON(MIN)

V

= ±.ꢀV

V

= 38V

V

= 38V

OUT

T

IN

T

IN

OUT

R

ADJUSTED FOR f

= 2MHz

R

ADJUSTED FOR f

= 2MHz

4

= ±.ꢀV

CLKOUT

±

ꢁ

1ꢁ 2± 2ꢁ 3± 3ꢁ 4±

(V)

1±

±

1

3

–

ꢁ

ꢀ

2±±

ꢁ±±

11±± 14±± 16±± 2±±±

2

8±±

V

(V)

CLKOUT/SWITCHING FREQUENCY (kHz)

IN

SENSE

3839 G2ꢁ

3839 G24

3839 G2ꢀ

3839fa

7

LTC3839

TYPICAL PERFORMANCE CHARACTERISTICS

Current Sense Voltage

vs ITH Voltage

Maximum Current Sense Voltage

vs Temperature

Maximum Current Sense Voltage

vs Voltage on SENSE^–Pin

12±

1±±

8±

12±

1±±

8±

ꢀ±

4±

2±

±

12±

1±±

8±

ꢀ±

4±

2±

±

FORCED CONTINUOUS MODE

V

= 2V

V

= 2V

RNG

ꢀ±

4±

V

= 1V

V

= 1V

RNG

2±

±

V

= ±.ꢀV

V

= ±.ꢀV

RNG

–2±

–4±

V

RNG

V

RNG

V

RNG

= 2V

= 1V

= ±.ꢀV

–ꢀ±

6ꢁ 1±±

–ꢁ± –2ꢁ

±

2ꢁ ꢁ±

12ꢁ 1ꢁ±

–±.ꢁ

1.ꢁ

2.ꢁ

3.ꢁ

4.ꢁ

ꢁ.ꢁ

±

±.4

±.8

1.2

2.4

±.ꢁ

1.ꢀ

2

TEMPERATURE (°C)

SENSE PIN VOLTAGE (V)

ITH VOLTAGE (V)

3839 G29

3839 G22

3839 G28

RUN Pin Thresholds

vs Temperature

RUN Pull-Up Currents

vs Temperature

TRACK/SS Pull-Up Currents

vs Temperature

1.ꢀ

1ꢀ

14

12

1±

8

1.2±

1.1ꢁ

1.1±

1.±ꢁ

1.±±

±.9ꢁ

±.9±

±.8ꢁ

±.8±

SWITCHING REGION

STAND-BY REGION

1.4

1.2

1.±

±.8

±.ꢀ

±.4

±.2

±

RUN PIN ABOVE 1.2V

SWITCHING THRESHOLD

ꢀ

RUN PIN BELOW 1.2V

SWITCHING THRESHOLD

SHUTDOWN REGION

4

2

±

ꢁ± 6ꢁ

TEMPERATURE (°C)

ꢁ± 6ꢁ

TEMPERATURE (°C)

ꢁ± 6ꢁ

TEMPERATURE (°C)

–ꢁ± –2ꢁ

±

2ꢁ

1±± 12ꢁ 1ꢁ±

–ꢁ± –2ꢁ

±

2ꢁ

1±± 12ꢁ 1ꢁ±

–ꢁ± –2ꢁ

±

2ꢁ

1±± 12ꢁ 1ꢁ±

3839 G3±

3839 G31

3839 G32

INTV_CCUndervoltage ꢁockout

Thresholds vs Temperature

Shutdown Current Into V_INPin

vs Voltage on V_INPin

Quiescent Current Into V_INPin

vs Temperature

3.ꢁ

4±

3ꢁ

3±

2ꢁ

2±

1ꢁ

1±

ꢁ

4.ꢁ

4.3

4.1

3.9

3.6

3.ꢁ

3.3

UVLO RELEASE

(INTV RISING)

CC

3.±

2.ꢁ

2.±

1.ꢁ

1.±

UVLO LOCK

(INTV FALLING)

CC

13±°C

2ꢁ°C

–4ꢁ°C

±

2± 2ꢁ

(V)

ꢁ±

TEMPERATURE (°C)

±

ꢁ

1± 1ꢁ

3± 3ꢁ 4±

–ꢁ± –2ꢁ

±

2ꢁ

6ꢁ 1±± 12ꢁ 1ꢁ±

6ꢁ 1±±

–ꢁ± –2ꢁ

±

2ꢁ ꢁ±

12ꢁ 1ꢁ±

TEMPERATURE (°C)

V

IN

3839 G34

3839 G3ꢁ

3839 G33

3839fa

8

LTC3839

PIN FUNCTIONS

PHASMD (Pin 1): Phase Selector Input. This pin

determines the relative phases of channels and the

CLKOUT signal. With zero phase being defined as the

rising edge of TG1: Pulling this pin to SGND locks TG2 to

pull-up current source is connected to TRACK/SS pin. A

capacitor to ground at this pin sets the ramp time to the

finalregulatedoutputvoltage.Alternatively,anothervoltage

supply connected to this pin allows the output to track the

other supply during start-up.

18±°, and CLKOUT to ꢀ±°. Connecting this pin to INTV

CC

locks TG2 to 24±° and CLKOUT to 12±°. Floating this pin

+

V

(Pin 8): Differential Output Sense Amplifier

OUTSENSE

locks TG2 to 18±° and CLKOUT to 9±°.

(+) Input. Connect this pin to a feedback resistor divider

between the positive and negative output capacitor ter-

MODE/PꢁꢁIN(Pin2):OperationModeSelectionorExternal

minals of V . In nominal operation the LTC3839 will

Clock Synchronization Input. When this pin is tied to IN-

OUT

attempt to regulate the differential output voltage V

±.ꢀV divided by the feedback resistor divider ratio.

to

TV ,forcedcontinuousmodeoperationisselected.Tying

OUT

CC

this pin to SGND allows discontinuous mode operation.

When an external clock is applied at this pin, both chan-

nels operate in forced continuous mode and synchronize

to the external clock.

–

V

(Pin 9): Differential Output Sense Amplifier

OUTSENSE

(–) Input. Connect this pin to the negative terminal of the

output load capacitor of V

.

OUT

+

CꢁKOUT (Pin 3): Clock Output of Internal Clock Genera-

SENSE1 , SENSE2 (Pin 10, Pin 31): Differential Current

tor. Its output level swings between INTV and SGND. If

CC

Sense Comparator (+) Inputs. The ITH pin voltage and

controlled offsets between the SENSE and SENSE pins

set the current trip threshold. The comparator can be used

+

–

clock input is present at the MODE/PLLIN pin, it will be

synchronized to the input clock, with phase set by the

PHASMD pin. If no clock is present at MODE/PLLIN, its

frequency will be set by the RT pin. To synchronize other

controllers,itcanbeconnectedtotheirMODE/PLLINpins.

for R

sensing or inductor DCR sensing. For R

SENSE

+

sensing, Kelvin (4-wire) connect the SENSE pin to the

(+) terminal of R

+

. For DCR sensing, tie the SENSE

SENSE

pins to the connection between the DCR sense capacitor

and sense resistor tied across the inductor.

SꢂND(Pins4, 29):SignalGround. Allsmall-signalanalog

and compensation components should be connected to

this ground. Connect both SGND pins to the exposed pad

and PGND pin using a single PCB trace.

–

SENSE1 ,SENSE2 (Pin11,Pin30):DifferentialCurrent

SenseComparator(–)Input.Thecomparatorcanbeused

for R

sensing or inductor DCR sensing. For R

SENSE

RT (Pin 5): Clock Generator Frequency Programming Pin.

Connect an external resistor from RT to SGND to program

the switching frequency between 2±±kHz and 2MHz. An

external clock applied to MODE/PLLIN should be within

±3±7 of this programmed frequency to ensure frequency

lock.WhentheRTpinisfloating,thefrequencyisinternally

set to be slightly under 2±±kHz.

–

sensing,Kelvin(4-wire)connecttheSENSE pintothe(–)

–

terminal of R

. For DCR sensing, tie the SENSE pin

SENSE

totheDCRsensecapacitortiedtotheinductorV

node

OUT

connection. These pins also function as output voltage

sense pins for the top MOSFET on-time adjustment. The

impedance looking into these pins is different from the

+

SENSE pins because there is an additional ꢁ±±k internal

–

ITH (Pins 6): Current Control Threshold. This pin is the

output of the error amplifier and the switching regulator’s

compensation point. The current comparator threshold

increases with this control voltage. The voltage ranges

from ±V to 2.4V, with ±.8V corresponding to zero sense

voltage (zero inductor valley current).

resistor from each of the SENSE pins to SGND.

DTR(Pin12):DetectLoad-ReleaseTransientforOvershoot

Reduction.Whenloadcurrentsuddenlydrops,ifvoltageon

this DTR pin drops below half of INTV , the bottom gate

CC

(BG) could turn off, allowing the inductor current to drop

to zero faster, thus reducing the V

overshoot. (Refer

OUT

TRACK/SS (Pin ꢀ): External Tracking and Soft-Start Input.

to Load-Release Transient Detection in the Applications

Information section for more details.) An internal ꢁꢂA

+

The LTC3839 regulates the feedback voltage (V

OUTSENSE

–

– V

) to the smaller of ±.ꢀV or the voltage on the

TRACK/SS pin. An internal 1μA temperature-independent

current source pulls this pin toward INTV . To disable

OUTSENSE

CC

the DTR feature, simply tie the DTR pin to INTV .

CC

3839fa

9

LTC3839

PIN FUNCTIONS

PꢂOOD (Pin 13): Power Good Indicator Output. This

open-drain logic output is pulled to ground when the

output voltage goes out of a ±6.ꢁ7 window around the

regulation point, after a ꢁ±μs power-bad-masking delay.

Returning to the regulation point, there is a 2±μs delay to

power good, and a hysteresis of around 27 on both sides

of the voltage window.

C

and the (–) terminal of C . Connect the exposed

DRVCC IN

pad and PGND pin to SGND pin using a single PCB trace

under the IC. The exposed pad must be soldered to the

circuit board ground for electrical connection and rated

thermal performance.

INTV (Pin 21): Supply Input for Internal Circuitry (Not

CC

IncludingGateDrivers).NormallypoweredfromtheDRV

CC

BOOST1, BOOST2 (Pin 14, Pin 2ꢀ): Boosted Floating

pins through a decoupling RC filter to SGND (typically

Supplies for Top MOSFET Drivers. The (+) terminal of the

2Ω and 1μF).

bootstrap capacitor, C , connects to this pin. The BOOST

B

EXTV (Pin 22): External Power Input. When EXTV

CC

pins swing by a V between a diode drop below DRV ,

IN

CC

exceedstheswitchovervoltage(typically4.ꢀV),aninternal

or (DRV – V ) and (V + DRV – V ).

CC

D

IN

CC

D

switch connects this pin to DRV and shuts down the

CC2

CC

Tꢂ1, Tꢂ2 (Pin 15, Pin 26): Top Gate Driver Outputs. The

internal regulator so that INTV and gate drivers draw

TGpinsdrivethegatesofthetopN-channelpowerMOSFET

power from EXTV . The V pin still needs to be powered

CC IN

with a voltage swing of V

between SW and BOOST.

up but draws minimum current.

DRVCC

SW1, SW2 (Pin 16, Pin 25): Switch Node Connection to

RUN (Pin 28): Run Control Inputs. An internal propor-

tional-to-absolute-temperature (PTAT) pull-up current

source (~2.ꢁμA at 2ꢁ°C) is constantly connected to this

pin. Taking the RUN pin below a threshold voltage (~±.8V

Inductors. Voltage swings are from a diode voltage below

ground to V . The (–) terminal of the bootstrap capacitor,

IN

C , connects to this node.

B

at 2ꢁ°C) shuts down all bias of INTV and DRV and

CC

Bꢂ1, Bꢂ2 (Pin 1ꢀ, Pin 24): Bottom Gate Driver Outputs.

places the LTC3839 into micropower shutdown mode.

Allowing the RUN pin to rise above this threshold would

turn on the internal bias supply and the circuitry. When

the RUN pin rises above 1.2V, both channels’ TG and BG

drivers are turned on and an additional 1±μA temperature-

independent pull-up current is connected internally to the

RUN pin. The RUN pin can sink up to 1±±μA, or be forced

no higher than ꢀV.

TheBGpinsdrivethegatesofthebottomN-channelpower

MOSFET between PGND and DRV .

CC

DRV , DRV

(Pin 18, Pin 23): Supplies of Bottom

CC1

CC2

Gate Drivers. DRV is also the output of an internal ꢁ.3V

regulator. DRV is also the output of the EXTV switch.

CC2

CC

Normally the two DRV pins are shorted together on the

CC

PCB, and decoupled to PGND with a minimum of 4.6μF

ceramic capacitor, C

.

DRVCC

V

(Pin 32): Current Sense Voltage Range Input. When

RNꢂ

V

IN

(Pin 19): Input Voltage Supply. The supply voltage

programmed between ±.ꢀV and 2V, the voltage applied to

can range from 4.ꢁV to 38V. For increased noise immunity

decouple this pin to SGND with an RC filter. Voltage at this

pin is also used to adjust top gate on-time, therefore it

is recommended to tie this pin to the main power input

supply through an RC filter.

V

is twenty times (2±×) the maximum sense voltage

RNG

+

–

between SENSE1,2 and SENSE1,2 , i.e., for either chan-

+

–

nel, (V

– V

) = ±.±ꢁ • V . If a V

is tied

SENSE

RNG

to SGND, the channel operates with a maximum sense

voltage of 3±mV, equivalent to a V of ±.ꢀV; If tied to

RNG

INTV , a maximum sense voltage of ꢁ±mV, equivalent

CC

PꢂND (Pin 20, Exposed Pad Pin 33): Power Ground.

Connect this pin as close as practical to the source of

the bottom N-channel power MOSFET, the (–) terminal of

to a V

of 1V.

RNG

3839fa

10

LTC3839

FUNCTIONAL DIAGRAM

V

IN

EN LDO

OUT SD

2-ꢁμA

1±μA

PTAT

+

–

4.2V

UVLO

BOOST

TG

DRV

RUN

C

B

D

B

+

M

T

R

SENSE

L

SW

EN_DRV

1.2V

–

V

OUT

DRV

CC

EXTV

CC

+

–

+

~4.ꢀV

INTV

~±.8V

CC

–

LOGIC

CONTROL

C

OUT

INTVCC

DRV

CC2

CC1

–

SENSE

START

STOP

V

2ꢁ±k

IN

C

DRVCC

ONE-SHOT

TIMER

R

FB2

FB1

BG DRV

BG

2ꢁ±k

M

B

FORCED

CONTINUOUS

MODE

ON-TIME

ADJUST

PGND

MODE/PLLIN

PHASE

DETECTOR

MODE/CLK

DETECT

I

REV

CMP

+

–

CLK1

CLK2

+

–

RT

SENSE

CLOCK PLL/

GENERATOR

TO CHANNEL 2

SENSE

R

T

DUPLICATE DASHED

LINE BOX FOR

CHANNEL 2

CLKOUT

1μA

g

m

g

m

INTV

CC

EA

TRACK/SS

+

–

+

±.ꢁꢁꢁV

R

±.ꢀV

PGD

C

SS

UV

PGOOD

+

V

OUTSENSE1

–

+

–

DIFFAMP

(A = 1)

DELAY

–

V

OUTSENSE1

+

3839 FD

OV

SGND

INTV

CC

±.ꢀ4ꢁV

–

LOAD

1/2 INTV

DTR

+

–

RELEASE

CC

DETECTION

TO LOGIC

CONTROL

V

I

TH

RNG

INTV

CC

INTV

CC

C

ITH1

R

ITH2

R

ITH1

C

ITH2

3839fa

11

LTC3839

OPERATION ^{(Refer to Functional Diagram)}

Main Control ꢁoop

TheLTC3839featuresadetecttransient(DTR)pintodetect

“load-release”, or a transient where the load current sud-

denly drops, by monitoring the first derivative of the ITH

voltage. When detected, the bottom gate (BG) is turned

off and inductor current flows through the body diode

in the bottom MOSFET, allowing the SW node voltage to

dropbelowPGNDbythebodydiode’sforward-conduction

voltage. This creates a more negative differential voltage

The LTC3839 is a controlled on-time, valley current mode

step-down DC/DC single-output controller with two chan-

nelsoperatingoutofphase.Eachchanneldrivesbothmain

and synchronous N-channel MOSFETs.

ThetopMOSFETisturnedonforatimeintervaldetermined

by a one-shot timer. The duration of the one-shot timer is

controlled to maintain a fixed switching frequency. As the

top MOSFET is turned off, the bottom MOSFET is turned

on after a small delay. The delay, or dead time, is to avoid

both top and bottom MOSFETs being on at the same time,

(V – V ) across the inductor, allowing the inductor

SW

OUT

current to drop faster to zero, thus creating less overshoot

onV . SeeLoad-ReleaseTransientDetectioninApplica-

OUT

tions Information for details.

causing shoot-through current from V directly to power

IN

ground. The next switching cycle is initiated when the cur-

Differential Output Sensing

rent comparator, I

, senses that inductor current falls

CMP

TheLT3839featuresdifferentialoutputvoltagesensing.The

output voltage is resistively divided externally to create a

feedback voltage for the controller. The internal difference

amplifier (DIFFAMP) senses this feedback voltage with

respecttotheoutput’sremotegroundreferencetocreatea

differential feedback voltage. This scheme eliminates any

ground offsets between local ground and remote output

ground, resulting in a more accurate output voltage. It al-

lowsremoteoutputgroundtodeviateasmuchas±ꢁ±±mV

with respect to local ground (SGND).

below the trip level set by voltages at the ITH and V

RNG

pins. The bottom MOSFET is turned off immediately and

the top MOSFET on again, restarting the one-shot timer

and repeating the cycle. In order to avoid shoot-through

current, there is also a small dead-time delay before the

top MOSFET turns on. At this moment, the inductor cur-

rent hits its “valley” and starts to rise again.

Inductor current is determined by sensing the voltage

+

–

between SENSE and SENSE , either by using an explicit

resistorconnectedinserieswiththeinductororbyimplic-

itly sensing the inductor’s DC resistive (DCR) voltage drop

through an RC filter connected across the inductor. The

DRV /EXTV /INTV Power

CC

DRV

are the power for the bottom MOSFET drivers.

CC1,2

trip level of the current comparator, I

, is proportional

CMP

Normally the two DRV pins are shorted together on

CC

to the voltage at the ITH pin, with a zero-current threshold

the PCB, and decoupled to PGND with a minimum 4.6μF

corresponding to an ITH voltage of around ±.8V.

ceramic capacitor, C

. The top MOSFET drivers are

DRVCC

biased from the floating bootstrap capacitors (C

)

The error amplifier (EA) adjusts this ITH voltage by com-

paring the feedback signal to the internal ±.ꢀV reference

voltage. The difference amplifier (DIFFAMP) converts the

B1,2

whicharerechargedduringeachcyclethroughanexternal

Schottky diode when the top MOSFET turns off and the

SW pin swings down.

+

–

differential feedback signal (V

– V

) to

OUTSENSE

a single-ended input for the EA. Output voltage is regu-

lated so that the feedback voltage is equal to the internal

±.ꢀV reference. If the load current increases/decreases, it

causes a momentary drop/rise in the differential feedback

voltage relative to the reference. The EA then moves ITH

voltage, or inductor valley current setpoint, higher/lower

until the average inductor current again matches the load

current, so that the output voltage comes back to the

regulated voltage.

The DRV can be powered on two ways: an internal low-

CC

dropout (LDO) linear voltage regulator that is powered

from V and can output ꢁ.3V to DRV . Alternatively,

IN

CC1

an internal EXTV switch (with on-resistance of around

CC

2Ω) can short the EXTV pin to DRV

.

CC

CC2

If the EXTV pin is below the EXTV switchover voltage

CC

(typically 4.ꢀV with 2±±mV hysteresis, see the Electrical

3839fa

12

LTC3839

OPERATION ^{(Refer to Functional Diagram)}

Characteristics Table), then the internal ꢁ.3V LDO is en-

The start-up of the output voltage (V ) is controlled by

OUT

abled.IftheEXTV pinistiedtoanexternalvoltagesource

the voltage on the TRACK/SS pin. When the voltage on the

TRACK/SS pin is less than the ±.ꢀV internal reference, the

differential feedback voltage is regulated to the TRACK/SS

voltage instead of the ±.ꢀV reference. The TRACK/SS

pin can be used to program the output voltage soft-start

ramp-uptimebyconnectinganexternalcapacitorfromthe

TRACK/SS pin to signal ground. An internal temperature-

independent 1μA pull-up current charges this capacitor,

creating a voltage ramp on the TRACK/SS pin. As the

TRACK/SS voltage rises linearly from ground to ±.ꢀV, the

CC

greaterthanthisEXTV switchovervoltage, thentheLDO

CC

is shut down and the internal EXTV switch shorts the

CC

EXTV pin to the DRV

pin, thereby powering DRV

and INTV with the external voltage source and helping

CC

CC2

CC

to increase overall efficiency and decrease internal self

heating from power dissipated in the LDO. This external

power source could be the output of the step-down con-

verteritself(iftheoutputisprogrammedtohigherthanthe

switchover voltage’s higher limit, 4.8V). The V pin still

IN

needs to be powered up but now draws minimum current.

switchingstarts, V

rampsupsmoothlytoitsfinalvalue

OUT

and the feedback voltage to ±.ꢀV. TRACK/SS will keep

rising beyond ±.ꢀV, until being clamped to around 3.6V.

Power for most internal control circuitry other than gate

drivers is derived from the INTV pin. INTV can be

CC

powered from the combined DRV pins (either directly,

Alternatively, the TRACK/SS pin can be used to track an

external supply like in a master slave configuration. Typi-

cally, this requires connecting a resistor divider from the

master supply to the TRACK/SS pin (see the Applications

Information section).

CC

orthroughanexternalRCfiltertoSGNDtofilteroutnoises

due to switching).

Shutdown and Start-Up

The RUN pin has an internal proportional-to-absolute-

temperature (PTAT) pull-up current source (around 2.ꢁμA

at 2ꢁ°C). Taking the RUN pin below a certain threshold

voltage (around ±.8V at 2ꢁ°C) shuts down all bias of

TRACK/SS is pulled low internally when the RUN pin is

pulled below the 1.2V threshold (hysteresis applies), or

when INTV or DRV drop below their undervoltage

CC

lockout (UVLO) threshold.

INTV andDRV andplacestheLTC3839intomicropower

CC

shutdown mode with a minimum I at the V pin. The

ꢁight ꢁoad Current Operation

Q

IN

LTC3839’s DRV (through the internal ꢁ.3V LDO regula-

CC

IftheMODE/PLLINpinistiedtoINTV oranexternalclock

CC

tor or EXTV ) and the corresponding channel’s internal

CC

is applied to MODE/PLLIN, the LTC3839 will be forced to

operate in continuous mode. With load current less than

one-half of the full load peak-to-peak ripple, the inductor

current valley can drop to zero or become negative. This

allows constant-frequency operation but at the cost of low

efficiency at light loads.

circuitry off INTV will be biased up when either or both

CC

RUN pins are pulled up above the ±.8V threshold, either by

the internal pull-up current or driven directly by external

voltage source such as logic gate output.

Neither of the two channels will start switching until

the RUN pin is pulled up to 1.2V. When the RUN pin

rises above 1.2V, both channels’ TG and BG drivers are

enabled, and TRACK/SS released. An additional 1±μA

temperature-independent pull-up current is connected

internally to the RUN pin. To turn off TG, BG and the ad-

ditional1±μApull-upcurrent,RUNneedstobepulleddown

below 1.2V by about 1±±mV. These built-in current and

voltagehysteresespreventfalsejitteryturn-onandturn-off

due to noise. Such features on the RUN pin allow input

undervoltage lockout (UVLO) to be set up using external

If the MODE/PLLIN pin is left open or connected to signal

ground,thechannelwilltransitionintodiscontinuousmode

operation,whereacurrentreversalcomparator(I )shuts

REV

off the bottom MOSFET (M ) as the inductor current ap-

B

proaches zero, thus preventing negative inductor current

and improving light-load efficiency. In this mode, both

switches can remain off for extended periods of time. As

the output capacitor discharges by load current and the

output voltage droops lower, EA will eventually move the

ITH voltage above the zero current level (±.8V) to initiate

another switching cycle.

voltage divider from V .

IN

3839fa

13

LTC3839

OPERATION ^{(Refer to Functional Diagram)}

Power ꢂood and Fault Protection

Frequency Selection and External Clock

Synchronization

The PGOOD pin is connected to an internal open-drain

N-channel MOSFET. An external resistor or current

An internal oscillator (clock generator) provides phase-

interleaved internal clock signals for individual channels

to lock up to. The switching frequency and phase of each

switching channel are independently controlled by adjust-

ing the top MOSFET turn-on time (on-time) through the

one-shot timer. This is achieved by sensing the phase

relationship between a top MOSFET turn-on signal and

its internal reference clock through a phase detector, and

the time interval of the one-shot timer is adjusted on a

cycle-by-cycle basis, so that the rising edge of the top

MOSFET turn-on is always trying to synchronize to the

internal reference clock signal for the respective channel.

source can be used to pull this pin up to ꢀV (e.g., V

OUT

or DRV ). Overvoltage or undervoltage comparators

CC

(OV, UV) turn on the MOSFET and pull the PGOOD pin low

when the feedback voltage is outside the ±6.ꢁ7 window

of the ±.ꢀV reference voltage. The PGOOD pin is also

pulled low when the RUN pin is below the 1.2V threshold

(hysteresis applies), or in undervoltage lockout (UVLO).

Note that feedback voltage is sensed differentially through

+

–

V

with respect to V

.

OUTSENSE

When the feedback voltage is within the ±6.ꢁ7 window,

the open-drain NMOS is turned off and the pin is pulled

up by the external source. The PGOOD pin will indicate

power good immediately after the feedback is within the

window. But when a feedback voltage of a channel goes

out of the window, there is an internal ꢁ±μs delay before

its PGOOD is pulled low. In an overvoltage (OV) condition,

Thefrequencyoftheinternaloscillatorcanbeprogrammed

from2±±kHzto2MHzbyconnectingaresistor,R ,fromthe

T

RT pin to signal ground (SGND). The RT pin is regulated

to 1.2V internally.

For applications with stringent frequency or interference

requirements, an external clock source connected to the

MODE/PLLIN pin can be used to synchronize the internal

clock signals through a clock phase-locked loop (Clock

PLL). The LTC3839 operates in forced continuous mode

of operation when it is synchronized to the external clock.

The external clock frequency has to be within ±3±7 of the

internal oscillator frequency for successful synchroniza-

tion. The clock input levels should be no less than 2V for

“high” and no greater than ±.ꢁV for “low”. The MODE/

PLLIN pin has an internal ꢀ±±k pull-down resistor.

M is turned off and M is turned on immediately without

T

B

delay and held on until the overvoltage condition clears.

Foldback current limiting is provided if the output is below

one-half of the regulated voltage, such as being shorted to

ground.Asthefeedbackapproaches±V,theinternalclamp

voltage for the ITH pin drops from 2.4V to around 1.3V,

which reduces the inductor valley current level to about

3±7 of its maximum value. Foldback current limiting is

disabled at start-up.

3839fa

14

LTC3839

OPERATION ^{(Refer to Functional Diagram)}

Multichip Operation

Table 2

NUMBER OF

ꢁTC3839

PIN CONNECTIONS

The PHASMD pin determines the relative phases between

the internal reference clock signals for the two channels

as well as the CLKOUT signal, as shown in Table 1. The

phases tabulated are relative to zero degree (±°) being

defined as the rising edge of the internal reference clock

signal of channel 1. The CLKOUT signal can be used to

synchronizeadditionalpowerstagesinamultiphasepower

supplysolutionfeedingeitherasinglehighcurrentoutput,

or separate outputs.

PHASES

[PIN NAME (CHIP NUMBER)]

2

3

1

PHASMD(1) = FLOAT or SGND

2, or 1 +

LTC3833

PHASMD(1) = INTV

CC

MODE/PLLIN(2) = CLKOUT(1)

4

ꢀ

2

PHASMD(1) = FLOAT

PHASMD(2) = FLOAT or SGND

MODE/PLLIN(2) = CLKOUT(1)

3

PHASMD(1) = SGND

PHASMD(2) = SGND

MODE/PLLIN(2) = CLKOUT(1)

PHASMD(3) = FLOAT or SGND

MODE/PLLIN(3) = CLKOUT(2)

The system can be configured for up to 12-phase opera-

tion with a multichip solution. Typical configurations are

shown in Table 2 to interleave the phases of the channels.

12

ꢀ

PHASMD(1) = SGND

PHASMD(2) = SGND

MODE/PLLIN(2) = CLKOUT(1)

PHASMD(3) = FLOAT

Table 1

MODE/PLLIN(3) = CLKOUT(2)

PHASMD(4) = SGND

PHASMD

Channel 1

Channel 2

CLKOUT

SꢂND

±°

FꢁOAT

±°

INTV

CC

MODE/PLLIN(4) = CLKOUT(3)

PHASMD(ꢁ) = SGND

±°

18±°

ꢀ±°

18±°

9±°

24±°

12±°

MODE/PLLIN(ꢁ) = CLKOUT(4)

PHASMD(ꢀ) = FLOAT or SGND

MODE/PLLIN(ꢀ) = CLKOUT(ꢁ)

Tomakeasingle-outputconverterofthreeormorephases,

additional LTC3839 or LTC3833 chips can be used.

• Tie the ITH pin to the ITH pin of the first chip

• Tie the RUN pin to the RUN pin of the first chip

+

• Tie the V

chip

pin to the V

pin of the first

OUTSENSE

–

• Tie the V

chip

pin to the V

pin of the first

OUTSENSE

• Tie the TRACK/SS pin to the TRACK/SS pin of the first

chip

3839fa

15

LTC3839

APPLICATIONS INFORMATION

Once the required output voltage and operating frequency

have been determined, external component selection is

driven by load requirement, and begins with the selec-

tion of inductors and current sense method (either sense

Differentialoutputsensingallowsformoreaccurateoutput

regulation in high power distributed systems having large

line losses. Figure 2 illustrates the potential variations in

the power and ground lines due to parasitic elements.

The variations may be exacerbated in multi-application

systems with shared ground planes. Without differential

outputsensing, thesevariationsdirectlyreflectasanerror

in the regulated output voltage. The LTC3839’s differential

output sensing can correct for up to ±ꢁ±±mV of variation

in the output’s power and ground lines.

resistors R

or inductor DCR sensing). Next, power

SENSE

MOSFETs are selected. Finally, input and output capaci-

tors are selected.

Output Voltage Programming

As shown in Figure 1, an external resistor divider is

used from the regulated output to its ground references

The LTC3839’s differential output sensing scheme is

distinct from conventional schemes where the regulated

output and its ground reference are directly sensed with

a difference amplifier whose output is then divided down

with an external resistor divider and fed into the error

amplifier input. This conventional scheme is limited by

the common mode input range of the difference amplifier

and typically limits differential sensing to the lower range

of output voltages.

to program the output voltage. The resistive divider is

+

tapped by the V

pin and the ground reference

OUTSENSE

–

is remotely sensed by the V

pin. By regulating

the differential feedback voltages to the internal reference

±.ꢀV, the resulting output voltage is:

–

V

OUT

– V

= ±.ꢀV • (1 + R /R

)

OUTSENSE

FB2 FB1

For example, if V

is programmed to ꢁV and the out-

OUT

put ground reference is sitting at –±.ꢁV with respect to

SGND, then the absolute value of the output will be 4.ꢁV

with respect to SGND. The minimum differential output

voltage is limited to the internal reference ±.ꢀV, and the

maximum is ꢁ.ꢁV.

The LTC3839 allows for seamless differential output sens-

ing by sensing the resistively divided feedback voltage

differentially. This allows for differential sensing in the full

output range from ±.ꢀV to ꢁ.ꢁV. The difference amplifier

(DIFFAMP) has a bandwidth of 8MHz, high enough so that

it will not affect main loop compensation and transient

behavior.

V

OUT

To avoid noise coupling into the feedback voltage, the

+

resistordividersshouldbeplacedclosetotheV

LTC3839

V

OUTSENSE

R

FB2

FB1

–

and V

pins. Remote output and ground traces

OUTSENSE

+

–

C

OUT

OUTSENSE

should be routed together as a differential pair to the

remote output. For best accuracy, these traces to the

remote output and ground should be connected as close

as possible to the desired regulation point.

3839 F±1

V

OUTSENSE

Figure 1. Setting Output Voltage

Switching Frequency Programming

+

The choice of operating frequency is a trade-off between

efficiencyandcomponentsize.Loweringtheoperatingfre-

quencyimprovesefficiencybyreducingMOSFETswitching

losses but requires larger inductance and/or capacitance

The V

pin is a high impedance pin with no in-

OUTSENSE

put bias current other than leakage in the nA range. The

–

V

pin has about 3±μA of current flowing out

OUTSENSE

of the pin.

3839fa

16

LTC3839

APPLICATIONS INFORMATION

+

C

IN

V

C

IN

–

POWER TRACE

PARASITICS

M

T

L

LTC3839

+

±V

DROP(PWR)

B

–

V

R

V

OUTSENSE

I

LOAD

C

OUT1

OUT2

I

R

LOAD

FB2

FB1

GROUND TRACE

PARASITICS

±V

DROP(GND)

OTHER CURRENTS

FLOWING IN

SHARED GROUND

PLANE

3839 F±2

Figure 2. Differential Output Sensing Used to Correct ꢁine ꢁoss Variations

in a High Power Distributed System with a Shared ꢂround Plane

to maintain low output ripple voltage. Conversely, raising

the operating frequency degrades efficiency but reduces

component size.

generally results in lower efficiency because of MOSFET

gate charge losses. In addition to this basic trade-off, the

effect of inductor value on ripple current and low current

operation must also be considered.

The switching frequency of the LTC3839 can be pro-

grammed from 2±±kHz to 2MHz by connecting a resistor

from the RT pin to signal ground. The value of this resistor

can be chosen according to the following formula:

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆I decreases with higher

L

inductance or frequency and increases with higher V :

IN

41550

⎛

⎞

V

f •L

V_OUT

⎛

⎞

OUT

R kΩ =

–2.2

[

]

T

ΔI_L=

1–

⎜

⎝

⎟

⎠

⎜

⎟

f kHz

[

]

V

⎝

⎠

IN

The overall controller system, including the clock PLL

and switching channels, has a synchronization range of

no less than ±3±7 around this programmed frequency.

Therefore, during external clock synchronization be sure

thattheexternalclockfrequencyiswithinthis±3±7range

of the RT programmed frequency. It is advisable that the

RT programmed frequency be equal the external clock for

maximum synchronization margin. Refer to the “Phase

and Frequency Synchronization” section for more details.

Accepting larger values of ∆I allows the use of low induc-

L

tances, but results in higher output voltage ripple, higher

ESRlossesintheoutputcapacitor,andgreatercorelosses.

A reasonable starting point for setting ripple current is ∆I

L

= ±.4 • I

. The maximum ∆I occurs at the maximum

MAX

L

input voltage. To guarantee that ripple current does not

exceed a specified maximum, the inductance should be

chosen according to:

⎛

⎞ ⎛

⎟ ⎜

⎞

V_OUT

f • ΔI

V_OUT

L =

1–

⎜

⎟

Inductor Value Calculation

V

⎝

_L(MAX)⎠ ⎝

⎠

IN(MAX)

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smaller inductor and capacitor values. A higher frequency

3839fa

17

LTC3839

APPLICATIONS INFORMATION

Inductor Core Selection

Current ꢁimit Programming

Once the value for L is known, the type of inductor must

be selected. The two basic types are iron powder and fer-

rite. The iron powder types have a soft saturation curve

which means they do not saturate hard like ferrites do.

However, iron powder type inductors have higher core

losses. Ferrite designs have very low core loss and are

preferred at high switching frequencies, so design goals

canconcentrateoncopperlossandpreventingsaturation.

The current sense comparators’ maximum trip voltage

+

–

between SENSE and SENSE (or “sense voltage”), when

ITH is clamped at its maximum 2.4V, is set by the voltage

applied to the V

pin and is given by:

RNG

V

= ±.±ꢁV

RNG

SENSE(MAX)

The valley current mode control loop does not allow the

inductor current valley to exceed ±.±ꢁV . Note that ITH

RNG

is close to 2.4V when in current limit.

Core loss is independent of core size for a fixed inductor

value, but it is very dependent on inductance selected. As

inductanceincreases,corelossesgodown.Unfortunately,

increased inductance requires more turns of wire and

therefore copper losses will increase.

AnexternalresistivedividerfromINTV canbeusedtoset

CC

the voltage on a V

pin between ±.ꢀV and 2V, resulting

RNG

in a maximum sense voltage between 3±mV and 1±±mV.

Such wide voltage range allows for variety of applications.

The V

pin can also be tied to either SGND or INTV

RNG

CC

Ferrite core material saturates hard, which means that in-

ductance collapses abruptly when the peak design current

is exceeded. This results an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

to force internal defaults. When V

is tied to SGND, the

RNG

device has an equivalent V

is tied to INTV , the device has an equivalent V

of ±.ꢀV. When the V

RNG

of 2V.

CC

RNG

Sufficient margin should be allowed to account for IC

and external component tolerances. The Electrical Char-

acteristics (EC) table gives the maximum valley current

A variety of inductors designed for high current, low volt-

ageapplicationsareavailablefrommanufacturerssuchas

Sumida, Panasonic, Coiltronics, Coilcraft, Toko, Vishay,

Pulse and Würth.

sense threshold, V

, which is the guaranteed

SENSE(MAX)1,2

specificationovertheoperatingjunctiontemperaturerange

foreitherofthetwochannelsofLTC3839. Whendesigning

an application, the maximum value in the EC table should

always be used to assure that the maximum possible

current in a single channel does not exceed the rating of

the external components, such as power MOSFETs and

inductors, in a worse case fault condition.

Current Sense Pins

Inductor current is sensed through voltage between

+

–

SENSE andSENSE pins,theinputsoftheinternalcurrent

comparators. TheinputvoltagerangeoftheSENSEpinsis

–±.ꢁV to ꢁ.ꢁV. Care must be taken not to float these pins

Toensureamultiphasesingle-outputapplicationcandeliver

its desired full load current, the minimum output current

capability of the application can be determined from the

+

during normal operation. The SENSE pins are quasi-high

+

impedance inputs. There is no bias current into a SENSE

–

pin when its corresponding channel’s SENSE pin ramps

lowerlimitsofV

. ForLTC3839, thiscanbedone

SENSE(MAX)

up from below 1.1V and stays below 1.4V. But there is a

using either worst-case or statistical tolerancing. Worst-

casetolerancingisthemostconservativeandiscalculated

+

small (~1ꢂA) current flowing into a SENSE pin when its

–

corresponding SENSE pin ramps down from 1.4V and

fromtheminimumvalueofthesinglechannelV

SENSE(MAX)

–

staysabove1.1V.SuchcurrentsalsoexistonSENSE pins.

in the EC table, multiplied by the number of phases (e.g.,

2x in a 2-phase application). Statistical tolerancing takes

into consideration the distribution of both current limit

channelstopredicttheeffectivestatisticallimitsofthesum

–

But in addition, each SENSE pin has an internal ꢁ±±k

resistor to SGND. The resulted current (V /ꢁ±±k) will

OUT

–

dominate the total current flowing into the SENSE pins.

+

–

of multiple channels’ V

. Based on distributions

SENSE and SENSE pin currents have to be taken into

SENSE(MAX)

over temperature of the 2-channel-sum [V

+

account when designing either R

current sensing.

or DCR inductor

SENSE(MAX)1

SENSE

V

] from the characterization LTC3839, the

SENSE(MAX)2

3839fa

18

LTC3839

APPLICATIONS INFORMATION

R

RESISTOR

recommended lower limits of V

(by each indi-

SENSE

SENSE(MAX)

AND

PARASITIC INDUCTANCE

vidualchannel,calculatedashalfofthe2-channel-sum)for

statistical tolerancing design of a 2-phase application are:

R

ESL

V

OUT

• 24mV at V

• 42mV at V

• 8ꢁmV at V

= ±.ꢀV or SGND (3±mV typical);

RNG

LTC3839

C ꢀtꢀꢁ3 ≤ ESL/R

F

S

POLE-ZERO

R

= 1V or INTV (ꢁ±mV typical);

F

CC

CANCELLATION

+

–

SENSE

= 2V (1±±mV typical).

C

F

3839 F±3a

SENSE

Either worst-case or statistical limits can be chosen to

establish absolute minimums for current limit of the

LTC3839. Linear guarantees the worst-case minimum

and maximum for each channel, but does not guarantee

any statistical distributions of or relationship between the

two channels.

FILTER COMPONENTS

PLACED NEAR SENSE PINS

Figure 3a. R_SENSECurrent Sensing

TO SENSE FILTER,

NEXT TO THE CONTROLLER

R

Inductor Current Sensing

SENSE

The LTC3839 can be configured to sense the inductor

currents through either low value series current sensing

C

OUT

3839 F±3b

R

SENSE

resistors (R

) or inductor DC resistance (DCR). The

SENSE

choicebetweenthetwocurrentsensingschemesislargely

a design trade-off between cost, power consumption and

accuracy. DCR sensing is becoming popular because it

saves expensive current sensing resistors and is more

power efficient, especially in high current applications.

However, current sensing resistors provide the most ac-

curate current limits for the controller.

Figure 3b. Sense ꢁines Placement with Sense Resistor

Conversely, given R

and I

, V

and

SENSE

OUT(MAX) SENSE(MAX)

thusV

voltagecanbedeterminedfromtheaboveequa-

RNG

tion. To ensure the maximum output current, sufficient

margin should be built in the calculations to account for

variationsofLTC3839underdifferentoperatingconditions

and tolerances of external components.

AtypicalR

inductorcurrentsensingschemeisshown

SENSE

in Figure 3a. The filter components (R , C ) need to be

F

placed close to the IC. The positive and negative sense

traces need to be routed as a differential pair close to-

getherandKelvin(4-wire)connectedunderneaththesense

resistor, asshowninFigure3b. Sensingcurrentelsewhere

caneffectivelyaddparasiticinductancetothecurrentsense

element, degrading the information at the sense terminals

and making the programmed current limit unpredictable.

Because of possible PCB noise in the current sensing

loop, the current sensing voltage ripple ∆V

= ∆I •

SENSE

L

R

SENSE

also needs to be checked in the design to get a

good signal-to-noise ratio. In general, for a reasonably

is recommended as

good PCB layout, 1±mV of ∆V

SENSE

a conservative number to start with, either for R

Inductor DCR sensing applications.

or

SENSE

R

is chosen based on the required maximum output

SENSE

For today’s highest current density solutions the value

of the sense resistor can be less than 1mΩ and the

peak sense voltage can be as low as 2±mV. In addition,

inductor ripple currents greater than ꢁ±7 with operation

up to 2MHz are becoming more common. Under these

conditions, the voltage drop across the sense resistor’s

parasitic inductance becomes more relevant. A small RC

current.Giventhemaximumcurrent,I

,maximum

OUT(MAX)

sense voltage, V

, set by V , and maximum

L(MAX)

SENSE(MAX)

RNG

inductor ripple current ∆I

, the value of R

can

SENSE

be chosen as:

V_SENSE(MAX)

R_SENSE

=

ΔI_L(MAX)

I_OUT(MAX)

–

2

3839fa

19

LTC3839

APPLICATIONS INFORMATION

filter placed near the IC has been traditionally used to

reducetheeffectsofcapacitiveandinductivenoisecoupled

in the sense traces on the PCB. A typical filter consists of

two series 1±Ω resistors connected to a parallel 1±±±pF

capacitor, resulting in a time constant of 2±ns.

V

SENSE

2±mV/DIV

V

ESL(STEP)

This same RC filter, with minor modifications, can be

used to extract the resistive component of the current

sense signal in the presence of parasitic inductance.

For example, Figure 4a illustrates the voltage waveform

across a 2mΩ sense resistor with a 2±1± footprint for a

1.2V/1ꢁAconverteroperatingat1±±7load.Thewaveform

is the superposition of a purely resistive component and a

purely inductive component. It was measured using two

scope probes and waveform math to obtain a differential

measurement. Based on additional measurements of the

inductor ripple current and the on-time and off-time of

the top switch, the value of the parasitic inductance was

determined to be ±.ꢁnH using the equation:

3839 F±4a

ꢁ±±ns/DIV

Figure 4a. Voltage Waveform Measured

Directly Across the Sense Resistor

V

SENSE

2±mV/DIV

V_ESL(STEP)

t_ON• t_OFF

t_ON+ t_OFF

3839 F±4b

ESL =

•

ꢁ±±ns/DIV

ΔI_L

Figure 4b. Voltage Waveform Measured After the

Sense Resistor Filter. C_F= 1000pF, R_F= 100Ω

where V

is the voltage step caused by the ESL

ESL(STEP)

and shown in Figure 4a, and t and t are top MOSFET

ON

OFF

–

offset V

= V

• R /ꢁ±±k = 1mV. Such

SENSE(OFFSET)

SENSE

F

on-time and off-time respectively. If the RC time constant

ischosentobeclosetotheparasiticinductancedividedby

the sense resistor (L/R), the resulting waveform looks re-

sistiveagain,asshowninFigure4b.Forapplicationsusing

small offset may seem harmless for current limit, but

could be significant for current reversal detection (I ),

REV

causingexcessnegativeinductorcurrentatdiscontinuous

mode. Also, at V

= 3±mV, a mere 1mV offset

SENSE(MAX)

low V

, check the sense resistor manufacturer’s

SENSE(MAX)

will cause a significant shift of zero-current ITH voltage

by (2.4V – ±.8V) • 1mV/3±mV = ꢁ3mV. Too much shift

maynotallowtheoutputvoltagetoreturntoitsregulated

value after the output is shorted due to ITH foldback.

data sheet for information about parasitic inductance. In

the absence of data, measure the voltage drop directly

across the sense resistor to extract the magnitude of the

ESLstepandusetheequationabovetodeterminetheESL.

However, do not over filter. Keep the RC time constant less

than or equal to the inductor time constant to maintain a

Therefore, when a larger filter resistor R value is used,

F

it is recommended to use an external ꢁ±±k resistor from

+

each SENSE pin to SGND, to balance the internal ꢁ±±k

high enough ripple voltage on V

.

RSENSE

–

resistor at its corresponding SENSE pin.

–

Note that the SENSE1 and SENSE2 pins are also used

for sensing the output voltage for the adjustment of top

The previous discussion generally applies to high density/

high current applications where I

> 1±A and low

OUT(MAX)

gate on time, t . For this purpose, there is an additional

ON

inductorvaluesareused.ForapplicationswhereI

–

OUT(MAX)

internal ꢁ±±k resistor from each SENSE pin to SGND,

< 1±A, set R to 1±Ω and C to 1±±±pF. This will provide

F

therefore there is an impedance mismatch with their cor-

a good starting point.

+

responding SENSE pins. The voltage drop across the

R causes an offset in sense voltage. For example, with

The filter components need to be placed close to the IC.

The positive and negative sense traces need to be routed

3839fa

F

–

R = 1±±Ω, at V

= V

= ꢁV, the sense-voltage

OUT

SENSE

20

LTC3839

APPLICATIONS INFORMATION

as a differential pair and Kelvin (4-wire) connected to the

sense resistor.

Resistor R1 should be placed close to the switching node,

to prevent noise from coupling into sensitive small-signal

nodes. Capacitor C1 should be placed close to the IC pins.

DCR Inductor Current Sensing

The first step in designing DCR current sensing is to

determine the DCR of the inductor. Where provided, use

themanufacturer’smaximumvalue, usuallygivenat2ꢁ°C.

Increase this value to account for the temperature coef-

ficient of resistance, which is approximately ±.47/°C. A

For applications requiring higher efficiency at high load

currents, the LTC3839 is capable of sensing the voltage

drop across the inductor DCR, as shown in Figure ꢁ. The

DCR of the inductor represents the small amount of DC

windingresistance,whichcanbelessthan1mΩfortoday’s

low value, high current inductors.

conservative value for inductor temperature T is 1±±°C.

L

TheDCRoftheinductorcanalsobemeasuredusingagood

RLC meter, but the DCR tolerance is not always the same

and varies with temperature; consult the manufacturers’

data sheets for detailed information.

In a high current application requiring such an inductor,

conductionlossthroughasenseresistorwouldcostseveral

points of efficiency compared to DCR sensing.

From the DCR value, V

is easily calculated as:

SENSE(MAX)

The inductor DCR is sensed by connecting an RC filter

across the inductor. This filter typically consists of one or

tworesistors(R1andR2)andonecapacitor(C1)asshown

in Figure ꢁ. If the external (R1||R2) • C1 time constant is

chosen to be exactly equal to the L/DCR time constant, the

voltage drop across the external capacitor is equal to the

voltage drop across the inductor DCR multiplied by R2/

(R1 + R2). Therefore, R2 may be used to scale the voltage

across the sense terminals when the DCR is greater than

the target sense resistance. With the ability to program

V_SENSE(MAX)=DCR_MAX(25°C)

⎡

⎤

⎦

• 1+0.4% T

–25°C

(

)

L(MAX)

⎣

⎛

ΔI_L

⎞

• I

–

⎜ ^OUT(MAX)

⎟

⎠

⎝

2

IfV

iswithinthemaximumsensevoltage(3±mV

SENSE(MAX)

to 1±±mV) of the LTC3839 as programmed by the V

RNG

pin, then the RC filter only needs R1. If V

is

SENSE(MAX)

current limit through the V

pin, R2 may be optional. C1

RNG

higher, then R2 may be used to scale down the maximum

sense voltage so that it falls within range.

is usually selected in the range of ±.±1μF to ±.46μF. This

forcesR1||R2toaround2kto4k,reducingerrorthatmight

have been caused by the SENSE pins’ input bias currents.

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

INDUCTOR

V

_IN(MAX)– V_OUT• V

(

)

OUT

L

DCR

P

R1 =

V

_LOSS( )

OUT

R1

C

OUT

L/DCR = (R1||R2) C1

R1

LTC3839

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

+

–

SENSE

R2

(OPT)

C1

3839 F±ꢁ

SENSE

R

sensing. Light load power loss can be modestly

SENSE

higher with a DCR network than with a sense resistor due

totheextraswitchinglossesincurredthroughR1.However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efficiency at heavy loads.

Peak efficiency is about the same with either method.

C1 NEAR SENSE PINS

Figure 5. DCR Current Sensing

3839fa

21

LTC3839

APPLICATIONS INFORMATION

To maintain a good signal-to-noise ratio for the current

whereδisthetemperaturedependencyofR

,R

DS(ON) TG(UP)

is the TG pull-

sense signal, start with a ∆V

of 1±mV. For a DCR

sensing application, the actual ripple voltage will be de-

termined by:

is the TG pull-up resistance, and R

SENSE

TG(DOWN)

is the Miller effect V voltage

down resistance. V

MILLER

GS

and is taken graphically from the MOSFET’s data sheet.

V – V_OUTV_OUT

2

IN

BothMOSFETshaveI RlosseswhilethetopsideN-channel

ΔV_SENSE

=

•

R1•C1 V • f

equation includes an additional term for transition losses,

IN

which are highest at high input voltages. For V < 2±V,

IN

the high current efficiency generally improves with larger

Power MOSFET Selection

MOSFETs, while for V > 2±V, the transition losses rapidly

IN

Two external N-channel power MOSFETs must be selected

for each channel of the LTC3839 controller: one for the

top (main) switch and one for the bottom (synchronous)

increasetothepointthattheuseofahigherR

device

DS(ON)

withlowerC

actuallyprovideshigherefficiency.The

MILLER

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

short-circuit when the synchronous switch is on close to

1±±7 of the period.

switch. The gate drive levels are set by the DRV voltage.

CC

This voltage is typically ꢁ.3V. Pay close attention to the

BV

specification for the MOSFETs as well; most of the

DSS

logic-level MOSFETs are limited to 3±V or less.

The term (1 + δ) is generally given for a MOSFET in the

Selection criteria for the power MOSFETs include the on-

form of a normalized R

vs temperature curve in the

DS(ON)

resistance, R

, Miller capacitance, C

, input

DS(ON)

MILLER

power MOSFET data sheet. For low voltage MOSFETs,

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

±.ꢁ7 per degree (°C) can be used to estimate δ as an

C

MILLER

approximation of percentage change of R

:

DS(ON)

usuallyprovidedontheMOSFETmanufacturers’datasheet.

is equal to the increase in gate charge along the

C

MILLER

δ = ±.±±ꢁ/°C • (T – T )

J

A

horizontal axis while the curve is approximately flat (or

whereT isestimatedjunctiontemperatureoftheMOSFET

J

the parameter Q if specified on a manufacturer’s data

sheet), divided by the specified V test voltage:

GD

and T is ambient temperature.

A

DS

Q_GD

V_DS(TEST)

C Selection

IN

C_MILLER

≅

In continuous mode, the source current of the top N-

channel MOSFET is a square wave of duty cycle V

/

OUT

When the IC is operating in continuous mode, the duty

cycles for the top and bottom MOSFETs are given by:

V . To prevent large voltage transients, a low ESR input

IN

capacitor sized for the maximum RMS current must be

used. The worst-case RMS current occurs by assuming

a single-phase application. The maximum RMS capacitor

current is given by:

V_OUT

D_TOP

=

V

IN

V_OUT

D_BOT=1–

V_OUT

V

V_OUT

V

IN

I_RMS≅I_OUT(MAX)

•

–1

V

IN

The MOSFET power dissipations at maximum output

current are given by:

P_TOP=D_TOP•I_OUT(MAX)²•R_DS(ON)(MAX)1+δ + V

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT(MAX)/2. This simple worst-case condition

is commonly used for design because even significant

deviations do not offer much relief. Note that capacitor

manufacturers’ ripple current ratings are often based on

only 2±±± hours of life. This makes it advisable to further

2

(

)

IN

I

R_TG(UP)

R_TG(DOWN)

⎛

⎝

⎞

⎡

⎤

OUT(MAX)

•

•C_{MILLER ⎢}

+

•f

⎥

⎦

⎜

⎟

2

V_DRVCC– V_MILLER

V_MILLER

⎠

⎣

2

P

= D

• I

• R

• (1 + δ )

derate the capacitor or to choose a capacitor rated at a

BOT

BOT OUT(MAX)

DS(ON)(MAX)

3839fa

22

LTC3839

APPLICATIONS INFORMATION

highertemperaturethanrequired.Severalcapacitorsmay

also be paralleled to meet size or height requirements in

the design. Due to the high operating frequency of the

LTC3839, additional ceramic capacitors should also be

used in parallel for C_INclose to the IC and power switches

to bypass the high frequency switching noises. Typically

multipleXꢁRorX6Rceramiccapacitorsareputinparallel

with either conductive-polymer or aluminum-electrolytic

types of bulk capacitors. Because of its low ESR, the

ceramic capacitors will take most of the RMS ripple cur-

rent.Vendorsdonotconsistentlyspecifytheripplecurrent

rating for ceramics, but ceramics could also fail due to

excessiveripplecurrent.Alwaysconsultthemanufacturer

if there is any question.

OS-CON) can be used for its higher ripple current rating

and lower ESR. For a wide V_INrange that also require

highervoltagerating,aluminum-electrolyticcapacitorsare

more attractive since it can provide a larger capacitance

for more damping. An aluminum-electrolytic capacitor

with a ripple current rating that is high enough to handle

all of the ripple current by itself will be very large. But

when in parallel with ceramics, an aluminum-electrolytic

capacitor will take a much smaller portion of the RMS

ripple current due to its high ESR. However, it is crucial

that the ripple current through the aluminum-electrolytic

capacitor should not exceed its rating since this will

produce significant heat, which will cause the electrolyte

inside the capacitor to dry over time and its capacitance

to go down and ESR to go up.

Figureꢀrepresentsasimplifiedcircuitmodelforcalculat-

ing the ripple currents in each of these capacitors. The

input inductance (L_IN) between the input source and the

inputoftheconverterwillaffecttheripplecurrentthrough

the capacitors. A lower input inductance will result in less

ripple current through the input capacitors since more

ripple current will now be flowing out of the input source.

The benefit of PolyPhase operation is reduced RMS cur-

rents and therefore less power loss on the input capaci-

tors. Also, the input protection fuse resistance, battery

resistance, and PC board trace resistance losses are also

reduced due to the reduced peak currents in a PolyPhase

system. The details of a close form equation can be found

in Application Note 66 “High Efficiency, High Density,

PolyPhase Converters for High Current Applications”.

Figure 6 shows the input capacitor RMS ripple currents

normalized against the DC output currents with respect

to the duty cycle. This graph can be used to estimate the

maximum RMS capacitor current for a multiple-phase

application, assuming the channels are identical and their

phases are fully interleaved.

L

IN

1μH

ESR

ESL

ESR

ESL

(BULK)

(CERAMIC)

+

V

I

PULSE(PHASE2)

IN

PULSE(PHASE1)

(BULK)

(CERAMIC)

–

+

C

IN(CERAMIC)

IN(BULK)

3839 F±ꢀ

±.ꢀ

Figure 6. Circuit Model for Input Capacitor

Ripple Current Simulation

±.ꢁ

1-PHASE

For simulations with this model, look at the ripple current

during steady-state for the case where one phase is fully

loaded and the other was not loaded. This will in general

be the worst case for ripple current since the ripple cur-

rentfromonephasewillnotbecancelledbyripplecurrent

from the other phase.

±.4

2-PHASE

3-PHASE

4-PHASE

±.3

ꢀ-PHASE

±.2

±.1

±

Note that the bulk capacitor also has to be chosen for

RMS rating with ample margin beyond its RMS current

persimulationwiththecircuitmodelprovided.Foralower

V_INrange, a conductive-polymer type (such as Sanyo

±.1 ±.2 ±.3 ±.4 ±.ꢁ ±.ꢀ ±.6 ±.8 ±.9

DUTY FACTOR (V /V

)

O

IN

3839 F±6

Figure ꢀ. Normalized RMS Input Ripple Current

3839fa

23

LTC3839

APPLICATIONS INFORMATION

Figure 6 shows that the use of more phases will reduce

the ripple current through the input capacitors due to

ripple current cancellation. However, since LTC3839 is

onlytrulyphase-interleavedatsteadystate,transientRMS

currentscouldbehigherthanthecurvesforthedesignated

number of phase. Therefore, it is advisable to choose

capacitors by taking account the specific load situations

of the applications. It is always the safest to choose input

capacitors’ RMS current rating closer to the worst case of

a single-phase application discussed above, calculated by

assuming the loss that would have resulted if controller

channels switched on at the same time.

where f is operating frequency, and ∆I is ripple content in

L

thesumofinductorcurrentsofallphases.Theoutputripple

is highest at maximum input voltage since ∆I increases

L

with input voltage. Typically, once the ESR requirement

for C

has been met, the RMS current rating generally

OUT

far exceeds that required from ripple current.

For LTC3839’s multiphase operation, it is advisable to

consider ripple requirements at specific load conditions

when determining the ∆I for the output capacitor selec-

L

tion. At steady state, the LTC3839’s individual phases are

interleaved,andtheirripplescanceleachotherattheoutput,

so ripple on C

is reduced. During transient, when the

OUT

However, itisgenerallynotneededtosizetheinputcapaci-

tor for such worst-case conditions where on-times of the

phases coincide all the time. During a load step event, the

overlap of on-time will only occur for a small percentage

of time, especially when duty cycles are low. A transient

event where the switch nodes align for several cycles at

a time should not damage the capacitor. In most applica-

tions, sizing the input capacitors for 1±±7 steady-state

load should be adequate. For example, a microprocessor

load may cause frequent overlap of the on-times, which

makes the ripple current higher, but the load current may

phases are not fully interleaved, the ripple cancellation

may not be as effective. For example, a large step of load

current increase may cause the phases to align for several

cycles, quickly ramping up the total inductor current and

pulling the V

from the droop. While the worst-case ∆I

OUT

L

is the sum of the ∆I ’s of individual phases aligned during

L

a fast transient, such larger ripple lasts for only a short

time before the phase interleaving is restored.

The choice of using smaller output capacitance increases

the ripple voltage due to the discharging term but can be

compensated for by using capacitors of very low ESR to

maintain the ripple voltage.

rarely be at 1±±7 of I

. Using the worst-case load

OUT(MAX)

current should already have margin built in for transient

conditions.

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramiccapacitorsareallavailableinsurfacemountpack-

ages. Special polymer capacitors offer very low ESR but

havelowercapacitancedensitythanothertypes.Tantalum

capacitors have the highest capacitance density but it is

important to only use types that have been surge tested

foruseinswitchingpowersupplies.Aluminumelectrolytic

capacitors have significantly higher ESR, but can be used

in cost-sensitive applications provided that consideration

is given to ripple current ratings and long-term reliability.

The V sources of the top MOSFETs should be placed

IN

close to each other and share common C (s). Separating

IN

the sources and C may produce undesirable voltage and

IN

current resonances at V .

IN

A small (±.1μF to 1μF) bypass capacitor between the IC’s

V pin and ground, placed close to the IC, is suggested.

IN

A 2.2Ω to 1±Ω resistor placed between C and the V

IN

pin is also recommended as it provides further isolation

from switching noise of the two channels.

C

Selection

OUT

CeramiccapacitorshaveexcellentlowESRcharacteristics

but can have a high voltage coefficient and audible piezo-

electriceffects.ThehighQofceramiccapacitorswithtrace

inductancecanalsoleadtosignificantringing. Whenused

asinputcapacitors,caremustbetakentoensurethatring-

ing from inrush currents and switching does not pose an

The selection of output capacitance C

is primarily

OUT

determined by the effective series resistance, ESR, to

minimize voltage ripple. The output voltage ripple ∆V

in continuous mode is determined by:

,

OUT

⎛

⎞

1

ΔV_OUT≤ ΔI_LR_ESR

+

⎜

⎝

⎟

8• f •C_OUT

overvoltage hazard to the power switches and controller.

⎠

3839fa

24

LTC3839

APPLICATIONS INFORMATION

Forhighswitchingfrequencies,reducingoutputrippleand

betterEMIfilteringmayrequiresmallvaluecapacitorsthat

have low ESL (and correspondingly higher self-resonant

frequencies) to be placed in parallel with larger value

capacitors that have higher ESL. This will ensure good

noise and EMI filtering in the entire frequency spectrum

of interest. Even though ceramic capacitors generally

have good high frequency performance, small ceramic

capacitors may still have to be parallel connected with

large ones to optimize performance.

ceramic capacitor. Good bypassing is needed to supply

the high transient currents required by the MOSFET gate

drivers and to minimize interaction between the channels.

HighinputvoltageapplicationsinwhichlargeMOSFETsare

being driven at high frequencies may cause the maximum

junctiontemperatureratingfortheLTC3839tobeexceeded,

especially if the LDO is active and provides DRV . Power

CC

dissipation for the IC in this case is highest and is ap-

proximately equal to V • I

. The gate charge current

IN DRVCC

is dependent on operating frequency as discussed in the

EfficiencyConsiderationssection.Thejunctiontemperature

can be estimated by using the equation given in Note 2

of the Electrical Characteristics. For example, when using

High performance through-hole capacitors may also be

used, but an additional ceramic capacitor in parallel is

recommendedtoreducetheeffectoftheirleadinductance.

Rememberalsotoplacehighfrequencydecouplingcapaci-

tors as close as possible to the power pins of the load.

the LDO, LTC3839’s DRV current is limited to less than

CC

32mA from a 38V supply at T = 6±°C:

A

T = 6±°C + (32mA)(38V)(44°C/W) = 12ꢁ°C

J

Top MOSFET Driver Supply (C , D )

B

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

An external bootstrap capacitor, C , connected to the

B

BOOST pin supplies the gate drive voltage for the topside

operatingincontinuousconductionmodeatmaximumV .

IN

MOSFET. This capacitor is charged through diode D from

B

DRV whentheswitchnodeislow.WhenthetopMOSFET

When the voltage applied to the EXTV pin rises above

CC

turns on, the switch node rises to V and the BOOST pin

the switchover voltage (typically 4.ꢀV), the V LDO is

IN

rises to approximately V + INTV . The boost capacitor

turnedoffandtheEXTV isconnectedtoDRV pinwith

CC CC2

IN

CC

needs to store approximately 1±± times the gate charge

required by the top MOSFET. In most applications a ±.1μF

to ±.46μF, XꢁR or X6R dielectric capacitor is adequate. It

is recommended that the BOOST capacitor be no larger

an internal switch. This switch remains on as long as the

voltage applied to EXTV remains above the hysteresis

CC

(around 2±±mV) below the switchover voltage. Using

EXTV allows the MOSFET driver and control power to

CC

than 1±7 of the DRV capacitor, C

, to ensure that

be derived from the LTC3839’s switching regulator output

CC

DRVCC

the C

can supply the upper MOSFET gate charge

V

during normal operation and from the LDO when the

DRVCC

OUT

and BOOST capacitor under all operating conditions. Vari-

able frequency in response to load steps offers superior

transient performance but requires higher instantaneous

gate drive. Gate charge demands are greatest in high

frequency low duty factor applications under high load

steps and at start-up.

output is out of regulation (e.g., start up, short circuit). If

morecurrentisrequiredthroughtheEXTV thanisspeci-

CC

fied, an external Schottky diode can be added between the

EXTV and DRV pins. Do not apply more than ꢀV to the

CC

EXTV pin and make sure that EXTV is less than V .

CC

IN

Significant efficiency and thermal gains can be realized

by powering DRV from the switching converter output,

CC

DRV Regulator and EXTV Power

CC

since the V current resulting from the driver and control

IN

The LTC3839 features a PMOS low dropout (LDO) linear

regulatorthatsuppliespowertoDRV fromtheV supply.

currentswillbescaledbyafactorof(DutyCycle)/(Switcher

Efficiency).

CC

IN

The LDO regulates its output at the DRV

pin to ꢁ.3V.

CC1

Tying the EXTV pin to a ꢁV supply reduces the junction

CC

The LDO can supply a maximum current of 1±±mA and

must be bypassed to ground with a minimum of 4.6μF

temperature in the previous example from 12ꢁ°C to:

T = 6±°C + (32mA)(ꢁV)(44°C/W) = 66°C

J

3839fa

25

LTC3839

APPLICATIONS INFORMATION

However, for 3.3V and other low voltage outputs, ad-

Input Undervoltage ꢁockout (UVꢁO)

ditional circuitry is required to derive DRV power from

CC

The LTC3839 has two functions that help protect the con-

trollerincaseofinputundervoltageconditions.Aninternal

the converter output.

The following list summarizes the four possible connec-

UVLO comparator constantly monitors the INTV and

CC

tions for EXTV :

DRV voltagestoensurethatadequatevoltagesarepres-

CC

ent. The comparator enables internal UVLO signal, which

1. EXTV left open (or grounded). This will cause INTV

CC

locks out the switching action of both channels, until the

to be powered from the internal ꢁ.3V LDO resulting

in an efficiency penalty of up to 1±7 at high input

voltages.

INTV and DR

pins are all above their respective

VCC1,2

CC

UVLO thresholds. The rising threshold (to release UVLO)

of the INTV is typically 4.2V, with ±.ꢁV falling hysteresis

CC

2. EXTV connecteddirectlytoswitchingconverteroutput

(tore-enableUVLO).TheUVLOthresholdsforDR

are

CC

VCC1,2

V

ishigherthantheswitchovervoltage’shigherlimit

lower than that of INTV but higher than typical threshold

OUT

CC

(4.8V). This provides the highest efficiency.

voltagesofpowerMOSFETs, topreventthemfromturning

on without sufficient gate drive voltages.

3. EXTV connected to an external supply. If a 4.8V or

CC

greater external supply is available, it may be used to

GenerallyforV >ꢀV,aUVLOcanbesetthroughmonitoring

IN

power EXTV providing that the external supply is

the V supply by using an external voltage divider at the

CC

IN

sufficient for MOSFET gate drive requirements.

RUN pin from V to SGND. To design the voltage divider,

IN

note that the RUN pin has two levels of threshold voltages.

4. EXTV connectedtoanoutput-derivedboostnetwork.

CC

The precision gate-drive-enable threshold voltage of 1.2V

For 3.3V and other low voltage converters, efficiency

can be used to set a V to turn on a channel’s switching.

IN

gains can still be realized by connecting EXTV to an

CC

If a resistor divider is used on the RUN pin, when V is

IN

output-derivedvoltagethathasbeenboostedtogreater

low enough and the RUN pin is pulled below the ~±.8V

than 4.8V.

threshold, the part will shut down all bias of INTV and

CC

Forapplicationswherethemaininputpowerneverexceeds

DRV and be put in micropower shutdown mode.

CC

ꢁ.3V, tie the DRV

and DRV pins to the V input

CC2 IN

CC1

TheRUNpin’sbiascurrentdependsontheRUNpinvoltage.

The bias current changes should be taken into account

when designing the external voltage divider UVLO circuit.

An internal proportional-to-absolute-temperature (PTAT)

pull-up current source (~2.ꢁμA at 2ꢁ°C) is constantly con-

nected to this pin. When the RUN pin rises above 1.2V, the

TG and BG drives are enabled on and an additional 1±μA

temperature-independent pull-up current is connected

internally to the RUN pin. Pulling the RUN pin below 1.2V

by more than an 8±mV hysteresis turns off TG and BG,

and the additional 1±μA pull-up current is disconnected.

through a small resistor, (such as 1Ω to 2Ω) as shown

in Figure 8 to minimize the voltage drop caused by the

gate charge current. This will override the LDO and will

prevent DRV from dropping too low due to the dropout

CC

voltage.MakesuretheDRV voltageexceedstheR

CC

DS(ON)

test voltage for the external MOSFET which is typically at

4.ꢁV for logic-level devices.

LTC3839

DRV

CC2

CC1

R

DRVCC

DRV

V

IN

C

DRVCC

IN

3839 F±8

Figure 8. Setup for V_IN≤ 5.3V

3839fa

26

LTC3839

APPLICATIONS INFORMATION

As voltage on the RUN pin increases, typically beyond

3V, its bias current will start to reverse direction and flow

into the RUN pin. Keep in mind that the RUN pin can sink

up to ꢁ±μA; Even if a RUN pin may slightly exceed ꢀV

when sinking ꢁ±μA, the RUN pin should never be forced

to higher than ꢀV by a low impedance voltage source to

prevent faulty conditions.

When the LTC3839 is configured to soft-start by itself, a

capacitorshouldbeconnectedtoitsTRACK/SSpin.TRACK/

SS is pulled low until the RUN pin voltage exceeds 1.2V

and UVLO is released, at which point an internal current

of 1μA charges the soft-start capacitor, C , connected

SS

to the TRACK/SS pin. Current-limit foldback is disabled

during this phase to ensure smooth soft-start or track-

ing. The soft-start or tracking range is defined to be the

voltage range from ±V to ±.ꢀV on the TRACK/SS pin. The

total soft-start time can be calculated as:

Soft-Start and Tracking

The LTC3839 has the ability to either soft-start by itself

with a capacitor or track an external supply. Note that the

soft-start and tracking features are achieved not by limit-

ing the maximum output current of the controller, but by

controlling the output ramp voltage according to the ramp

rate on the TRACK/SS pin.

C_SS(µF)

t_SS(SEC)= 0.6(V)•

1(µA)

EXTERNAL SUPPLY

V

OUT

3839 F±9a

TIME

Coincident Tracking

Ratiometric Tracking

Figure 9a. Two Different Modes of Output Tracking

EXTERNAL SUPPLY

TO

V

OUT

R

FB2(2)

FB1(2)

FB2(1)

TO

OUTSENSE

TO

V

+

TRACK/SS

V

FB1(1)

–

OUTSENSE

3839 F±9b

Figure 9b. Setup for External Supply Tracking

3839fa

27

LTC3839

APPLICATIONS INFORMATION

When the LTC3839 is configured to track an external sup-

ply, a voltage divider can be used from the external supply

to the TRACK/SS pin to scale the ramp rate appropriately.

Two common implementations are coincidental tracking

and ratiometric tracking. For coincident tracking, make

the divider ratio from the external supply the same as

the divider ratio for the differential feedback voltage. Ra-

tiometric tracking could be achieved by using a different

ratio than the differential feedback.

significantly different from the local output point due to

linelosses,andlocaloutputversuslocalgroundistypically

the V

required for the calculation of t .

OUT

ON

However, there could be circumstances where this V

OUT

programmed on-time differs significantly different from

the on-time required in order to maintain frequency

and phase lock. For example, lower efficiencies in the

switching regulator can cause the required on-time to be

substantially higher than the internally set on-time (see

Note that the 1μA soft-start capacitor charging current is

still flowing, producing a small offset error. To minimize

this error, select the tracking resistive divider values to be

small enough to make this offset error negligible.

Efficiency Considerations). If a regulated V

is relatively

OUT

low, proportionally there could be significant error caused

by the difference between the local ground and remote

ground, due to other currents flowing through the shared

ground plane.

Withratiometrictracking,whenexternalsupplyexperience

dynamic excursion, the regulated output will be affected

as well. For better output regulation, use the coincident

tracking mode instead of ratiometric.

If necessary, the R resistor value, voltage on the V pin,

T

IN

or even the common mode voltage of the SENSE pins may

be programmed externally to correct for such systematic

errors. The goal is to set the on-time programmed by V ,

IN

Phase and Frequency Synchronization

V

and R close to the steady-state on-time so that the

OUT

T

systemwillhavesufficientrangetocorrectforcomponent

andoperatingconditionvariations,ortosynchronizetothe

external clock. Note that there is an internal ꢁ±±k resistor

For applications that require better control of EMI and

switchingnoiseorhavespecialsynchronizationneeds,the

LTC3839 can synchronize the turn-on of the top MOSFET

to an external clock signal applied to the MODE/PLLIN pin.

The applied clock signal needs to be within ±3±7 of the

RT programmed frequency to ensure proper frequency

and phase lock. The clock signal levels should generally

–

+

on each SENSE pin to SGND, but not on the SENSE pin.

During dynamic transient conditions either in the line

voltage or load current (e.g., load step or release), the top

switch will turn on more or less frequently in response

to achieve faster transient response. This is the benefit

of the LTC3839’s controlled on-time, valley current mode

architecture. However, this process may understandably

lose phase and even frequency lock momentarily. For

relatively slow changes, phase and frequency lock can

still be maintained. For large load current steps with fast

slew rates, phase lock will be lost until the system returns

back to a steady-state condition (see Figure 1±). It may

take up to several hundred microseconds to fully resume

the phase lock, but the frequency lock generally recovers

quickly, long before phase lock does.

comply to V

> 2V and V

< ±.ꢁV. The MODE/

PLLIN(H)

PLLIN(L)

PLLINpinhasaninternalꢀ±±kpull-downresistortoensure

discontinuouscurrentmodeoperationifthepinisleftopen.

The LTC3839 uses the voltages on V and V

as well

IN

OUT

as R to adjust the top gate on-time in order to maintain

T

phase and frequency lock for wide ranges of V , V

IN OUT

and R -programmed switching frequency f:

T

V_OUT

t_ON

≈

V • f

IN

As the on-time is a function of the switching regulator’s

For light load conditions, the phase and frequency syn-

chronization depends on the MODE/PLLIN pin setting. If

theexternalclockisapplied, synchronizationwillbeactive

and switching in continuous mode. If MODE/PLLIN is tied

–

output voltage, this output is measured by the SENSE pin

–

to set the required on-time. The SENSE pin is tied to the

regulator’s local output point to the IC for most applica-

tions, as the remotely regulated output point could be

3839fa

28

LTC3839

APPLICATIONS INFORMATION

to INTV , it will operate in forced continuous mode at

Minimum On-Time, Minimum Off-Time

CC

the R -programmed frequency. If the MODE/PLLIN pin is

and Dropout Operation

T

tied to SGND, the LTC3839 will operate in discontinuous

The minimum on-time is the smallest duration that

LTC3839’s TG (top gate) pin can be in high or “on” state.

It has dependency on the operating conditions of the

switching regulator, and is a function of voltages on the

mode at light load and switch into continuous conduction

attheR programmedfrequencyasloadincreases.TheTG

T

on-time during discontinuous conduction is intentionally

slightlyextended(approximately1.2timesthecontinuous

V and V

pins, as well as the value of external resistor

IN

OUT

conduction on-time as calculated from V , V

and f) to

IN OUT

R . A minimum on-time of 3±ns can be achieved when the

T

create hysteresis at the load-current boundary of continu-

ous/discontinuous conduction.

V

pin is tied to its minimum value of ±.ꢀV while the V

OUT

IN

is tied to its maximum value of 38V. For larger values of

V and/orsmallervaluesofV ,theminimumachievable

OUT

Ifanapplicationrequiresverylow(approachingminimum)

on-time, the system may not be able to maintain its full

frequency synchronization range. Getting closer to mini-

mumon-time, itmayevenlosephase/frequencylockatno

load or light load conditions, under which the SW on-time

is effectively longer than TG on-time due to TG/BG dead

times. This is discussed further under Minimum On-Time,

Minimum Off-Time and Dropout Operation.

IN

on-timewillbelonger.Thevalleymodecontrolarchitecture

allows low on-time, making the LTC3839 suitable for high

step-down ratio applications.

The effective on-time, as determined by the SW node

pulse width, can be different from this TG on-time, as it

also depends on external components, as well as loading

I

LOAD

CLOCK

INPUT

PHASE AND

FREQUENCY

LOCKED

PHASE AND

FREQUENCY

LOCK LOST

DUE TO FAST

LOAD STEP

FREQUENCY

RESTORED

QUICKLY

PHASE LOCK

RESUMED

PHASE AND

FREQUENCY

LOCK LOST

DUE TO FAST

LOAD STEP

FREQUENCY

RESTORED

QUICKLY

SW

V

OUT

3839 F1±

Figure 10. Phase and Frequency ꢁocking Behavior During Transient Conditions

3839fa

29

LTC3839

APPLICATIONS INFORMATION

TG-SW

conditionsoftheswitchingregulator.Oneofthefactorsthat

contributestothisdiscrepancyisthecharacteristicsofthe

power MOSFETs. For example, if the top power MOSFET’s

turn-on delay is much smaller than the turn-off delay,

the effective on-time will be longer than the TG on-time,

limiting the effective minimum on-time to a larger value.

(V OF TOP

GS

MOSFET)

DEAD-TIME

DELAYS

BG

(V OF

GS

BOTTOM

MOSFET)

I

±

L

Light-load operation, in forced continuous mode, will

further elongate the effective on-time due to the dead

times between the “on” states of TG and BG, as shown in

Figure 11. During the dead time from BG turn-off to TG

turn-on,theinductorcurrentflowsinthereversedirection,

charging the SW node high before the TG actually turns

on. The reverse current is typically small, causing a slow

rising edge. On the falling edge, after the top FET turns off

and before the bottom FET turns on, the SW node lingers

high for a longer duration due to a smaller peak inductor

current available in light load to pull the SW node low. As

a result of the sluggish SW node rising and falling edges,

the effective on-time is extended and not fully controlled

by the TG on-time. Closer to minimum on-time, this may

cause some phase jitter to appear at light load. As load

currentincrease,theedgesbecomesharper,andthephase

locking behavior improves.

NEGATIVE

INDUCTOR

CURRENT

IN FCM

V

IN

SW

3839 F11

DURING BG-TG DEAD TIME,

DURING TG-BG DEAD TIME,

THE RATE OF SW NODE DISCHARGE

WILL DEPEND ON THE CAPACITANCE

ON THE SW NODE AND INDUCTOR

CURRENT MAGNITUDE

NEGATIVE INDUCTOR CURRENT

WILL FLOW THROUGH TOP MOSFET’S

BODY DIODE TO PRECHARGE SW NODE

+

V

I

IN

L

–

L

SW

I

L

TOTAL CAPACITANCE

ON THE SW NODE

Figure 11. ꢁight ꢁoading On-Time Extension for Forced

Continuous Mode Operation

Incontinuousmodeoperation, theminimumon-timelimit

imposes a minimum duty cycle of:

with different V , V

and/or f, the t

that can

IN OUT

ON(MIN)

D

= f • t

MIN

ON(MIN)

be achieved will generally be larger. Also, to guarantee

frequency and phase locking at light load, sufficient

margin needs to be added to account for the dead times

where t

is the effective minimum on-time for the

ON(MIN)

switching regulator. As the equation shows, reducing the

operating frequency will alleviate the minimum duty cycle

constraint. If the minimum on-time that LTC3839 can

provide is longer than the on-time required by the duty

cycle to maintain the switching frequency, the switching

frequency will have to decrease to maintain the duty cycle,

but the output voltage will still remain in regulation. This is

generally more preferable to skipping cycles and causing

larger ripple at the output, which is typically seen in fixed

frequency switching regulators.

(t

+ t

in the Electrical Characteristics).

D(TG/BG)

Forapplicationsthatrequirerelativelylowon-time, proper

cautionhastobetakenwhenchoosingthepowerMOSFET.

If the gate of the MOSFET is not able to fully turn on due

to insufficient on-time, there could be significant heat dis-

sipation and efficiency loss as a result of larger R

This may even cause early failure of the power MOSFET.

.

DS(ON)

The minimum off-time is the smallest duration of time

that the TG pin can be turned low and then immediately

turned back high. This minimum off-time includes the

time to turn on the BG (bottom gate) and turn it back off,

plus the dead-time delays from TG off to BG on and from

The t

curves in the Typical Performance Charac-

ON(MIN)

teristics are measured with minimum load on TG and BG,

at extreme cases of V = 38V, and/or V

= ±.ꢀV, and/

IN

OUT

or programmed f = 2MHz (i.e., R = 18k). In applications

T

3839fa

30

LTC3839

APPLICATIONS INFORMATION

BG off to TG on. The minimum off-time that the LTC3839

can achieve is 9±ns.

In the LTC3839, the maximum sense voltage is controlled

by the voltage on the V

pin. With valley current mode

RNG

control, the maximum sense voltage and the sense re-

sistance determine the maximum allowed inductor valley

current. The corresponding output current limit is:

The effective minimum off-time of the switching regulator,

or the shortest period of time that the SW node can stay

low,canbedifferentfromthisminimumoff-time.Themain

factor impacting the effective minimum off-time is the top

and bottom power MOSFETs’ electrical characteristics,

such as Qg and turn-on/off delays. These characteristics

can either extend or shorten the SW nodes’ effective

minimum off-time. Large size (high Qg) power MOSFETs

generally tend to increase the effective minimum off-time

due to longer gate charging and discharging times. On

the other hand, imbalances in turn-on and turn-off delays

could reduce the effective minimum off-time.

V

1

2

I_LIMIT

=

^SENSE(MAX)+ • ΔI_L

R_SENSE

The current limit value should be checked to ensure that

> I . The current limit value should

I

LIMIT(MIN)

OUT(MAX)

be greater than the inductor current required to produce

maximum output power at the worst-case efficiency.

Worst-case efficiency typically occurs at the highest V

IN

and highest ambient temperature. It is important to check

The minimum off-time limit imposes a maximum duty

cycle of:

for consistency between the assumed MOSFET junction

temperatures and the resulting value of I

the MOSFET switches.

which heats

LIMIT

D

= 1 – f • t

OFF(MIN)

MAX

To further limit current in the event of a short circuit to

ground, the LTC3839 includes foldback current limiting.

If the output falls by more than ꢁ±7, the maximum sense

voltage is progressively lowered, to about 3±7 of its full

value as the feedback voltage reaches ±V.

where t

is the effective minimum off-time of the

OFF(MIN)

switchingregulator.Reducingtheoperatingfrequencycan

alleviate the maximum duty cycle constraint.

If the maximum duty cycle is reached, due to a drooping

input voltage for example, the output will drop out of

regulation.Theminimuminputvoltagetoavoiddropoutis:

A feedback voltage exceeding 6.ꢁ7 of the regulated target

of ±.ꢀV is considered as overvoltage (OV). In such an OV

condition, the top MOSFET is immediately turned off and

the bottom MOSFET is turned on indefinitely until the OV

condition is removed, i.e., the feedback voltage falling

back below the 6.ꢁ7 threshold by more than a hysteresis

of typical 27. Current limiting is not active during an OV.

If the OV persists, and the BG turns on for a longer time,

the current through the inductor and the bottom MOSFET

mayexceedtheirmaximumratings,sacrificingthemselves

to protect the load.

V_OUT

D_MAX

V

=

IN(MIN)

At the onset of drop-out, there is a region of V of about

IN

ꢁ±±mV that generates two discrete off-times, one being

the minimum off time and the other being an off-time that

is about 4±ns to ꢀ±ns longer than the minimum off-time.

This secondary off-time is due to the extra delay in trip-

ping the internal current comparator. The two off-times

average out to the required duty cycle to keep the output

inregulation.TheremaybehigherSWnodejitter,apparent

especially when synchronized to an external clock, but the

output voltage ripple remains relatively small.

OPTI-ꢁOOP Compensation

OPTI-LOOP compensation, through the availability of the

ITH pin, allows the transient response to be optimized for

a wide range of loads and output capacitors. The ITH pin

not only allows optimization of the control-loop behavior

butalsoprovidesaDC-coupledandAC-filteredclosed-loop

Fault Conditions: Current ꢁimiting and Overvoltage

The maximum inductor current is inherently limited in a

current mode controller by the maximum sense voltage.

3839fa

31

LTC3839

APPLICATIONS INFORMATION

response test point. The DC step, rise time and settling

at this test point truly reflects the closed-loop response.

Assuming a predominantly 2nd order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin.

phasemargin.Theoutputvoltagesettlingbehaviorismore

relatedtothestabilityoftheclosed-loopsystem. However,

itisbettertolookatthefilteredandcompensatedfeedback

loop response at the ITH pin.

The gain of the loop increases with the R and the band-

ITH

The external series R -C

filter at the ITH pin sets the

width of the loop increases with decreasing C

. If R

ITH ITH1

ITH1 ITH

dominant pole-zero loop compensation. The values can

be adjusted to optimize transient response once the final

PCBlayoutisdoneandtheparticularoutputcapacitortype

and value have been determined. The output capacitors

need to be selected first because their various types and

values determine the loop feedback factor gain and phase.

isincreasedbythesamefactorthatC

isdecreased, the

ITH1

zero frequency will be kept the same, thereby keeping the

phase the same in the most critical frequency range of the

feedback loop. In addition, a feedforward capacitor, C ,

FF

can be added to improve the high frequency response, as

shown in Figure 1. Capacitor C provides phase lead by

FF

creating a high frequency zero with R which improves

FB2

An additional small capacitor, C

, can be placed from

ITH2

the phase margin.

the ITH pin to SGND to attenuate high frequency noise.

Note this C contributes an additional pole in the loop

A more severe transient can be caused by switching in

loadswithlargesupplybypasscapacitors.Thedischarged

bypass capacitors of the load are effectively put in parallel

ITH2

gain therefore can affect system stability if too large. It

should be chosen so that the added pole is higher than

the loop bandwidth by a significant margin.

with the converter’s C , causing a rapid drop in V

.

OUT

No regulator can deliver current quick enough to prevent

The regulator loop response can also be checked by

looking at the load transient response. An output current

pulse of 2±7 to 1±±7 of full-load current having a rise

time of 1μs to 1±μs will produce V_OUTand ITH voltage

transient-responsewaveformsthatcangiveasenseofthe

overall loop stability without breaking the feedback loop.

For a detailed explanation of OPTI-LOOP compensation,

refer to Application Note 6ꢀ.

this sudden step change in output voltage, if the switch

connecting the C

to the load has low resistance and is

OUT

driven quickly. The solution is to limit the turn-on speed of

theloadswitchdriver.HotSwap™controllersaredesigned

specificallyforthispurposeandusuallyincorporatecurrent

limiting, short-circuit protection and soft starting.

ꢁoad-Release Transient Detection

Switching regulators take several cycles to respond to

a step in load current. When a load step occurs, V

Astheoutputvoltagerequirementofstep-downswitching

OUT

• ESR,

LOAD

regulators becomes lower, V to V

step-down ratio

IN

OUT

immediately shifts by an amount equal to ∆I

LOAD

increases, and load transients become faster, a major

whereESRistheeffectiveseriesresistanceofC .∆I

OUT

challenge is to limit the overshoot in V

load current drop, or “load-release” transient.

during a fast

OUT

also begins to charge or discharge C , generating a

OUT

feedback error signal used by the regulator to return V

OUT

Inductor current slew rate di /dt = V /L is proportional

to its steady-state value. During this recovery time, V

L

to voltage across the inductor V = V – V . When

can be monitored for overshoot or ringing that would

indicate a stability problem.

L

SW

OUT

the top MOSFET is turned on, V = V – V , inductor

L

IN

OUT

current ramps up. When bottom MOSFET turns on, V =

L

ConnectingaresistiveloadinserieswithapowerMOSFET,

then placing the two directly across the output capacitor

and driving the gate with an appropriate signal generator

is a practical way to produce a realistic load step condi-

tion. The initial output voltage step resulting from the step

change in load current may not be within the bandwidth

of the feedback loop, so it cannot be used to determine

V

SW

– V

= –V , inductor current ramps down. At

very low V , the low differential voltage, V , across the

OUT OUT

OUT

L

inductor during the ramp down makes the slew rate of the

inductor current much slower than needed to follow the

load current change. The excess inductor current charges

up the output capacitor, which causes overshoot at V

.

OUT

3839fa

32

LTC3839

APPLICATIONS INFORMATION

If the bottom MOSFET could be turned off during the load-

release transient, the inductor current would flow through

the body diode of the bottom MOSFET, and the equation

can be modified to include the bottom MOSFET body

INTV . Compensation performance will be identical by

CC

using the same C

and make R

//R

equal the

ITH1

ITH1 ITH2

R

ITH

as used in conventional single resistor OPTI-LOOP

compensation.ThiswillalsoprovidetheR-Ctimeconstant

needed for the DTR duration. The DTR sensitivity can be

adjusted by the DC bias voltage difference between DTR

diode drop to become V = –(V

+ V ). Obviously the

L

OUT

BD

benefit increases as the output voltage gets lower, since

V

BD

would increase the sum significantly, compared to a

and half INTV . This difference could be set as low as

CC

single V

only.

2±±mV, as long as the ITH ripple voltage with DC load

current does not trigger the DTR. Note the ꢁꢂA pull-up

current from the DTR pin will generate an additional offset

on top of the resistor divider itself, making the total dif-

ference between the DC bias voltage on the DTR pin and

OUT

Theload-releaseovershootatV causestheerrorampli-

OUT

fieroutput,ITH,todropquickly.ITHvoltageisproportional

to the inductor current setpoint. A load transient will

result in a quick change of this load current setpoint, i.e.,

a negative spike of the first derivative of the ITH voltage.

half INTV :

CC

V

– ±.ꢁ • V

= [R

/(R

+ R

) – ±.ꢁ]

ITH2

DTR(DC)

INTVCC

ITH1

The LTC3839 uses a detect transient (DTR) pin to monitor

the first derivative of the ITH voltage, and detect the load-

release transient. Referring to the Functional Diagram, the

DTR pin is the input of a DTR comparator, and the internal

• ꢁ.3V + ꢁμA • (R

//R

)

ITH1 ITH2

As illustrated in Figure 12, when load current suddenly

drops,V overshoots,andITHdropsquickly.Thevoltage

OUT

referencevoltagefortheDTRcomparatorishalfofINTV .

on the DTR pin will also drop quickly, since it is coupled

to the ITH pin through a capacitor. If the load transient

is fast enough that the DTR voltage drops below half of

CC

To use this pin for transient detection, ITH compensation

needs an additional R resistor tied to INTV , and con-

ITH

CC

nectsthejunctionpointofITHcompensationcomponents

INTV , a load release event is detected. The bottom gate

CC

C

, R and R to the DTR pin as shown in the

(BG) will be turned off, so that the inductor current flows

through the body diode in the bottom MOSFET. This al-

lows the SW node to drop below PGND by a voltage of

a forward-conducted silicon diode. This creates a more

ITH1 ITH1

ITH2

Functional Diagram. The DTR pin is now proportional to

thefirstderivativeoftheinductorcurrentsetpoint,through

the highpass filter of C

and (R

//R

ITH1 ITH2

).

ITH1

negative differential voltage (V

– V ) across the

SW

OUT

The two R resistors establish a voltage divider from

ITH

inductor, allowing the inductor current to drop at a faster

INTV to SGND, and bias the DC voltage on DTR pin (at

CC

rate to zero, therefore creating less overshoot on V

.

OUT

steady-state load or ITH voltage) slightly above half of

SW

ꢁV/DIV

SW

ꢁV/DIV

BG

ꢁV/DIV

BG REMAINS ON

DURING THE LOAD

RELEASE EVENT

DTR

1V/DIV

ITH

1V/DIV

BG TURNS BACK ON, INDUCTOR

CURRENT (I ) GOES NEGATIVE

L

I

L

1±A/DIV

3839 F12

DTR DETECTS LOAD

ꢁμs/DIV

RELEASE, TURNS OFF BG

FOR FASTER INDUCTOR

V

= ꢁV

V

= ꢁV

IN

OUT

IN

OUT

= ±.ꢀV

CURRENT (I ) DECAY

L

(12a) DTR Enabled

(12b) DTR Disabled

Figure 12. Comparison of Detect Transient ꢁoad-Release (DTR) Feature Enabled and Disabled

3839fa

33

LTC3839

APPLICATIONS INFORMATION

The DTR comparator output is overridden by reverse

produce the most improvement. Percentage efficiency

can be expressed as:

inductor current detection (I ) and overvoltage (OV)

REV

+

condition. This means BG will be turned off when SENSE

7Efficiency = 1±±7 – (L17 + L27 + L37 + ...)

–

is higher than SENSE (i.e., inductor current is positive),

where L17, L27, etc. are the individual losses as a per-

centage of input power. Although all dissipative elements

in the circuit produce power losses, several main sources

usuallyaccountformostofthelossesinLTC3839circuits:

as long as the OV condition is not present. When inductor

current drops to zero and starts to reverse, BG will turn

back on in forced continuous mode (e.g., the MODE/

PLLIN pin tied to INTV , or an input clock is present),

CC

2

even if DTR is still below half INTV . This is to allow the

CC

1. I R loss. These arise from the DC resistances of the

inductor current to go negative to quickly pull down the

MOSFETs,inductor,currentsenseresistorandisthema-

jority of power loss at high output currents. In continu-

ous mode the average output current flows though the

inductor L, but is chopped between the top and bottom

MOSFETs. If the two MOSFETs have approximately the

V

OUT

overshoot. Of course, if the MODE/PLLIN pin is set

to discontinuous mode (i.e., tied to SGND), BG will stay

off as inductor current reverse, as it would with the DTR

feature disabled.

same R

, then the resistance of one MOSFET can

Also,ifV getshigherthantheOVwindow(6.ꢁ7typical),

DS(ON)

OUT

simply be summed with the inductor’s DC resistances

the DTR function is defeated and BG will turn on regard-

2

(DCR) and the board traces to obtain the I R loss. For

example,ifeachR

less.Therefore,inorderfortheDTRfeaturetoreduceV

OUT

=8mΩ,R =ꢁmΩ,andR

overshoot effectively, sufficient output capacitance needs

to be used in the application so that OV is not triggered.

This is best to be tested experimentally with a load step

desired to have its overshoot suppressed.

DS(ON)

L SENSE

= 2mΩ the loss will range from 1ꢁmW to 1.ꢁW as the

outputcurrentvariesfrom1Ato1±A.Thisresultsinloss

from ±.37 to 37 a ꢁV output, or 17 to 1±7 for a 1.ꢁV

output. Efficiency varies as the inverse square of V

OUT

This detect transient feature significantly reduces the

overshoot peak voltage, as well as time to recover (see

Typical Performance Characteristics).

for the same external components and output power

level. The combined effects of lower output voltages

and higher currents load demands greater importance

of this loss term in the switching regulator system.

Note that it is expected that this DTR feature will cause

additional loss on the bottom MOSFET, due to its body

diode conduction. The bottom MOSFET temperature may

be higher with a load of frequent and large load steps.

This is an important design consideration. An experiment

shows a 2±°C increase when a continuous 1±±7 to ꢁ±7

load step pulse train with ꢁ±7 duty cycle and 1±±kHz

frequency is applied to the output.

2. Transition loss. This loss mostly arises from the brief

amount of time the top MOSFET spends in the satura-

tion (Miller) region during switch node transitions. It

depends upon the input voltage, load current, driver

strength and MOSFET capacitance, among other fac-

tors, and can be significant at higher input voltages or

higher switching frequencies.

If not needed, this DTR feature can be disabled by tying

3. DRV current. This is the sum of the MOSFET driver

CC

the DTR pin to INTV , or simply leave the DTR pin open

CC

and INTV control currents. The MOSFET driver cur-

CC

so that an internal 2.ꢁμA current source will pull itself up

rents result from switching the gate capacitance of the

power MOSFETs. Each time a MOSFET gate is switched

from low to high to low again, a packet of charge dQ

to INTV .

CC

Efficiency Considerations

moves from DRV to ground. The resulting dQ/dt is a

CC

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 1±±7.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

current out of DRV that is typically much larger than

CC

the controller I current. In continuous mode,

Q

I

= f • (Qg

+ Qg

),

GATECHG

(TOP)

(BOT)

3839fa

34

LTC3839

APPLICATIONS INFORMATION

where Qg

and Qg

are the gate charges of the

Design Example

Consider a 2-phase step-down converter from V

(TOP)

(BOT)

top and bottom MOSFETs, respectively.

=

IN

Supplying DRV power through EXTV could save

4.ꢁV to 2ꢀV to V

= 1.2V, with I

= 3±A, and

CC

OUT

OUT(MAX)

several percents of efficiency, especially for high V

f = 3ꢁ±kHz (see Figure 13).

IN

applications. Connecting EXTV to an output-derived

CC

The regulated output voltage is determined by:

source will scale the V current required for the driver

IN

⎛

⎞

and controller circuits by a factor of (Duty Cycle)/

R_FB2

R_FB1

V_OUT= 0.6V • 1+

⎜

⎝

⎟

(Efficiency). For example, in a 2±V to ꢁV application,

⎠

1±mAofDRV currentresultsinapproximately2.ꢁmA

CC

of V current. This reduces the mid-current loss from

IN

Using a 1±k resistor for R , R is also 1±k.

FB1 FB2

1±7 or more (if the driver was powered directly from

The frequency is programmed by:

V ) to only a few percent.

IN

41550

f kHz

41550

350

4. C loss. The input capacitor filters large square-wave

R kΩ =

–2.2=

–2.2≈116.5

IN

[

]

T

[

]

input current drawn by the regulator into an averaged

DC current from the supply. The capacitor itself has

a zero average DC current, but square-wave-like AC

current flows through it. Therefore the input capacitor

must have a very low ESR to minimize the RMS current

loss on ESR. It must also have sufficient capacitance

to filter out the AC component of the input current to

prevent additional RMS losses in upstream cabling,

fusesorbatteries.TheLTC3839’sPolyPhasearchitecture

improves the ESR loss.

Use the nearest 17 resistor standard value of 11ꢁk.

Theminimumon-timeoccursformaximumV .Usingthe

IN

t

curvesintheTypicalPerformanceCharacteristics

ON(MIN)

asreferences, makesurethatthet

atmaximumV

ON(MIN)

IN

is greater than that the LTC3839 can achieve, and allow

sufficient margin to account for the extension of effective

on-time at light load due to the dead times (t

+

D(TG/BG)

t

in the Electrical Characteristics). The minimum

D(TG/BG)

on-time for this application is:

“Hidden” copper trace, fuse and battery resistance, even

at DC current, can cause a significant amount of efficiency

degradation, so it is important to consider them during

V_OUT

1.2V

t_ON(MIN)

=

=143ns

V_IN(MAX)• f 24V •350kHz

the design phase. Other losses, which include the C

OUT

ESR loss, bottom MOSFET’s body diode reverse-recovery

loss, and inductor core loss generally account for less

than 27 additional loss.

Settheinductorvaluetogive4±7ripplecurrentofasingle

phase (3±A/2 = 1ꢁA) at maximum V using the adjusted

IN

operating frequency:

Power losses in the switching regulator will reflect as

a higher than ideal duty cycle, or a longer on-time for a

constant frequency. This efficiency accounted on-time

can be calculated as:

1.2V

24V

⎛

⎞ ⎛

⎞

L =

1–

= 0.54µH

⎜

⎝

⎟ ⎜

⎠ ⎝

⎟

⎠

350kHz •40%•15A

Select ±.ꢁꢀμH which is the nearest standard value.

The resulting maximum ripple current is:

t

≈ t /Efficiency

ON(IDEAL)

ON

Whenmakingadjustmentstoimproveefficiency, theinput

current is the best indicator of changes in efficiency. If you

make a change and the input current decreases, then the

efficiency has increased.

⎛

1.2V

350kHz •0.56µH

⎞

1.2V

24V

⎛

⎞

ΔI_L=

1–

= 5.8A

⎜

⎝

⎟

⎠

⎜

⎝

⎟

⎠

3839fa

35

LTC3839

APPLICATIONS INFORMATION

V

IN

4.ꢁV TO 2ꢀV

C

+

IN2

C

IN1

1±μF

2.2Ω

22±μF

w3

LTC3839

1μF

V

IN

–

SENSE1

SENSE2

1ꢁk

±.1μF

1ꢁk

+

SENSE1

SENSE2

±.1μF

BOOST1

TG1

BOOST2

TG2

3.ꢁ6k

L2

MT1

MB1

MT2

MB2

L1

±.ꢁꢀμH

DB1

DB2

±.ꢁꢀμH

V

1.2V

3±A

OUT

SW1

SW2

2.2Ω

DRV

CC1

DRV

CC2

EXTV

C

+

C

+

C

OUT3

OUT1

OUT2

OUT4

INTV

CC

1±±μF

33±μF

1±±μF

1μF

4.6μF

w2

BG1

BG2

PGND

1±k

+

–

V

OUTSENSE

1±k

V

OUTSENSE

1±±k

22pF

PGOOD

±.±1μF

PHASMD

PGOOD

TRACK/SS

ITH

MODE/PLLIN

CLKOUT

22±pF

11ꢁk

9±.9k

68.6k

C

: PANASONIC EEEFK1V221P

: MURATA GRM32ER61H1±ꢀK

IN1

IN2

, C

: SANYO 2RꢁTPE33±M9

OUT2 OUT4

, C

DTR

: MURATA GRM31CRꢀ±J1±6ME39L

OUT1 OUT3

V

DB1, DB2: CENTRAL SEMI CMDSH-4ETR

L1, L2: VISHAY IHLP4±4±DZERRꢁꢀM±1

MT1, MT2: RENESAS RJK±3±ꢁDPB

MB1, MB2: RENESAS RJK±33±DPB

RNG

RT

SGND

RUN

3839 F13a

ꢁ

4

3

2

1

±

ꢁ

1±±

9±

8±

6±

ꢀ±

ꢁ±

1±±

9±

8±

6±

ꢀ±

ꢁ±

V

= 12V

FORCED

V

= ꢁV

IN

CONTINUOUS MODE

DISCONTINUOUS

MODE

4

3

2

1

±

DISCONTINUOUS

MODE

FORCED

CONTINUOUS

MODE

LOSS

FORCED

CM

LOSS

FORCED

CM

LOSS

DCM

LOSS

DCM

±.1

1

1±

1±±

±.1

1

1±

1±±

LOAD CURRENT (A)

3839 F13b

3839 F13c

Figure 13. Design Example: 4.5V to 26V Input, 1.2V/30A Output, 350kHz, DCR Sense, DTR Enabled, Step-Down Converter

3839fa

36

LTC3839

APPLICATIONS INFORMATION

Often in a high power application, DCR current sensing is

for details). Note the equivalent R

= 3.ꢁ6k//1ꢁk = 2.9k,

DCR

preferred over R

in order to maximize efficiency. In

slightlylowerthanthe3.1kcalculatedaboveforamatched

SENSE

order to determine the DCR filter values, first the inductor

manufacturerhastobechosen.Forthisdesign,theVishay

IHLP-4±4±DZ-±1 model is chosen with a value of ±.ꢁꢀμH

R

-C

and L-DCR network. The resulted mismatch

DCR DCR

allows for a slightly higher ripple in V

.

SENSE

Remembertocheckthepeakinductorcurrent,considering

the upper spec limit of individual channel’s V

and a DCR

=1.8mΩ. This implies that:

MAX

SENSE(MAX)

V

= 1.8mΩ • [1 + (1±±°C – 2ꢁ°C) • ±.47/°C]

• (1ꢁA – ꢁ.8A/2) = 28mV

and the DCR

at lowest operating temperature, is not

SENSE(MAX)

(MIN)

going to saturate the inductor or exceed the rating of

power MOSFETs.

The maximum sense voltage, V

, is within the

SENSE(MAX)

range that LTC3839 can handle without any additional

scaling. Therefore, the DCR filter can use a simple RC

filter across the inductor. If the C is chosen to be ±.1μF,

then the R can be calculated as:

For the external N-channel MOSFETs, Renesas

RJK±3±ꢁDBP(R

=13mΩmax,C

J(MAX)

=1ꢁ±pF,V

MILLER GS

DS(ON)

=4.ꢁV,θ =4±°C/W,T

=1ꢁ±°C)ischosenforthetop

JA

MOSFET (main switch). RJK±33±DBP (R

= 3.9mΩ

DS(ON)

max,V =4.ꢁV,θ =4±°C/W,T =1ꢁ±°C)ischosenfor

GS

JA

J(MAX)

L

0.56µH

thebottomMOSFET(synchronousswitch).Thepowerdis-

R_DCR

=

= 3.1kΩ

DCR •C_DCR1.8mΩ•0.1µF

sipationforeachMOSFETcanbecalculatedforV =24Vand

IN

typical T = 12ꢁ°C:

J

The resulting V pin voltage is:

RNG

1.2V

24V

⎛

⎞

2

⎡

⎤

P_TOP

=

15A 13mΩ 1+0.4% 125°C–25°C

(

) (

)

(

)

V_SENSE(MAX)

0.05

⎜

⎝

⎟

⎠

⎣

⎦

V_RNG

=

= 28mV •20= 0.56V

15A

2

2.5Ω

5.3V –3V 3V

1.2Ω

⎛

⎞

⎡

⎤

2

+ 24V

(

150pF

+

350kHz

)

(

)

(

)

⎜

⎝

⎟

⎠

⎢

⎣

⎥

⎦

This voltage can be generated with a resistive divider from

= 0.54W

the INTV pin (ꢁ.3V) or RT pin (1.2V) to signal ground

CC

24V –1.2V

24V

⎛

⎞

2

(SGND). To make sure that the maximum load current can

⎡

⎤

P

=

15A 3.9mΩ 1+0.4% 125°C–25°C

(

) (

)

(

)

⎜

⎝

⎟

⎠

BOT

⎣

⎦

be supplied under all conditions, such as lower INTV

CC

=1.2W

due to a lower V , and account for the range of IC’s own

IN

V

variation within specification, a higher V

should be used to provide margin.

SENSE(MAX)

RNG

The resulted junction temperatures at an ambient tem-

perature T = 6ꢁ°C are:

A

A better and the recommended way to set V

is to sim-

RNG

T

= 6ꢁ°C + (±.ꢁ4W)(4±°C/W) = 96°C

= 6ꢁ°C + (1.2W)(4±°C/W) = 123°C

J(TOP)

J(BOT)

ply tie the V

pin to SGND for an equivalent of V

=

RNG

±.ꢀV, while using an additional resistor in the DCR filter,

as discussed in DCR Inductor Current Sensing, to scale

These numbers show that careful attention should be paid

to proper heat sinking when operating at higher ambient

temperatures. For higher frequency, higher input voltage,

and/or higher load current applications, the LTC3839 IC’s

junction temperature should be estimated to make sure

themaximumjunctiontemperatureratingisnotexceeded,

the V

down by a comfortable margin below

SENSE(MAX)

the lower limit of the IC’s own V

specification,

SENSE(MAX)

so that the maximum output current can be guaranteed.

In this design example, a 3.ꢁ6k and 1ꢁk resistor divider is

used.ThepreviouslycalculatedV

isscaleddown

SENSE(MAX)

from 28mV to 22.ꢀmV, which is less than half of the lower

as discussed in the DRV Regulator and EXTV Power

CC

limit of LTC3839’s statistical 2-channel-sum V

section.

SENSE(MAX)

at V

= ±.ꢀV (see Current Limit Programming section

RNG

3839fa

37

LTC3839

APPLICATIONS INFORMATION

Select the C capacitors to give ample capacitance and

ITH pin to SGND, to roll off the system gain at switching

frequency and attenuate high frequency noise.

IN

RMSripplecurrentrating.Considerworst-casedutycycles

per Figure ꢀ: If operated at steady-state with SW nodes

fully interleaved, the two channels would generate not

more than 6.ꢁA RMS at full load. In this design example,

3 × 1±μF ceramic capacitors are put in parallel to take the

RMS ripple current, with a 22±μF aluminum-electrolytic

bulk capacitor for stability. The number of ceramic ca-

pacitors is chosen to keep the ripple current less than 3A

RMS through each device. The bulk capacitor is chosen

per manufacturer’s RMS rating based on simulation with

To set up the detect transient (DTR) feature, pick resistors

foranequivalentR =R

//R

closetothe4±k.Here,

ITH

ITH1 ITH2

17 resistors R

= 9±.9k (low side) and R

= 68.6k

ITH1

ITH2

(high side) are used, which yields an equivalent R of

ITH

42.2k, and a DC-bias threshold of 4±±mV above one-half

of INTV (taking into account the ꢁμA pull-up current

CC

from DTR pin). This threshold can be adjusted to as low as

2±±mVifmoresensitivityisneeded(seetheLoad-Release

Transient Detection section). Note that even though the

the circuit model provided in the C Selection section.

IN

accuracy of the equivalent compensation resistance R

ITH

The output capacitor C

is chosen for a low ESR to

is not as important, always use 17 or better resistors for

OUT

minimize output voltage changes due to inductor ripple

current and load steps. For the worst-case output ripple

(when the two phases momentarily align and their ripples

add up), consider a single channel’s ripple current flowing

into half of the two channel’s total output capacitance:

the resistor divider from INTV to SGND to guarantee the

CC

relative accuracy of this DC-bias threshold. To disable the

DTR feature, simply use a single R resistor to SGND,

ITH

and tie the DTR pin to INTV .

CC

PCB ꢁayout Checklist

∆V

= ∆I

• ESR = ꢁ.8ꢁA • 4.ꢁmΩ = 2ꢀmV

L(MAX)

OUT(RIPPLE)

The printed circuit board layout is illustrated graphically

in Figure 14. Figure 1ꢁ illustrates the current waveforms

present in the various branches of 2-phase synchronous

regulators operating in continuous mode. Use the follow-

ing checklist to ensure proper operation:

However, such phase alignment typically occurs only for

severalcyclesduringloadtransients.Atsteadyloadcondi-

tions when the phases are interleaved, the ripple currents

from individual channels tend to cancel each other at the

output, which results in lower V

ripple.

OUT

• Amultilayerprintedcircuitboardwithdedicatedground

planes is generally preferred to reduce noise coupling

and improve heat sinking. The ground plane layer

should be immediately next to the routing layer for the

power components, e.g., MOSFETs, inductors, sense

resistors, input and output capacitors etc.

Another important factor to consider is the droop caused

by load step. Here, a 1±A per channel load step will cause

an output change of up to:

∆V

= ∆I

• ESR = 1±A • 4.ꢁmΩ = 4ꢁmV

LOAD

OUT(STEP)

Twooptional1±±μFceramicoutputcapacitorsperchannel

are included to minimize the effect of ESR and ESL in the

output ripple and to improve load step response.

• Keep SGND and PGND separate. Upon finishing the

layout, connect SGND and PGND together with a single

PCBtraceunderneaththeICfromtheSGNDpinthrough

the exposed PGND pad to the PGND pin.

The ITH compensation resistor R of 4±k and a C of

ITH

22±pF are chosen empirically for fast transient response,

and an additional C

= 22pF is added directly from

ITH2

3839fa

38

LTC3839

APPLICATIONS INFORMATION

L2

R

SENSE2

C

B2

MT2

MB2

+

–

V

SENSE2

TG2

SGND

RUN

BOOST2

SW2

RNG

PHASMD

BG2

CERAMIC

D

B2

MODE/PLLIN

CLKOUT

SGND

LTC3839

DRV

CC2

LOCALIZED

EXTV

CC

SGND TRACE

C

OUT2

INTV

CC

R

T

RT

C

ITH1

R

ITH1

ITH2

PGND

V

OUT

PGND

IN

ITH

+

C

VIN

C

R

IN

VIN

V

IN

CERAMIC

C

SS

C

OUT1

DRV

CC1

TRACK/SS

+

D

B1

V

BG1

OUTSENSE

–

+

–

V

SENSE1

DTR PGOOD BOOST1 TG1 SW1

OUTSENSE

R

MT1

FB1

MB1

C

B1

R

FB2

R

SENSE1

L1

3839 F14

BOLD LINES INDICATE HIGH SWITCHING CURRENT KEEP LINES TO A MINIMUM LENGTH

Figure 14. Recommended PCB ꢁayout Diagram

L2

R

SENSE2

SW2

V

IN

R

IN

C

R

LOAD

C

IN

OUT

L1

R

SENSE1

SW1

3839 F1ꢁ

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

Figure 15. Branch Current Waveforms

3839fa

39

LTC3839

APPLICATIONS INFORMATION

• All power train components should be referenced to

of the same ceramic C capacitor(s). These ceramic

IN

PGND; all components connected to noise-sensitive

capacitor(s) bypass the high di/dt current locally, and

both top and bottom MOSFET should have short PCB

trace lengths to minimize high frequency EMI and

prevent MOSFET voltage stress from inductive ringing.

pins, e.g., ITH, RT, TRACK/SS and V , should return

RNG

to the SGND pin. Keep PGND ample, but SGND area

compact.Useamodified“starground”technique:alow

impedance, large copper area central PCB point on the

same side of the as the input and output capacitors.

• The path formed by the top and bottom N-channel

MOSFETs, and the C capacitors should have short

IN

• Placepowercomponents,suchasC ,C ,MOSFETs,

leads and PCB trace. The (–) terminal of output capaci-

IN OUT

D and inductors, in one compact area. Use wide but

tors should be connected close to the (–) terminal of

B

shortest possible traces for high current paths (e.g.,

C , but away from the loop described above. This is

IN

V , V , PGND etc.) to this area to minimize copper

to achieve an effect of Kevin (4-wire) connection to the

input ground so that the “chopped” switching current

will not flow through the path between the input ground

andtheoutputground,andcausecommonmodeoutput

voltage ripple.

IN OUT

loss.

• Keep the switch nodes (SW1,2), top gates (TG1,2) and

boost nodes (BOOST1,2) away from noise-sensitive

small-signal nodes, especially from the opposite chan-

nel’s voltage and current sensing feedback pins. These

nodes have very large and fast moving signals and

therefore should be kept on the “output side” of the

IC (power-related pins are toward the right hand side

of the IC), and occupy minimum PC trace area. Use

compact switch node (SW) planes to improve cooling

of the MOSFETs and to keep EMI down. If DCR sensing

is used, place the top filter resistor (R1 only in Figure ꢁ)

close to the switch node.

• Several smaller sized ceramic output capacitors, C

,

OUT

can be placed close to the sense resistors and before

the rest bulk output capacitors.

+

–

• ThefiltercapacitorbetweentheSENSE andSENSE pins

should always be as close as possible to these pins.

Ensure accurate current sensing with Kevin (4-wire)

connections to the soldering pads from underneath

the sense resistors or inductor. A pair of sense traces

should be routed together with minimum spacing.

• The top N-channel MOSFETs of the two channels have

to be located within a short distance from (preferably

<1cm) each other with a common drain connection at

R

, if used, should be connected to the inductor

SENSE

on the noiseless output side, and its filter resistors

+

–

close to the SENSE /SENSE pins. For DCR sensing,

however, filter resistor should be placed close to the

inductor, and away from the SENSE /SENSE pins, as

its terminal is the SW node.

C . Do not attempt to split the input decoupling for the

IN

+

–

two channels as it can result in a large resonant loop.

• Connect the input capacitor(s), C , close to the power

IN

MOSFETs.ThiscapacitorprovidestheMOSFETtransient

spike current. Connect the drain of the top MOSFET as

close as possible to the (+) plate of the ceramic portion

• Keepsmall-signalcomponentsconnectednoise-sensi-

+

–

+

tivepins(giveprioritytoSENSE /SENSE ,V

/

OUTSENSE1

–

V

, RT, ITH, V

pins) on the left hand side

OUTSENSE1

RNG

of input capacitors C . Connect the source of the bot-

of the IC as close to their respective pins as possible.

This minimizes the possibility of noise coupling into

IN

tom MOSFET as close as possible to the (–) terminal

3839fa

40

LTC3839

APPLICATIONS INFORMATION

these pins. If the IC can be placed on the bottom side

of a multilayer board, use ground planes to isolate from

the major power components on the top side of the

board, and prevent noise coupling to noise sensitive

components on the bottom side.

PCB ꢁayout Debugging

Only after each controller is checked for its individual

performance should both controllers be turned on at the

same time. It is helpful to use a current probe to monitor

thecurrentintheinductorwhiletestingthecircuit.Monitor

the output switching node (SW pin) to synchronize the

oscilloscope to the internal oscillator output CLKOUT, or

external clock if used. Probe the actual output voltage as

well. Check for proper performance over the operating

voltage and current range expected in the application.

• Place the resistor feedback divider R , R close to

FB1 FB2

pins, so that the feed-

+

–

V

and V

OUTSENSE1

back voltage tapped from the resistor divider will not

be disturbed by noise sources. Route remote sense

PCB traces (use a pair of wires closely together for

differential sensing) directly to the terminals of output

capacitors for best output regulation.

The frequency of operation should be maintained over

the input voltage range. The phase should be maintained

from cycle to cycle in a well designed, low noise PCB

implementation. Variation in the phase of SW node pulse

can suggest noise pickup at the current or voltage sensing

inputs or inadequate loop compensation. Overcompensa-

tion of the loop can be used to tame a poor PCB layout if

regulator bandwidth optimization is not required.

• Place decoupling capacitors C

next to the ITH and

ITH2

SGND pins with short, direct trace connections.

• Use sufficient isolation when routing a clock signal into

the MODE/PLLIN pin or out of the CLKOUT pin, so that

the clock does not couple into sensitive pins.

• PlacetheceramicdecouplingcapacitorC

between

INTVCC

Pay special attention to the region of operation when one

controller channel is turning on (right after its current

comparator trip point) while the other channel is turning

off its top MOSFET at the end of its on-time. This may

cause minor phase-lock jitter at either channel due to

noise coupling.

the INTV pin and SGND and as close as possible to

CC

the IC.

• Place the ceramic decoupling capacitor C

to the IC, between the combined DRV

close

DRVCC

pins and

CC1,2

PGND.

• Filter the V input to the IC with an RC filter. Place the

Reduce V from its nominal level to verify operation of

IN

filter capacitor close to the V pin.

the regulator in dropout. Check the operation of the un-

IN

dervoltage lockout circuit by further lowering V while

IN

• If vias have to be used, use immediate vias to connect

components to the SGND and PGND planes of the IC.

Use multiple large vias for power components.

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins.

• Floodallunusedareasonalllayerswithcopper.Flooding

with copper will reduce the temperature rise of power

components. ConnectthecopperareastoDCrailsonly,

e.g., PGND.

3839fa

41

LTC3839

APPLICATIONS INFORMATION

Thecapacitorplacedacrossthecurrentsensingpinsneeds

to be placed immediately adjacent to the pins of the IC.

This capacitor helps to minimize the effects of differential

noise injection due to high frequency capacitive coupling.

High Switching Frequency Operation

At high switching frequencies there may be an increased

sensitivity to noise. Special care may need to be taken to

prevent cycle-by-cycle instability and/or phase-lock jitter.

First, carefullyfollowtherecommendedlayouttechniques

toreducecouplingfromthehighswitchingvoltage/current

traces. Additionally, use low ESR and low impedance XꢁR

or X6R ceramic input capacitors: up to ꢁꢂF per Ampere of

load current may be needed. If necessary, increase ripple

sense voltage by increasing sense resistance value and

If problems are encountered with high current output

loadingatlowerinputvoltages,lookforinductivecoupling

between C , top and bottom MOSFET components to the

IN

sensitive current and voltage sensing traces.

Inaddition,investigatecommongroundpathvoltagepickup

between these components and the SGND pin of the IC.

V

RNG

setting, to improve noise immunity.

3839fa

42

LTC3839

TYPICAL APPLICATIONS

V

IN

4.ꢁV TO 38V

C

+

IN2

C

IN1

1±μF

2.2Ω

1±±μF

w3

LTC3839

1μF

V

IN

–

SENSE1

SENSE2

1ꢁk

±.1μF

1ꢁk

+

SENSE1

SENSE2

±.1μF

BOOST1

TG1

BOOST2

TG2

3.ꢁ6k

L2

MT1

MB1

MT2

MB2

L1

±.ꢁꢀμH

DB1

DB2

±.ꢁꢀμH

V

1.2V

3±A

OUT

SW1

SW2

2.2Ω

DRV

CC1

DRV

CC2

EXTV

C

+

C

+

C

OUT3

OUT1

OUT2

OUT4

INTV

CC

1±±μF

33±μF

1±±μF

1μF

4.6μF

w2

BG1

BG2

PGND

1±k

+

–

V

OUTSENSE

1±k

V

OUTSENSE

1±±k

22pF

PGOOD

±.±1μF

PGOOD

TRACK/SS

ITH

PHASMD

C

: NICHICON UCJ1H1±1MCL1ꢀꢁ

: MURATA GRM32ER61H1±ꢀK

IN1

IN2

, C

: SANYO 2RꢁTPE33±M9

OUT2 OUT4

, C

MODE/PLLIN

CLKOUT

RUN

: MURATA GRM31CRꢀ±J1±6ME39L

OUT1 OUT3

22±pF

11ꢁk

DB1, DB2: DIODES INC. SDM1±K4ꢁ

L1, L2: TOKO FDA1±ꢁꢁ-RꢁꢀM

MT1, MT2: INFINEON BSC±93N±4LSG

MB1, MB2: INFINEON BSC±3ꢁN±4LSG

4±.2k

DTR

V

RNG

RT

SGND

3839 F1ꢀa

ꢁ

4

3

2

1

±

ꢁ

4

3

2

1

±

1±±

9±

8±

6±

ꢀ±

ꢁ±

1±±

9±

8±

6±

ꢀ±

ꢁ±

FORCED

V

= 12V

V

= ꢁV

IN

CONTINUOUS MODE

DISCONTINUOUS

MODE

DISCONTINUOUS

MODE

FORCED

CONTINUOUS

MODE

LOSS

FORCED CM

LOSS

FORCED

CM

LOSS

DCM

LOSS

DCM

±.1

1

1±

1±±

±.1

1

1±

1±±

LOAD CURRENT (A)

3839 F1ꢀb

3839 F1ꢀc

Figure 16. 4.5V to 38V Input, 1.2V/30A Output, 350kHz, DCR Sense, Step-Down Converter

3839fa

43

LTC3839

TYPICAL APPLICATIONS

V

IN

ꢀV TO 2ꢀV

C

+

IN2

C

IN1

22±μF

1±μF

2.2Ω

w3

LTC3839

1μF

1nF

V

IN

2±Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

±.1μF

2.2Ω

±.1μF

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

±.46μH

L2

±.46μH

R

S2

S1

±.±±2Ω

DB1

DB2

V

1.2V

3±A

±.±±2Ω

OUT

SW1

SW2

DRV

CC1

DRV

CC2

EXTV

C

+

C

OUT2

33±μF

+

C

OUT1

OUT3

OUT4

INTV

CC

1±±μF

33±μF

1±±μF

1μF

4.6μF

w2

BG1

BG2

PGND

1±k

+

–

V

OUTSENSE

1±k

V

OUTSENSE

1±±k

PGOOD

±.±1μF

PGOOD

TRACK/SS

ITH

PHASMD

C

: PANASONIC EEEFK1V221P

IN1

IN2

: MURATA GRM32ER61H1±ꢀK

, C

: MURATA GRM31CRꢀ±J1±6ME39L

: SANYO 2RꢁTPE33±M9

OUT1 OUT4

, C

39pF

OUT2 OUT3

DB1, DB2: CENTRAL SEMI CMDSH-4ETR

L1, L2: WÜRTH 644333±±46

MT1, MT2: RENESAS RJK±3±ꢁDPB

MB1, MB2: RENESAS RJK±33±DPB

MODE/PLLIN

CLKOUT

RUN

22±pF

11ꢁk

39.2k

DTR

V

RNG

ꢀ±.4k

RT

1±k

SGND

3839 F16a

ꢁ

4

3

2

1

±

ꢁ

1±±

9±

8±

6±

ꢀ±

ꢁ±

1±±

V

= 12V

V

= ꢁV

FORCED

CONTINUOUS MODE

IN

DISCONTINUOUS

MODE

4

3

2

1

±

9±

8±

6±

ꢀ±

ꢁ±

DISCONTINUOUS

MODE

FORCED

CONTINUOUS

MODE

LOSS

FORCED

CM

LOSS

FORCED

CM

LOSS

DCM

LOSS

DCM

±.1

1

1±

1±±

±.1

1

1±

1±±

LOAD CURRENT (A)

3839 F16b

3839 F16c

Figure 1ꢀ. 6V to 26V Input, 1.2V/30A Output, 350kHz, R_SENSE, Step-Down Converter

3839fa

44

LTC3839

TYPICAL APPLICATIONS

V

IN

4.ꢁV TO 14V

C

+

IN2

C

IN1

22μF

2.2Ω

18±μF

w4

LTC3839

1μF

V

IN

–

SENSE1

SENSE2

±.1μF

+

SENSE1

SENSE2

±.1μF

2.2Ω

BOOST1

TG1

BOOST2

TG2

2.ꢁꢁk

L2

2.ꢁꢁk

MT2

MB2

MT1

MB1

L1

±.33μH

DB1

DB2

±.33μH

V

1.2V

ꢁ±A

OUT

SW1

SW2

DRV

CC1

DRV

CC2

EXTV

C

+

C

+

C

OUT4

OUT1

OUT2

OUT3

INTV

CC

1±±μF

33±μF

1±±μF

1μF

4.6μF

w2

BG1

BG2

PGND

1±k

+

–

V

OUTSENSE

1±k

V

OUTSENSE

1±±k

PGOOD

±.±1μF

PGOOD

TRACK/SS

ITH

PHASMD

C

: SANYO 1ꢀSVP18±MX

IN1

IN2

: MURATA GRM32ERꢀ1C22ꢀKE2±L

, C

: MURATA GRM31CRꢀ±J1±6ME39L

: SANYO 2RꢁTPE33±M9

OUT1 OUT4

, C

46pF

OUT2 OUT3

DB1, DB2: CENTRAL SEMI CMDSH-4ETR

L1, L2: VISHAY IHLPꢁ±ꢁ±CEERR33M±1

MT1, MT2: INFINEON BSC±ꢁ±NE2LS

MB1, MB2: INFINEON BSC±1±NE2LS

MODE/PLLIN

CLKOUT

RUN

46±pF

136k

46.ꢁk

41.2k

DTR

V

RNG

RT

SGND

3839 F18a

1±

8

1±

1±±

9±

8±

6±

ꢀ±

ꢁ±

V

= 12V

V

= ꢁV

IN

DISCONTINUOUS

MODE

8

ꢀ

4

2

±

9±

8±

6±

ꢀ±

ꢁ±

DISCONTINUOUS

MODE

FORCED

CONTINUOUS

MODE

ꢀ

FORCED

CONTINUOUS

MODE

4

LOSS

FORCED

CM

LOSS

FORCED CM

2

LOSS

DCM

LOSS

DCM

±

±.1

1

1±

1±±

±.1

1

1±

1±±

LOAD CURRENT (A)

3839 F18b

3839 F18c

Figure 18. 4.5V to 14V Input, 1.2V/50A Output, 300kHz, DCR Sense, DTR Enabled, Step-Down Converter

3839fa

45

LTC3839

TYPICAL APPLICATIONS

V

IN

ꢀ.ꢁV TO 34V

C

+

IN1

IN2

ꢁꢀμF

1±μF

2.2Ω

w3

LTC3839

1μF

1nF

V

IN

2±Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

±.1μF

2.2Ω

±.1μF

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

2.2μH

L2

2.2μH

R

S2

S1

±.±±2Ω

DB1

DB2

V

±.±±2Ω

OUT

ꢁV

SW1

SW2

2ꢁA

DRV

CC1

DRV

CC2

+

C

OUT2

1ꢁ±μF

V

INTV

EXTV

C

OUT

CC

OUT3

OUT4

1±±μF

OUT1

1±±μF

1ꢁ±μF

1μF

4.6μF

w2

BG1

BG2

PGND

63.2k

+

–

V

OUTSENSE

1±k

V

OUTSENSE

1±±k

PGOOD

±.±1μF

PGOOD

TRACK/SS

ITH

PHASMD

C

: SUNCON ꢁ±HVHꢁꢀM

IN1

IN2

: MURATA GRM32ER61H1±ꢀKA12L

, C

: MURATA GRM31CRꢀ±J1±6ME39L

: SANYO ꢀTPE1ꢁ±MIC2

OUT1 OUT4

, C

22pF

OUT2 OUT3

DB1, DB2: ZETEX ZLLS1±±±

MODE/PLLIN

CLKOUT

RUN

46±pF

L1, L2: WÜRTH 644332±22±

MT1, MT2: INFINEON BSC±93N±4LSG

MB1, MB2: INFINEON BSC±3ꢁN±4LSG

26.4k

DTR

V

RNG

136k

RT

SGND

3839 F19a

8

1±±

9±

8±

6±

ꢀ±

8

ꢀ

4

2

±

1±±

V

= 28V

V

= 12V

IN

DISCONTINUOUS

MODE

DISCONTINUOUS

MODE

ꢀ

4

2

±

9±

FORCED

CONTINUOUS

MODE

FORCED

CONTINUOUS

MODE

8±

6±

ꢀ±

LOSS

DCM

LOSS

FORCED CM

LOSS

FORCED CM

LOSS

DCM

±.1

1

1±

1±±

±.1

1

1±

1±±

LOAD CURRENT (A)

3839 F19c

3839 F19b

Figure 19. 6.5V to 34V Input, 5V/25A Output, 300kHz, R_SENSE, 5V Output Tied to EXTV_CC, Step-Down Converter

3839fa

46

LTC3839

TYPICAL APPLICATIONS

V

IN

4.ꢁV TO 14V

C

+

IN2

C

IN1

22μF

2.2Ω

18±μF

w4

LTC3839

1μF

1nF

V

IN

1±Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

±.1μF

2.2Ω

±.1μF

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

±.3μH

L2

±.3μH

R

S2

±.±±4Ω

S1

DB1

DB2

V

3.3V

2ꢁA

±.±±4Ω

OUT

SW1

SW2

DRV

CC2

CC1

C

OUT1

INTV

EXTV

CC

1±±μF

1μF

4.6μF

wꢀ

BG1

BG2

PGND

4ꢁ.3k

+

–

V

OUTSENSE

1±k

C

: SANYO 1ꢀSVP18±MX

IN1

IN2

V

OUTSENSE

: MURATA GRM32ERꢀ1C22ꢀKE2±L

, C : MURATA GRM31CRꢀ±J1±6ME39L

1±±k

PGOOD

±.±1μF

PGOOD

OUT1 OUT2

PHASMD

DB1, DB2: CENTRAL CMDSH-3

L1, L2: WÜRTH 644334±±3±

MT1, MT2: INFINEON BSC±ꢁ±NE2LS

MB1, MB2: INFINEON BSC±32NE2LS

TRACK/SS

MODE/PLLIN

CLKOUT

RUN

1ꢁ±pF

33.2k

18.6k

ITH

DTR

V

RNG

RT

SGND

3839 F2±a

1±

8

1±

8

1±±

9±

8±

6±

ꢀ±

ꢁ±

1±±

9±

8±

6±

ꢀ±

ꢁ±

V

= 12V

IN

V

= ꢁV

IN

DISCONTINUOUS

MODE

DISCONTINUOUS

MODE

FORCED

ꢀ

CONTINUOUS

FORCED

CONTINUOUS

MODE

4

LOSS

FORCED

CM

2

LOSS

FORCED CM

LOSS

DCM

±

1±±

±

1±±

±.1

1

1±

±.1

1

1±

LOAD CURRENT (A)

3839 F2±c

3839 F2±b

Figure 20. 4.5V to 14V Input, 3.3V/25A Output, 2MHz, R_SENSE, Step-Down Converter

3839fa

47

LTC3839

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UH Package

32-ꢁead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # ±ꢁ-±8-1ꢀ93 Rev D)

±.6± p±.±ꢁ

ꢁ.ꢁ± p±.±ꢁ

4.1± p±.±ꢁ

3.4ꢁ p ±.±ꢁ

3.ꢁ± REF

(4 SIDES)

3.4ꢁ p ±.±ꢁ

PACKAGE OUTLINE

±.2ꢁ p ±.±ꢁ

±.ꢁ± BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = ±.3± TYP

OR ±.3ꢁ s 4ꢁ° CHAMFER

R = ±.±ꢁ

TYP

±.±± – ±.±ꢁ

R = ±.11ꢁ

TYP

±.6ꢁ p ±.±ꢁ

ꢁ.±± p ±.1±

(4 SIDES)

31 32

±.4± p ±.1±

PIN 1

TOP MARK

(NOTE ꢀ)

1

2

3.4ꢁ p ±.1±

3.ꢁ± REF

(4-SIDES)

3.4ꢁ p ±.1±

(UH32) QFN ±4±ꢀ REV D

±.2±± REF

±.2ꢁ p ±.±ꢁ

±.ꢁ± BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M±-22± VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED ±.2±mm ON ANY SIDE

ꢁ. EXPOSED PAD SHALL BE SOLDER PLATED

ꢀ. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3839fa

48

LTC3839

REVISION HISTORY

REV

DATE

DESCRIPTION

PAꢂE NUMBER

A

ꢀ/12

Electrical specs clarification, 4.ꢀV EXTV switch over

3, 4, 1±, 11

CC

3839fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

49

LTC3839

TYPICAL APPLICATION

4.5V to 14V Input, 0.6V/30A Output, 400kHz, R_SENSE, DTR Enabled, Step-Down Converter

V

IN

4.ꢁV TO 14V

C

+

IN2

C

IN1

18±μF

22μF

2.2Ω

w3

LTC3839

1μF

1nF

V

IN

2±Ω

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

±.1μF

2.2Ω

±.1μF

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

±.22μH

L2

±.22μH

R

S1

±.±±2Ω

S2

±.±±2Ω

DB1

DB2

V

±.ꢀV

3±A

OUT

SW1

SW2

DRV

CC1

DRV

CC2

EXTV

C

+

C

OUT2

33±μF

OUT1

INTV

CC

1±±μF

1μF

4.6μF

w4

BG1

BG2

PGND

+

–

V

OUTSENSE

V

OUTSENSE

1±±k

PGOOD

±.±1μF

C

: SANYO 1ꢀSVP18±MX

IN1

IN2

PGOOD

TRACK/SS

ITH

: MURATA GRM32ERꢀ1C22ꢀKE2±L

PHASMD

: MURATA GRM31CRꢀ±J1±6ME39L

: SANYO 2RꢁTPE33±M9

OUT1

OUT2

46pF

DB1, DB2: CENTRAL SEMI CMDSH-4ETR

L1, L2: WÜRTH 6443±6±22

MT1, MT2: INFINEON BSC±ꢁ±NE2LS

MB1, MB2: INFINEON BSC±1±NE2LS

MODE/PLLIN

22±pF

4±.2k

3ꢀ.ꢁk

3±.1k

DTR

CLKOUT

RUN

V

RNG

ꢀ±.4k

RT

SGND

3839 TA±2

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC3838

Dual Output, Fast Controlled On-Time, High Frequency

Synchronous Step-down Controller with Diff Amp

2±±kHz to 2MHz Operating Frequency, 4.ꢁV ≤ V ≤ 38V,

IN

±.ꢀV ≤ V

≤ ꢁ.ꢁV, , ꢁmm × 6mm QFN-38, TSSOP-38

OUT

LTC386ꢀ

LTC3833

Dual, DC/DC Controller for DDR Memory Power with

Differential Voltage Sensing and ±ꢁ±mA VTT Reference

2±±kHz to 2MHz Operating Frequency, 4.ꢁV ≤ V ≤ 38V,

IN

1V ≤ VDDQ ≤ 2.ꢁV, , ꢁmm × 6mm QFN-38, TSSOP-38

Fast Controlled On-Time, High Frequency Synchronous

Step-Down Controller with Diff Amp

2±±kHz to 2MHz Operating Frequency, 4.ꢁV ≤ V ≤ 38V,

IN

±.ꢀV ≤ V

≤ ꢁ.ꢁV, , 3mm × 4mm QFN-2±, TSSOP-2±

OUT

2

LTC388±/LTC388±-1 Dual Output PolyPhase Step-Down DC/DC Controller with

Digital Power System Management

I C/PMBus Interface with EEPROM and 1ꢀ-Bit ADC, V Up to 24V,

IN

±.ꢁV ≤ V

≤ ꢁ.ꢁV, Analog Control Loop

OUT

LTC38ꢀ9/LTC38ꢀ9-2 Dual Output, 2-Phase Synchronous Step-Down DC/DC

Controller, with Accurate Current Sharing

PLL Fixed 2ꢁ±kHz to 6ꢁ±kHz Frequency, 4V ≤ V ≤ 38V,

IN

OUT3

V

Up to 12.ꢁV

LTC38ꢁꢁ

LTC38ꢁꢀ

LTC38ꢀ±

LTC3829

LTC38ꢁ3

Dual Output, 2-phase, Synchronous Step-Down DC/DC

PLL Fixed Frequency 2ꢁ±kHz to 66±kHz, 4.ꢁV ≤ V ≤ 38V,

IN

Controller with Diff Amp and DCR Temperature Compensation ±.8V ≤ V

≤ 12V

OUT

Single Output 2-Channel Synchronous Step-Down DC/DC

Controller with Diff Amp and Up to 12-Phase Operation

PLL Fixed 2ꢁ±kHz to 66±kHz Frequency, 4.ꢁV ≤ V ≤ 38V,

IN

±.8V ≤ V

≤ ꢁV

OUT

Dual, Multiphase, Synchronous Step-Down DC/DC Controller Operates with Power Blocks, DRMOS Devices or External Drivers/

with Diff Amp and Three-State Output Drive MOSFETs, 3V ≤ V ≤ 24V, t = 2±ns

IN

ON(MIN)

Single Output 3-Channel Synchronous Step-Down DC/DC with Controller Phase-Lockable Fixed 2ꢁ±kHz to 66±kHz Frequency,

Diff Amp and Up to ꢀ-phase Operation

4.ꢁV ≤ V ≤ 38V, ±.8V ≤ V

≤ ꢁV

IN

OUT

Triple Output, Multiphase Synchronous Step-Down DC/DC

PLL Fixed 2ꢁ±kHz to 6ꢁ±kHz Frequency, 4V ≤ V ≤ 24V,

IN

Controller, R

or DCR Current Sensing and Tracking

V

Up to 13.ꢁV

OUT3

SENSE

3839fa

LT 0612 REV A • PRINTED IN USA

LinearTechnology Corporation

1ꢀ3± McCarthy Blvd., Milpitas, CA 9ꢁ±3ꢁ-6416

50

●

(4±8) 432-19±± FAX: (4±8) 434-±ꢁ±6 www.linear.com


型号：	LTC3876
厂家：	Linear
描述：	Fast, Accurate, 2-Phase, Single-Output Step-Down DC/DC Controller 快速，准确，两相单输出降压型DC / DC控制器控制器
文件：	总50页 (文件大小：696K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3876 [Linear]

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