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LTC4274C_15 [Linear]

Single PoE/PoE/LTPoE PSE Controller;
LTC4274C_15
型号： LTC4274C_15
厂家： Linear    Linear
描述：

Single PoE/PoE/LTPoE PSE Controller
文件： 总30页 (文件大小：360K)
中文：  中文翻译
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LTC4274A/LTC4274C  
++  
+
Single PoE/PoE /LTPoE  
PSE Controller  
FEATURES  
DESCRIPTION  
n
Compliant with IEEE 802.3at Type 1 and 2  
The LTC®4274A is a single Power Sourcing Equipment  
n
++  
(PSE)controllercapableofdeliveringupto90WofLTPoE  
Low Power Dissipation  
++  
n
power to a compatible LTPoE Powered Device (PD). A  
0.25Ω Sense Resistance Per Channel  
n
proprietarydetection/classificationschemeallowsmutual  
Very High Reliability 4-Point PD Detection  
++  
++  
n
identification between a LTPoE PSE and LTPoE PD  
whileremainingcompatibleandinteroperablewithexisting  
Type 1 (13W) and Type 2 (25.5W) PDs. The LTC4274A  
feature set is a superset of the popular LTC4274. These  
2-Point Forced Voltage  
2-Point Forced Current  
n
n
n
n
n
n
High Capacitance Legacy Device Detection  
2
1MHz I C Compatible Serial Control Interface  
PSE controllers feature low-R external MOSFETs and  
ON  
Midspan Backoff Timer  
0.25Ω sense resistors which are especially important at  
Supports 2-Pair and 4-Pair Output Power  
++  
theLTPoE currentlevelstomaintainthelowestpossible  
Available in Multiple Power Grades  
heat dissipation.  
n
++  
LTC4274A-1: LTPoE ™ 38.7W  
n
n
n
n
++  
LTC4274A-2: LTPoE 52.7W  
TheLTC4274CtargetsfullyautomaticPSEsystemspower-  
ing Type 1 (up to 13W) PDs.  
++  
LTC4274A-3: LTPoE 70W  
++  
LTC4274A-4: LTPoE 90W  
Advanced power management features include: a 14-bit  
currentmonitoringADC,DAC-programmablecurrentlimit,  
and versatile quick port shutdown. PD Discovery uses  
a proprietary dual-mode 4-point detection mechanism  
ensuring excellent immunity from false PD detection.  
The LTC4274A/LTC4274C includes an I C serial interface  
operable up to 1MHz.  
LTC4274C: PoE 13W  
n
Available in 38-Lead 5mm × 7mm QFN Package  
APPLICATIONS  
2
n
++  
LTPoE PSE Switches/Routers  
n
n
n
++  
LTPoE PSE Midspans  
IEEE 802.3at Type 1 PSE Switches/Routers  
IEEE 802.3at Type 1 PSE Midspans  
The LTC4274A/LTC4274C is available in multiple power  
grades, allowing delivered PD power of 13W, 25.5W,  
38.7W, 52.7W, 70W and90W. Thesecontrollers are avail-  
able in a 38-lead 5mm × 7mm QFN package.  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and  
++  
LTPoE are trademarks of Linear Technology Corporation. All other trademarks are the  
property of their respective owners.  
TYPICAL APPLICATION  
Complete Single-Port Ethernet High Power Source  
10Ω  
AD0 AD1 AD2 AD3  
SCL SDAIN SDAOUT INT  
3.3V  
V
DD  
AUTO  
MSD  
RESET  
MID  
SHDN  
0.1µF  
SMAJ5.0A  
10µF  
+
+
DGND  
AGND  
LTC4274AC  
10Ω  
V
SENSE GATE OUT  
EE  
SMAJ58A  
1µF  
C
BULK  
–54V  
0.22µF  
100V  
100V  
S1B  
S1B  
TVS  
BULK  
PORT  
4274AC TA01  
–54V  
4274acfd  
1
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
ABSOLUTE MAXIMUM RATINGS  
PIN CONFIGURATION  
Supply Voltages (Note 1)  
TOP VIEW  
AGND – V ........................................... –0.3V to 80V  
EE  
DGND – V ........................................... –0.3V to 80V  
EE  
V
– DGND ......................................... –0.3V to 5.5V  
DD  
38 37 36 35 34 33 32  
Digital Pins  
SDAOUT  
NC  
1
2
3
4
5
6
7
8
9
31 GATE  
SCL, SDAIN, SDAOUT, INT, SHDN, MSD, AD,  
RESET, AUTO, MID........... DGND –0.3V to V + 0.3V  
30 SENSE  
SDAIN  
AD3  
NC  
29  
DD  
NC  
28  
27  
26  
25  
Analog Pins  
AD2  
V
V
V
EE  
EE  
EE  
GATE, SENSE, OUT................ V –0.3V to V + 80V  
EE  
EE  
AD1  
Operating Temperature Range .................–40°C to 85°C  
Junction Temperature (Note 2) ............................. 125°C  
Storage Temperature Range .................. –65°C to 150°C  
Lead Temperature (Soldering, 10 sec)...................300°C  
V
EE  
AD0  
39  
DNC  
NC  
24 NC  
23 NC  
DGND 10  
NC 11  
22  
21 NC  
20  
V
EE  
NC 12  
NC  
13 14 15 16 17 18 19  
UHF PACKAGE  
38-LEAD (5mm × 7mm) PLASTIC QFN  
EXPOSED PAD IS V (PIN 39) MUST BE SOLDERED TO PCB  
EE  
JMAX  
T
= 125°C, θ = 34°C/W  
JA  
ORDER INFORMATION  
LEAD FREE FINISH  
TAPE AND REEL  
PART MARKING  
PACKAGE DESCRIPTION  
MAX PWR TEMPERATURE RANGE  
LTC4274CIUHF#PBF  
LTC4274CIUHF#TRPBF  
4274C  
38-Lead (5mm × 7mm) Plastic QFN  
38-Lead (5mm × 7mm) Plastic QFN  
38-Lead (5mm × 7mm) Plastic QFN  
38-Lead (5mm × 7mm) Plastic QFN  
38-Lead (5mm × 7mm) Plastic QFN  
13W  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
LTC4274AIUHF-1#PBF LTC4274AIUHF-1#TRPBF 4274A1  
LTC4274AIUHF-2#PBF LTC4274AIUHF-2#TRPBF 4274A2  
LTC4274AIUHF-3#PBF LTC4274AIUHF-3#TRPBF 4274A3  
LTC4274AIUHF-4#PBF LTC4274AIUHF-4#TRPBF 4274A4  
38.7W  
52.7W  
70W  
90W  
Consult LTC Marketing for parts specified with wider operating temperature ranges.  
Consult LTC Marketing for information on non-standard lead based finish parts.  
For more information on lead free part marking, go to: http://www.linear.com/leadfree/  
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/  
4274acfd  
2
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
ELECTRICAL CHARACTERISTICS  
The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V  
unless otherwise noted. (Notes 3, 4)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
EE  
Main PoE Supply Voltage  
AGND – V  
For IEEE Type 1 Compliant Output  
For IEEE Type 2 Compliant Output  
EE  
l
l
l
45  
51  
54.75  
57  
57  
57  
V
V
V
++  
For LTPoE Compliant Output  
l
l
l
l
l
l
Undervoltage Lockout  
AGND – V  
20  
25  
3.3  
2.2  
30  
V
V
EE  
V
V
Supply Voltage  
V – DGND  
DD  
3.0  
4.3  
DD  
DD  
Undervoltage Lockout  
V
Allowable Digital Ground Offset  
DGND – V  
25  
57  
–5  
3
V
EE  
I
I
V
V
Supply Current  
Supply Current  
(AGND – V ) = 55V  
–2.4  
1.1  
mA  
mA  
EE  
EE  
EE  
(V – DGND) = 3.3V  
DD  
DD  
DD  
Detection  
l
l
Detection Current – Force Current  
Detection Voltage – Force Voltage  
First Point, AGND – V  
Second Point, AGND – V  
= 9V  
220  
140  
240  
160  
260  
180  
µA  
µA  
OUT  
= 3.5V  
OUT  
AGND – V , 5µA ≤ I  
≤ 500µA  
OUT  
OUT  
l
l
First Point  
Second Point  
7
3
8
4
9
5
V
V
l
l
l
l
l
Detection Current Compliance  
Detection Voltage Compliance  
Detection Voltage Slew Rate  
AGND – V  
= 0V  
0.8  
0.9  
12  
mA  
V
OUT  
V
AGND – V , Open Port  
10.4  
OC  
OUT  
AGND – V , C  
= 0.15µF  
0.01  
18.5  
32  
V/µs  
kΩ  
kΩ  
OUT PORT  
Minimum Valid Signature Resistance  
Maximum Valid Signature Resistance  
15.5  
27.5  
17  
29.7  
Classification  
l
l
V
CLASS  
Classification Voltage  
AGND – V , 0mA ≤ I ≤ 50mA  
CLASS  
16.0  
53  
20.5  
67  
V
OUT  
Classification Current Compliance  
Classification Threshold Current  
V
OUT  
= AGND  
61  
mA  
l
l
l
l
l
Class 0 – 1  
Class 1 – 2  
Class 2 – 3  
Class 3 – 4  
5.5  
6.5  
14.5  
23  
33  
48  
7.5  
mA  
mA  
mA  
mA  
mA  
13.5  
21.5  
31.5  
45.2  
15.5  
24.5  
34.9  
50.8  
Class 4 – Overcurrent  
l
l
V
MARK  
Classification Mark State Voltage  
Mark State Current Compliance  
AGND – V , 0.1mA ≤ I ≤ 10mA  
CLASS  
7.5  
53  
9
10  
67  
V
OUT  
V
OUT  
= AGND  
61  
mA  
Gate Driver  
l
l
GATE Pin Pull-Down Current  
Port Off, V  
Port Off, V  
= V + 5V  
0.4  
0.08  
mA  
mA  
GATE  
GATE  
EE  
= V + 1V  
0.12  
30  
EE  
GATE Pin Fast Pull-Down Current  
GATE Pin On Voltage  
V
GATE  
GATE  
= V + 5V  
mA  
V
EE  
l
V
– V , I  
= 1µA  
8
12  
14  
EE GATE  
Output Voltage Sense  
l
l
V
PG  
Power Good Threshold Voltage  
V
– V  
EE  
2
2.4  
2.8  
V
OUT  
OUT Pin Pull-Up Resistance to AGND  
0V ≤ (AGND – V ) ≤ 5V  
300  
500  
700  
kΩ  
OUT  
4274acfd  
3
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V  
unless otherwise noted. (Notes 3, 4)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Current Sense  
V
CUT  
Overcurrent Sense Voltage  
V
SENSE  
– V , hpen = 01h, cut[5:0] ≥ 4 (Note 12)  
EE  
l
l
cutrng = 0  
cutrng = 1  
9
4.5  
9.38  
4.69  
9.75  
4.88  
mV/LSB  
mV/LSB  
l
l
l
l
Overcurrent Sense in AUTO Pin Mode  
Class 0, Class 3  
Class 1  
Class 2  
90  
26  
49  
94  
28  
52  
98  
30  
55  
mV  
mV  
mV  
mV  
Class 4  
152  
159  
166  
V
V
Active Current Limit in 802.3af  
Compliant Mode  
V
– V , hpen = 01h, lim = 80h,  
SENSE EE  
LIM  
V
EE  
= 55V (Note 12)  
l
l
V
EE  
< V  
< AGND – 29V  
102  
20  
106  
110  
50  
mV  
mV  
OUT  
AGND – V  
= 0V  
OUT  
Active Current Limit in High Power Mode  
Active Current Limit in AUTO Pin Mode  
hpen = 01h, lim = C0h, V = 55V  
EE  
LIM  
l
l
l
V
V
– V = 0V to 10V  
204  
100  
20  
212  
106  
221  
113  
50  
mV  
mV  
mV  
OUT  
EE  
+ 23V < V  
< AGND –  
EE  
OUT  
29V  
AGND – V  
= 0V  
OUT  
V
LIM  
V
– V = 0V to 10V, V = 55V  
OUT EE EE  
l
l
Class 0 to Class 3  
Class 4  
102  
204  
106  
212  
110  
221  
mV  
mV  
l
l
V
V
DC Disconnect Sense Voltage  
Short-Circuit Sense  
V
V
– V , rdis = 0  
2.6  
1.3  
3.8  
1.9  
4.8  
2.41  
mV  
mV  
MIN  
SENSE  
SENSE  
EE  
– V , rdis = 1  
EE  
l
l
V
SENSE  
V
SENSE  
– V – V , rdis = 0  
160  
75  
200  
100  
255  
135  
mV  
mV  
SC  
EE  
LIM  
– V – V , rdis = 1  
EE  
LIM  
Port Current ReadBack  
Resolution  
No Missing Codes, fast_iv = 0  
– V  
14  
30.5  
30  
Bits  
µV/LSB  
dB  
LSB Weight  
V
SENSE  
EE  
50Hz to 60Hz Noise Rejection  
(Note 7)  
Port Voltage ReadBack  
Resolution  
No Missing Codes, fast_iv = 0  
14  
5.835  
30  
bits  
mV/LSB  
dB  
LSB Weight  
AGND – V  
(Note 7)  
OUT  
50Hz to 60Hz Noise Rejection  
Digital Interface  
l
V
Digital Input Low Voltage  
ADn, SHDN, RESET, MSD, AUTO, MID  
(Note 6)  
0.8  
0.8  
V
ILD  
2
l
l
I C Input Low Voltage  
SCL, SDAIN (Note 6)  
(Note 6)  
V
V
V
Digital Input High Voltage  
Digital Output Low Voltage  
2.2  
IHD  
l
l
I
I
= 3mA, I = 3mA  
0.4  
0.7  
V
V
SDAOUT  
SDAOUT  
INT  
= 5mA, I = 5mA  
INT  
4274acfd  
4
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V  
unless otherwise noted. (Notes 3, 4)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
50  
MAX  
UNITS  
kΩ  
Internal Pull-Up to V  
ADn, SHDN, RESET, MSD  
AUTO, MID  
DD  
Internal Pull-Down to DGND  
Timing Characteristics  
50  
kΩ  
l
l
t
Detection Time  
Detection Delay  
Beginning to End of Detection (Note 7)  
270  
300  
290  
12  
310  
470  
ms  
ms  
DET  
t
From PD Connected to Port to Detection  
Complete (Note 7)  
DETDLY  
l
l
l
l
l
t
t
t
t
t
Class Event Duration  
(Note 7)  
ms  
ms  
ms  
ms  
ms  
CLE  
Class Event Turn-On Duration  
Mark Event Duration  
C
PORT  
= 0.6µF (Note 7)  
0.1  
60  
CLEON  
ME  
(Notes 7, 11)  
(Notes 7, 11)  
8.6  
22  
Last Mark Event Duration  
Power On Delay in AUTO Pin Mode  
16  
15  
MEL  
PON  
From End of Valid Detect to Application of Power  
to Port (Note 7)  
l
Turn On Rise Time  
(AGND – V ): 10% to 90% of (AGND – V ),  
24  
µs  
OUT  
EE  
C
PORT  
= 0.15µF (Note 7)  
l
l
l
l
Turn On Ramp Rate  
C
= 0.15µF (Note 7)  
10  
V/µs  
PORT  
Fault Delay  
From I  
Fault to Next Detect  
1.0  
2.3  
1.0  
1.1  
2.5  
1.3  
s
s
s
CUT  
Midspan Mode Detection Backoff  
Power Removal Detection Delay  
Rport = 15.5kΩ (Note 7)  
2.7  
2.5  
From Power Removal After t to Next Detect  
DIS  
(Note 7)  
l
l
l
t
t
t
Maximum Current Limit Duration During  
Port Start-Up  
(Note 7)  
52  
62.5  
11.9  
62.5  
6.3  
66  
ms  
ms  
ms  
START  
Maximum Current Limit Duration After Port t Enable = 1 (Notes 7, 12)  
Start-Up  
LIM  
LIM  
Maximum Overcurrent Duration After Port (Note 7)  
Start-Up  
52  
66  
CUT  
l
l
Maximum Overcurrent Duty Cycle  
(Note 7)  
5.8  
1.6  
6.7  
3.6  
%
t
t
Maintain Power Signature (MPS) Pulse  
Width Sensitivity  
Current Pulse Width to Reset Disconnect Timer  
(Notes 7, 8)  
ms  
MPS  
l
Maintain Power Signature (MPS) Dropout (Notes 5, 7)  
Time  
320  
350  
2
380  
ms  
DIS  
l
l
l
l
t
t
Masked Shut Down Delay  
Port Shut Down Delay  
(Note 7)  
(Note 7)  
6.5  
6.5  
3
µs  
µs  
s
MSD  
SHDN  
2
I C Watchdog Timer Duration  
1.5  
3
Minimum Pulse Width for Masked Shut  
Down  
(Note 7)  
µs  
l
l
Minimum Pulse Width for SHDN  
Minimum Pulse Width for RESET  
(Note 7)  
(Note 7)  
3
µs  
µs  
4.5  
4274acfd  
5
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless  
otherwise noted. (Notes 3, 4)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
2
I C Timing  
l
l
l
l
l
Clock Frequency  
Bus Free Time  
Start Hold Time  
SCL Low Time  
SCL High Time  
Data Hold Time  
(Note 7)  
1
MHz  
ns  
t
t
t
t
t
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
480  
240  
480  
240  
60  
1
2
3
4
5
ns  
ns  
ns  
l
l
Figure 5 (Notes 7, 9) Data into Chip  
Data Out of Chip  
ns  
ns  
120  
l
l
l
l
l
l
l
l
l
t
t
t
t
t
Data Set-Up Time  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
(Notes 7, 9, 10)  
80  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
ns  
6
7
8
r
Start Set-Up Time  
240  
240  
Stop Set-Up Time  
SCL, SDAIN Rise Time  
SCL, SDAIN Fall Time  
Fault Present to INT Pin Low  
Stop Condition to INT Pin Low  
ARA to INT Pin High Time  
SCL Fall to ACK Low  
120  
60  
f
150  
1.5  
1.5  
120  
(Notes 7, 9, 10)  
(Notes 7, 9)  
(Notes 7, 9)  
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 2: This IC includes overtemperature protection that is intended  
to protect the device during momentary overload conditions. Junction  
temperature will exceed 140°C when overtemperature protection is active.  
Continuous operation above the specified maximum operating junction  
temperature may impair device reliability.  
Note 3: All currents into device pins are positive; all currents out of device  
pins are negative.  
Note 4: The LTC4274A/LTC4274C operates with a negative supply voltage  
(with respect to ground). To avoid confusion, voltages in this data sheet  
are referred to in terms of absolute magnitude.  
Note 6: The LTC4274A/LTC4274C digital interface operates with respect to  
DGND. All logic levels are measured with respect to DGND.  
Note 7: Guaranteed by design, not subject to test.  
Note 8: The IEEE 802.3af specification allows a PD to present its  
Maintain Power Signature (MPS) on an intermittent basis without being  
disconnected. In order to stay powered, the PD must present the MPS for  
t
within any t  
time window.  
MPS  
MPDO  
Note 9: Values measured at V  
Note 10: If fault condition occurs during an I C transaction, the INT pin  
will not be pulled down until a stop condition is present on the I C bus.  
and V  
.
ILD(MAX)  
IHD(MIN)  
2
2
Note 11: Load Characteristic of the LTC4274A/LTC4274C during Mark:  
7V < (AGND – V ) < 10V or I  
< 50µA  
OUT  
OUT  
Note 12: See the LTC4274A/LTC4274C Software Programming  
documentation for information on serial bus usage and device  
configuration and status registers.  
Note 5: t is the same as t  
defined by IEEE 802.3at.  
DIS  
MPDO  
4274acfd  
6
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
TYPICAL PERFORMANCE CHARACTERISTICS  
Power-On Sequence in  
802.3af Classification in  
AUTO Pin Mode  
AUTO Pin Mode  
Powering Up into a 180µF Load  
10  
0
GND  
GND  
FORCED CURRENT DETECTION  
GND  
V
DD  
V
EE  
= 3.3V  
= –54V  
PORT  
VOLTAGE  
20V/DIV  
LOAD  
FULLY  
–10  
–20  
–30  
CHARGED  
–18.4  
FORCED VOLTAGE  
DETECTION  
V
EE  
PORT  
CURRENT  
200 mA/DIV  
802.3af  
FOLDBACK  
V
DD  
V
EE  
= 3.3V  
= –55V  
PORT  
VOLTAGE  
10V/DIV  
425mA  
CURRENT LIMIT  
V
DD  
V
EE  
= 3.3V  
= –54V  
CLASSIFICATION  
–40  
–50  
–60  
–70  
PD IS CLASS 1  
POWER ON  
0mA  
FET ON  
GATE  
VOLTAGE  
10V/DIV  
V
EE  
V
V
EE  
EE  
5ms/DIV  
5ms/DIV  
100ms/DIV  
4274AC G02  
4274AC G01  
4274AC G03  
2-Event Classification in  
AUTO Pin Mode  
Classification Transient Response  
to 40mA Load Step  
Classification Current Compliance  
0
–2  
GND  
V
V
T
= 3.3V  
= –54V  
DD  
EE  
V
DD  
V
EE  
= 3.3V  
= –54V  
40mA  
0mA  
= 25°C  
PORT  
CURRENT  
20mA/DIV  
A
–4  
–17.6  
–6  
1ST CLASS EVENT  
–8  
2ND CLASS EVENT  
–10  
–12  
–14  
–16  
–18  
–20  
PORT  
VOLTAGE  
10V/DIV  
V
V
= 3.3V  
= –55V  
DD  
EE  
PORT  
VOLTAGE  
1V/DIV  
PD IS CLASS 4  
–20V  
V
EE  
0
10  
20  
30  
40  
50  
60  
70  
50µs/DIV  
10ms/DIV  
CLASSIFICATION CURRENT (mA)  
4274AC G04  
4274AC G05  
4274AC G06  
802.3at ILIM Threshold  
vs Temperature  
V
DD Supply Current vs Voltage  
VEE Supply Current vs Voltage  
1.8  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
215  
214  
213  
212  
211  
210  
860  
856  
852  
848  
844  
840  
2.4  
2.3  
2.2  
2.1  
85°C  
25°C  
–40°C  
V
V
= 3.3V  
= –54V  
SENSE  
DD  
EE  
R
= 0.25Ω  
REG 48h = C0h  
85°C  
25°C  
–40°C  
2.0  
–40  
0
40  
–80  
120  
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3  
SUPPLY VOLTAGE (V)  
–60 –55 –50 –45 –40 –35 –30 –25 –20  
SUPPLY VOLTAGE (V)  
TEMPERATURE (°C)  
V
V
DD  
EE  
4274AC G09  
4274AC G07  
4274AC G08  
4274acfd  
7
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
TYPICAL PERFORMANCE CHARACTERISTICS  
802.3af ILIM Threshold  
vs Temperature  
802.3at ICUT Threshold  
vs Temperature  
163  
162  
652  
648  
644  
640  
108.00  
107.25  
106.50  
432  
429  
V
V
= 3.3V  
= –54V  
SENSE  
V
V
= 3.3V  
= –54V  
SENSE  
DD  
EE  
DD  
EE  
R
= 0.25Ω  
R
= 0.25Ω  
REG 47h = E2h  
REG 48h = 80h  
161  
160  
159  
158  
426  
423  
420  
105.75  
105.00  
636  
630  
–40  
0
40  
80  
120  
–40  
0
40  
80  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4274AC G10  
4274AC G11  
802.3af ICUT Threshold  
vs Temperature  
DC Disconnect Threshold  
vs Temperature  
8.00  
7.75  
7.50  
7.25  
7.00  
2.0000  
1.9375  
96.00  
95.25  
94.50  
93.75  
93.00  
384  
381  
V
V
= 3.3V  
= –54V  
SENSE  
V
V
= 3.3V  
= –54V  
SENSE  
DD  
EE  
DD  
EE  
R
= 0.25Ω  
R
= 0.25Ω  
REG 47h = E2h  
REG 47h = D4h  
1.8750  
1.8125  
1.7500  
378  
375  
372  
–40  
0
40  
80  
120  
–40  
0
40  
80  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4274AC G13  
4274AC G12  
ADC Noise Histogram  
Current Readback in Fast Mode  
ADC Integral Nonlinearity  
Current Limit Foldback  
Current Readback in Fast Mode  
400  
350  
300  
250  
200  
1.0  
0.5  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
225  
V
– V = 110.4mV  
EE  
V
= 3.3V  
SENSE  
DD  
EE  
SENSE  
V
= –54V  
200  
175  
150  
125  
100  
75  
R
= 0.25Ω  
REG 48h = C0h  
0
150  
100  
50  
–0.5  
–1.0  
50  
25  
0
0
191  
192  
193  
ADC OUTPUT  
196  
–54  
–45  
–36  
–9  
0
194  
195  
–27  
–18  
0
50 100 150  
200  
250 300 350 400 450 500  
V
(V)  
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)  
OUTn  
4274AC G15  
4274AC G14  
4274AC G16  
4274acfd  
8
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
TYPICAL PERFORMANCE CHARACTERISTICS  
ADC Noise Histogram  
ADC Integral Nonlinearity  
ADC Noise Histogram Port  
Voltage Readback in Fast Mode  
600  
Current Readback in Slow Mode  
Current Readback in Slow Mode  
300  
250  
200  
150  
100  
50  
1.0  
0.5  
V
– V = 110.4mV  
EE  
AGND – V  
= 48.3V  
SENSE  
OUT  
500  
400  
300  
200  
100  
0
0
–0.5  
–1.0  
0
6139  
260  
261  
262  
ADC OUTPUT  
6141  
6143  
6145  
6147  
263  
264  
265  
0
50 100 150 200 250 300 350 400 450 500  
ADC OUTPUT  
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)  
4274AC G17  
4274AC G19  
4274AC G18  
ADC Integral Nonlinearity  
Voltage Readback in Fast Mode  
ADC Noise Histogram Port  
ADC Integral Nonlinearity  
Voltage Readback in Slow Mode  
Voltage Readback in Slow Mode  
1.0  
0.5  
600  
500  
400  
300  
200  
100  
0
1.0  
0.5  
AGND – V  
= 48.3V  
OUT  
0
0
–0.5  
–1.0  
–0.5  
–1.0  
0
10  
20  
30  
40  
50  
60  
8532  
8533  
8534  
8535  
8536  
0
10  
20  
30  
40  
50  
60  
ADC OUTPUT  
PORT VOLTAGE (V)  
PORT VOLTAGE (V)  
4274AC G21  
4274AC G20  
4274AC G22  
INTandSDAOUTPull-DownVoltage  
vs Load Current  
MOSFET Gate Drive with Fast  
Pull-Down  
3
2.5  
2
GND  
V
V
= 3.3V  
DD  
EE  
= –54V  
PORT  
VOLTAGE  
20V/DIV  
V
V
EE  
EE  
FAST PULL-DOWN  
1.5  
1
GATE  
VOLTAGE  
10V/DIV  
CURRENT LIMIT  
50Ω  
FAULT  
APPLIED  
PORT  
0.5  
0
50Ω FAULT REMOVED  
CURRENT  
500mA/DIV  
0mA  
0
5
10  
LOAD CURRENT (mA)  
15 20 25 30 35 40  
100µs/DIV  
4274AC G23  
4274AC G24  
4274acfd  
9
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
TEST TIMING DIAGRAMS  
t
CLASSIFICATION  
DET  
FORCED-  
VOLTAGE  
FORCED-CURRENT  
0V  
t
ME  
V
t
PORT  
MEL  
V
OC  
V
MARK  
15.5V  
20.5V  
V
CLASS  
t
CLE  
t
CLE  
PD  
CONNECTED  
t
CLEON  
t
PON  
V
EE  
INT  
4274AC F01  
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes  
V
LIM  
0V  
V
CUT  
V
TO V  
EE  
SENSE  
t
, t  
START ICUT  
INT  
4274AC F02  
Figure 2. Current Limit Timing  
V
SENSE  
EE  
V
MIN  
TO V  
INT  
t
t
DIS  
MPS  
4274AC F03  
Figure 3. DC Disconnect Timing  
4274acfd  
10  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
TEST TIMING DIAGRAMS  
V
GATE  
t
MSD  
V
EE  
t
SHDN  
MSD or  
SHDN  
4274AC F04  
Figure 4. Shut Down Delay Timing  
t
t
r
3
t
t
f
4
SCL  
t
t
6
t
t
8
t
5
7
2
SDA  
t
1
4274AC F05  
Figure 5. I2C Interface Timing  
4274acfd  
11  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
I2C TIMING DIAGRAMS  
4274acfd  
12  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
I2C TIMING DIAGRAMS  
SCL  
SDA  
0
1
0
AD3 AD2 AD1 AD0 R/W  
FRAME 1  
ACK  
D7 D6 D5 D4 D3 D2 D1 D0  
ACK  
STOP BY  
MASTER  
START BY  
MASTER  
ACK BY  
SLAVE  
NO ACK BY  
MASTER  
FRAME 2  
DATA BYTE  
SERIAL BUS ADDRESS BYTE  
4274AC F08  
Figure 8. Reading the Interrupt Register (Short Form)  
SCL  
SDA  
0
0
0
1
1
0
0
R/W  
ACK  
0
1
0
AD3 AD2 AD1 AD0  
1
ACK  
STOP BY  
MASTER  
START BY  
MASTER  
ACK BY  
SLAVE  
NO ACK BY  
MASTER  
FRAME 1  
ALERT RESPONSE ADDRESS BYTE  
FRAME 2  
SERIAL BUS ADDRESS BYTE  
4274AC F09  
Figure 9. Reading from Alert Response Address  
4274acfd  
13  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
PIN FUNCTIONS  
RESET: Chip Reset, Active Low. When the RESET pin is  
low,theLTC4274A/LTC4274Cisheldinactivewiththeport  
off and all internal registers reset to their power-up states.  
When RESET is pulled high, the LTC4274A/LTC4274C  
begins normal operation. RESET can be connected to  
an external capacitor or RC network to provide a power  
turn-on delay. Internal filtering of the RESET pin prevents  
glitches less than 1µs wide from resetting the LTC4274A/  
AD3: Address Bit 3. Tie the address pins high or low to set  
2
the I C serial address to which the LTC4274A/LTC4274C  
responds. This address will be 010A A A A b. Internally  
3 2 1 0  
pulled up to V .  
DD  
AD2: Address Bit 2. See AD3.  
AD1: Address Bit 1. See AD3.  
AD0: Address Bit 0. See AD3.  
LTC4274C. Internally pulled up to V .  
DD  
NC, DNC: All pins identified with “NC” or “DNC” must be  
left unconnected.  
MID: Midspan Mode Input. When high, the LTC4274A/  
LTC4274C acts as a midspan device. Internally pulled  
down to DGND.  
DGND: Digital Ground. DGND is the return for the V  
DD  
supply.  
INT:InterruptOutput,OpenDrain.INTwillpulllowwhenany  
one of several events occur in the LTC4274A/LTC4274C.  
It will return to a high impedance state when bits 6 or 7  
are set in the Reset PB register (1Ah). The INT signal can  
be used to generate an interrupt to the host processor,  
eliminating the need for continuous software polling.  
Individual INT events can be disabled using the Int Mask  
register (01h). See the LTC4274A/LTC4274C Software  
Programming documentation for more information. The  
V :Logic Power Supply. Connectto a 3.3V power supply  
DD  
relative to DGND. V must be bypassed to DGND near  
DD  
the LTC4274A/LTC4274C with at least a 0.1µF capacitor.  
SHDN: Shutdown, Active Low. When pulled low, SHDN  
shuts down the port, regardless of the state of the internal  
registers. Pulling SHDN low is equivalent to setting the  
Reset Port bit in the Reset Pushbutton register (1Ah).  
Internal filtering of the SHDN pin prevents glitches less  
than 1µs wide from resetting the port. Internally pulled  
2
INT pin is only updated between I C transactions.  
up to V .  
DD  
SCL:SerialClockInput.Highimpedanceclockinputforthe  
2
I C serial interface bus. SCL must be tied high if not used.  
AGND: Analog Ground. AGND is the return for the V  
supply.  
EE  
SDAOUT: Serial Data Output, Open Drain Data Output for  
2
the I C Serial Interface Bus. The LTC4274A/LTC4274C  
SENSE: Current Sense Input. SENSE monitors the exter-  
uses two pins to implement the bidirectional SDA function  
nal MOSFET current via a 0.5Ω or 0.25Ω sense resistor  
2
to simplify optoisolation of the I C bus. To implement a  
between SENSE and V . Whenever the voltage across  
EE  
standard bidirectional SDA pin, tie SDAOUT and SDAIN  
together. SDAOUT should be grounded or left floating if  
not used. See the Applications Information section for  
more information.  
the sense resistor exceeds the overcurrent detection  
threshold V , the current limit fault timer counts up. If  
CUT  
the voltage across the sense resistor reaches the current  
limit threshold V , the GATE pin voltage is lowered to  
LIM  
maintain constant current in the external MOSFET. See  
SDAIN: Serial Data Input. High impedance data input for  
2
the Applications Information section for further details.  
the I C serial interface bus. The LTC4274A/LTC4274C  
uses two pins to implement the bidirectional SDA function  
2
to simplify optoisolation of the I C bus. To implement a  
standard bidirectional SDA pin, tie SDAOUT and SDAIN  
together. SDAIN must be tied high if not used. See the  
Applications Information section for more information.  
4274acfd  
14  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
PIN FUNCTIONS  
GATE: Gate Drive. GATE should be connected to the gate  
of the external MOSFET for the port. When the MOSFET  
is turned on, the gate voltage is driven to 12V (typ) above  
AUTO: AUTO Pin Mode Input. AUTO pin mode allows the  
LTC4274A/LTC4274C to detect and power up a PD even  
2
if there is no host controller present on the I C bus. The  
V . During a current limit condition, the voltage at GATE  
voltageoftheAUTOpindeterminesthestateoftheinternal  
registerswhentheLTC4274A/LTC4274Cisresetorcomes  
EE  
will be reduced to maintain constant current through the  
external MOSFET. If the fault timer expires, GATE is pulled  
out of V UVLO (see the LTC4274A/LTC4274C Software  
DD  
down, turning the MOSFET off and recording a t  
or  
Programmingdocumentation).Thestatesoftheseregister  
CUT  
2
t
event.  
bits can subsequently be changed via the I C interface.  
START  
The real-time state of the AUTO pin is read at bit 0 in the  
Pin Status register (11h). Internally pulled down to DGND.  
OUT: Output Voltage Monitor. OUT should be connected  
to the output port. A current limit foldback circuit limits  
the power dissipation in the external MOSFET by reduc-  
ing the current limit threshold when the drain-to-source  
voltage exceeds 10V. The Power Good bit is set when the  
Must be tied locally to either V or DGND.  
DD  
MSD: Maskable Shutdown Input. Active low. When pulled  
low, all ports that have their corresponding mask bit set  
in the Misc Config register (17h) will be reset, equivalent  
to pulling the SHDN pin low. Internal filtering of the MSD  
pin prevents glitches less than 1µs wide from resetting  
voltage from OUT to V drops below 2.4V (typ). A 500k  
EE  
resistor is connected internally from OUT to AGND when  
the port is idle.  
ports. Internally pulled up to V .  
DD  
V : Main Supply Input. Connect to a –45V to –57V  
EE  
supply, relative to AGND.  
OPERATION  
Overview  
++  
PoE Evolution  
+
Even during the process of creating the IEEE PoE 25.5W  
specification, it became clear that there was a significant  
and increasing need for more than 25.5W of delivered  
power. The LTC4274A family responds to this market by  
allowing a reliable means of providing up to 90W of deliv-  
Power over Ethernet, or PoE, is a standard protocol for  
sending DC power over copper Ethernet data wiring.  
The IEEE group that administers the 802.3 Ethernet data  
standards added PoE powering capability in 2003. This  
original PoE spec, known as 802.3af, allowed for 48V DC  
power at up to 13W. This initial spec was widely popular,  
but 13W was not adequate for some requirements. In  
2009, the IEEE released a new standard, known as 802.3at  
++  
++  
ered power to a LTPoE PD. The LTPoE specification  
providesreliabledetectionandclassificationextensionsto  
the existing IEEE PoE technique that are backward com-  
patible and interoperable with existing Type 1 and Type 2  
+
or PoE , increasing the voltage and current requirements  
++  
PDs. Unlike other proprietary PoE solutions, Linear’s  
to provide 25W of power.  
++  
LTPoE solution provides mutual identification between  
The IEEE standard also defines PoE terminology. A device  
that provides power to the network is known as a PSE, or  
powersourcingequipment,whileadevicethatdrawspower  
from the network is known as a PD, or powered device.  
PSEs come in two types: Endpoints (typically network  
switches or routers), which provide data and power; and  
Midspans, which provide power but pass through data.  
MidspansaretypicallyusedtoaddPoEcapabilitytoexisting  
non-PoE networks. PDs are typically IP phones, wireless  
access points, security cameras, and similar devices.  
++  
the PSE and PD. This ensures that the LTPoE PD knows  
it may use the requested power at start-up because it has  
++  
++  
++  
detected a LTPoE PSE. LTPoE PSEs can differentiate  
between a LTPoE PD and all other types of IEEE compli-  
++  
ant PDs allowing LTPoE PSEs to remain compliant and  
interoperable with existing equipment.  
4274acfd  
15  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
OPERATION  
LTC4274 Product Family  
TheC-gradeLTC4274isafullyautonomous802.3atType1  
PSE solution. Intended for use only in AUTO pin mode,  
the C-grade chipset autonomously supports detection,  
classification and powering of Type 1 PDs. As a Type 1  
PSE, 2-event classification is prohibited and Class 4 PDs  
are automatically treated as Class 0 PDs.  
The LTC4274 is a third-generation single PSE controller  
that implements four PSE ports in either an end-point  
or midspan design. Virtually all necessary circuitry is  
included to implement an IEEE 802.3at compliant PSE  
design, requiring only an external power MOSFET and  
sense resistor; these minimize power loss compared to  
alternative designs with an on-board MOSFET.  
PoE Basics  
Common Ethernet data connections consist of two or four  
twisted pairs of copper wire (commonly known as CAT-5  
cable), transformer-coupled at each end to avoid ground  
loops. PoE systems take advantage of this coupling ar-  
rangement by applying voltage between the center-taps  
of the data transformers to transmit power from the PSE  
to the PD without affecting data transmission. Figure 10  
shows a high-level PoE system schematic.  
The LTC4274 comes in three grades which support dif-  
ferent PD power levels.  
The A-grade LTC4274 extends PoE power delivery capa-  
++  
++  
bilities to LTPoE levels. LTPoE is a Linear Technology  
proprietary specification allowing for the delivery of up to  
++  
++  
90WtoLTPoE compliantPDs.TheLTPoE architecture  
extends the IEEE physical power negotiation to include  
38.7W, 52.7W, 70W and 90W power levels. The A-grade  
LTC4274 also incorporates all B- and C-grade features.  
To avoid damaging legacy data equipment that does not  
expect to see DC voltage, the PoE spec defines a protocol  
that determines when the PSE may apply and remove  
power. Valid PDs are required to have a specific 25k  
common-mode resistance at their input. When such a PD  
is connected to the cable, the PSE detects this signature  
resistance and turns on the power. When the PD is later  
disconnected, the PSE senses the open circuit and turns  
power off. The PSE also turns off power in the event of a  
current fault or short-circuit.  
The B-grade LTC4274 is a fully IEEE-compliant Type 2  
PSE supporting autonomous detection, classification  
and powering of Type 1 and Type 2 PDs. The B-grade  
LTC4274 also incorporates all C-grade features. The  
B-grade LTC4274 is marketed and numbered without the  
B suffix for legacy reasons; the absence of power grade  
suffix infers a B-grade part.  
CAT 5  
20Ω MAX  
ROUNDTRIP  
0.05µF MAX  
PSE  
PD  
RJ45  
4
RJ45  
4
5
5
GND  
SPARE PAIR  
1
1
AGND  
Tx  
Rx  
2
3
2
3
DATA PAIR  
DATA PAIR  
LTC4274AC  
GATE  
2
I C  
Rx  
Tx  
V
EE  
GND  
DC/DC  
6
6
PWRGD  
+
OUT  
CONVERTER  
V
LTC4265  
–54V –54V  
–54V  
7
8
7
–
IN  
OUT  
8
SPARE PAIR  
4274AC F10  
Figure 10. Power Over Ethernet System Diagram  
4274acfd  
16  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
OPERATION  
++  
Extended Power LTPoE  
When a PD is detected, the PSE optionally looks for a  
classification signature that tells the PSE the maximum  
power the PD will draw. The PSE can use this information  
to allocate power among several ports, police the current  
consumption of the PD, or to reject a PD that will draw  
more power that the PSE has available. For a 802.3af PSE,  
the classification step is optional; if a PSE chooses not to  
classify a PD, it must assume that the PD is a 13W (full  
802.3af power) device.  
TheLTC4274Aaddsthecapabilitytoautonomouslydeliver  
++  
up to 90W of power to the PD. LTPoE PDs may forego  
++  
802.3LLDPsupportandrelysolelyontheLTPoE Physi-  
++  
cal Classification to negotiate power with LTPoE PSEs;  
this greatly simplifies high-power PD implementations.  
++  
LTPoE classification may be optionally enabled for the  
LTC4274A by setting both the High Power Enable and  
++  
LTPoE Enable bits.  
New in 802.3at  
++  
The higher levels of LTPoE delivery impose additional  
layoutandcomponentselectionconstraints.TheLTC4274A  
is offered in four power levels (-1, -2, -3, and -4) which  
allows the AUTO pin mode LTC4274A to autonomously  
power up to supported power levels. If the AUTO pin is  
high, internal circuitry determines the maximum deliver-  
able power. PDsrequesting more than theavailablepower  
limits are not powered.  
Thenewer802.3atstandardsupersedes802.3afandbrings  
several new features:  
• A PD may draw as much as 25.5W. Such PDs (and the  
PSEs that support them) are known as Type 2. Older  
13W 802.3af equipment is classified as Type 1. Type 1  
PDs will work with all PSEs; Type 2 PDs may require  
Type2PSEstoworkproperly.TheLTC4274A/LTC4274C  
is designed to work in both Type 1 and Type 2 PSE de-  
signs, and also supports non-standard configurations  
at higher power levels.  
++  
Table 1. LTPoE Auto Pin Mode Maximum Delivered  
Power Capabilities  
PART  
PAIRS  
PD POWER  
38.7W  
52.7W  
70W  
LTC4274A-1  
LTC4274A-2  
LTC4274A-3  
LTC4274A-4  
4
4
4
4
• The Classification protocol is expanded to allow Type 2  
PSEs to detect Type 2 PDs, and to allow Type 2 PDs to  
determine if they are connected to a Type 2 PSE. Two  
versions of the new Classification protocol are avail-  
able: an expanded version of the 802.3af Class Pulse  
protocol, and an alternate method integrated with the  
existing LLDP protocol (using the Ethernet data path).  
The LTC4274A/LTC4274C fully supports the new Class  
Pulse protocol and is also compatible with the LLDP  
protocol(whichisimplementedinthedatacommunica-  
tions layer, not in the PoE circuitry).  
90W  
• Fault protection current levels and timing are adjusted  
to reduce peak power in the MOSFET during a fault;  
this allows the new 25.5W power levels to be reached  
using the same MOSFETs as older 13W designs.  
4274acfd  
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LTC4274A/LTC4274C  
APPLICATIONS INFORMATION  
Operating Modes  
disconnect detection is enabled. The host controller may  
also command the port to remove power at any time.  
TheLTC4274A/LTC4274Ccanoperateinoneoffourmodes:  
manual, semi-auto, AUTO pin, or shutdown.  
Reset and the AUTO/MID Pins  
Table 2. Operating Modes  
AUTOMATIC  
The initial LTC4274A/LTC4274C configuration depends on  
the state of the AUTO and MID pins during reset. Reset oc-  
curs at power-up, or whenever the RESET pin is pulled low  
or the global Reset All bit is set. Changing the state of AUTO  
or MID after power-up will not properly change the port  
behavior of the LTC4274A/LTC4274C until a reset occurs.  
AUTO  
PIN OPMD  
DETECT/  
CLASS  
I
/I  
CUT LIM  
MODE  
POWER-UP ASSIGNMENT  
AUTO Pin  
1
11b  
Enabled at Automatically  
Reset  
Yes  
Reserved  
Semi-auto  
0
0
11b  
10b  
N/A  
N/A  
N/A  
No  
Host  
Enabled  
Upon  
Request  
Although typically used with a host controller, the  
LTC4274A/LTC4274C can also be used in a standalone  
mode with no connection to the serial interface. If there is  
no host present, the AUTO pin must be tied high so that, at  
reset, the port will be configured to operate automatically.  
The port will detect and classify repeatedly until a PD is  
Manual  
0
0
01b Once Upon  
Request  
Upon  
Request  
No  
No  
Shutdown  
00b  
Disabled  
Disabled  
• Inmanualmode,theportwaitsforinstructionsfromthe  
host system before taking any action. It runs a single  
detection or classification cycle when commanded to  
by the host, and reports the result in its Port Status  
register. The host system can command the port to  
turn on or off the power at any time. This mode should  
only be used for diagnostic and test purposes.  
discovered, set I  
and I according to the classifica-  
CUT  
LIM  
tion results, apply power after successful detection, and  
remove power when a PD is disconnected.  
Table 3 shows the I  
and I  
values that will be auto-  
LIM  
CUT  
matically set in standalone (AUTO pin) mode, based on  
the discovered class.  
• In semi-auto mode, the port repeatedly attempts to  
detect and classify any PD attached to it. It reports the  
status of these attempts back to the host, and waits for  
a command from the host before turning on power to  
theport.Thehostmustenabledetection(andoptionally  
classification) for the port before detection will start.  
Table 3. ICUT and ILIM Values in AUTO Pin Mode  
CLASS  
I
I
LIM  
CUT  
Class 1  
112mA  
206mA  
375mA  
638mA  
425mA  
425mA  
425mA  
850mA  
Class 2  
Class 3 or Class 0  
Class 4  
• AUTO pin mode operates the same as semi-auto mode  
except that it will automatically turn on the power to the  
TheautomaticsettingoftheI andI valuesonlyoccurs  
CUT  
LIM  
port if detection is successful. In AUTO pin mode, I  
CUT  
if the LTC4274A/LTC4274C is reset with the AUTO pin high.  
and I values are set automatically by the LTC4274A/  
LIM  
Ifthestandaloneapplicationisamidspan, theMIDpinmust  
be tied high to enable correct midspan detection timing.  
LTC4274C. This operational mode is only valid if the  
AUTO pin is high at reset or power-up and remains high  
during operation.  
DETECTION  
• In shutdown mode, the port is disabled and will not  
detect or power a PD.  
Detection Overview  
Regardlessofwhichmodeitisin,theLTC4274A/LTC4274C  
will remove power automatically from a port which gener-  
ates a current limit fault. It will also automatically remove  
power from any port that generates a disconnect event if  
Toavoiddamagingnetworkdevicesthatwerenotdesigned  
to tolerate DC voltage, a PSE must determine whether  
the connected device is a real PD before applying power.  
The IEEE specification requires that a valid PD have a  
4274acfd  
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LTC4274A/LTC4274C  
APPLICATIONS INFORMATION  
measured and subtracted. Both methods must report  
valid resistances for the port to report a valid detection.  
PD signature resistances between 17k and 29k (typically)  
are detected as valid and reported as Detect Good in the  
corresponding Port Status register. Values outside this  
range,includingopenandshort-circuits,arealsoreported.  
Iftheportmeasureslessthan1Vatthefirstforced-current  
test, the detection cycle will abort and Short Circuit will  
be reported. Table 4 shows the possible detection results.  
common-mode resistance of 25k 5% at any port volt-  
age below 10V. The PSE must accept resistances that fall  
between 19k and 26.5k, and it must reject resistances  
above 33k or below 15k (shaded regions in Figure 11).  
The PSE may choose to accept or reject resistances in  
the undefined areas between the must-accept and must-  
reject ranges. In particular, the PSE must reject standard  
computer network ports, many of which have 150Ω  
common-mode termination resistors that will be dam-  
aged if power is applied to them (the black region at the  
left of Figure 11).  
Table 4. Detection Status  
MEASURED PD SIGNATURE  
Incomplete or Not Yet Tested  
<2.4k  
DETECTION RESULT  
Detect Status Unknown  
Short Circuit  
RESISTANCE 0Ω  
10k  
20k  
30k  
150Ω (NIC)  
23.75k  
26.25k  
26.5k  
PD  
Capacitance > 2.7µF  
C
Too High  
Too Low  
PD  
PSE  
15k 19k  
33k  
2.4k < R < 17k  
R
SIG  
4274AC F11  
PD  
17k < R < 29k  
Detect Good  
R Too High  
SIG  
PD  
Figure 11. IEEE 802.3af Signature Resistance Ranges  
>29k  
>50k  
Open Circuit  
4-Point Detection  
Voltage > 10V  
Port Voltage Outside Detect Range  
TheLTC4274A/LTC4274Cusesa4-pointdetectionmethod  
todiscoverPDs.False-positivedetectionsareminimizedby  
checkingforsignatureresistancewithbothforced-current  
and forced-voltage measurements. Initially, two test cur-  
rents are forced onto the port (via the OUT pin) and the  
resulting voltages are measured. The detection circuitry  
subtractsthetwoV-Ipointstodeterminetheresistiveslope  
while removing offset caused by series diodes or leakage  
at the port (see Figure 12). If the forced-current detection  
yields a valid signature resistance, two test voltages are  
then forced onto the port and the resulting currents are  
More On Operating Modes  
Theport’soperatingmodedetermineswhentheLTC4274A/  
LTC4274C runs a detection cycle. In manual mode, the  
port will idle until the host orders a detect cycle. It will  
then run detection, report the results, and return to idle  
to wait for another command.  
In semi-auto mode, the LTC4274A/LTC4274C autono-  
mously polls a port for PDs, but it will not apply power  
until commanded to do so by the host. The Port Status  
register is updated at the end of each detection cycle. If  
a valid signature resistance is detected and classification  
is enabled, the port will classify the PD and report that  
result as well. The port will then wait for at least 100ms (or  
2secondsifmidspanmodeisenabled), andwillrepeatthe  
detection cycle to ensure that the data in the Port Status  
register is up-to-date.  
275  
FIRST  
DETECTION  
POINT  
25kΩ SLOPE  
165  
SECOND  
DETECTION  
POINT  
If the port is in semi-auto mode and high power opera-  
tion is enabled, the port will not turn on in response to  
a power-on command unless the current detect result is  
Detect Good. Any other detect result will generate a t  
fault if a power-on command is received. If the port is not  
VALID PD  
0V-2V  
OFFSET  
VOLTAGE  
START  
4274AC F12  
Figure 12. PD Detection  
4274acfd  
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LTC4274A/LTC4274C  
APPLICATIONS INFORMATION  
in high power mode, it will ignore the detection result and  
apply power when commanded, maintaining backwards  
compatibility with the LTC4259A.  
60  
50  
40  
30  
20  
10  
0
PSE LOAD LINE  
48mA  
OVER  
CURRENT  
CLASS 4  
CLASS 3  
Behavior in AUTO pin mode is similar to semi-auto; how-  
ever,afterDetectGoodisreportedandtheportisclassified  
(if classification is enabled), it is automatically powered  
on without further intervention. In standalone (AUTO pin)  
33mA  
23mA  
CLASS 2  
TYPICAL  
CLASS 3  
PD LOAD  
LINE  
14.5mA  
6.5mA  
mode, the I  
and I thresholds are automatically set;  
CUT  
LIM  
CLASS 1  
CLASS 0  
see the Reset and the AUTO/MID Pin section for more  
information.  
0
5
10  
15  
20  
25  
VOLTAGE (V  
)
CLASS  
The signature detection circuitry is disabled when the port  
is initially powered up with the AUTO pin low, in shutdown  
mode, or when the corresponding Detect Enable bit is  
cleared.  
4274AC F13  
Figure 13. PD Classification  
the classification signature current (in this case, Class 3)  
in the V  
range. Table 5 shows the possible clas-  
CLASS  
sification values.  
Detection of Legacy PDs  
Proprietary PDs that predate the original IEEE 802.3af  
standard are commonly referred to today as legacy de-  
vices. One type of legacy PD uses a large common-mode  
capacitance (>10μF) as the detection signature. Note that  
PDs in this range of capacitance are defined as invalid, so  
a PSE that detects legacy PDs is technically noncompliant  
with the IEEE spec.  
Table 5. Classification Values  
CLASS  
Class 0  
Class 1  
Class 2  
Class 3  
Class 4  
RESULT  
No Class Signature Present; Treat Like Class 3  
3W  
7W  
13W  
25.5W (Type 2)  
TheLTC4274A/LTC4274Ccanbeconfiguredtodetectthis  
type of legacy PD. Legacy detection is disabled by default,  
but can be manually enabled. When enabled, the port will  
report Detect Good when it sees either a valid IEEE PD or  
ahigh-capacitancelegacyPD. Withlegacymodedisabled,  
only valid IEEE PDs will be recognized.  
If classification is enabled, the port will classify the PD  
immediatelyafterasuccessfuldetectioncycleinsemi-auto  
or AUTO pin modes, or when commanded to in manual  
mode. It measures the PD classification signature by ap-  
plying 18V for 12ms (both values typical) to the port via  
the OUT pin and measuring the resulting current; it then  
reports the discovered class in the Port Status register.  
If the LTC4274A/LTC4274C is in AUTO pin mode, it will  
CLASSIFICATION  
802.3af Classification  
additionally use the classification result to set the I  
CUT  
and I thresholds. See the Reset and the AUTO/MID Pin  
LIM  
A PD can optionally present a classification signature to  
the PSE to indicate the maximum power it will draw while  
operating. The IEEE specification defines this signature as  
aconstantcurrentdrawwhenthePSEportvoltageisinthe  
section for more information.  
The classification circuitry is disabled when the port is  
initially powered up with the AUTO pin low, in shutdown  
mode, or when the corresponding Class Enable bit is  
cleared.  
V
CLASS  
range(between15.5Vand20.5V), withthecurrent  
level indicating one of 5 possible PD classes. Figure 13  
shows a typical PD load line, starting with the slope of the  
25kΩ signature resistor below 10V, then transitioning to  
4274acfd  
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APPLICATIONS INFORMATION  
802.3at 2-Event Classification  
Class 0 to 3), the LTC4274A will not provide power and  
will restart the detection process. To aid in diagnosis, the  
Port Status register will always report the results of the  
lastclasspulse,so,forexample,aninvalidClass4–Class2  
combination would report a second class pulse was run  
in the High Power Status register (which implies that the  
first cycle found Class 4), and Class 2 in the Port Status  
register.  
The 802.3at specification defines two methods of clas-  
sifying a Type 2 PD. The LTC4274A supports 802.3at  
2-event classification. The LTC4274C does not support  
2-event classification.  
One method adds extra fields to the Ethernet LLDP data  
protocol;althoughtheLTC4274A/LTC4274Ciscompatible  
with this classification method, it cannot perform clas-  
sification directly since it doesn’t have access to the data  
path. LLDP classification requires the PSE to power the  
PD as a standard 802.3af (Type 1) device. It then waits  
for the host to perform LLDP communication with the PD  
and update the PSE port data. The LTC4274A/LTC4274C  
POWER CONTROL  
External MOSFET, Sense Resistor Summary  
The primary function of the LTC4274A/LTC4274C is to  
control the delivery of power to the PSE port. It does this  
by controlling the gate drive voltage of an external power  
MOSFET while monitoring the current via an external  
sense resistor and the output voltage at the OUT pin. This  
supports changing the I  
and I  
levels on the fly, al-  
LIM  
CUT  
lowing the host to complete LLDP classification.  
The second 802.3at classification method, known as  
2-event classification or ping-pong, is supported by the  
LTC4274A. A Type 2 PD that is requesting more than 13W  
will indicate Class 4 during normal 802.3af classification.  
If the LTC4274A sees Class 4, it forces the port to a speci-  
fied lower voltage (called the mark voltage, typically 9V),  
pauses briefly, and then re-runs classification to verify the  
Class 4 reading (Figure 1). It also sets a bit in the High  
Power Status register to indicate that it ran the second  
classification cycle. The second cycle alerts the PD that  
it is connected to a Type 2 PSE which can supply Type 2  
power levels.  
circuitry serves to couple the raw V input supply to the  
EE  
port in a controlled manner that satisfies the PD’s power  
needs while minimizing power dissipation in the MOSFET  
and disturbances on the V backplane.  
EE  
TheLTC4274A/LTC4274Cisdesignedtouse0.25Ωsense  
resistors to minimize power dissipation. It also supports  
0.5Ωsenseresistors,whicharethedefaultwhenLTC4258/  
LTC4259A compatibility is desired.  
Inrush Control  
Once the command has been given to turn on a port,  
the LTC4274A/LTC4274C ramps up the GATE pin of the  
port’s external MOSFET in a controlled manner. Under  
normal power-up circumstances, the MOSFET gate will  
rise until the port current reaches the inrush current limit  
level (typically 450mA), at which point the GATE pin will  
2-event ping-pong classification is enabled by setting a bit  
in the port’s High Power Mode register. Note that a ping-  
pongenabledportonlyrunsthesecondclassificationcycle  
when it detects a Class 4 device; if the first cycle returns  
Class 0 to 3, the port assumes it is connected to a Type 1  
PD and does not run the second classification cycle.  
be servoed to maintain the specified I  
current. Dur-  
INRUSH  
) runs. When output  
ing this inrush period, a timer (t  
START  
Invalid Type 2 Class Combinations  
chargingiscomplete,theportcurrentwillfallandtheGATE  
pin will be allowed to continue rising to fully enhance the  
The 802.3at specification defines a Type 2 PD class sig-  
nature as two consecutive Class 4 results; a Class 4 fol-  
lowed by a Class 0-3 is not a valid signature. In AUTO pin  
mode, the LTC4274A will power a detected PD regardless  
of the classification results, with one exception: if the PD  
presents an invalid Type 2 signature (Class 4 followed by  
MOSFET and minimize its on-resistance. The final V is  
GS  
nominally 12V. The inrush period is maintained until the  
t
timer expires. At this time if the inrush current limit  
START  
level is still exceeded the port will be turned back off and  
a t fault reported.  
START  
4274acfd  
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APPLICATIONS INFORMATION  
Current Limit  
TomaintainIEEEcompliance,I shouldbekeptat425mA  
LIM  
for all Type 1 PDs, and 850mA if a Type 2 PD is detected.  
The LTC4274A/LTC4274C port includes two current limit-  
I
is automatically reset to 425mA when a port turns off.  
LIM  
Table 6. Example Current Limit Settings  
INTERNAL REGISTER SETTING (hex)  
= 0.5Ω = 0.25Ω  
ing thresholds (I  
and I ), each with a corresponding  
CUT  
LIM  
timer (t  
and t ). Setting the I  
and I thresholds  
CUT LIM  
CUT  
LIM  
depends on several factors: the class of the PD, the volt-  
age of the main supply (V ), the type of PSE (Type 1 or  
EE  
I
(mA)  
R
SENSE  
R
SENSE  
LIM  
Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of  
the MOSFET, and whether or not the system is required  
to implement class enforcement.  
53  
88  
106  
159  
213  
266  
319  
372  
08  
89  
80  
8A  
09  
8B  
88  
08  
89  
Per the IEEE specification, the LTC4274A/LTC4274C will  
allow the port current to exceed I  
for a limited period  
CUT  
of time before removing power from the port, whereas it  
willactivelycontroltheMOSFETgatedrivetokeeptheport  
current below I . The port does not take any action to  
LIM  
425  
478  
00  
8E  
92  
CB  
10  
D2  
40  
4A  
50  
5A  
60  
52  
80  
limit the current when only the I threshold is exceeded,  
CUT  
but does start the t  
timer. If the current drops below  
CUT  
531  
8A  
the I  
current threshold before its timer expires, the  
CUT  
584  
t
timer counts back down, but at 1/16 the rate that it  
CUT  
638  
90  
9A  
C0  
CA  
D0  
DA  
E0  
49  
40  
4A  
50  
5A  
60  
52  
counts up. If the t  
timer reaches 60ms (typical) the  
CUT  
744  
port is turned off and the port t  
fault is set. This allows  
CUT  
850  
the current limit circuitry to tolerate intermittent overload  
signalswithdutycyclesbelowabout6%;longerdutycycle  
overloads will turn the port off.  
956  
1063  
1169  
1275  
1488  
1700  
1913  
2125  
2338  
2550  
2975  
The I  
current limiting circuit is always enabled and  
LIM  
actively limiting port current. The t  
timer is enabled  
LIM  
only when the programmable t  
allows t to be set to a shorter value than t  
field is non-zero. This  
LIM  
to provide  
LIM  
CUT  
more aggressive MOSFET protection and turn off a port  
before MOSFET damage can occur. The t timer starts  
LIM  
when the I threshold is exceeded. When the t timer  
LIM  
LIM  
reaches1.7ms(typ)timestheprogrammablet fieldthe  
LIM  
port is turned off and the port t  
LIM  
timer, which counts up during both I and I  
fault is set. When the  
LIM  
t
field is zero, t  
behaviors are tracked by the t  
LIM CUT  
I
Foldback  
LIM  
events.  
LIM  
CUT  
The LTC4274A/LTC4274C features a two-stage foldback  
circuit that reduces the port current if the port voltage falls  
below the normal operating voltage. This keeps MOSFET  
power dissipation at safe levels for typical 802.3af MOS-  
FETs, even at extended 802.3at power levels. Current limit  
and foldback behavior are programmable. Table 6 gives  
I
is typically set to a lower value than I to allow the  
LIM  
CUT  
port to tolerate minor faults without current limiting.  
Per the IEEE specification, the LTC4274A/LTC4274C will  
automatically set I to 425mA (shown in bold in Table 6)  
LIM  
during inrush at port turn-on, and then switch to the  
programmed I  
setting once inrush has completed.  
LIM  
examples of recommended I register settings.  
LIM  
4274acfd  
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APPLICATIONS INFORMATION  
The LTC4274A/LTC4274C will support current levels well  
beyond the maximum values in the 802.3at specification.  
The shaded areas in Table 6 indicate settings that may  
require a larger external MOSFET, additional heat sinking,  
Disconnect  
The LTC4274A/LTC4274C monitors the port to make  
sure that the PD continues to draw the minimum speci-  
fied current. A disconnect timer counts up whenever port  
current is below 7.5mA (typ), indicating that the PD has  
or enabling t  
.
LIM  
been disconnected. If the t timer expires, the port will  
DIS  
MOSFET Fault Detection  
be turned off and the disconnect bit in the fault event reg-  
The LTC4274A/LTC4274C PSE port is designed to toler-  
ate significant levels of abuse, but in extreme cases it is  
possible for the external MOSFET to be damaged. A failed  
MOSFET may short source to drain, which will make the  
port appear to be on when it should be off; this condition  
may also cause the sense resistor to fuse open, turning  
off the port but causing the LTC4274A/LTC4274C SENSE  
pin to rise to an abnormally high voltage. A failed MOSFET  
may also short from gate to drain, causing the LTC4274A/  
LTC4274C GATE pin to rise to an abnormally high voltage.  
The LTC4274A/LTC4274C OUT, SENSE and GATE pins  
are designed to tolerate up to 80V faults without damage.  
ister will be set. If the current returns before the t timer  
DIS  
runs out, the timer resets and will start counting from the  
beginning if the undercurrent condition returns. As long  
as the PD exceeds the minimum current level more often  
than t , it will stay powered.  
DIS  
Although not recommended, the DC disconnect feature  
can be disabled by clearing the DC Disconnect Enable  
bit. Note that this defeats the protection mechanisms  
built into the IEEE spec, since a powered port will stay  
powered after the PD is removed. If the still-powered port  
is subsequently connected to a non-PoE data device, the  
device may be damaged.  
If the LTC4274A/LTC4274C sees any of these conditions  
for more than 180μs, it disables all port functionality,  
reduces the gate drive pull-down current for the port and  
reports a FET Bad fault. This is typically a permanent fault,  
but the host can attempt to recover by resetting the port,  
or by resetting the entire chip if a port reset fails to clear  
the fault. If the MOSFET is in fact bad, the fault will quickly  
return, and the port will disable itself again.  
The LTC4274A/LTC4274C does not include AC discon-  
nect circuitry, but includes an AC Disconnect Enable bit  
to maintain compatibility with the LTC4259A. If the AC  
Disconnect Enable bit is set, DC disconnect will be used.  
Shutdown Pin  
The LTC4274A/LTC4274C includes a hardware SHDN pin.  
When the SHDN pin is pulled to DGND, the port will be  
shut off immediately. The port remains shut down until  
AnopenormissingMOSFETwillnottriggeraFETBadfault,  
but will cause a t  
fault if the LTC4274A/LTC4274C  
2
START  
re-enabled via I C or a device reset in AUTO pin mode.  
attempts to turn on the port.  
Masked Shutdown  
Voltage and Current Readback  
The LTC4274A/LTC4274C provides a low latency port  
shedding feature to quickly reduce the system load when  
required. By allowing a pre-determined set of ports to  
be turned off, the current on an overloaded main power  
supply can be reduced rapidly while keeping high priority  
devices powered. Each port can be configured to high or  
low priority; all low-priority ports will shut down within  
6.5μs after the MSD pin is pulled low. If a port is turned off  
via MSD, the corresponding Detection and Classification  
Enable bits are cleared, so the port will remain off until  
the host explicitly re-enables detection.  
The LTC4274A/LTC4274C measures the output voltage  
and current at the port with an internal A/D converter.  
Port data is only valid when the port power is on. The  
converter has two modes:  
• Slow mode: 14 samples per second, 14.5 bits resolution  
• Fast mode: 440 samples per second, 9.5 bits resolution  
In fast mode, the least significant 5 bits of the lower byte  
are zeroes so that bit scaling is the same in both modes.  
4274acfd  
23  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
APPLICATIONS INFORMATION  
SERIAL DIGITAL INTERFACE  
EXTERNAL COMPONENT SELECTION  
Overview  
Power Supplies and Bypassing  
TheLTC4274A/LTC4274Ccommunicateswiththehostus-  
The LTC4274A/LTC4274C requires two supply voltages to  
2
ingastandardSMBus/I C2-wireinterface.TheLTC4274A/  
operate. V requires 3.3V (nominally) relative to DGND.  
DD  
LTC4274C is a slave-only device, and communicates  
with the host master using the standard SMBus proto-  
cols. Interrupts are signaled to the host via the INT pin.  
The timing diagrams (Figures 5 through 9) show typical  
communicationwaveformsandtheirtimingrelationships.  
More information about the SMBus data protocols can be  
found at www.smbus.org.  
V requires a negative voltage of between –45V and –57V  
EE  
for Type 1 PSEs, –51V to –57V for Type 2 PSEs or –54.75V  
++  
to –57V for LTPoE PSEs, relative to AGND. The relation-  
ship between the two grounds is not fixed; AGND can be  
referenced to any level from V to DGND, although it  
DD  
should typically be tied to either V or DGND.  
DD  
V
provides power for most of the internal LTC4274A/  
DD  
The LTC4274A/LTC4274C requires both the V and V  
LTC4274C circuitry, and draws a maximum of 3mA. A  
DD  
EE  
supplyrailstobepresentfortheserialinterfacetofunction.  
ceramic decoupling cap of at least 0.1μF should be placed  
fromV toDGND,ascloseaspracticaltoeachLTC4274A/  
DD  
Bus Addressing  
LTC4274C chip.  
The LTC4274A/LTC4274C’s primary serial bus address  
is 010xxxxb, with the lower four bits set by the AD3-AD0  
pins; this allows up to 16 LTC4274A/LTC4274Cs on a  
single bus. All LTC4274A/LTC4274Cs also respond to  
the address 0110000b, allowing the host to write the  
same command (typically configuration commands) to  
multiple LTC4274A/LTC4274Cs in a single transaction. If  
the LTC4274A/LTC4274C is asserting the INT pin, it will  
also respond to the alert response address (0001100b)  
per the SMBus spec.  
Figure 14 shows a three component low dropout regula-  
tor for a negative supply to DGND generated from the  
negative V supply. V is tied to AGND and DGND is  
EE  
DD  
negativereferencedtoAGND.Thisregulatordrivesasingle  
LTC4274A/LTC4274C device. In Figure 15, DGND is tied  
to AGND in this boost converter circuit for a positive V  
DD  
supply of 3.3V above AGND. This circuit candrive multiple  
LTC4274A/LTC4274C devices and opto couplers.  
V
EE  
is the main supply that provides power to the PD.  
Because it supplies a relatively large amount of power and  
issubjecttosignificantcurrenttransients,itrequiresmore  
design care than a simple logic supply. For minimum IR  
Interrupts and SMBALERT  
MostLTC4274A/LTC4274Cporteventscanbeconfigured  
to trigger an interrupt, asserting the INT pin and alerting  
the host to the event. This removes the need for the host  
to poll the LTC4274A/LTC4274C, minimizing serial bus  
trafficandconservinghostCPUcycles.MultipleLTC4274A/  
LTC4274Cs can share a common INT line, with the host  
using the SMBALERT protocol (ARA) to determine which  
LTC4274A/LTC4274C caused an interrupt.  
loss and best system efficiency, set V near maximum  
EE  
amplitude (57V), leaving enough margin to account for  
transient over- or undershoot, temperature drift, and the  
line regulation specs of the particular power supply used.  
10Ω  
AGND  
V
DD  
1µF  
100V  
CMHZ4687-4.3V  
0.1µF  
LTC4274AC  
DGND  
Register Description  
CMPTA92  
SMAJ58A  
For information on serial bus usage and device configura-  
tionandstatus,refertotheLTC4274A/LTC4274CSoftware  
Programming documentation.  
V
EE  
4274AC F14  
750k  
V
EE  
Figure 14. Negative LDO to DGND  
4274acfd  
24  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
APPLICATIONS INFORMATION  
L3  
100µH  
L4  
10µH  
D28  
B1100  
SUMIDA CDRH5D28-101NC  
SUMIDA CDRH4D28-100NC  
3.3V AT 400mA  
C74  
100µF  
6.3V  
C73  
10µF  
6.3V  
C75  
R51  
4.7k  
1%  
R53  
10µF  
R52  
3.32k  
1%  
4.7k  
16V  
1%  
C76  
10µF  
100V  
C78  
0.22µF  
100V  
+
5
Q13  
Q14  
FMMT723  
C77  
0.22µF  
100V  
V
FMMT723  
CC  
1
3
6
Q15  
ITH/RUN  
NGATE  
SENSE  
FDC2512  
R58  
10Ω  
LTC3803  
R54  
56k  
4
R55  
806Ω  
1%  
R56  
47.5k  
1%  
V
FB  
R57  
1k  
R59  
0.100Ω  
1%, 1W  
C79  
2200pF  
GND  
2
R60  
10Ω  
V
EE  
4274AC F15  
Figure 15. Positive VDD Boost Converter  
Bypass capacitance between AGND and V is very impor-  
If the device is part of a larger system, contains additional  
external non-Ethernet ports, or must be referenced to  
protective ground for some other reason, the Power over  
Ethernetsubsystem(includingallLTC4274A/LTC4274Cs)  
must be electrically isolated from the rest of the system.  
Figure 16 shows a typical isolated serial interface. The  
SDAOUT pin of the LTC4274A/LTC4274C is designed to  
EE  
tant for reliable operation. If a short-circuit occurs at the  
output port it can take as long as 1μs for the LTC4274A/  
LTC4274C to begin regulating the current. During this  
time the current is limited only by the small impedances  
in the circuit and a high current spike typically occurs,  
causing a voltage transient on the V supply and possibly  
EE  
2
causing the LTC4274A/LTC4274C to reset due to a UVLO  
drive the inputs of an opto-coupler directly. Standard I C/  
fault. A 1μF, 100V X7R capacitor placed near the V pin  
SMBusdevicestypicallycannotdriveopto-couplers,soU1  
is used to buffer the signals from the host controller side.  
EE  
is recommended to minimize spurious resets.  
Isolating the Serial Bus  
External MOSFET  
TheLTC4274A/LTC4274CincludesasplitSDApin(SDAINand  
SDAOUT) to ease opto-isolation of the bidirectional SDA line.  
CarefulselectionofthepowerMOSFETiscriticaltosystemreli-  
ability.LTCrecommendseitherFairchildIRFM120A,FDT3612,  
FDMC3612orPhilipsPHT6NQ10Tfortheirprovenreliabilityin  
Type1andType2PSEapplications.Non-standardapplications  
thatprovidemorecurrentthanthe850mAIEEEmaximummay  
requireheatsinkingandotherMOSFETdesignconsiderations.  
Contact LTC Applications before using a MOSFET other than  
one of these recommended parts.  
IEEE 802.3 Ethernet specifications require that network  
segments (including PoE circuitry) be electrically isolated  
from the chassis ground of each network interface de-  
vice. However, network segments are not required to be  
isolated from each other, provided that the segments are  
connected to devices residing within a single building on  
a single power distribution system.  
Sense Resistor  
For simple devices such as small PoE switches, the isola-  
tion requirement can be met by using an isolated main  
power supply for the entire device. This strategy can be  
used if the device has no electrically conducting ports  
other than twisted-pair Ethernet. In this case, the SDAIN  
and SDAOUT pins can be tied together and will act as a  
The LTC4274A/LTC4274C is designed to use either  
0.5Ω or 0.25Ω current sense resistors. For new designs  
0.25Ω is recommended to reduce power dissipation; the  
0.5Ω option is intended for existing systems where the  
LTC4274A/LTC4274Cisusedasadrop-inreplacementfor  
theLTC4258orLTC4259A.Thelowersenseresistorvalues  
reduceheatdissipation.Fourcommonlyavailable1Ωresis-  
tors (0402 or larger package size) can be used in parallel  
4274acfd  
2
standard I C/SMBus SDA pin.  
25  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
APPLICATIONS INFORMATION  
0.1µF  
2k  
2k  
U2  
200Ω  
V
DD  
CPU  
SCL  
U1  
10Ω  
LTC4274AC  
V
INT  
SCL  
DD  
200Ω  
SDAIN  
SDAOUT  
AD0  
AD1  
AD2  
2
I C  
SDA  
ADDRESS  
0100001  
HCPL-063L  
0.1µF  
TO  
SMAJ5.0A  
AD3  
CONTROLLER  
U3  
DGND  
AGND  
200Ω  
200Ω  
10Ω  
V
EE  
1µF  
100V  
4274AC F16  
SMAJ58A  
SMBALERT  
0.1µF  
GND CPU  
HCPL-063L  
U1: FAIRCHILD NC7WZ17  
U2, U3: AGILENT HCPL-063L  
ISOLATED  
3.3V  
+
10µF  
ISOLATED  
GND  
+
TVS  
C
BULK  
BULK  
ISOLATED  
–54V  
Figure 16. Opto-Isolating the I2C Bus  
4274acfd  
26  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
APPLICATIONS INFORMATION  
in place of a single 0.25Ω resistor. In order to meet the  
supply positive rail to the LTC4274A/LTC4274C V pin.  
DD  
I
and I accuracy required by the IEEE specification,  
AcrosstheLTC4274A/LTC4274CV pinandDGNDpinare  
CUT  
LIM  
DD  
the sense resistors should have 1% tolerance or better,  
an SMAJ5.0A, 5.0V TVS (D2) and a 0.1μF capacitor (C2).  
These components must be placed close to the LTC4274A/  
LTC4274Cpins.DGNDistieddirectlytotheprotected AGND  
pin.Pull-upsatthelogicpinsshouldbetotheprotectedside  
and no more than 200ppm/°C temperature coefficient.  
Port Output Cap  
The port requires a 0.22μF cap across its output to keep  
the LTC4274A/LTC4274C stable while in current limit  
during startup or overload. Common ceramic capacitors  
often have significant voltage coefficients; this means the  
capacitance is reduced as the applied voltage increases.  
To minimize this problem, X7R ceramic capacitors rated  
for at least 100V are recommended.  
of the 10Ω resistors at the V pin. Pull-downs at the logic  
DD  
pins should be to the protected side of the 10Ω resistors  
at the tied AGND and DGND pins.  
Finally, each port requires a pair of S1B clamp diodes, one  
from OUTn to supply AGND (D3) and one from OUTn to  
supply V (D4). The diodes at the ports steer harmful  
EE  
surges into the supply rails where they are absorbed by  
the surge suppressors and the V bypass capacitance.  
Surge Protection  
EE  
The layout of these paths must be low impedance.  
Ethernet ports can be subject to significant cable surge  
events.TokeepPoEvoltagesbelowasafelevelandprotect  
the application against damage, protection components,  
as shown in Figure 17, are required at the main supply, at  
the LTC4274A/LTC4274C pins, and at each port.  
FurtherconsiderationsincludeLTC4274A/LTC4274Cappli-  
cationswithoff-boardconnections,suchasadaughtercard  
to a mother board or headers to an external supply or host  
control board. Additional protection may be required at the  
LTC4274A/LTC4274C pins to these off-board connections.  
Bulk transient voltage suppression (TVS  
) and bulk ca-  
BULK  
pacitance (C  
) are required across the main PoE supply  
BULK  
LAYOUT GUIDELINES  
and should be sized to accommodate system level surge  
requirements. A large capacitance of 10μF or greater (C3)  
Strict adherence to board layout,parts placement and routing  
guidelinesiscriticalforoptimalcurrentreadingaccuracy,IEEE  
compliance, system robustness, and thermal dissipation.  
is required across the +3.3V supply if V is above AGND.  
DD  
Each LTC4274A/LTC4274C requires a 10Ω, 0805 resistor  
(R1)inseriesfromsupplyAGNDtotheLTC4274A/LTC4274C  
AGNDpin. AcrosstheLTC4274A/LTC4274CAGNDpinand  
Power delivery above 25.5W imposes additional compo-  
nent and layout restraints. Specifically MOSFET, sense  
resistor and transformer selection is crucial to safe and  
reliable system operation.  
V
pin are an SMAJ58A, 58V TVS (D1) and a 1μF, 100V  
EE  
bypass capacitor (C1). These components must be placed  
close to the LTC4274A/LTC4274C pins.  
Contact LTC Applications to obtain a full set of layout  
guidelines, example layouts and BOMs.  
IftheV supplyisaboveAGND,eachLTC4274A/LTC4274C  
DD  
requires a 10Ω, 0805 resistor (R2) in series from the +3.3V  
R2  
10Ω  
V
+3.3V  
DD  
C2  
0.1µF  
D2  
AUTO  
SCL  
SMAJ5.0A  
+
+
SDAIN  
DGND  
AGND  
LTC4274AC  
C3  
R1  
10µF  
10Ω  
V
SENSE GATE OUT  
EE  
TVS  
C
BULK  
D1  
OUT  
0.22μF  
D3  
1µF  
C
100V  
S1B  
X7R  
100V  
X7R  
BULK  
SMAJ58A  
R
S
OUTn  
–54V  
Q1  
D4 S1B  
4274AC F17  
Figure 17. LTC4274 Surge Protection  
4274acfd  
27  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
PACKAGE DESCRIPTION  
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.  
UHF Package  
38-Lead Plastic QFN (5mm × 7mm)  
(Reference LTC DWG # 05-08-1701 Rev C)  
0.70 ± 0.05  
5.50 ± 0.05  
5.15 0.05  
4.10 ± 0.05  
3.15 0.05  
3.00 REF  
PACKAGE  
OUTLINE  
0.25 ± 0.05  
0.50 BSC  
5.5 REF  
6.10 ± 0.05  
7.50 ± 0.05  
RECOMMENDED SOLDER PAD LAYOUT  
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED  
PIN 1 NOTCH  
R = 0.30 TYP OR  
0.35 × 45° CHAMFER  
0.75 ± 0.05  
3.00 REF  
5.00 ± 0.10  
37  
38  
0.00 – 0.05  
0.40 ±0.10  
PIN 1  
TOP MARK  
1
2
(SEE NOTE 6)  
5.15 0.10  
5.50 REF  
7.00 ± 0.10  
3.15 0.10  
(UH) QFN REF C 1107  
0.200 REF 0.25 ± 0.05  
R = 0.125  
TYP  
R = 0.10  
TYP  
0.50 BSC  
BOTTOM VIEW—EXPOSED PAD  
NOTE:  
1. DRAWING CONFORMS TO JEDEC PACKAGE  
OUTLINE M0-220 VARIATION WHKD  
2. DRAWING NOT TO SCALE  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE  
5. EXPOSED PAD SHALL BE SOLDER PLATED  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION  
ON THE TOP AND BOTTOM OF PACKAGE  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
4274acfd  
28  
For more information www.linear.com/LTC4274A  
LTC4274A/LTC4274C  
REVISION HISTORY  
REV  
DATE  
DESCRIPTION  
PAGE NUMBER  
A
9/11  
Changed GATE typ voltage to 12V.  
3, 15, 21  
Revised V text under Digital Interface.  
4
ILD  
Table 4 reference and caption changed to Table 5.  
20  
Revised power supply voltage figures under Power Supplies and Bypassing.  
24  
Text CUT/LIM changed to I /I in the Related Parts section.  
30  
CUT LIM  
Specified SMAJ58A for Zener diode.  
30  
++  
B
1/12  
Changed LTPoE power levels from 35W, 45W to 38.7W, 52.7W respectively.  
1, 2, 16, 17  
2
Revised Max value for V I C Input Low Voltage.  
4
ILD  
Clarified AUTO Pin mode relationship to Reset pin.  
18  
C
D
8/12  
7/15  
Table 1: Changed twisted pair requirement from 2-pair to 4-pair for 38.7W and 52.7W  
17  
Updated surge protection recommendations  
1, 24, 26, 27, 30  
Simplified Power over Ethernet system diagram  
16  
25  
Added component value (Figure 15)  
4274acfd  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-  
tion that the interconnection of itscircuits as described h einwill not infringe on existing patent rights.  
er
29  
LTC4274A/LTC4274C  
TYPICAL APPLICATION  
One Complete 100base-t Isolated Powered Ethernet IEEE 802.3at Port  
ISOLATED  
3.3V  
10Ω  
+
10µF  
0.1µF  
0.1µF  
SMAJ5.0A  
2k  
V
DD  
DGND  
SCL  
U2  
SDAIN  
SDAOUT  
INT  
200Ω  
200Ω  
V
CPU  
LTC4274AC  
DD  
U1  
10Ω  
AGND  
SCL  
FB1  
FB2  
V
SENSE GATE OUT  
EE  
2k  
0.22µF  
100V  
X7R  
TVS  
1µF  
BULK  
S1B  
+
100V  
X7R  
C
BULK  
R
SENSE  
0.25Ω  
SMAJ58A  
SDA  
Q1  
HCPL-063L  
ISOLATED  
–54V  
S1B  
U3  
RJ45  
CONNECTOR  
200Ω  
200Ω  
T1  
1
2
•
•
•
•
0.01µF  
200V  
0.01µF  
200V  
3
4
5
6
7
8
75Ω  
75Ω  
INTERRUPT  
PHY  
0.1µF  
GND CPU  
(NETWORK  
PHYSICAL  
LAYER  
HCPL-063L  
CHIP)  
•
•
•
•
0.01µF  
200V  
0.01µF  
200V  
75Ω  
75Ω  
Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T  
U1: FAIRCHILD NC7WZ17  
U2, U3: AGILENT HCPL-063L  
FB1, FB2: TDK MPZ2012S601A  
T1: PULSE H6096NL OR COILCRAFT ETH1-230LD  
4274AC TA02  
1000pF  
2000V  
RELATED PARTS  
PART NUMBER  
LTC4270/LTC4271  
LTC4266  
DESCRIPTION  
COMMENTS  
Transformer Isolation, Supports Type 1, Type 2 and LTPoE PDs  
2-Event Classification, Programmable I /I  
+
++  
++  
12-Port PoE/PoE /LTPoE PSE Controller  
Quad IEEE 802.3at PoE PSE Controller  
Quad IEEE 802.3at PoE PSE Controller  
Single IEEE 802.3at PoE PSE Controller  
IEEE 802.3at PD Interface Controller  
CUT LIM  
LTC4266A/LTC4266C  
LTC4274  
13W through 90W Support  
2-Event Classification, Programmable I /I  
CUT LIM  
LTC4265  
100V, 1A Internal Switch, 2-Event Classification Recognition  
LTC4267  
IEEE 802.3af PD Interface with Integrated Switching  
Regulator  
Internal 100V, 400mA Switch, Dual Inrush Current,  
Programmable Class  
LTC4269-1  
LTC4269-2  
LTC4278  
IEEE 802.3at PD Interface with Integrated Flyback  
Switching Regulator  
2-Event Classification, Programmable Classification, Synchronous  
No-Opto Flyback Controller, 50kHz to 250kHz, Auxiliary Support  
IEEE 802.3at PD Interface with Integrated Forward  
Switching Regulator  
2-Event Classification, Programmable Classification, Synchronous  
Forward Controller, 100kHz to 500kHz, Auxiliary Support  
IEEE 802.3at PD Interface with Integrated Flyback  
Switching Regulator  
2-Event Classification, Programmable Classification, Synchronous  
No-Opto Flyback Controller, 50kHz to 250kHz, 12V Auxiliary Support  
4274acfd  
LT 0715 REV D • PRINTED IN USA  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
30  
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC4274A  
●
●
LINEAR TECHNOLOGY CORPORATION 2011  

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