LTC6403CUD-1#PBF [Linear]
LTC6403-1 - 200MHz, Low Noise, Low Power Fully Differential Input/Output Amplifier/Driver; Package: QFN; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LTC6403CUD-1#PBF |
| 厂家： | 
Linear |
| 描述： | LTC6403-1 - 200MHz, Low Noise, Low Power Fully Differential Input/Output Amplifier/Driver; Package: QFN; Pins: 16; Temperature Range: 0°C to 70°C 放大器 |
| 文件： | 总22页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6403-1
200MHz, Low Noise,
Low Power Fully Differential
Input/Output Amplifier/Driver
FEATURES
DESCRIPTION
The LTC®6403-1 is a precision, very low noise, low dis-
tortion, fully differential input/output amplifier optimized
for 3V to 5V, single supply operation. The LTC6403-1 is
unity gain stable. The LTC6403-1 closed-loop bandwidth
extends from DC to 200MHz. In addition to the normal
unfilteredoutputs(+OUTand–OUT), theLTC6403-1hasa
built-in44.2MHzdifferentialsingle-polelowpassfilterand
an additional pair of filtered outputs (+OUTF, and –OUTF).
An input referred voltage noise of 2.8nV/√Hz enables the
LTC6403-1 to drive state-of-the-art 14- to 18-bit ADCs
whileoperatingonthesamesupplyvoltage,savingsystem
costandpower.TheLTC6403-1maintainsitsperformance
for supplies as low as 2.7V. It draws only 10.8mA, and
has a hardware shutdown feature which reduces current
consumption to 170µA.
n
Very Low Distortion: (2V , 3MHz): –95dBc
P-P
n
Fully Differential Input and Output
n
Low Noise: 2.8nV/√Hz Input-Referred
n
200MHz Gain-Bandwidth Product
n
Built-In Clamp: Fast Overdrive Recovery
n
Slew Rate: 200V/µs
n
Adjustable Output Common Mode Voltage
n
Rail-to-Rail Output Swing
n
Input Range Extends to Ground
n
Large Output Current: 60mA (Typ)
n
DC Voltage Offset <1.5mV (Max)
n
10.8mA Supply Current
n
2.7V to 5.25V Supply Voltage Range
n
Low Power Shutdown
n
Tiny 3mm × 3mm × 0.75mm 16-Pin QFN Package
The LTC6403-1 is available in a compact 3mm × 3mm
16-pin leadless QFN package and operates over a –40°C
to 125°C temperature range.
APPLICATIONS
n
Differential Input A/D Converter Driver
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog
n
Single-Ended to Differential Conversion/Amplification
Devices, Inc. All other trademarks are the property of their respective owners.
n
Common Mode Level Translation
n
Low Voltage, Low Noise, Signal Processing
TYPICAL APPLICATION
Single-Ended Input to Differential Output
Harmonic Distortion vs Frequency
With Common Mode Level Shifting
–30
SINGLE-ENDED INPUT
2V
P-P
V
V
R
R
V
= 3V
OCM
S
–40
–50
= V = 1.5V
0V
ICM
= R = 402Ω
F
I
V
S
= 800Ω
50Ω
392Ω
402Ω
0.1µF
LOAD
–60
= 2V
OUTDIFF P-P
3V
–70
54.9Ω
SECOND
–80
SIGNAL
1V
P-P
THIRD
GENERATOR
–90
1.5V
1.5V
+
V
OCM
–100
–110
–120
LTC6403-1
0.01µF
422Ω
–
1V
P-P
1
10
FREQUENCY (MHz)
100
64031 TA01
64031 TA01b
402Ω
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For more information www.linear.com/LTC6403-1
LTC6403-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
+
–
Total Supply Voltage (V to V )................................5.5V
Input Voltage
+
–
16 15 14 13
(+IN, –IN, V
Input Current
(+IN, –IN, V
, SHDN) (Note 2)................... V to V
OCM
–
+
+
–
SHDN
1
2
3
4
12
11
10
9
V
V
V
V
+
V
, SHDN) (Note 2)..................... 10mA
17
OCM
–
V
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4)
V
OCM
5
6
7
8
LTC6403C-1/LTC6403I-1......................–40°C to 85°C
LTC6403H-1....................................... –40°C to 125°C
Specified Temperature Range (Note 5)
LTC6403C-1/LTC6403I-1......................–40°C to 85°C
LTC6403H-1....................................... –40°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
T
= 150°C, θ = 160°C/W, θ = 4.2°C/W
JMAX
JA
JC
–
EXPOSED PAD (PIN 17) IS V , MUST BE SOLDERED TO PCB
ORDER INFORMATION
http://www.linear.com/product/LTC6403-1#orderinfo
LEAD FREE FINISH
LTC6403CUD-1#PBF
LTC6403IUD-1#PBF
LTC6403HUD-1#PBF
TAPE AND REEL
PART MARKING*
LDBM
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC6403CUD-1#TRPBF
LTC6403IUD-1#TRPBF
LTC6403HUD-1#TRPBF
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
LDBM
–40°C to 85°C
LDBM
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
LTC6403-1 DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-Supply,
VSHDN = OPEN, RI = 402Ω, RF = 402Ω, RL = OPEN, RBAL = 100k (See Figure 1) unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is
defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
V = 2.7V
MIN
TYP
MAX
UNITS
l
l
l
V
Differential Offset Voltage (Input Referred)
0.4
0.4
0.4
1.5
1.5
2
mV
mV
mV
OSDIFF
S
V = 3V
S
V = 5V
S
Differential Offset Voltage Drift (Input Referred)
Input Bias Current (Note 6)
V = 2.7V
1
1
1
µV/°C
µV/°C
µV/°C
ΔV
/ΔT
OSDIFF
S
V = 3V
S
V = 5V
S
l
l
l
I
V = 2.7V
–25
–25
–25
–7.5
–7.5
–7.5
0
0
0
µA
µA
µA
B
S
V = 3V
S
V = 5V
S
l
l
l
I
OS
Input Offset Current (Note 6)
V = 2.7V
0.2
0.2
0.2
5
5
5
µA
µA
µA
S
V = 3V
S
V = 5V
S
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For more information www.linear.com/LTC6403-1
LTC6403-1
LTC6403-1 DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-Supply,
VSHDN = OPEN, RI = 402Ω, RF = 402Ω, RL = OPEN, RBAL = 100k (See Figure 1) unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is
defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
Input Resistance
Common Mode
Differential Mode
1.7
14
MΩ
kΩ
IN
C
Input Capacitance
Differential Mode
1
pF
IN
e
Differential Input Referred Noise Voltage Density
Input Noise Current Density
f = 1MHz
f = 1MHz
2.8
1.8
17
nV/√Hz
pA/√Hz
nV/√Hz
n
i
n
e
Input Referred Common Mode Output Noise
Voltage Density
f = 1MHz, V
Shorted to Ground,
nVOCM
OCM
–
+
V = 1.5V, V = –1.5V
l
l
V
Input Signal Common Mode Range (Note 7)
V = 3V
S
0
0
1.6
3.6
V
V
ICMR
S
V = 5V
l
l
CMRRI
CMRRIO
PSRR
Input Common Mode Rejection Ratio
50
50
72
72
dB
dB
V = 3V, ΔV
S
= 0.75V
= 1.25V
S
ICM
ICM
(Input Referred) ΔV /ΔV
(Note 8)
OSDIFF
V = 5V, ΔV
ICM
l
l
l
Output Common Mode Rejection Ratio (Input
Referred) ΔV /ΔV (Note 8)
50
60
45
90
97
63
dB
dB
dB
V = 5V, ΔV
= 2V
S
OCM
OCM
OSDIFF
Differential Power Supply Rejection
(ΔV /ΔV ) (Note 9)
V = 2.7V to 5.25V
S
S
OSDIFF
PSRRCM
Output Common Mode Power Supply Rejection
(ΔV /ΔV ) (Note 9)
V = 2.7V to 5.25V
S
S
OSCM
l
l
G
1
V/V
%
Common Mode Gain (ΔV
/ΔV
)
V = 5V, ΔV
= 2V
CM
OUTCM
OCM
S
OCM
Common Mode Gain Error (100 • (G – 1))
–0.4
–0.1
0.3
ΔG
V = 5V, ΔV
= 2V
CM
CM
S
OCM
BAL
Output Balance (ΔV /ΔV
OUTCM
)
ΔV
= 2V
OUTDIFF
OUTDIFF
l
l
–63
–66
–45
–45
dB
dB
Single-Ended Input
Differential Input
l
l
l
V
Common Mode Offset Voltage (V
– V
)
V = 2.7V
10
10
10
25
25
25
mV
mV
mV
OSCM
OUTCM
OCM
S
V = 3V
S
V = 5V
S
Common Mode Offset Voltage Drift
Output Signal Common Mode Range
V = 2.7V
20
20
20
µV/°C
µV/°C
µV/°C
ΔV
/ΔT
S
OSCM
V = 3V
S
V = 5V
S
l
l
V
V = 3V
1.1
1.1
2
4
V
V
OUTCMR
S
(Voltage Range for the V
Pin) (Note 7)
V = 5V
S
OCM
l
l
R
Input Resistance, V
Pin
15
23
32
kΩ
INVOCM
OCM
V
V
Voltage at the V
Pin (Self-Biased)
V = 3V, V = Open
OCM
1.45
1.5
1.55
V
OCM
OCM
S
Output Voltage, High, Either Output Pin (Note 10) V = 3V, I = 0
OUT
S
L
l
l
–40°C to 85°C
–40°C to 125°C
190
194
300
330
mV
mV
V = 3V, I = 5mA
S
L
l
l
–40°C to 85°C
190
193
300
330
mV
mV
–40°C to 125°C
V = 3V, I = 20mA
S
L
–40°C to 85°C
l
l
340
342
490
520
mV
mV
–40°C to 125°C
V = 5V, I = 0
S
L
l
l
–40°C to 85°C
170
173
300
330
mV
mV
–40°C to 125°C
V = 5V, I = 5mA
S
L
l
l
–40°C to 85°C
195
197
340
370
mV
mV
–40°C to 125°C
V = 5V, I = 20mA
S
L
–40°C to 85°C
l
l
380
383
550
580
mV
mV
–40°C to 125°C
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For more information www.linear.com/LTC6403-1
LTC6403-1
LTC6403-1 DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-Supply,
VSHDN = OPEN, RI = 402Ω, RF = 402Ω, RL = OPEN, RBAL = 100k (See Figure 1) unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is
defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Output Voltage, Low, Either Output Pin (Note 10)
V = 3V, I = 0
OUT
S
L
l
l
–40°C to 85°C
150
154
220
250
mV
mV
–40°C to 125°C
V = 3V, I = –5mA
S
L
l
l
–40°C to 85°C
165
171
245
275
mV
mV
–40°C to 125°C
V = 3V, I = –20mA
S
L
–40°C to 85°C
l
l
210
224
300
330
mV
mV
–40°C to 125°C
V = 5V, I = 0
S
L
l
l
–40°C to 85°C
165
170
265
295
mV
mV
–40°C to 125°C
V = 5V, I = –5mA
S
L
l
l
–40°C to 85°C
175
182
275
305
mV
mV
–40°C to 125°C
V = 5V, I = –20mA
S
L
–40°C to 85°C
l
l
225
242
350
380
mV
mV
–40°C to 125°C
l
l
l
I
Output Short-Circuit Current, Either Output Pin
(Note 11)
V = 2.7V
30
30
35
58
60
74
mA
mA
mA
SC
S
V = 3V
S
V = 5V
S
A
V
Large-Signal Voltage Gain
Supply Voltage Range
Supply Current
V = 3V
90
dB
V
VOL
S
l
2.7
5.25
S
l
l
l
I
V = 2.7V
10.7
10.8
11
11.8
11.8
12.1
mA
mA
mA
S
S
V = 3V
S
V = 5V
S
l
l
l
Supply Current in Shutdown
V = 2.7V
0.16
0.17
0.26
0.5
0.5
1
mA
mA
mA
I
S
SHDN
V = 3V
S
V = 5V
S
+
l
l
V
V
SHDN Input Logic Low
SHDN Input Logic High
SHDN Pull-Up Resistor
Turn-On Time
V = 2.7V to 5V
V – 2.1
V
V
IL
S
+
V = 2.7V to 5V
S
V – 0.6
40
IH
66
4
90
kΩ
µs
ns
R
t
V = 5V, V
= 2.9V to 0V
= 0.5V to 3V
= 3V to 0.5V
S
SHDN
SHDN
SHDN
SHDN
V = 3V, V
S
ON
t
Turn-Off Time
350
V = 3V, V
S
OFF
LTC6403-1 AC ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-Supply,
VSHDN = OPEN, RI = 402Ω, RF = 402Ω, RT = 25.5Ω, unless otherwise noted (See Figure 2). VS is defined (V+ – V–). VOUTCM is defined
as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
Output Overdrive Recovery
Slew Rate
No Glitches
70
ns
OVDR
SR
V = 3V
200
200
V/µS
V/µS
S
V = 5V
S
GBW
Gain-Bandwidth Product
V = 3V
S
200
200
MHz
MHz
S
V = 5V
l
l
f
–3dB Frequency (See Figure 2)
V = 3V
S
100
100
200
200
MHz
MHz
3dB
S
V = 5V
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For more information www.linear.com/LTC6403-1
LTC6403-1
LTC6403-1 AC ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-Supply,
VSHDN = OPEN, RI = 402Ω, RF = 402Ω, RT = 25.5Ω, unless otherwise noted (See Figure 2). VS is defined (V+ – V–). VOUTCM is defined
as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
V = 3V, V
MIN
TYP
MAX
UNITS
3MHz Distortion
= 2V
S
OUTDIFF
P-P
Single-Ended Input
2nd Harmonic
HD2
HD3
–97
–95
dBc
dBc
3rd Harmonic
3MHz Distortion
V = 3V, V
= 2V
S
OUTDIFF
P-P
Differential Input
2nd Harmonic
3rd Harmonic
HD2
HD3
–106
–94
dBc
dBc
IMD
Third-Order IMD at 10MHz
f1 = 9.5MHz, f2 = 10.5MHz
V = 3V, V
= 2V Envelope
–72
dBc
S
OUTDIFF
P-P
OIP3
Equivalent OIP3 at 3MHz (Note 12)
V = 3V
S
48
dBm
t
S
Settling Time
2V Step at Output
V = 3V, Single-Ended Input
S
1% Settling
20
30
ns
ns
0.1% Settling
NF
Noise Figure, f = 3MHz
10.8
dB
R
= 804
= 200SΩ, R = 100
Ω
, R = 402
Ω
,
,
I
RSO=U4R0C2EΩ, V = 3V
F
8.9
dB
R
Ω
RSO=U4R0C2EΩ, V = 3V
I
F
S
f
Differential Filter 3dB Bandwidth
44.2
MHz
3dBFILTER
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs +IN, –IN are protected by a pair of back-to-back diodes.
If the differential input voltage exceeds 1.4V, the input current should be
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by applying a voltage on the V pin and testing at
OCM
both mid supply and at the Electrical Characteristics table limits to verify
that the differential gain has not deviated from the mid supply V case
OCM
by more than 1%, and the common mode offset (V
by more than 10mV from the mid supply case.
) has not deviated
OSCM
limited to less than 10mA. Input pins (+IN, –IN, V
protected by steering diodes to either supply. If the inputs should exceed
either supply voltage, the input current should be limited to less than 10mA.
, and SHDN) are also
Note 8: Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred voltage offset. Output CMRR is defined as the ratio of the
OCM
change in the voltage at the V
pin to the change in differential input
OCM
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely. Long term application of output currents in excess of the
absolute maximum ratings may impair the life of the device.
Note 4: The LTC6403C-1/LTC6403I-1 are guaranteed functional over the
operating temperature range –40°C to 85°C. The LTC6403H-1 is guaranteed
functional over the operating temperature range –40°C to 125°C.
Note 5: The LTC6403C-1 is guaranteed to meet specified performance from
0°C to 70°C. The LTC6403C-1 is designed, characterized, and expected to
meet specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LTC6403I-1 is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6403H-1 is guaranteed
to meet specified performance from –40°C to 125°C.
referred voltage offset. These specifications are strongly dependent on
feedback ratio matching between the two outputs and their respective inputs,
and it is difficult to measure actual amplifier performance. See The Effects of
Resistor Pair Mismatch in the Applications Information section of this data
sheet. For a better indicator of actual amplifier performance independent of
feedback component matching, refer to the PSRR specification.
Note 9: Differential power supply rejection (PSRR) is defined as the ratio
of the change in supply voltage to the change in differential input referred
voltage offset. Common mode power supply rejection (PSRRCM) is
defined as the ratio of the change in supply voltage to the change in the
common mode offset, V
– V
.
OUTCM
OCM
Note 10: Output swings are measured as differences between the output
and the respective power supply rail.
Note 11: Extended operation with the output shorted may cause junction
temperatures to exceed the 150°C limit and is not recommended. See Note
3 for more details.
Note 12: A resistive load is not required when driving an AD converter with
the LTC6403-1. Therefore, typical output power is very small. In order to
compare the LTC6403-1 with amplifiers that require 50Ω output load, the
Note 6: Input bias current is defined as the average of the input currents flowing
into Pin 6 and Pin 15 (–IN, and +IN). Input offset current is defined as the
+
–
difference of the input currents flowing into Pin 15 and Pin 6 (I = I – I )
OS
B
B
Note 7: Input common mode range is tested using the test circuit of
Figure 1 by measuring the differential gain with a 1V differential output
with V
= mid-supply, and also with V
at the input common mode
ICM
ICM
range limits listed in the Electrical Characteristics table, verifying that the
differential gain has not deviated from the mid supply common mode input
case by more than 1%, and the common mode offset (V ) has not
LTC6403-1 output voltage swing driving a given R is converted to OIP3
as if it were driving a 50Ω load. Using this modified convention, 2V is
by definition equal to 10dBm, regardless of actual R .
L
P-P
OSCM
L
deviated from the mid-supply case by more than 10mV.
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For more information www.linear.com/LTC6403-1
LTC6403-1
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Offset Voltage
vs Temperature
Common Mode Offset Voltage
vs Temperature
Supply Current vs Supply Voltage
0.8
0.6
8
6
14
12
10
8
V
V
V
= 3V
V
SHDN
= OPEN
S
= 1.5V
OCM
=1.5V
ICM
FIVE TYPICAL UNITS
0.4
4
0.2
2
0.0
0
6
–0.2
–0.4
–0.6
–0.8
–2
–4
–6
–8
V
V
V
= 3V
S
4
= 1.5V
–40°C
25°C
85°C
125°C
OCM
ICM
= R = 402Ω
= 1.5V
F
2
R
L
FIVE TYPICAL UNITS
0
–45
0
25
40
85
125
–45
0
25
40
85
125
0
1
2
3
4
5
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
64031 G01
64031 G02
64031 G03
Shutdown Supply Current
vs Supply Voltage
Frequency Response
vs Load Capacitance
Supply Current vs SHDN Voltage
350
300
250
200
150
100
50
14
12
10
8
5
–
V
SHDN
= V
–40°C
25°C
85°C
125°C
0
–5
C
C
C
= 0pF
= 3.9pF
= 10pF
L
L
L
–10
–15
–20
–25
–30
–35
–40
6
V
V
= 3V
S
= V
= 1.5V
ICM
OCM
LOAD
4
R
= 800Ω
–40°C
25°C
R = R = 402Ω
I
F
CAPACITOR VALUES ARE FROM
EACH OUTPUT TO GROUND.
NO SERIES RESISTORS ARE USED.
2
85°C
V
S
= 3V
125°C
0
0
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
1
10 100
1000
SUPPLY VOLTAGE (V)
SHDN VOLTAGE (V)
FREQUENCY (MHz)
64031 G05
64031 G04
64031 G06
Frequency Response vs Gain
50
40
A
= 100
= 20
V
A (V/V)
R (Ω)
R (Ω)
V
I
F
A
= 10
A
V
1
2
402
402
402
402
402
402
402
806
A
V
30
= 5
V
20
A
= 2
V
10
5
2k
0
10
20
100
4.02k
8.06k
40.2k
–10
–20
–30
–40
–50
A
= 1
V
V
V
R
= 3V
S
= V
= 1.5V
ICM
OCM
= 800Ω
LOAD
0.1
1
10
100
1000
FREQUENCY (MHz)
64031 G08
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6
For more information www.linear.com/LTC6403-1
LTC6403-1
TYPICAL PERFORMANCE CHARACTERISTICS
Harmonic Distortion
vs Output Amplitude
Harmonic Distortion vs Frequency
Harmonic Distortion vs Frequency
SINGLE-ENDED INPUT
–40
–50
–60
–70
–30
–40
DIFFERENTIAL INPUTS
DIFFERENTIAL INPUTS
V
V
= 3V
OCM
V
V
= 3V
OCM
V
V
= 3V
OCM
S
S
S
= V
= 1.5V
= V
= 1.5V
ICM
= V
= 1.5V
ICM
ICM
R = R = 402Ω
R = R = 402Ω
R = R = 402Ω
F
I
–50
F
I
F
I
–60
R
f
= 800Ω
R
V
= 800Ω
R
V
= 800Ω
LOAD
LOAD
LOAD
–80
–90
= 3MHz
–60
= 2V
OUTDIFF P-P
= 2V
IN
OUTDIFF
P-P
–70
THIRD
–70
–80
SECOND
HD3
–80
THIRD
–90
–100
–110
–120
–90
HD2
–100
–110
–120
SECOND
–100
–110
–120
1
10
FREQUENCY (MHz)
100
1
2
3
4
5
1
10
FREQUENCY (MHz)
100
V
(V
)
OUTDIFF P-P
64031 G12
64031 G09
64031 G11
Harmonic Distortion
vs Output Amplitude
Differential Output Impedance
vs Frequency
Input Noise Density vs Frequency
100
10
1
100
10
1
1000
100
10
–30
–40
SINGLE-ENDED INPUT
V
= 3V
F
V
V
= 3V
ICM
S
I
S
V
V
= 3V
OCM
R = R = 402Ω
= 1.5V
S
= V
= 1.5V
ICM
R = R = 402Ω
–50
F
I
THIRD
R
= 800Ω
LOAD
–60
f
= 10MHz
IN
i
n
–70
SECOND
–80
1
e
n
–90
–100
–110
0.1
0.01
–120
0.1
1
10
100
1000
100
1k
10k
100k
1M
10M
0
1
2
3
5
4
FREQUENCY (MHz)
FREQUENCY (Hz)
V
(V
)
OUTDIFF P-P
64031 G18
64031 G17
64031 G14
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For more information www.linear.com/LTC6403-1
LTC6403-1
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Slew Rate
vs Temperature
CMRR vs Frequency
Small Signal Step Response
70
60
50
40
30
20
220
206
192
178
164
150
V
= 5V
S
S
V
= 3V
+OUT
V
V
= 3V
OCM
S
= V
ICM
= 1.5V
LOAD
R
= 800Ω
R = R = 402Ω
I
L
F
C
V
= 0pF
= 180mV
,
IN
P-P
DIFFERENTIAL
V
V
= 3V
OCM
S
= 1.5V
–OUT
R = R = 402Ω
I
F
0.05% FEEDBACK NETWORK RESISTORS
0.1
1
10
100
1000
–60 –40 –20
0
20 40 60 80 100 120 140
5ns/DIV
FREQUENCY (MHz)
TEMPERATURE (°C)
64031 G20
64031 G19
64031 G22
Large Signal Step Response
Overdrive Transient Response
3.0
2.5
2.0
1.5
V
V
= 3V, R
= 800Ω
LOAD
S
–OUT
= 2V DIFFERENTIAL
P-P
IN
–OUT
V
V
= 3V
OCM
S
= 1.5V
1.0
0.5
0
+OUT
+OUT
50ns/DIV
20ns/DIV
64031 G24
64031 G23
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For more information www.linear.com/LTC6403-1
LTC6403-1
PIN FUNCTIONS
+
SHDN(Pin1):WhenSHDNisfloatingordirectlytiedtoV ,
driving the input impedance presented by the V
pin.
OCM
the LTC6403-1 is in the normal (active) operating mode.
On the LTC6403-1, the V
pin has an input resistance
OCM
+
When Pin 1 is pulled a minimum of 2.1V below V , the
of approximately 23k to a mid-supply potential. The V
OCM
LTC6403-1 enters into a low power shutdown state. See
Applications Information for more details.
pinshouldbebypassedwithahighqualityceramicbypass
capacitor of at least 0.01µF, (unless you are using split
supplies, then connect directly to a low impedance, low
noise ground plane) to minimize common mode noise
from being converted to differential noise by impedance
mismatches both external and internal to the IC.
+
–
V , V (Pins 2, 10, 11 and Pins 3, 9, 12): Power Supply
Pins.Threepairsofpowersupplypinsareprovidedtokeep
the power supply inductance as low as possible to prevent
anydegradationofamplifier2ndharmonicperformance.It
is critical that close attention be paid to supply bypassing.
Forsinglesupplyapplications(Pins3, 9and12grounded)
it is recommended that high quality 0.1µF surface mount
ceramic bypass capacitors be placed between Pins 2 and
3, between Pins 11 and 12, and between Pins 10 and 9
with direct short connections. Pins 3, 9 and 10 should be
tieddirectlytoalowimpedancegroundplanewithminimal
routing.Fordual(split)powersupplies,itisrecommended
that at least two additional high quality, 0.1µF ceramic
NC (Pins 5, 16): No Connection. These pins are not con-
nected internally.
+OUT, –OUT (Pins 7, 14): Unfiltered Output Pins. Each
amplifier output is designed to drive a load capacitance of
10pF. This means the amplifier can drive 10pF from each
output to ground or 5pF differentially. Larger capacitive
loads should be decoupled with at least 25Ω resistors
from each output.
+
–
+OUTF, –OUTF (Pins 8, 13): Filtered Output Pins. These
pins have a series 100Ω resistor connected between the
filtered and unfiltered outputs and three 12pF capacitors.
capacitors are used to bypass pin V to ground and V to
ground,againwithminimalrouting.Fordrivinglargeloads
(<200Ω),additionalbypasscapacitancemaybeneededfor
optimal performance. Keep in mind that small geometry
(e.g.0603)surfacemountceramiccapacitorshaveamuch
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
–
Both+OUTF,and–OUTFhave12pFtoV ,plusanadditional
12pF differentially between +OUTF and –OUTF. This filter
creates a differential lowpass pole with a –3dB bandwidth
of 44.2MHz.
+IN, –IN (Pins 15, 6): Noninverting and Inverting Input
pins of the amplifier, respectively. For best performance,
it is highly recommended that stray capacitance be kept
to an absolute minimum by keeping printed circuit con-
nections as short as possible and stripping back nearby
surrounding ground plane away from these pins.
V
(Pin 4): Output Common Mode Reference Voltage.
OCM
ThevoltageonV
setstheoutputcommonmodevoltage
OCM
level (which is defined as the average of the voltages on
the +OUT and –OUT pins). The V
pin is the midpoint
OCM
+
of an internal resistive voltage divider between V and
–
V that develops a (default) mid-supply voltage potential
–
to maximize output signal swing. The V
pin can be
OCM
Exposed Pad (Pin 17): Tie the pad to V (Pins 3, 9, and
overdriven by an external voltage reference capable of
12). If split supplies are used, do not tie the pad to ground.
64031fb
9
For more information www.linear.com/LTC6403-1
LTC6403-1
BLOCK DIAGRAM
NC
+IN
–OUT
–OUTF
16
15
14
13
+
V
–
–
+
+
V
V
V
V
–
+
V
V
+
V
12pF
–
V
V
66k
SHDN
1
12
+
V
100Ω
100Ω
–
–
+
+
V
V
+
–
+
2
11
V
46k
–
+
12pF
V
V
+
V
V
OCM
–
+
V
V
V
V
46k
3
4
10
V
–
V
–
12pF
OCM
–
V
9
–
–
+
+
V
V
V
V
–
V
–
+
V
V
NC
–IN
+OUT
+OUTF
5
6
7
8
64031 BD
64031fb
10
For more information www.linear.com/LTC6403-1
LTC6403-1
APPLICATIONS INFORMATION
I
L
R
R
I
F
V
V
–OUT
+IN
+
–
V
–OUTF
V
INP
NC
+IN
–OUT
–OUTF
16
15
14
13
LTC6403-1
SHDN
–
R
V
BAL
SHDN
–
12
V
V
1
2
SHDN
–
–
0.1µF
0.1µF
0.1µF
+
+
V
V
V
+
+
–
11
V
V
+
V
OUTCM
+
+
V
OCM
V
V
0.1µF
V
CM
–
+
V
V
V
0.1µF
–
–
3
4
10
V
V
V
–
V
R
BAL
OCM
–
V
9
V
OCM
0.1µF
0.01µF
NC
–IN
+OUT
+OUT
+OUTF
–
+
5
6
7
8
64031 F01
V
INM
I
L
R
I
R
F
V+
OUTF
V
V
–IN
Figure 1. DC Test Circuit
0.1µF
0.1µF
R
R
F
340Ω
I
V
V
V
+IN
–OUT
INP
V
–OUTF
R
140Ω
T
NC
+IN
–OUT
–OUTF
16
15
14
13
LTC6403-1
SHDN
–
V
MINI-CIRCUITS
TCM4-19
SHDN
–
12
V
50Ω
V
1
SHDN
–
0.1µF
M/A-COM
ETC1-1-13
0.1µF
+
+
V
V
V
+
–
+
+
–
2
11
V
V
+
50Ω
V
IN
+
+
V
V
V
0.1µF
OCM
–
+
V
V
V
0.1µF
–
–
3
4
10
V
V
–
V
–
0.1µF
0.1µF
V
OCM
–
V
9
V
OCM
0.1µF
0.01µF
NC
–IN
+OUT
+OUT
+OUTF
5
6
7
8
64031 F02
0.1µF
R
R
F
V
340Ω
I
+OUTF
V
V
–IN
V
INM
R
140Ω
T
Figure 2. AC Test Circuit (–3dB BW Testing)
64031fb
11
For more information www.linear.com/LTC6403-1
LTC6403-1
APPLICATIONS INFORMATION
Functional Description
Additional outputs (+OUTF and –OUTF) are available that
providefilteredversionsofthe+OUTand–OUToutputs.An
on-chipsinglepoleRCpassivefilterbandlimitsthefiltered
outputs to a –3dB frequency of 44.2MHz. The user has a
choice of using the unfiltered outputs, the filtered outputs,
or modifying the filtered outputs to adjust the frequency
response by adding additional components (see Output
Filter Considerations and Use section).
The LTC6403-1 is a small outline, wide band, low noise,
andlowdistortionfully-differentialamplifierwithaccurate
output phase balancing. The LTC6403-1 is optimized to
drive low voltage, single-supply, differential input analog-
to-digital converters (ADCs). The LTC6403-1’s output is
capable of swinging rail-to-rail on supplies as low as 2.7V,
which makes the amplifier ideal for converting ground
referenced, single-ended signals into V
referenced
In applications where the full bandwidth of the LTC6403-
1 is desired, the unfiltered outputs (+OUT and –OUT)
should be used. The unfiltered outputs +OUT and –OUT
are designed to drive 10pF to ground (or 5pF differen-
tially).Capacitancesgreaterthan10pFwillproduceexcess
peaking, which can be mitigated by placing at least 25Ω
in series with the output.
OCM
differential signals in preparation for driving low voltage,
single-supply, differential input ADCs. Unlike traditional
op amps which have a single output, the LTC6403-1 has
two outputs to process signals differentially. This allows
for two times the signal swing in low voltage systems
when compared to single-ended output amplifiers. The
balanced differential nature of the amplifier also provides
even-order harmonic distortion cancellation, and less
susceptibility to common mode noise (like power supply
noise). The LTC6403-1 can be used as a single ended
input to differential output amplifier, or as a differential
input to differential output amplifier.
Input Pin Protection
The LTC6403-1’s input stage is protected against differ-
ential input voltages that exceed 1.4V by two pairs of back
to back diodes connected in anti-parallel series between
+IN and –IN (Pins 6 and 15). In addition, the input pins
have steering diodes to either power supply. If the input
pair is over-driven, the current should be limited to under
10mA to prevent damage to the IC. The LTC6403-1 also
The LTC6403-1’s output common mode voltage, defined
as the average of the two output voltages, is independent
of the input common mode voltage, and is adjusted by
has steering diodes to either power supply on the V
,
applying a voltage on the V
pin. If the pin is left open,
OCM
OCM
and SHDN pins (Pins 4 and 1), and if exposed to voltages
which exceed either supply, they too, should be current
limited to under 10mA.
an internal resistive voltage divider develops a potential
+
–
halfway between the V and V pin voltages. Whenever
is not hard tied to a low impedance ground plane, it
V
OCM
is recommended that a high quality ceramic capacitor is
used to bypass the V pin to a low impedance ground
SHDN Pin
OCM
plane (See Layout Considerations in this document). The
LTC6403-1’sinternalcommonmodefeedbackpathforces
accurate output phase balancing to reduce even order
harmonics, and centers each individual output about the
If the SHDN pin (Pin 1), is pulled 2.1V below the positive
supply, the LTC6403-1 will power down. The pin has the
+
Theveninequivalentimpedanceofapproximately66ktoV .
If the pin is left unconnected, an internal pull-up resistor
of 150k will keep the part in normal active operation. Care
should be taken to control leakage currents at this pin to
under 1µA to prevent inadvertently putting the LTC6403-1
into shutdown. In shutdown, all biasing current sources
areshutoff, andtheoutputpins, +OUTand–OUT, willeach
appear as an open collector with a non-linear capacitor in
parallel and steering diodes to either supply. Because of
thenon-linearcapacitance,theoutputsstillhavetheability
potential set by the V
pin.
OCM
V+OUT +V–OUT
VOUTCM = VOCM
=
2
The outputs (+OUT and –OUT) of the LTC6403-1 are
capable of swinging rail-to-rail. They can source or sink
up to approximately 60mA of current.
64031fb
12
For more information www.linear.com/LTC6403-1
LTC6403-1
APPLICATIONS INFORMATION
to sink and source small amounts of transient current if
exposed to significant voltage transients. The inputs (+IN
and –IN) appear as anti-parallel diodes which can conduct
if voltage transients at the input exceed 1.4V. The inputs
also have steering diodes to either supply. The turn-on
time between the shutdown and active states is typically
4µs, and turn-off time is typically 350ns.
where:
R is the average of R , and R , and R is the average
F
F1
F2
I
of R , and R .
I1
I2
b
is defined as the average feedback factor (or gain)
AVG
from the outputs to their respective inputs:
1
RI1
RI2
RI2 +R
bAVG = •
+
2 R +R
F2
I1
F1
General Amplifier Applications
As levels of integration have increased and correspond-
ingly, system supply voltages decreased, there has been
a need for ADCs to process signals differentially in order
to maintain good signal to noise ratios. These ADCs are
typically operated from a single supply voltage which can
be as low as 3V (2.7V min), and will have an optimal com-
mon mode input range near mid-supply. The LTC6403-1
makes interfacing to these ADCs trivial, by providing both
single ended to differential conversion as well as common
modelevelshifting.Thefrontpageofthisdatasheetshows
a typical application. Referring to Figure 1, the gain to
Δb is defined as the difference in feedback factors:
RI2 RI1
RI2 +RF2 RI1+RF1
is defined as the average of the two input voltages
Δb=
–
V
V
INCM
, and V (also called the source-referred input com-
INP
INM
mon mode voltage):
1
2
V
= • VINP +V
(
)
INM
INCM
and V
is defined as the difference of the input
V
from V
and V is:
INDIFF
voltages:
OUTDIFF
INM INP
RF
RI
VOUTDIFF = V+OUT – V–OUT
≈
• VINP – V
(
INM
)
V
INDIFF
= V – V
INP INM
When the feedback ratios mismatch (Δb), common mode
Note from the above equation, the differential output
voltage (V – V ) is completely independent of
input and output common mode voltages. This makes
the LTC6403-1 ideally suited for pre-amplification, level
shifting and conversion of single-ended input signals to
differential output signals in preparation for driving dif-
ferential input ADCs.
to differential conversion occurs.
+OUT
–OUT
R
I2
R
F2
V
+IN
V
–OUT
V
–OUTF
+
–
V
NC
+IN
–OUT –OUTF
INP
16
15
14
13
LTC6403-1
SHDN
–
V
SHDN
–
12
V
V
1
2
SHDN
–
+
+
V
V
V
V
0.1µF
0.1µF
+
+
–
V
V
11
+
Effects of Resistor Pair Mismatch
+
+
V
V
0.1µF
V
OCM
–
+
V
V
V
Figure 3 shows a circuit diagram with takes into consid-
eration that real world resistors will not perfectly match.
Assuming infinite open loop gain, the differential output
relationship is given by the equation:
–
–
V
3
4
V
10
0.1µF
–
–
V
OCM
0.1µF
–
V
VOCM
9
V
0.01µF
–
+
NC
–IN
+OUT
+OUTF
64031 F03
0.1µF
5
6
7
8
V
INM
R
R
F1
I1
V
+OUTF
V
–IN
RF
RI
V
+OUT
VOUTDIFF = V+OUT – V–OUT
≈
•V
+
INDIFF
Figure 3. Real World Application With Feedback Resistor
Pair Mismatch
Δb
bAVG
Δb
bAVG
•V
–
•VOCM
INCM
64031fb
13
For more information www.linear.com/LTC6403-1
LTC6403-1
APPLICATIONS INFORMATION
Setting the differential input to zero (V
= 0), the de-
Input Impedance and Loading Effects
The input impedance looking into the V or V input of
INDIFF
gree of common mode to differential conversion is given
by the equation:
INP
INM
Figure 1 depends on whether the sources V and V
INP
INM
Δb
are fully differential. For balanced input sources (V
–V ), theinputimpedanceseenateitherinputissimply:
=
INP
VOUTDIFF = V+OUT – V–OUT ≈ VINCM – VOCM
•
(
)
INM
bAVG
R
= R
= R
INP
INM I
In general, the degree of feedback pair mismatch is a
source of common mode to differential conversion of
both signals and noise. Using 1% resistors or better will
mitigatemostproblems,andwillprovideabout34dBworst
case of common mode rejection. Using 0.1% resistors
will provide about 54dB of common mode rejection. A
low impedance ground plane should be used as a refer-
For single ended inputs, because of the signal imbalance
at the input, the input impedance increases over the bal-
anced differential case. The input impedance looking into
either input is:
RI
RINP =RINM
=
1
RF
1– •
ence for both the input signal source and the V
pin.
OCM
2 R +R
I
F
Directly shorting V
OCM
to this ground or bypassing the
OCM
V
with a high quality 0.1µF ceramic capacitor to this
Inputsignalsourceswithnon-zerooutputimpedancescan
alsocausefeedbackimbalancebetweenthepairoffeedback
networks. For the best performance, it is recommended
that the source’s output impedance be compensated. If
input impedance matching is required by the source, R1
should be chosen (see Figure 4):
ground plane will further mitigate against common mode
signals being converted to differential.
There may be concern on how feedback ratio mismatch
affectsdistortion.Distortioncausedbyfeedbackratiomis-
match using 1% resistors or better is negligible. However,
in single supply level shifting applications where there is
a voltage difference between the input common mode
voltage and the output common mode voltage, resistor
mismatch can make the apparent voltage offset of the
amplifier appear worse than specified.
RINM •RS
RINM –RS
R1 =
According to Figure 4, the input impedance looking into
thedifferentialamp(R )reflectsthesingleendedsource
INM
The apparent input referred offset induced by feedback
ratio mismatch is derived from the above equation:
case, thus:
RI
RINM
=
V
≈ (V
– V ) • Δb
OCM
OSDIFF(APPARENT)
INCM
1
RF
1– •
Using the LTC6403-1 in a single supply application on a
single5Vsupplywith1%resistors, andtheinputcommon
2 R +R
I
F
mode grounded, with the V
pin biased at mid-supply,
OCM
R2 is chosen to balance R1 || RS:
the worst case mismatch can induce 25mV of apparent
offset voltage. With 0.1% resistors, the worst case appar-
ent offset reduces to 2.5mV.
RI •RS
RI +RS
R2 =
64031fb
14
For more information www.linear.com/LTC6403-1
LTC6403-1
APPLICATIONS INFORMATION
R
INM
V
(setting V
to zero), the input common voltage is
INP
INM
R
S
R
I
R
F
approximately:
R1
V
S
V+IN +V–IN
RI
R +R
–
+
–
V
=
≈ VVOCM
•
+
ICM
V
OCM
2
F
I
R1 CHOSEN SO THAT R1 || R
INM
= R
S
+
R2 CHOSEN TO BALANCE R || R1
S
R
I
R
F
RF
V
RF
R +R
INP
2
VCM
•
+
•
64031 F04
R2 = R || R1
S
R +R
I
I
F
F
Figure 4. Optimal Compensation for Signal Source Impedance
Output Common Mode Voltage Range
The output common mode voltage is defined as the aver-
age of the two outputs:
Input Common Mode Voltage Range
The LTC6403-1’s input common mode voltage (V ) is
ICM
V+OUT +V–OUT
defined as the average of the two input voltages, V
,
+IN
VOUTCM = VVOCM
The V
=
–
+
2
and V . It extends from V to 1.4V below V .
–IN
Forfullydifferentialinputapplications,whereV =–V
,
pin sets this average by an internal common
INP
INM
OCM
the input common mode voltage is approximately (Refer
mode feedback loop. The output common mode range
–
+
to Figure 5):
extends from 1.1V above V to 1V below V . The V
OCM
pin sits in the middle of an internal voltage divider which
V+IN +V–IN
RI
R +R
V
=
≈ VVOCM
•
+
sets the default mid-supply open circuit potential.
ICM
2
F
I
In single supply applications, where the LTC6403-1 is
used to interface to an ADC, the optimal common mode
input range to the ADC is often determined by the ADC’s
reference. If the ADC makes a reference available for set-
ting the input common mode voltage, it can be directly
RF
VCM
•
R +R
I
F
With singled ended inputs, there is an input signal com-
ponent to the input common mode voltage. Applying only
tied to the V
pin, but must be capable of driving the
OCM
input impedance presented by the V
as listed in the
OCM
R
R
F
I
V
+IN
Electrical Characteristics Table. This impedance can be
V
–OUT
V
–OUTF
+
–
assumed to be connected to a mid-supply potential. If an
V
INP
NC
+IN
–OUT –OUTF
16
15
14
13
LTC6403-1
external reference drives the V
pin, it should still be
OCM
SHDN
–
bypassed with a high quality 0.01µF or higher capacitor
to a low impedance ground plane to filter any thermal
noise and to prevent common mode signals on this pin
from being inadvertently converted to differential signals.
V
SHDN
–
12
V
V
1
2
SHDN
–
+
+
V
V
V
V
0.1µF
0.1µF
+
+
–
V
V
11
+
V
CM
+
+
V
V
V
0.1µF
OCM
–
+
V
V
V
–
–
V
3
4
V
10
0.1µF
–
–
Output Filter Considerations and Use
V
OCM
0.1µF
–
V
9
V
VOCM
Filtering at the output of the LTC6403-1 is often desired
to provide either anti-aliasing or improved signal to noise
ratio. To simplify this filtering, the LTC6403-1 includes an
additional pair of differential outputs (+OUTF and –OUTF)
which incorporate an internal lowpass filter network with
a –3dB bandwidth of 44.2MHz (Figure 6).
0.01µF
–
+
NC
–IN
+OUT
+OUTF
64031 F05
0.1µF
5
6
7
8
V
INM
R
R
F
I
V
+OUTF
V
–IN
V
+OUT
Figure 5. Circuit for Common Mode Range
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15
For more information www.linear.com/LTC6403-1
LTC6403-1
APPLICATIONS INFORMATION
These pins each have an output impedance of 100Ω. In-
+OUTF and –OUTF can also be used, and since it is being
driven differentially it will appear at each filtered output
as a single-ended capacitance of twice the value. To halve
the filter bandwidth, for example, two 36pF capacitors
could be added (one from each filtered output to ground).
Alternatively, one 18pF capacitor could be added between
the filtered outputs, again halving the filter bandwidth.
Combinations of capacitors could be used as well; a three
capacitor solution of 12pF from each filtered output to
ground plus a 12pF capacitor between the filtered outputs
would also halve the filter bandwidth (Figure 8).
–
ternal capacitances are 12pF to V on each filtered output,
plus an additional 12pF capacitor connected differentially
between the two filtered outputs. This resistor/capacitor
combination creates filtered outputs that look like a se-
ries 100Ω resistor with a 36pF capacitor shunting each
filtered output to AC ground, providing a –3dB bandwidth
of 44.2MHz, and a noise bandwidth of 69.4MHz. The
filter cutoff frequency is easily modified with just a few
external components. To increase the cutoff frequency,
simply add 2 equal value resistors, one between +OUT
and +OUTF and the other between –OUT and –OUTF
(Figure 7). These resistors, in parallel with the internal
100Ω resistors, lower the overall resistance and therefore
increase filter bandwidth. For example, to double the filter
bandwidth, add two external 100Ω resistors to lower the
series filter resistance to 50Ω. The 36pF of capacitance
remains unchanged, so filter bandwidth doubles. Keep in
mind, the series resistance also serves to decouple the
outputs from load capacitance. The unfiltered outputs of
the LTC6403-1 are designed to drive 10pF to ground or
5pF differentially, so care should be taken to not lower the
effective impedance between +OUT and +OUTF or –OUT
and –OUTF below 25Ω.
100Ω
–OUT
–OUTF
14
13
LTC6403-1
12pF
–
V
12
–
100Ω
V
+
–
FILTERED OUTPUT
(88.4MHz)
12pF
100Ω
–
V
–
12pF
V
9
+OUT
100Ω
+OUTF
7
8
64031 F07
To decrease filter bandwidth, add two external capacitors,
one from +OUTF to ground, and the other from –OUTF to
ground. A single differential capacitor connected between
Figure 7. LTC6403-1 Filter Topology Modified for 2x
Filter Bandwidth (2 External Resistors)
–OUT
–OUTF
–OUT
100Ω
–OUTF
14
13
14
13
LTC6403-1
12pF
LTC6403-1
12pF
–
V
12pF
–
V
12
12
–
100Ω
V
–
–
V
+
–
FILTERED OUTPUT
(22.1MHz)
+
–
12pF
FILTERED OUTPUT
(44.2MHz)
12pF
12pF
100Ω
100Ω
–
V
12pF
–
12pF
V
V
–
12pF
V
9
9
+OUT
+OUTF
+OUT
+OUTF
7
8
64031 F08
7
8
64031 F06
Figure 6. LTC6403-1 Internal Filter Topology
Figure 8. LTC6403-1 Filter Topology Modified for 1/2x
Filter Bandwidth (3 External Capacitors)
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16
For more information www.linear.com/LTC6403-1
LTC6403-1
APPLICATIONS INFORMATION
Noise Considerations
The LTC6403-1’s input referred voltage noise contributes
theequivalentnoiseofa480Ωresistor.Whenthefeedback
network is comprised of resistors whose values are less
than this, the LTC6403-1’s output noise is voltage noise
dominant (See Figure 10.):
The LTC6403-1’s input referred voltage noise is on the
order of 2.8nV/√Hz. Its input referred current noise is on
the order of 1.8pA/√Hz. In addition to the noise gener-
ated by the amplifier, the surrounding feedback resistors
also contribute noise. A noise model is shown in Figure
9. The output noise generated by both the amplifier and
the feedback components is governed by the equation:
R
F
e ≈ e • 1+
no
ni
R
I
Feedback networks consisting of resistors with values
greater than about 1k will result in output noise which is
resistor noise and amplifier current noise dominant.
2
RF
RI
2
e • 1+
+2• I •R
F
+
(
)
ni
n
eno =
2
RF
eno ≈ 2 • I •R 2 + 1+
•4•k •T•R
F
RF
2
(
)
n
F
2• e
•
+2•enRF
nRI
R
I
R
I
Lowerresistorvalues(<400Ω)alwaysresultinlowernoise
at the penalty of increased distortion due to increased
loading of the feedback network on the output. Higher
A plot of this equation, and a plot of the noise generated
by the feedback components for the LTC6403-1 is shown
in Figure 10.
2
2
e
nRI2
e
nRF2
R
I2
R
F2
+2
i
n
NC
+IN
–OUT
–OUTF
13
16
15
14
LTC6403-1
SHDN
–
V
SHDN
–
12
V
V
V
1
2
–
+
+
V
V
V
+
–
+
–
11
V
V
V
+
+
+
–
2
2
V
V
OCM
e
nof
e
no
–
+
V
V
V
–
3
4
10
V
–
2
V
e
ncm
–
V
OCM
9
NC
–IN
+OUT
+OUTF
5
6
7
8
64031 F09
–2
i
n
2
e
ni
2
2
e
nRI1
e
nRF1
R
I1
R
F1
Figure 9. Noise Model of the LTC6403-1
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17
For more information www.linear.com/LTC6403-1
LTC6403-1
APPLICATIONS INFORMATION
100
with minimal routing. For dual (split) power supplies, it is
recommendedthatatleasttwoadditionalhighquality,0.1µF
+
ceramic capacitors are used to bypass pin V to ground
TOTAL (AMPLIFIER AND
FEEDBACK NETWORK)
OUTPUT NOISE
–
and V to ground, again with minimal routing. For driving
largeloads(<200Ω),additionalbypasscapacitancemaybe
needed for optimal performance. Keep in mind that small
geometry (e.g. 0603) surface mount ceramic capacitors
haveamuchhigherselfresonantfrequencythandoleaded
capacitors, and perform best in high speed applications.
10
FEEDBACK RESISTOR
NETWORK NOISE ALONE
1
Any stray parasitic capacitances to ground at the sum-
ming junctions +IN, and –IN should be kept to an absolute
minimum even if it means stripping back the ground plane
away from any trace attached to this node. This becomes
especially true when the feedback resistor network uses
100
1k
10k
R = R (Ω)
F
I
64031 F10
Figure 10. LTC6403-1 Output Spot Noise vs Spot Noise
Contributed by Feedback Network Alone
resistor values >2k in circuits with R = R . Excessive
F
I
resistor values (but still less than 2k) will result in higher
output noise, but improved distortion due to less loading
on the output. The optimal feedback resistance for the
LTC6403-1 runs between 400Ω to 2k.
peaking in the frequency response can be mitigated by
adding small amounts of feedback capacitance around
R . Always keep in mind the differential nature of the
F
LTC6403-1, and that it is critical that the load impedances
seen by both outputs (stray or intended) should be as bal-
anced and symmetric as possible. This will help preserve
the natural balance of the LTC6403-1, which minimizes
the generation of even order harmonics, and preserves
the rejection of common mode signals and noise.
Thedifferentialfilteredoutputs+OUTFand–OUTFwillhave
a little higher spot noise than the unfiltered outputs (due
to the two 100Ω resistors which contribute 1.3nV/√Hz
each), but actually will provide superior signal-to-noise
ratios in noise bandwidths exceeding 69.4Mhz due to the
noise-filtering function the filter provides.
It is highly recommended that the V
pin be either hard
OCM
tied to a low impedance ground plane (in split supply
applications), or bypassed to ground with a high quality
ceramic capacitor whose value exceeds 0.01µF. This will
help stabilize the common mode feedback loop as well as
preventthermalnoisefromtheinternalvoltagedividerand
other external sources of noise from being converted to
differential noise due to divider mismatches in the feed-
back networks. It is also recommended that the resistive
feedback networks comprise 1% resistors (or better) to
enhancetheoutputcommonmoderejection.Thiswillalso
Layout Considerations
Because the LTC6403-1 is a very high speed amplifier, it is
sensitive to both stray capacitance and stray inductance.
Three pairs of power supply pins are provided to keep the
power supply inductance as low as possible to prevent
any degradation of amplifier 2nd Harmonic distortion
performance. It is critical that close attention be paid to
supply bypassing. For single supply applications (Pins 3,
9 and 12 grounded) it is recommended that 3 high quality
0.1µF surface mount ceramic bypass capacitor be placed
betweenpins2and3,betweenpins11and12,andbetween
pins10 and 9 with direct short connections. Pins 3, 9 and
10shouldbetieddirectlytoalowimpedancegroundplane
prevent the V
-referred common mode noise of the
OCM
common mode amplifier path (which cannot be filtered)
from being converted to differential noise, degrading the
differential noise performance.
64031fb
18
For more information www.linear.com/LTC6403-1
LTC6403-1
APPLICATIONS INFORMATION
Interfacing the LTC6403-1 to A/D Converters
to help absorb the charge injection that comes out of the
ADC from the sampling process. The capacitance of the
filter network serves as a charge reservoir to provide high
frequency charging during the sampling process, while
the two resistors of the filter network are used to dampen
and attenuate any charge kickback from the ADC. The
selection of the R-C time constant is trial and error for a
givenADC,butthefollowingguidelinesarerecommended:
Choosing too large of a resistor in the decoupling network
will create a voltage divider between the dynamic input
impedanceoftheADCandthedecouplingresistorsleaving
insufficient settling time. Choosing too small of a resistor
willpossiblypreventtheresistorfromproperlydampening
the load transient caused by the sampling process, pro-
longing the time required for settling. 16-bit applications
require a minimum of 11 R-C time constants to settle. It
is recommended that the capacitor chosen have a high
quality dielectric (for example, C0G multilayer ceramic).
The LTC6403-1’s rail-to-rail output and fast settling time
make the LTC6403-1 ideal for interfacing to low voltage,
singlesupply,differentialinputADCs.Thesamplingprocess
of ADCs creates a sampling glitch caused by switching
in the sampling capacitor on the ADC front end which
momentarily shorts the output of the amplifier as charge
is transferred between the amplifier and the sampling
capacitor. The amplifier must recover and settle from
this load transient before this acquisition period ends for
a valid representation of the input signal. In general, the
LTC6403-1 will settle much more quickly from these pe-
riodic load impulses than from a 2V input step, but it is
a good idea to either use the filtered outputs to drive the
ADC (Figure 11 shows an example of this), or to place a
discrete R-C filter network between the differential unfil-
tered outputs of the LTC6403-1 and the input of the ADC
402Ω
NC
402Ω
+IN
–OUT
–OUTF
16
15
14
13
LTC6403-1
SHDN
SHDN
CONTROL
–
V
V
CM
12
2.2µF
1
2
–
+
+
V
V
V
D15
•
0.1µF
0.1µF
+
–
+
–
AIN
11
3.3V
V
V
+
•
+
0.1µF
V
3.3V
LTC2207
GND
V
D0
OCM
–
+
V
V
V
V
–
AIN
3
4
10
3.3V
V
DD
–
V
–
1µF
OCM
9
0.1µF
NC
–IN
+OUT
+OUTF
5
6
7
8
64031 F11
V
, 2V
P-P
IN
402Ω
402Ω
Figure 11. Interfacing the LTC6403-1 to ADC (Shared 3.3V Supply Voltage)
64031fb
19
For more information www.linear.com/LTC6403-1
LTC6403-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC6403-1#packaging for the most recent package drawings.
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
1.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ±0.05
3.00 ±0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
1.45 ± 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 ±0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
64031fb
20
For more information www.linear.com/LTC6403-1
LTC6403-1
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
06/17 Added a –40°C to 125°C H-grade version and its performance characteristics.
2 - 8
64031fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
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64031fb
LT 0617 REV B • PRINTED IN USA
www.linear.com/LTC6403-1
LINEAR TECHNOLOGY CORPORATION 2008
22
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