LTC694IS8 [Linear]
Microprocessor Supervisory Circuits; 微处理器监控电路
| 型号： | LTC694IS8 |
| 厂家： | 
Linear |
| 描述： | Microprocessor Supervisory Circuits |
| 文件： | 总16页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC690/ LTC691
LTC694/ LTC695
Mic ro p ro c e sso r
Sup e rviso ry Circ uits
U
FEATURES
DESCRIPTIO
The LTC®690 family provides complete power supply
monitoringandbatterycontrolfunctions formicroproces-
sor reset, battery back-up, CMOS RAM write protection,
power failure warning and watchdog timing. A precise
internal voltage reference and comparator circuit monitor
thepowersupplyline. Whenanout-of-tolerancecondition
occurs,theresetoutputs areforcedtoactivestates andthe
chipenableoutputunconditionallywrite-protects external
memory. In addition, the RESET output is guaranteed to
■
UL Recognized
Guaranteed Reset Assertion at V = 1V
1.5mA Maximum Supply Current
Fast (35ns Max) Onboard Gating of RAM Chip
Enable Signals
File # E145770
®
■
CC
■
■
■
■
■
SO-8 and S16 Packaging
4.65V Precision Voltage Monitor
Power OK/Reset Time Delay: 50ms, 200ms
or Adjustable
■
■
■
Minimum External Component Count
1µA Maximum Standby Current
Voltage Monitor for Power-Fail
or Low-Battery Warning
Thermal Limiting
Performance Specified Over Temperature
Superior Upgrade for MAX690 Family
remain logic low even with V as low as 1V.
CC
The LTC690 family powers the active CMOS RAMs with a
charge pumped NMOS power switch to achieve low drop-
out and low supply current. When primary power is lost,
auxiliarypower,connectedtothebatteryinputpin,powers
the RAMs in standby through an efficient PMOS switch.
■
■
■
For an early warning of impending power failure, the
LTC690 family provides an internal comparator with a
user-definedthreshold. Aninternalwatchdogtimeris also
available, which forces the reset pins to active states when
thewatchdoginputis nottoggledpriortoapresettime-out
period.
U
APPLICATIO S
■
Critical µP Power Monitoring
Intelligent Instruments
Battery-Powered Computers and Controllers
Automotive Systems
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
RESET Output Voltage vs
Supply Voltage
5
LT®1086-5
T
= 25°C
A
V
IN
≥ 7.5V
5V
EXTERNAL PULL-UP = 10µA
= 0V
POWER TO
CMOS RAM POWER
µP
V
IN
V
OUT
V
CC
V
OUT
V
BATT
+
+
4
3
0.1µF
0.1µF
LTC690/LTC691
LTC694/LTC695
V
BATT
100µF
10µF
ADJ
µP
SYSTEM
3V
µP RESET
µP NMI
RESET
PFO
51k
10k
2
1
0
I/O LINE
PFI
WDI
GND
690 TA01
0.1µF
100Ω
MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
690 TA02
1
LTC690/ LTC691
LTC694/ LTC695
W W W
U
ABSOLUTE AXI U RATI GS (Notes 1 and 2)
Terminal Voltage
V .................................................... –0.3V to 6.0V
VOUT Output Current ................. Short-Circuit Protected
Power Dissipation............................................. 500mW
Operating Temperature Range
CC
VBATT ................................................ –0.3V to 6.0V
All Other Inputs .................. –0.3V to (VOUT + 0.3V)
LTC690/91/94/95C............................... 0°C to 70°C
LTC690/91/94/95I ........................... –40°C to 85°C
LTC690M ...................................... –55°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
Input Current
V .............................................................. 200mA
CC
VBATT ............................................................ 50mA
GND .............................................................. 20mA
W
U
/O
PACKAGE RDER I FOR ATIO
(Note 3)
TOP VIEW
TOP VIEW
ORDER PART
ORDER PART
NUMBER
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RESET
RESET
WDO
CE IN
CE OUT
WDI
1
2
RESET
RESET
WDO
NUMBER
16
15
14
13
BATT
BATT
V
V
OUT
OUT
V
V
3
4
5
6
7
8
CC
CC
LTC691CN
LTC691IN
LTC695CN
LTC695IN
LTC691CSW
LTC691ISW
LTC695CSW
LTC695ISW
GND
BATT ON
LOW LINE
OSC IN
GND
BATT ON
LOW LINE
OSC IN
CE IN
12
CE OUT
11 WDI
PFO
PFO
PFI
10
9
OSC SEL
PFI
OSC SEL
SW PACKAGE
16-LEAD WIDE PLASTIC SO
N PACKAGE
16-LEAD PDIP
T
JMAX = 110°C, θJA = 130°C/W Conditions: PCB mount on
FR4 Material, Still Air at 25°C, Copper Trace
TJMAX = 110°C, θJA = 130°C/W
LTC690CS8
LTC690IS8
LTC694CS8
LTC694IS8
TOP VIEW
TOP VIEW
LTC690CN8
LTC690IN8
LTC690MJ8
LTC694CN8
LTC694IN8
V
V
OUT
1
2
1
2
3
4
V
8
7
6
5
V
BATT
8
7
6
5
OUT
BATT
V
RESET
WDI
V
RESET
WDI
CC
CC
GND
PFI
3
4
GND
PFI
PFO
PFO
S8 PART
MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
J8 PACKAGE N8 PACKAGE
8-LEAD CERDIP 8-LEAD PDIP
690 694
690I 694I
T
JMAX = 110°C, θJA = 180°C/W Conditions: PCB Mount on
T
JMAX = 110°C, θJA = 100°C/W (J8)
FR4 Material, Still Air AT 25°C, Copper Trace
TJMAX = 110°C, θJA = 130°C/W (N8)
U
PRODUCT SELECTIO GUIDE
CONDITIONAL
WATCHDOG
TIMER
BATTERY
BACK-UP
POWER-FAIL
WARNING
RAM WRITE
PROTECT
PUSH-BUTTON
BATTERY
BACK-UP
PINS
8
RESET
RESET
LTC690
LTC691
LTC694
LTC695
LTC699
LTC1232
LTC1235
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
8
X
X
16
8
8
X
X
16
X
X
X
X
2
LTC690/ LTC691
LTC694/ LTC695
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITONS
MIN
TYP
MAX
UNITS
Battery Back-Up Switching
Operating Voltage Range
V
V
BATT
4.75
2.00
5.50
4.25
V
V
CC
V
OUT
Output Voltage
I
= 1mA
V
V
CC
– 0.05
– 0.10
V
– 0.005
V – 0.005
CC
V
V
OUT
CC
CC
●
I
= 50mA
V
– 0.50
V – 0.250
CC
V
V
OUT
CC
V
OUT
in Battery Back-Up Mode
I
= 250µA, V < V
V
BATT
– 0.1
V
– 0.02
OUT
CC
BATT
BATT
Supply Current (Exclude I
)
I
≤ 50mA
0.6
0.6
1.5
2.5
mA
mA
OUT
OUT
●
●
●
Supply Current in Battery Back-Up Mode
V
= 0V, V
= 2.8V
0.04
0.04
1
5
µA
µA
CC
BATT
Battery Standby Current (+ = Discharge, – = Charge)
5.5 > V > V
+ 0.2V
–0.1
–1.0
+0.02
+0.10
µA
µA
CC
BATT
Battery Switchover Threshold, V – V
Power Up
Power Down
70
50
mV
mV
CC
BATT
Battery Switchover Hysteresis
20
mV
V
BATT ON Output Voltage (Note 4)
I
= 3.2mA
0.4
25
SINK
BATT ON Output Short-Circuit Current (Note 4)
BATT ON = V
Sink Current
35
1
m
OUT
BATT ON = 0V Source Current
0.5
µA
Reset and Watchdog Timer
Reset Voltage Threshold
●
●
4.5
4.4
4.65
4.65
40
4.75
4.75
V
V
LTC690M
Reset Threshold Hysteresis
mV
Reset Active Time (LTC690/91) (Note 5)
OSC SEL HIGH, V = 5V
40
35
50
50
60
70
ms
ms
CC
●
●
●
●
Reset Active Time (LTC694/95) (Note 5)
OSC SEL HIGH, V = 5V
160
140
200
200
240
280
ms
ms
CC
Watchdog Time-Out Period, Internal Oscillator
Long Period, V = 5V
1.2
1.0
1.6
1.6
2.00
2.25
sec
sec
CC
Short Period, V = 5V
80
70
100
100
120
140
ms
ms
CC
Watchdog Time-Out Period, External Clock (Note 6)
Long Period
Short Period
4032
960
4097
1025
Clock
Cycles
Reset Active Time PSRR
1
1
ms/V
ms/V
ns
Watchdog Time-Out Period PSRR, Internal OSC
Minimum WDI Input Pulse Width
V = 0.4V, V = 3.5V
●
200
IL
IH
RESET Output Voltage at V = 1V
I
= 10µA, V = 1V
4
200
0.4
mV
CC
SINK
CC
RESET and LOW LINE Output Voltage (Note 4)
I
= 1.6mA, V = 4.25V
V
V
SINK
CC
I
= 1µA, V = 5V
3.5
3.5
SOURCE
CC
RESET and WDO Output Voltage (Note 4)
I
= 1.6mA, V = 5V
0.4
V
V
SINK
CC
I
= 1µA, V = 4.25V
CC
SOURCE
3
LTC690/ LTC691
LTC694/ LTC695
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITONS
MIN
TYP
3
MAX
UNITS
µA
RESET, RESET, WDO, LOW LINE
Output Short-Circuit Current (Note 4)
Output Source Current
Output Sink Current
1
25
25
mA
V
WDI Input Threshold
Logic Low
Logic High
0.8
50
3.5
WDI Input Current
WDI = V
●
●
4
–8
µA
OUT
WDI = 0V
–50
Power-Fail Detector
PFI Input Threshold
V
CC
= 5V
●
1.25
1.3
0.3
1.35
V
mV/V
nA
PFI Input Threshold PSRR
PFI Input Current
±0.01
±25
PFO Output Voltage (Note 4)
I
= 3.2mA
0.4
V
SINK
I
= 1µA
3.5
1
SOURCE
PFO Short-Circuit Source Current (Note 4)
PFI = HIGH, PFO = 0V
PFI = LOW, PFO = V
3
25
2
25
µA
mA
µs
OUT
PFI Comparator Response Time (Falling)
∆V = –20mV, V = 15mV
IN OD
PFI Comparator Response Time (Rising) (Note 4)
∆V = 20mV, V = 15mV
with 10kΩ Pull-Up
40
8
µs
IN
OD
Chip Enable Gating
CE IN Threshold
V
V
IH
0.8
0.4
V
IL
2.0
CE IN Pull-Up Current (Note 7)
CE OUT Output Voltage
3
µA
I
= 3.2mA
V
SINK
I
= 3.0mA
V
OUT
– 1.50
SOURCE
I
= 1µA, V = 0V
V
OUT
– 0.05
SOURCE
CC
CE Propagation Delay
V
CC
= 5V, C = 20pF
20
20
35
45
ns
L
●
CE OUT Output Short-Circuit Current
Output Source Current
Output Sink Current
30
35
mA
Oscillator
OSC IN Input Current (Note 7)
OSC SEL Input Pull-Up Current (Note 7)
OSC IN Frequency Range
±2
µA
µA
5
OSC SEL = 0V
●
0
250
kHz
kHz
OSC IN Frequency with External Capacitor
OSC SEL = 0V, C
= 47pF
4
OSC
Note 1: Absolute Maximum Ratings are those values beyond which the life
of device may be impaired.
reset active time of 140ms (200ms typically). The reset active time of the
LTC691 and LTC695 can be adjusted (see Table 2 in Applications
Information section).
Note 2: All voltage values are with respect to GND.
Note 6: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer (See Block Diagram).
Variation in the time-out period is caused by phase errors which occur
when the oscillator divides the external clock by 64. The resulting variation
in the time-out period is 64 clocks plus one clock of jitter.
Note 3: For military temperature range parts or for the LTC692 and
LTC693, consult the factory.
Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and
RESET have weak internal pull-ups of typically 3µA. However, external
pull-up resistors may be used when higher speed is required.
Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pullups which pull to the supply when the input pins are floating.
Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms
(50ms typically) while the LTC694 and LTC695 have longer minimum
4
LTC690/ LTC691
LTC694/ LTC695
W
BLOCK DIAGRA
M2
V
V
BATT
OUT
M1
V
CC
CHARGE
PUMP
–
BATT ON
C2
+
LOW LINE
+
C1
–
CE OUT
1.3V
GND
CE IN
PFI
–
C3
PFO
+
RESET
RESET
OSC IN
RESET PULSE
GENERATOR
OSC
OSC SEL
WATCHDOG
TIMER
WDO
TRANSITION
DETECTOR
WDI
690 BD
U U
U
PI FU CTIO S
V : 5V Supply Input. The VCC pin should be bypassed
CC
GND: Ground pin.
with a 0.1µF capacitor.
BATT ON: Battery On Logic Output from Comparator C2.
VOUT:Voltage Output for Backed Up Memory. Bypass with
a capacitor of 0.1µF or greater. During normal operation,
VOUT obtains power from VCC through an NMOS power
switch,M1,whichcandeliverupto50mAandhas atypical
BATT ON goes low when VOUT is internally connected to
V .Theoutputtypicallysinks 35mAandcanprovidebase
CC
drive for an external PNP transistor to increase the output
current above the 50mA rating of VOUT. BATT ON goes
on resistance of 5Ω. When V is lower than VBATT, VOUT high when VOUT is internally switched to V
.
CC
BATT
is internally switched to VBATT. If VOUT and VBATT are not
PFI: Power Failure Input. PFI is the noninverting input to
the power-fail comparator, C3. The inverting input is
internallyconnectedtoa1.3Vreference. Thepowerfailure
used, connect VOUT to V .
CC
V
BATT:Back-UpBatteryInput.WhenV falls belowV
,
CC
BATT
auxiliary power, connected to VBATT, is delivered to VOUT output remains high when PFI is above 1.3V and goes low
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, VBATT should be connected to GND.
when PFI is below 1.3V. Connect PFI to GND or VOUT when
C3 is not used.
5
LTC690/ LTC691
LTC694/ LTC695
U U
U
PI FU CTIO S
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
time-outperiod,WDOgoes low.WDOis sethighwhenever
thereis atransitionontheWDIpin, orLOWLINEgoes low.
The watchdog timer can be disabled by floating WDI (see
Figure 11).
1.3V. When V is lower than VBATT, C3 is shut down and
CC
PFO is forced low.
RESET: Logic Output for µP Reset Control. Whenever V
CC
falls below either the reset voltage threshold (4.65V,
typically) or VBATT, RESET goes active low. After V
CE IN: Logic input to the Chip Enable gating circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
CC
returns to 5V, reset pulse generator forces RESET to
remain active low for a minimum of 35ms for the LTC690
/LTC691 (140ms for the LTC694/LTC695). When the
watchdog timer is enabled but not serviced prior to a
preset time-out period, reset pulse generator also forces
RESET to active low for a minimum of 35ms for the
LTC690/LTC691 (140ms for the LTC694/5) for every
preset time-out period (see Figure 11). The reset active
time is adjustable on the LTC691/LTC695. An external
push-button reset can be used in connection with the
RESET output. See Push-Button Reset in Applications
Information section.
CE OUT: Logic Output on the Chip Enable Gating Circuit.
When V is above the reset voltage threshold, CE OUT is
CC
a buffered replica of CE IN. When V is below the reset
CC
voltage threshold CE OUT is forced high (see Figure 5).
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
timeandwatchdogtime-outperiod. ForcingOSCSELlow,
allows OSC IN be driven from an external clock signal or
external capacitor be connected between OSC IN and
GND.
RESET: RESET is an active high logic ouput. It is the
inverse of RESET.
OSC IN: Oscillator Input. OSC IN can be driven by an
externalclocksignalorexternalcapacitorcanbeconnected
between OSC IN and GND when OSC SEL is forced low. In
this configuration the nominal reset active time and
watchdog time-out period are determined by the number
ofclocks orsetbytheformula(seeApplications Information
section). When OSC SEL is high or floating, the internal
oscillator is enabled and the reset active time is fixed at
50ms typical for the LTC691 and 200ms typical for the
LTC695. OSC IN selects between the 1.6 seconds and
100ms typical watchdog time-out periods. In both cases,
thetime-outperiodimmediatelyafteraresetis 1.6seconds
typical.
LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the V input. When V
CC
CC
falls below the reset voltage threshold (4.65V typically),
LOW LINE goes low. As soon as V rises above the reset
CC
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when V drops below VBATT (see
CC
Table 1).
WDI: Watchdog Input, WDI, is a three level input. Driving
WDI either high or low for longer than the watchdog time-
outperiod,forces bothRESETandWDOlow.FloatingWDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
6
LTC690/ LTC691
LTC694/ LTC695
U W
TYPICALPERFOR A CE CHARACTERISTICS
Power Failure Input Threshold
vs Temperature
VOUT vs IOUT
VOUT vs IOUT
2.80
2.78
2.76
2.74
2.72
1.308
1.306
5.00
V
= 5V
= 2.8V
V
= 0V
= 2.8V
V
CC
= 5V
CC
CC
V
V
BATT
BATT
T
= 25°
C
T = 25°C
A
A
4.95
4.90
1.304
1.302
1.300
1.298
1.296
1.294
SLOPE = 125Ω
SLOPE = 5Ω
4.85
4.80
4.75
0
100
200
300
400
500
–50 –25
0
25
50
TEMPERATURE (°C)
75
100 125
0
10
20
30
40
50
LOAD CURRENT (µA)
LOAD CURRENT (mA)
690 G02
690 G03
690 G01
Reset Active Time
vs Temperature LTC690-1
Reset Active Time
vs Temperature LTC694-5
Reset Voltage Threshold
vs Temperature
4.66
58
56
54
52
232
224
216
208
V
= 5V
V
= 5V
CC
CC
4.65
4.64
4.63
4.62
50
48
46
200
192
184
4.61
4.60
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50
25
75
–25
0
690 G06
690 G04
690 G05
Power-Fail Comparator
Response Time
Power-Fail Comparator
Response Time
Power-Fail Comparator Response
Time with Pull-Up Resistor
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
= 5V
= 25°C
V
= 5V
V
T
= 5V
= 25°C
CC
CC
CC
A
T
T
= 25
˚C
A
A
V
+
PFI
PFO
–
V
30pF
+
PFO
–
1.3V
PFI
5V
10k
30pF
1.3V
V
+
–
PFI
PFO
30pF
1.3V
1.305V
1.285V
1.315V
1.295V
1.315V
1.295V
V
= 20mV STEP
V
= 20mV STEP
V
= 20mV STEP
6
10
PFI
PFI
PFI
0
1
2
3
4
5
7
8
6
0
60
140
0
14
12 16 18
120
160 180
20 40
80 100
2
4
8
TIME (µs)
TIME (µs)
TIME (µs)
690 G07
690 G08
690 G09
7
LTC690/ LTC691
LTC694/ LTC695
O U
W
U
PPLICATI
A
S I FOR ATIO
Microprocessor Reset
the reset voltage threshold, LOW LINE goes low. LOW
LINE returns high as soon as VCC rises above the reset
voltage threshold.
The LTC690 family uses a bandgap voltage reference and
a precision voltage comparator C1 to monitor the 5V
supply input on V (see Block Diagram). When V falls
below the reset voltage threshold, the RESET output is
forced to active low state. The reset voltage threshold
CC
CC
Battery Switchover
The battery switchover circuit compares V to the V
input, and connects VOUT to whichever is higher. When
CC
BATT
accounts for a 5% variation on V , so the RESET output
CC
becomes active low when VCC falls below 4.75V (4.65V
typical). On power-up, the RESET signal is held active low
for a minimum of 35ms for the LTC690/LTC691 (140ms
for the LTC694/LTC695) after reset voltage threshold is
reached to allow the power supply and microprocessor to
stabilize.Theresetactivetimeis adjustableontheLTC691/
LTC695. On power-down, the RESET signal remains ac-
V
CC rises to 70mV above VBATT, the battery switchover
comparator, C2, connects VOUT to V through a charge
pumped NMOS power switch, M1. When V falls to
50mV above VBATT, C2 connects VOUT to VBATT through a
PMOS switch, M2. C2 has typically 20mV of hysteresis to
prevent spurious switching when V remains nearly
CC
CC
CC
equal to VBATT. The response time of C2 is approximately
20µs.
tive low even with V as low as 1V. This capability helps
CC
hold the microprocessor in stable shutdown condition.
Figure 1 shows the timing diagram of the RESET signal.
Duringnormaloperation,theLTC690familyuses acharge
pumped NMOS power switch to achieve low dropout and
low supply current. This power switch can deliver up to
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at V pin do not
CC
50mA to VOUT from V and has a typical on resistance of
CC
activate the RESET output. Response time is typically
10µs.Tohelppreventmistriggeringduetotransientloads,
5Ω. The VOUT pin should be bypassed with a capacitor of
0.1µF or greater to ensure stability. Use of a larger bypass
capacitor is advantageous for supplying current to heavy
transient loads.
V pinshouldbebypassedwitha0.1µFcapacitorwiththe
CC
leads trimmed as short as possible.
The LTC691 and LTC695 have two additional outputs:
RESET and LOW LINE. RESET is an active high output and
is the inverse of RESET. LOW LINE is the output of the
precision voltage comparator C1. When VCC falls below
When operating currents larger than 50mA are required
from VOUT, or a lower dropout (VCC-VOUT voltage differen-
tial) is desired, the LTC691 and LTC695 should be used.
These products provide BATT ON output to drive the base
V2
V2
V1
V1
V1 = RESET VOLTAGE THRESHOLD
V
CC
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
RESET
t
1
t
1
t
= RESET ACTIVE TIME
1
LOW LINE
690 F01
Figure 1. Reset Active Time
8
LTC690/ LTC691
LTC694/ LTC695
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ofexternalPNPtransistor(Figure2). Ifhighercurrents are
needed with the LTC690 and LTC694, a high current
size double layer capacitors, can be used for short term
memory back-up instead of a battery. The charging resis-
tor for both capacitors and rechargeable batteries should
be connected to VOUT since this eliminates the discharge
Schottky diode can be connected from the V pin to the
CC
VOUT pin to supply the extra current.
path that exists when the resistor is connected to V
(Figure 3).
CC
ANY PNP POWER TRANSISTOR
V
– V
BATT
R
OUT
5
I =
BATT ON
3
1
2
5V
0.1µF
V
OUT
V
CC
R
LTC691
LTC695
0.1µF
5V
0.1µF
V
V
CC
OUT
V
BATT
0.1µF
LTC690
LTC691
LTC694
LTC695
GND
4
3V
690 F02
V
BATT
GND
3V
Figure 2. Using BATT ON to Drive External PNP Transistor
690 F03
The LTC690 family is protected for safe area operation
with short-circuit limit. Output current is limited to ap-
proximately 200mA. If the device is overloaded for long
period of time, thermal shutdown turns the power switch
off until the device cools down. The threshhold tempera-
ture for thermal shutdown is approximately 155°C with
about 10°C of hysteresis which prevents the device from
oscillating in and out of shutdown.
Figure 3. Charging External Battery Through V
OUT
Replacing the Back-Up Battery
When changing the back-up battery with system power
on, spurious resets can occur while battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge up
the stray capacitance on the VBATT pin. The oscillation
cycle is as follows: When VBATT reaches within 50mV of
V , the LTC690 switches to battery back-up. VOUT pulls
BATT low and the device goes back to normal operation.
The leakage current then charges up the VBATT pin again
and the cycle repeats.
The PNP switch used in competitive devices was not
chosen for the internal power switch because it injects
unwanted current into the substrate. This current is col-
lected by the VBATT pin in competitive devices and adds to
the charging current of the battery which can damage
lithiumbatteries.TheLTC690familyuses achargepumped
NMOS power switch to eliminate unwanted charging
current while achieving low dropout and low supply cur-
rent. Since no current goes to the substrate, the current
collected by VBATT pin is strictly junction leakage.
CC
V
If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, a resistor
fromVBATT toGNDwillholdthepinlowwhilechangingthe
battery. For example, the battery standby current is 1µA
maximum over temperature and the external resistor
A 125Ω PMOS switch connects the VBATT input to VOUT in
battery back-up mode. The switch is designed for very low
dropoutvoltage(input-to-outputdifferential). This feature
is advantageous for low current applications such as
batteryback-upinCMOSRAMandotherlowpowerCMOS
circuitry. The supply current in battery back-up mode is
1µA maximum.
required to hold VBATT below V is:
CC
V – 50mV
CC
R ≤
1µA
With VCC = 4.5V, a 4.3M resistor will work. With a 3V
battery, this resistorwilldrawonly0.7µAfromthebattery,
which is negligible in most cases.
The operating voltage at the VBATT pin ranges from 2.0V to
4.25V. Highvaluecapacitors, suchas electrolyticorfarad-
9
LTC690/ LTC691
LTC694/ LTC695
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PPLICATI
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Ifbatteryconnections aremadethroughlongwires, a10Ω
to 100Ω series resistor and a 0.1µF capacitor are recom-
OUT is an alternative signal to drive the CE, CS, or Write
input of battery-backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.
mended to prevent any overshoot beyond V due to the
CC
lead inductance (Figure 4).
10Ω
V
BATT
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile
CMOS RAM application.
LTC690
LTC691
LTC694
LTC695
0.1µF
4.3M
GND
Memory protection can also be achieved with the LTC690
and LTC694 by using RESET as shown in Figure 7.
690 F04
Figure 4. 10Ω/0.1µF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL
STATUS
C2 monitors V for active switchover.
V
CC
CC
V
V
is connected to V
through an internal PMOS switch.
OUT
OUT
BATT
Table1shows thestateofeachpinduringbatteryback-up.
When the battery switchover section is not used, connect
V
BATT
The supply current is 1µA maximum.
BATT ON Logic high. The open-circuit output voltage is equal to V
.
OUT
VBATT to GND and VOUT to VCC.
PFI
Power failure input is ignored.
Logic low
PFO
Memory Protection
RESET
RESET
Logic low
The LTC691 and LTC695 include memory protection
circuitry that ensures the integrity of the data in memory
Logic high. The open-circuit output voltage is equal to V
.
OUT
LOW LINE Logic low
by preventing write operations when V is at invalid level.
Two additional pins, CE IN and CE OUT, control the Chip
WDI
Watchdog input is ignored.
Logic high. The open-circuit output voltage is equal to V
CC
WDO
.
.
OUT
Enable or Write inputs of CMOS RAM. When V is 5V, CE
CE IN
CE OUT
OSC IN
Chip Enable Input is ignored.
CC
Logic high. The open-circuit output voltage is equal to V
OUT follows CE IN with a typical propagation delay of
OUT
OSC IN is ignored.
20ns. When V falls below the reset voltage threshold or
CC
OSC SEL OSC SEL is ignored.
VBATT, CE OUT is forced high, independent of CE IN. CE
V2
V
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CC
V1
CE IN
V
= V
BATT
OUT
CE OUT
V
= V
OUT
BATT
690 F05
Figure 5. Timing Diagram for CE IN and CE OUT
10
LTC690/ LTC691
LTC694/ LTC695
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Power-Fail Warning
5V
V
V
V
CC
CC
OUT
+
0.1µF
0.1µF
LTC691
LTC695
62512
RAM
10µF
The LTC690 family generates a Power Failure Output
(PFO) for early warning of failure in the microprocessor's
power supply. This is accomplished by comparing the
Power Failure Input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulatedDCinputoraregulated5Voutput.Thevoltage
divider ratio can be chosen such that the voltage at the PFI
pin falls below 1.3V several milliseconds before the 5V
supply falls below the maximum reset voltage threshold
4.75V. PFO is normally used to interrupt the microproces-
sor to execute shutdown procedure between PFO and
RESET or RESET.
CE OUT
CS
20ns PROPAGATION DELAY
FROM DECODER
GND
V
BATT
CE IN
RESET
3V
GND
RESET
TO µP
690 F06
Figure 6. A Typical Nonvolatile CMOS RAM Application
5V
0.1µF
V
V
V
CC
OUT
CC
+
0.1µF
62128
RAM
10µF
LTC690
LTC694
CS
CS1
CS2
V
RESET
GND
BATT
3V
GND
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis-
tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
690 F07
Figure 7. Write Protect for RAM with LTC690 or LTC694
LT1086-5
V
≥ 7.5V
IN
5V
V
V
OUT
IN
V
CC
When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.
+
+
0.1µF
ADJ
10µF
100µF
LTC690/LTC691
LTC694/LTC695
R4
10k
R3
300k
R1
51k
PFO
R1 R1
GND
PFI
V =1.3V 1+
+
H
R2 R3
R2
10k
690 F08
TO µP
WhenPFOoutputis high,theseries combinationofR3and
R4 source current into the PFI summing junction.
Figure 8. Monitoring Unregulated DC Supply
with the LTC690's Power-Fail Comparator
R1 (5V –1.3V)R1
V =1.3V 1+
–
L
R2 1.3V(R3 +R4)
LT1086-5
5V
V
≥ 6.5V
IN
V
V
V
OUT
IN
CC
+
+
R1
R3
R4
10k
0.1µF
R1
27k
ADJ
10µF
10µF
Assuming R4 << R3,V
= 5V
LTC690/LTC691
LTC694/LTC695
HYSTERESIS
R3
2.7M
PFO
Example 1: The circuit in Figure 8 demonstrates the use of
the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
GND
PFI
R2
8.2k
1690 F09
TO µP
R5
3.3k
supplyinputV is 100mV/ms andthetotaltimetoexecute
IN
a shutdown procedure is 8ms. Also the noise of V is
IN
200mV. With these assumptions in mind, we can reason-
ably set V = 7.5V which 1.25V greater than the sum of
maximum reset voltage threshold and the dropout voltage
L
Figure 9. Monitoring Regulated DC Supply
with the LTC690's Power-Fail Comparator
11
LTC690/ LTC691
LTC694/ LTC695
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A
5V
of LT1086-5 (4.75V + 1.5V) and VHYSTERESIS = 850mV.
V
R1
CC
V
BATT
V
= 5V = 850V
LOW-BATTERY SIGNAL
TO µP I/O PIN
HYSTERESIS
PFO
R3
R1
1M
LTC691
LTC695
PFI
R3 ≈ 5.88 R1
R2
1M
3V
CE IN
I/O PIN
Choose R3 = 300k and R1 = 51k. Also select R4 = 10k
which is much smaller than R3.
CE OUT
GND
R
L
690 F10
20K
51k (5V –1.3V)51k
7.5V =1.3V 1+
–
OPTIONAL TEST LOAD
R2
1.3V(310k)
Figure 10. Back-Up Battery Monitor with Optional Test Load
R2 = 9.7kΩ, Choose nearest 5% resistor 10k and recalcu-
late V ,
L
Watchdog Timer
51k (5V – 1.3V)51k
V = 1.3V 1+
–
= 7.32V
The LTC690 family provides a watchdog timer function to
monitor the activity of the microprocessor. If the micro-
processor does not toggle the Watchdog Input (WDI)
within a seleced time-out period, RESET is forced to active
low for a minimum of 35ms for the LTC690/LTC691
(140ms for the LTC694/LTC695). The reset active time is
adjustable on the LTC691/LTC695. Since many systems
can not service the watchdog timer immediately after a
reset, the LTC691 and LTC695 have longer time-out
period (1.0 second minimum) right after a reset is issued.
The normal time-out period (70ms minimum) becomes
effective following the first transition of WDI after RESET
is inactive. The watchdog time-out period is fixed at 1.0
second minimum on the LTC690 and LTC694. Figure 11
shows the timing diagram of watchdog time-out period
and reset active time. The watchdog time-out period is
restartedas soonas RESETis inactive.Wheneitherahigh-
to-low or low-to-high transition occurs at the WDI pin
prior to time-out, the watchdog time is reset and begins to
timeoutagain. Toensurethewatchdogtimedoes nottime
out, either a high-to-low or low-to-high transition on the
WDI pin must occur at or less than the minimum time-out
period. If the input to the WDI pin remains either high or
low, reset pulses will be issued every 1.6 seconds typi-
cally.Thewatchdogtimecanbedeactivatedbyfloatingthe
L
10k
1.3V(310k)
51k 51k
V = 1.3V 1+
+
= 8.151V
H
10k 300k
(7.32V – 6.25V)
100mV/ms
= 10.7ms
VHYSTERESIS = 8.151V – 7.32V = 831mV
The 10.7ms allows enough time to execute shutdown
procedure for microprocessor and 831mV of hysteresis
would prevent PFO from going low due to the noise of V .
IN
Example 2: The circuit in Figure 9 can be used to measure
the regulated 5V supply to provide early warning of power
failure. Because of variations in the PFI threshold, this
circuit requires adjustment to ensure the PFI comparator
trips beforetheresetthresholdis reached. AdjustR5such
thatthePFOoutputgoes lowwhentheV supplyreaches
CC
the desired level (e.g., 4.85V).
Monitoring the Status of the Battery
C3 can also monitor the status of the memory back-up
battery (Figure 10). If desired, the CE OUT can be used to
applyatestloadtothebattery.SinceCEOUTis forcedhigh
in battery back-up mode, the test load will not be applied
to the battery while it is in use, even if the microprocessor
is not powered.
WDI pin. The timer is also disabled when V falls below
CC
the reset voltage threshold or V
.
BATT
12
LTC690/ LTC691
LTC694/ LTC695
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The LTC691 and LTC695 provide an additional output
(Watchdog Output, WDO) which goes low if the watchdog
timer is allowed to time out and remains low until set high
by the next transition on the WDI pin. WDO is also set high
GNDwhenOSCSELis forcedlow. Intheseconfigurations,
the nominal reset active time and watchdog time-out
period are determined by the number of clocks or set by
the formula in Table 2. When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 35ms minimum for the LTC691 and 140ms
minimum for the LTC695. OSC IN selectes between the 1
second and 70ms minimum normal watchdog time-out
periods. In both cases, the time-out period immediately
after a reset is at least 1 second.
when V falls below the reset voltage threshold or V
.
CC
BATT
TheLTC691andLTC695havetwoadditonalpins OSCSEL
and OSC IN, which allow reset active time and watchdog
time-out period to be adjusted per Table 2. Several con-
figurations are shown in Figure 12.
OSC IN can be driven by an external clock signal or an
external capacitor can be connected between OSC IN and
V
= 5V
CC
WDI
t
t
t
= RESET ACTIVE TIME
1
2
3
= NORMAL WATCHDOG TIME-OUT PERIOD
= WATCHDOG TIME-OUT PERIOD IMMEDIATELY
AFTER A RESET
WDO
t
t
3
2
RESET
t
t
1
1
690 F11
Figure 11. Watchdog Time-Out Period and Reset Active Time
EXTERNAL OSCILLATOR
EXTERNAL CLOCK
3
8
7
8
3
4
V
OSC SEL
5V
5V
V
OSC SEL
CC
CC
LTC691
LTC695
LTC691
LTC695
7
4
GND
OSC IN
GND
OSC IN
INTERNAL OSCILLATOR
1.6 SECOND WATCHDOG
INTERNAL OSCILLATOR
100ms WATCHDOG
3
8
3
8
7
FLOATING
OR HIGH
FLOATING
OR HIGH
5V
5V
V
OSC SEL
V
OSC SEL
CC
CC
LTC691
LTC695
LTC691
LTC695
4
7
FLOATING
OR HIGH
4
GND
OSC IN
GND
OSC IN
690 F12
Figure 12. Oscillator Configurations
13
LTC690/ LTC691
LTC694/ LTC695
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Table 2. LTC691 and LTC695 Reset Active Time and Watchdog Time-Out Selections
WATCHDOG TIME-OUT PERIOD
RESET ACTIVE TIME
IMMEDIATELY
AFTER RESET
(Long Period)
NORMAL
(Short Period)
OSC SEL
OSC IN
LTC691
LTC695
Low
Low
External Clock Input
External Capacitor*
1024 clks
400ms
70pF
4096 clks
512 clks
200ms
70pF
2048 clks
800ms
70pF
1.6 sec
• C
• C
• C
• C
70pF
Floating or High
Floating or High
Low
Floating or High
100ms
1.6 sec
1.6 sec
1.6 sec
50ms
50ms
200ms
200ms
184,000
C(pF) • 1025
*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is f
(Hz) =
OSC
Push-Button Reset
TheLTC690familydoes notprovidealogicinputfordirect
V
5V
RESET
RESET
CC
connection to a pushbutton. However, a push-button in
series witha100ΩresistorconnectedtotheRESEToutput
pin (Figure 13) provides an alternative for manual reset.
Connecting a 0.1µF capacitor to the RESET pin debounces
the push-button input.
100Ω
0.1µF
MPU
(e.g. 6805)
LTC690/LTC691
LTC694/LTC695
690 F13
GND
The 100Ω resistor in series with the push-button is
required to prevent the ringing, due to the capacitance and
lead inductance, from pulling the RESET pins of the MPU
and LTC69X below ground.
Figure 13. The External Push-Button Reset
V
5V
RESET
LTC1235
RESET
CC
If a dedicated pushbutton reset input is desired, the
LTC1235 is a good choice (Figure 14). It has all the
functions of the LTC695 and provides push-button reset
as anextrafeature.Its push-buttonis internallydebounced
and invokes the normal 200ms reset sequence. This
eliminates the need for the 100Ω resistor and 0.1µF
capacitor. It also provides a more consistent reset pulse.
MPU
(e.g. 6805)
PBRST
GND
690 F14
Figure 14. The External Push-Button Reset with the LTC1235
14
LTC690/ LTC691
LTC694/ LTC695
U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.
J8 Package 8-Lead CERDIP (Narrow 0.300, Hermetic) (LTC DWG # 05-08-1110)
0.405
(10.287)
MAX
0.005
(5.080) (0.127)
0.200
0.300 BSC
CORNER LEADS OPTION
(4 PLCS)
(0.762 BSC)
MIN
MAX
6
5
8
7
0.015 – 0.060
(0.381 – 1.524)
0.023 – 0.045
0.025
0.220 – 0.310
(0.584 – 1.143)
HALF LEAD
OPTION
(0.635)
RAD TYP
(5.588 – 7.874)
0.008 – 0.018
0° – 15°
0.045 – 0.068
(0.203 – 0.457)
(1.143 – 1.727)
FULL LEAD
OPTION
J8 1197
1
2
3
4
0.045 – 0.068
0.125
(1.143 – 1.727)
3.175
MIN
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
0.100 ± 0.010
0.014 – 0.026
(2.540 ± 0.254)
(0.360 – 0.660)
N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
8
7
6
5
0.065
(1.651)
TYP
0.255 ± 0.015*
(6.477 ± 0.381)
0.009 – 0.015
0.125
(0.229 – 0.381)
0.020
(3.175)
MIN
+0.035
–0.015
(0.508)
MIN
1
2
4
3
0.325
N8 1197
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
+0.889
–0.381
8.255
(
)
(0.457 ± 0.076)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
7
5
8
6
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
SO8 0996
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
0.300 – 0.325
0.130 ± 0.005
0.045 – 0.065
(7.620 – 8.255)
(3.302 ± 0.127)
(1.143 – 1.651)
14
12
10
9
15
13
11
16
0.020
(0.508)
MIN
0.255 ± 0.015*
(6.477 ± 0.381)
0.065
0.009 – 0.015
(1.651)
TYP
(0.229 – 0.381)
+0.035
–0.015
2
1
3
4
6
8
5
7
0.325
0.125
0.018 ± 0.003
0.100 ± 0.010
(2.540 ± 0.254)
N16 1197
+0.889
–0.381
(3.175)
MIN
(0.457 ± 0.076)
8.255
(
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
15
LTC690/ LTC691
LTC694/ LTC695
U
O
TYPICAL APPLICATI S
Capacitor Back-Up with 74HC4016 Switch
Write Protect for Additional RAMs
5V
V
V
CC
V
OUT
CC
5V
+
V
V
CC
0.1µF
62512
RAM A
OUT
LTC691
LTC695
0.1µF
10µF
0.1µF
0.1µF
10 11 12 14
LTC691
LTC695
CS
CE OUT
R1
10k
20ns PROPAGATION
DELAY
V
BATT
2
1
LOW LINE
V
74HC4016
7
CE IN
CS A
BATT
3V
LOW LINE
R2
30k
13
100µF
GND
+
GND
V
CC
0.1µF
0.1µF
62128
RAM B
LTC690 TA03
CS B
CS1
CS2
V
CC
62128
RAM C
CS1
CS C
CS2
OPTIONAL CONNECTION FOR
ADDITIONAL RAMs
690 TA04
U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.291 – 0.299**
(7.391 – 7.595)
0.398 – 0.413*
(10.109 – 10.490)
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
15 14
12
10
9
16
13
11
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
TYP
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.014 – 0.019
0.004 – 0.012
(0.102 – 0.305)
0.016 – 0.050
(0.356 – 0.482)
TYP
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S16 (WIDE) 0396
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
2
3
5
7
8
1
4
6
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
4.725V, 3.118V, 1V Thresholds (±0.75%)
Meets PCI t Timing Specifications
LTC1326
Micropower Precision Triple Supply Monitor
Micropower Triple Supply Monitor for PCI Applications
LTC1536
FAIL
690fc LT/TP 0399 2K REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1992
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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