LTM4603HVIV#PBF_技术文档

LTM4603HV

6A, 28V DC/DC µModule

IN

with PLL, Output Tracking

and Margining

DescripTion

FeaTures

TheLTM^®4603HVisacomplete6Astep-downswitchmode

DC/DC power supply with onboard switching controller,

MOSFETs, inductor and all support components. The

µModule^TMis housed in a small surface mount 15mm ×

15mm × 2.82mm LGA package. Operating over an input

voltage range of 4.5 to 28V, the LTM4603HV supports

an output voltage range of 0.6V to 5V as well as output

voltagetrackingandmargining.Thehighefficiencydesign

delivers 6A continuous current (8A peak). Only bulk input

and output capacitors are needed to complete the design.

n

Complete Switch Mode Power Supply

n

Wide Input Voltage Range: 4.5V to 28V

n

6A DC Typical, 8A Peak Output Current

n

0.6V to 5V Output Voltage

n

Output Voltage Tracking and Margining

n

Remote Sensing for Precision Regulation

n

Typical Operating Frequency: 1MHz

n

PLL Frequency Synchronization

n

1.5% Regulation

n

Current Foldback Protection (Disabled at Start-Up)

n

Pin Compatible with the LTM4601/LTM4601HV/

The low profile (2.82mm) and light weight (1.7g) package

easily mounts on the unused space on the back side of

PC boards for high density point of load regulation. The

µModule can be synchronized with an external clock for

reducing undesirable frequency harmonics and allows

PolyPhase^®operation for high load currents.

LTM4603

n

Ultrafast Transient Response

n

Current Mode Control

n

Up to 93% Efficiency at 5V , 3.3V

IN

OUT

n

Programmable Soft-Start

Output Overvoltage Protection

A high switching frequency and adaptive on-time current

mode architecture deliver a very fast transient response

to line and load changes without sacrificing stability. An

onboard remote sense amplifier can be used to accurately

regulate an output voltage independent of load current.

L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule and PolyPhase are registered

trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patents including

5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210.

RoHS Compliant Package with Gold Finish Pads (e4)

Small Footprint, Low Profile (15mm × 15mm ×

2.82mm) Surface Mount LGA Package

applicaTions

n

Telecom and Networking Equipment

n

Servers

n

Industrial Equipment

Point of Load Regulation

n

Typical applicaTion

2.5V/6A with 4.5V to 28V Input µModule Regulator

Efficiency vs Load Current with 24V_IN

100

CLOCK SYNC

TRACK/SS CONTROL

V

IN

4.5V TO 28V

90

80

70

60

V

PLLIN TRACK/SS

V

2.5V

6A

IN

OUT

PGOOD

V

OUT

100pF

V

FB

ON/OFF

RUN

COMP

INTV

DRV

MARG0

MARG1

V

OUT_LCL

MARGIN

CONTROL

C

OUT

LTM4603HV

C

IN

CC

R

SET

19.1k

DIFFV

CC

MPGM

OUT

+

V

24V , 1.8V

IN

OSNS

OUT

–

24V , 2.5V

IN

50

40

OSNS

R1

392k

24V , 3.3V

IN

f

SGND PGND

SET

24V , 5V

IN

OUT

5% MARGIN

0

1

2

3

4

5

6

7

4603HV TA01a

LOAD CURRENT (A)

4603HV TA01b

4603hvfa

1

For more information www.linear.com/LTM4603HV

LTM4603HV

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

TOP VIEW

INTV , DRV , V

, V

(V

≤ 3.3V

CC

CC OUT_LCL OUT OUT

with Remote Sense Amp)............................. –0.3V to 6V

PLLIN, TRACK/SS, MPGM, MARG0, MARG1,

PGOOD, f

..............................–0.3V to INTV + 0.3V

SET

CC

V

f

IN

SET

MARG0

MARG1

DRV

RUN ............................................................. –0.3V to 5V

V , COMP................................................ –0.3V to 2.7V

FB

CC

V ............................................................. –0.3V to 28V

V

IN

OSNS

FB

PGND

+

–

PGOOD

V

, V

..........................–0.3V to INTV + 0.3V

OSNS CC

SGND

+

Operating Temperature Range (Note 2)....–40°C to 85°C

Junction Temperature ........................................... 125°C

Storage Temperature Range .................. –55°C to 125°C

V

OSNS

DIFFV

V

OUT

V

OUT

OUT_LCL

–

OSNS

LGA PACKAGE

118-LEAD (15mm × 15mm × 2.82mm)

T

JMAX

= 125°C, θ = 15°C/W, θ = 6°C/W θ DERIVED FROM 95mm × 76mm PCB WITH 4

JA

JC

JA

LAYERS, WEIGHT = 1.7g

orDer inForMaTion

PART MARKING*

PACKAGE

TYPE

MSL

RATING

TEMPERATURE RANGE

(SEE NOTE 2)

PART NUMBER

PAD OR BALL FINISH

DEVICE

FINISH CODE

LTM4603HVEV#PBF

LTM4603HVIV#PBF

Au (RoHS)

LTM4603HVV

e4

LGA

3

–40°C to 85°C

•ꢀ Consult Marketing for parts specified with wider operating temperature

ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.

•ꢀ Recommended LGA and BGA PCB Assembly and Manufacturing

Procedures: www.linear.com/umodule/pcbassembly

•ꢀ LGA and BGA Package and Tray Drawings: www.linear.com/packaging

•ꢀ Terminal Finish Part Marking: www.linear.com/leadfree

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range (Note 2), otherwise specifications are at T_A= 25°C, V_IN= 12V, per typical application (front page) configuration,

R_SET= 40.2k.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Input DC Voltage

Output Voltage

4.5

28

V

IN(DC)

C

= 10µF ×2, C

= 2× 100µF X5R Ceramic

OUT(DC)

IN

OUT

l

V

= 5V, V

= 1.5V, I = 0A

OUT

1.478

1.5

1.522

V

IN

OUT

= 12V, V

= 1.5V, I

= 0A

OUT

Input Specifications

V

Undervoltage Lockout Threshold

Input Inrush Current at Startup

I

= 0A

3.2

4

V

IN(UVLO)

OUT

I

= 0A. V

= 1.5V

OUT

INRUSH(VIN)

V

= 5V

= 12V

0.6

0.7

A

IN

V

4603hvfa

2

For more information www.linear.com/LTM4603HV

LTM4603HV

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range (Note 2), otherwise specifications are at T_A= 25°C, V_IN= 12V, per typical application (front page) configuration,

R_SET= 40.2k.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Input Supply Bias Current

V

= 12V, No Switching

3.8

25

mA

µA

Q(VIN,NOLOAD)

IN

= 12V, V

= 1.5V, Switching Continuous

OUT

= 5V, No Switching

= 5V, V = 1.5V, Switching Continuous

2.5

43

OUT

Shutdown, RUN = 0, V = 12V

22

IN

I

Input Supply Current

V

IN

V

IN

V

IN

= 12V, V

= 1.5V, I

= 3.3V, I

= 6A

0.92

1.83

2.12

A

S(VIN)

OUT

= 5V, V

= 1.5V, I

= 6A

OUT

INTV

V

= 12V, RUN > 2V

No Load

4.7

0

5

5.3

V

CC

IN

Output Specifications

I

Output Continuous Current Range

Line Regulation Accuracy

V

= 12V, V = 1.5V (Note 5)

OUT

6

A

OUTDC

IN

l

ΔV

= 1.5V, I

= 0A, V = 4.5V to 28V

0.3

%

OUT(LINE)

OUT

IN

V

OUT

OUT(LOAD)

ΔV

Load Regulation Accuracy

Output Ripple Voltage

V

= 1.5V, I

= 0A to 6A, V = 12V with

0.25

%

OUT

IN

Remote Sense Amp (Note 5)

V

OUT

OUT(AC)

V

I

= 0A, C

= 2× 100µF X5R Ceramic

OUT

V

= 12V, V

= 1.5V

10

mV

IN

OUT

P-P

V

= 5V, V

= 1.5V

OUT

f

Output Ripple Voltage Frequency

Turn-On Overshoot

I

= 3A, V = 12V, V

= 1.5V

1000

kHz

S

OUT

IN

OUT

ΔV

C

V

= 200µF

OUT(START)

OUT

V

= 1.5V, I

= 0A, TRACK/SS = 10nF

OUT

= 12V

= 5V

20

mV

IN

V

t

Turn-On Time

C

V

= 200µF, TRACK/SS = Open

OUT

START

= 1.5V, I

= 1A Resistive Load

OUT

V

= 12V

= 5V

0.5

ms

IN

V

ΔV

Peak Deviation for Dynamic Load

Load: 0% to 50% to 0% of Full Load,

= 2× 22µF Ceramic, 470µF 4V Sanyo

OUTLS

C

OUT

POSCAP

V

IN

V

IN

= 12V

= 5V

35

mV

t

I

Settling Time for Dynamic Load Step Load: 0% to 50% to 10% of Full Load

SETTLE

V

= 12V

25

µs

IN

Output Current Limit

C

= 2× 100µF X5R Ceramic

OUTPK

OUT

V

= 12V, V

= 1.5V

8

A

IN

OUT

= 1.5V

OUT

V

= 5V, V

Remote Sense Amp (Note 3)

+

–

V

, V

Common Mode Input Voltage Range

V

= 12V, RUN > 2V

0

INTV – 1

V

OSNS

IN

CC

CM Range

DIFFV Range

Output Voltage Range

Input Offset Voltage Magnitude

Differential Gain

= 12V, DIFFV

Load = 100k

INTV – 1

V

mV

OUT

IN

OUT

CC

V

OS

1.25

AV

1

3

V/V

MHz

V/µs

kW

GBP

SR

Gain Bandwidth Product

Slew Rate

2

+

R

Input Resistance

V

to GND

20

100

IN

OSNS

CMRR

Common Mode Rejection Ratio

dB

4603hvfa

3

For more information www.linear.com/LTM4603HV

LTM4603HV

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range (Note 2), otherwise specifications are at T_A= 25°C, V_IN= 12V, per typical application (front page) configuration,

R_SET= 40.2k.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Control Stage

l

V

Error Amplifier Input Voltage

Accuracy

I

= 0A, V = 1.5V

OUT

0.594

0.6

0.606

V

FB

OUT

V

RUN Pin On/Off Threshold

Soft-Start Charging Current

Minimum On Time

1

1.5

–1.5

50

1.9

–2

V

µA

ns

kW

mA

kW

V

RUN

I

t

V

= 0V

TRACK/SS

–1

TRACK/SS

ON(MIN)

OFF(MIN)

(Note 4)

100

400

Minimum Off Time

250

50

R

PLLIN Input Resistance

PLLIN

I

Current into DRV Pin

V

= 1.5V, I

= 1A, DRV = 5V

18

25

DRVCC

CC

OUT

CC

R

Resistor Between V

and V

FB

60.098

60.4

1.18

1.4

60.702

FBHI

OUT_LCL

V

Margin Reference Voltage

MPGM

, V

MARG0, MARG1 Voltage Thresholds

V

MARG0 MARG1

PGOOD Output

ΔV

PGOOD Upper Threshold

PGOOD Lower Threshold

PGOOD Hysteresis

V

Rising

Falling

7

10

–10

1.5

13

–13

3

%

V

FBH

FB

–7

FBL

FB

Returning (Note 4)

FB(HYS)

FB

V

PGOOD Low Voltage

I

= 5mA

0.15

0.4

PGL

PGOOD

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTM4603HV is tested under pulsed load conditions such

that T ≈ T . The LTM4603HVEV is guaranteed to meet performance

specifications from 0°C to 85°C. Specifications over the –40°C to 85°C

operating temperature range are assured by design, characterization

and correlation with statistical process controls. The LTM4603HVIV is

guaranteed over the –40°C to 85°C operating temperature range.

J

A

Note 3: Remote sense amplifier recommended for ≤3.3V output.

Note 4: 100% tested at die level only.

Note 5: See output current derating curves for different V , V

and T .

IN OUT

A

4603hvfa

4

For more information www.linear.com/LTM4603HV

LTM4603HV

Typical perForMance characTerisTics

(See Figure 20 for all curves)

Efficiency vs Load Current

with 24V_IN

Efficiency vs Load Current

with 5V_IN

Efficiency vs Load Current

with 12V_IN

100

90

80

70

60

50

40

100

90

80

70

60

50

40

100

90

80

70

12V , 1.2V

5V , 0.6V

IN

OUT

IN

OUT

60

50

40

12V , 1.5V

IN

5V , 1.2V

IN

24V , 1.8V

IN

12V , 1.8V

IN

5V , 1.5V

IN

OUT

24V , 2.5V

IN

12V , 2.5V

IN

5V , 1.8V

IN

24V , 3.3V

IN

12V , 3.3V

5V , 2.5V

IN

24V , 5V

OUT

12V , 5V

5V , 3.3V

IN

OUT

4

6

7

0

1

2

3

5

0

2

3

4

5

6

7

4

7

1

0

2

3

5

6

1

LOAD CURRENT (A)

4603HV G03

4603HV G01

4603HV G02

1.2V Transient Response

1.5V Transient Response

1.8V Transient Response

LOAD STEP

1A/DIV

LOAD STEP

1A/DIV

LOAD STEP

1A/DIV

V

OUT

50mV/DIV

4603HV G05

4603HV G04

4603HV G06

25µs/DIV

1.5V AT 3A/µs LOAD STEP

1.2V AT 3A/µs LOAD STEP

1.8V AT 3A/µs LOAD STEP

C

: 1x 22µF, 6.3V CERAMIC

C

: 1x 22µF, 6.3V CERAMIC

C

: 1x 22µF, 6.3V CERAMIC

OUT

1x 330µF, 4V SANYO POSCAP

2.5V Transient Response

3.3V Transient Response

LOAD STEP

1A/DIV

LOAD STEP

1A/DIV

V

OUT

50mV/DIV

OUT

50mV/DIV

4603HV G07

4603HV G08

25µs/DIV

2.5V AT 3A/µs LOAD STEP

3.3V AT 3A/µs LOAD STEP

C

: 1x 22µF, 6.3V CERAMIC

C

: 1x 22µF, 6.3V CERAMIC

OUT

1x 330µF, 4V SANYO POSCAP

4603hvfa

5

For more information www.linear.com/LTM4603HV

LTM4603HV

Typical perForMance characTerisTics _{(See Figure 20 for all curves)}

Start-Up, I_OUT= 6A

(Resistive Load)

Short-Circuit Protection,

I_OUT= 0A

Start-Up, I_OUT= 0A

V

OUT

0.5V/DIV

OUT

0.5V/DIV

I

IN

I

0.5A/DIV

IN

I

IN

2A/DIV

0.5A/DIV

4603HV G09

4603HV G10

4603HV G11

1ms/DIV

V

C

= 12V

OUT

1ms/DIV

100µs/DIV

V

C

= 12V

OUT

V

C

= 12V

IN

OUT

IN

= 1.5V

= 1x 22µF, 6.3V CERAMIC

1x 330µF, 4V SANYO POSCAP

SOFT-START = 3.9nF

Short-Circuit Protection,

_OUT= 6A

I

V_INto V_OUTStep-Down Ratio

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.3V OUTPUT WITH

82.5k FROM V

OUT

TO f

SET

V

OUT

5V OUTPUT WITH

150k RESISTOR

0.5V/DIV

ADDED FROM f

TO GND

SET

5V OUTPUT WITH

NO RESISTOR ADDED

FROM f

TO GND

I

IN

SET

2A/DIV

2.5V OUTPUT

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

4603 G12

100µs/DIV

V

C

= 12V

OUT

IN

= 1.5V

= 1x 22µF, 6.3V CERAMIC

1x 330µF, 4V SANYO POSCAP

0

4

8

12

16

20

24

28

SOFT-START = 3.9nF

INPUT VOLTAGE (V)

4603HV G13

4603hvfa

6

For more information www.linear.com/LTM4603HV

LTM4603HV

pin FuncTions ^{(See Package Description for Pin Assignment)}

V (Bank 1): Power Input Pins. Apply input voltage be-

INTV (Pin A7): This pin is for additional decoupling of

IN

CC

tween these pins and PGND pins. Recommend placing

the 5V internal regulator.

input decoupling capacitance directly between V pins

IN

PLLIN (Pin A8): External Clock Synchronization Input

to the Phase Detector. This pin is internally terminated

to SGND with a 50k resistor. Apply a clock with a high

and PGND pins.

V

OUT

(Bank 3): Power Output Pins. Apply output load

between these pins and PGND pins. Recommend placing

outputdecouplingcapacitancedirectlybetweenthesepins

and PGND pins. See Figure 17.

level above 2V and below INTV . See the Applications

CC

Information section.

TRACK/SS (Pin A9): Output Voltage Tracking and Soft-

Start Pin. When the module is configured as a master

output, then a soft-start capacitor is placed on this pin

to ground to control the master ramp rate. A soft-start

capacitor can be used for soft-start turn on as a stand

alone regulator. Slave operation is performed by putting

a resistor divider from the master output to ground, and

connecting the center point of the divider to this pin. See

the Applications Information section.

PGND (Bank 2): Power ground pins for both input and

output returns.

–

V

OSNS

(Pin M12): (–) Input to the Remote Sense Ampli-

fier. This pin connects to the ground remote sense point.

The remote sense amplifier is used for V

to INTV if not used.

≤3.3V. Tie

OUT

CC

+

V

(Pin J12): (+) Input to the Remote Sense Ampli-

OSNS

fier. This pin connects to the output remote sense point.

The remote sense amplifier is used for V

to ground if not used.

MPGM (Pin A12): Programmable Margining Input. A re-

sistor from this pin to ground sets a current that is equal

to 1.18V/R. This current multiplied by 10kΩ will equal a

value in millivolts that is a percentage of the 0.6V refer-

ence voltage. See the Applications Information section. To

parallel LTM4603HVs, each requires an individual MPGM

resistor. Do not tie MPGM pins together.

≤3.3V. Tie

OUT

DIFFV (PinK12):OutputoftheRemoteSenseAmplifier.

OUT

This pin connects to the V

remote sense amplifier is not used.

pin. Leave floating if

OUT_LCL

DRV (Pin E12): This pin normally connects to INTV

CC

for powering the internal MOSFET drivers. This pin can

be biased up to 6V from an external supply with about

50mA capability, or an external circuit shown in Figure

18. This improves efficiency at the higher input voltages

by reducing power dissipation in the module.

f

(Pin B12): Frequency Set Internally to 1MHz. An

SET

external resistor can be placed from this pin to ground

to increase frequency. See the Applications Information

section for frequency adjustment.

TOP VIEW

V

IN

f

SET

MARG0

MARG1

DRV

CC

V

FB

PGND

PGOOD

SGND

+

V

OSNS

DIFFV

V

OUT

V

OUT

OUT_LCL

–

V

OSNS

LGA PACKAGE

118-LEAD (15mm × 15mm × 2.82mm)

4603hvfa

7

For more information www.linear.com/LTM4603HV

LTM4603HV

pin FuncTions ^{(See Package Description for Pin Assignment)}

V

(Pin F12): The Negative Input of the Error Amplifier.

COMP (Pin A11): Current Control Threshold and Error

Amplifier Compensation Point. The current comparator

threshold increases with this control voltage. The voltage

ranges from 0V to 2.4V with 0.7V corresponding to zero

sense voltage (zero current).

FB

Internally, this pin is connected to V

with a 60.4k

OUT_LCL

precision resistor. Different output voltages can be pro-

grammed with an additional resistor between V and

FB

SGND pins. See the Applications Information section.

MARG0 (Pin C12): This pin is the LSB logic input for the

margining function. Together with the MARG1 pin will

determine if margin high, margin low or no margin state

is applied. The pin has an internal pull-down resistor of

50k. See the Applications Information section.

PGOOD (Pin G12): Output Voltage Power Good Indicator.

Open-drain logic output that is pulled to ground when the

output voltage is not within 10% of the regulation point,

after a 25µs power bad mask timer expires.

RUN (Pin A10): Run Control Pin. A voltage above 1.9V

will turn on the module, and when below 1V, will turn

off the module. A programmable UVLO function can be

accomplished by connecting to a resistor divider from

MARG1 (Pin D12): This pin is the MSB logic input for the

margining function. Together with the MARG0 pin will

determine if margin high, margin low or no margin state

is applied. The pin has an internal pull-down resistor of

50k. See the Applications Information section.

V to ground. See Figure 1. This pin has a 5.1V Zener to

IN

ground. Maximum pin voltage is 5V. Limit current into

the RUN pin to less than 1mA.

SGND (Pin H12): Signal Ground. This pin connects to

PGND at output capacitor point.

V

(Pin L12): V

connects directly to this pin to

OUT

OUT_LCL

bypass the remote sense amplifier, or DIFFV

connects

OUT

to this pin when remote sense amplifier is used.

4603hvfa

8

For more information www.linear.com/LTM4603HV

LTM4603HV

block DiagraM

V

1M

OUT_LCL

V

IN

V

OUT

>1.9V = ON

<1V = OFF

MAX = 5V

R1

R2

RUN

PGOOD

COMP

UVLO

FUNCTION

V

IN

4.5V TO 28V

+

5.1V

ZENER

1.5µF

C

IN

60.4k

INTERNAL

COMP

POWER CONTROL

Q1

Q2

SGND

V

2.5V

6A

OUT

MARG1

MARG0

22µF

V

FB

50k 50k

+

f

SET

R

SET

C

OUT

19.1k

33.2k

2.2Ω

INTV

PGND

MPGM

TRACK/SS

PLLIN

CC

10k

C

SS

–

+

10k

V

OSNS

–

+

50k

10k

4.7µF

INTV

DRV

CC

10k

CC

DIFFV

OUT

4603HV F01

Figure 1. Simplified LTM4603HV Block Diagram

T_A= 25°C. Use Figure 1 configuration.

CONDITIONS

Decoupling requireMenTs

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

C

IN

External Input Capacitor Requirement

I

= 6A

20

µF

OUT

(V = 4.5V to 28V, V

= 2.5V)

IN

OUT

C

OUT

External Output Capacitor Requirement

(V = 4.5V to 28V, V = 2.5V)

I

= 6A

100

200

µF

OUT

IN

OUT

4603hvfa

9

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LTM4603HV

operaTion

Power Module Description

in an overvoltage condition, internal top FET Q1 is turned

off and bottom FET Q2 is turned on and held on until the

overvoltage condition clears.

The LTM4603HV is a standalone nonisolated switching

mode DC/DC power supply. It can deliver up to 6A of DC

output current with few external input and output capaci-

tors.Thismoduleprovidespreciselyregulatedoutputvolt-

Pulling the RUN pin below 1V forces the controller into its

shutdown state, turning off both Q1 and Q2. At low load

current, the module works in continuous current mode by

default to achieve minimum output voltage ripple.

ageprogrammableviaoneexternalresistorfrom0.6V to

DC

5.0V over a 4.5V to 28V wide input voltage. The typical

DC

application schematic is shown in Figure 20.

When DRV pin is connected to INTV an integrated

CC

The LTM4603HV has an integrated constant on-time

current mode regulator, ultralow R

5V linear regulator powers the internal gate drivers. If a

FETs with fast

5V external bias supply is applied on the DRV pin, then

DS(ON)

CC

switching speed and integrated Schottky diodes. The typi-

cal switching frequency is 1MHz at full load. With current

mode control and internal feedback loop compensation,

the LTM4603HV module has sufficient stability margins

and good transient performance under a wide range of

operating conditions and with a wide range of output

capacitors, even all ceramic output capacitors.

an efficiency improvement will occur due to the reduced

powerlossintheinternallinearregulator.Thisisespecially

true at the higher input voltage range.

The LTM4603HV has a very accurate differential remote

sense amplifier with very low offset. This provides for

very accurate output voltage sensing at the load. The

MPGM pin, MARG0 pin and MARG1 pin are used to sup-

port voltage margining, where the percentage of margin

is programmed by the MPGM pin, and the MARG0 and

MARG1 select margining.

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limit. Besides, foldback current limiting is provided in an

overcurrent condition while V drops. Internal overvolt-

FB

age and undervoltage comparators pull the open-drain

PGOOD output low if the output feedback voltage exits a

10% window around the regulation point. Furthermore,

The PLLIN pin provides frequency synchronization of the

device to an external clock. The TRACK/SS pin is used

for power supply tracking and soft-start programming.

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The typical LTM4603HV application circuit is shown in

Figure 20. External component selection is primarily

determined by the maximum load current and output

voltage. Refer to Table 2 for specific external capacitor

requirements for a particular application.

where %V

is the percentage of V

OUT(MARGIN)

you want to

OUT

margin, and V

OUT

is the margin quantity in volts:

V_OUT

1.18V

R_PGM

=

•

•10k

0.6V V_OUT(MARGIN)

where R

is the resistor value to place on the MPGM

PGM

pin to ground.

V to V

Step-Down Ratios

OUT

IN

There are restrictions in the maximum V and V

step

IN

OUT

The margining voltage, V

, will be added or

OUT(MARGIN)

down ratio that can be achieved for a given input voltage.

subtractedfromthenominaloutputvoltageasdetermined

by the state of the MARG0 and MARG1 pins. See the truth

table below:

These constraints are shown in the Typical Performance

Characteristics curves labeled V to V

Step-Down

OUT

IN

Ratio.Notethatadditionalthermalderatingmayapply.See

the Thermal Considerations and Output Current Derating

section of this data sheet.

MARG1

LOW

MARG0

LOW

MODE

NO MARGIN

MARGIN UP

MARGIN DOWN

NO MARGIN

LOW

HIGH

LOW

Output Voltage Programming and Margining

HIGH

ThePWMcontrollerhasaninternal0.6Vreferencevoltage.

As shown in the Block Diagram, a 1M and a 60.4k 0.5%

Input Capacitors

internal feedback resistor connects V

together. The V

and V pins

OUT

FB

pin is connected between the 1M

LTM4603HV module should be connected to a low AC

impedance DC source. Input capacitors are required to

be placed adjacent to the module. In Figure 20, the 10µF

ceramic input capacitors are selected for their ability to

handle the large RMS current into the converter. An input

bulkcapacitorof100µFisoptional.This100µFcapacitoris

onlyneedediftheinputsourceimpedanceiscompromised

by long inductive leads or traces.

OUT_LCL

and the 60.4k resistor. The 1M resistor is used to protect

against an output overvoltage condition if the V

OUT_LCL

pin is not connected to the output, or if the remote sense

amplifier output is not connected to V

. The output

OUT_LCL

voltage will default to 0.6V. Adding a resistor R

from

SET

the V pin to SGND pin programs the output voltage:

FB

60.4k+R_SET

V_OUT= 0.6V

For a buck converter, the switching duty-cycle can be

estimated as:

R_SET

Table 1. R_SETStandard 1% Resistor Values vs V_OUT

V_OUT

D =

R

SET

Open 60.4

0.6 1.2

40.2

1.5

30.1

1.8

25.5

2

19.1

2.5

13.3

3.3

8.25

5

V

IN

(kW)

V

OUT

Without considering the inductor ripple current, the RMS

current of the input capacitor can be estimated as:

(V)

The MPGM pin programs a current that when multiplied

by an internal 10k resistor sets up the 0.6V reference

offset for margining. A 1.18V reference divided by the

I_OUT(MAX)

I_CIN(RMS)

=

• D•(1−D)

η%

R

resistor on the MPGM pin programs the current.

PGM

In the above equation, η% is the estimated efficiency of

Calculate V

:

OUT(MARGIN)

the power module. C can be a switcher-rated electrolytic

IN

aluminum capacitor, OS-CON capacitor or high value ce-

ramic capacitor. Note the capacitor ripple current ratings

%V_OUT

100

V_OUT(MARGIN)

=

• V_OUT

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are often based on temperature and hours of life. This

makes it advisable to properly derate the input capacitor,

or choose a capacitor rated at a higher temperature than

required. Always contact the capacitor manufacturer for

derating requirements.

DC load current of 10A equals ~2.5A of input RMS ripple

current for the external input capacitors.

Output Capacitors

TheLTM4603HVisdesignedforlowoutputripplevoltage.

The bulk output capacitors defined as C

are chosen

In Figure 20, the 10µF ceramic capacitors are together

used as a high frequency input decoupling capacitor. In

a typical 6A output application, two very low ESR, X5R or

X7R, 10µF ceramic capacitors are recommended. These

decoupling capacitors should be placed directly adjacent

to the module input pins in the PCB layout to minimize

the trace inductance and high frequency AC noise. Each

10µF ceramic is typically good for 2A to 3A of RMS ripple

current. Refer to your ceramics capacitor catalog for the

RMS current ratings.

OUT

with low enough effective series resistance (ESR) to meet

theoutputripplevoltageandtransientrequirements. C

OUT

can be a low ESR tantalum capacitor, a low ESR polymer

capacitororaceramiccapacitor.Thetypicalcapacitanceis

200µF if all ceramic output capacitors are used. Additional

output filtering may be required by the system designer,

if further reduction of output ripple or dynamic transient

spikes is required. Table 2 shows a matrix of different

output voltages and output capacitors to minimize the

voltage droop and overshoot during a 3A/µs transient.

The table optimizes total equivalent ESR and total bulk

capacitance to maximize transient performance.

MultiphaseoperationwithmultipleLTM4603HVdevicesin

parallelwilllowertheeffectiveinputRMSripplecurrentdue

to the interleaving operation of the regulators. Application

Note 77 provides a detailed explanation. Refer to Figure 2

fortheinputcapacitorripplecurrentrequirementasafunc-

tion of the number of phases. The figure provides a ratio

of RMS ripple current to DC load current as a function of

duty cycle and the number of paralleled phases. Pick the

corresponding duty cycle and the number of phases to

arrive at the correct ripple current value. For example, the

2-phase parallel LTM4603HV design provides 10A at 2.5V

output from a 12V input. The duty cycle is DC = 2.5V/12V

= 0.21. The 2-phase curve has a ratio of ~0.25 for a duty

cycle of 0.21. This 0.25 ratio of RMS ripple current to a

Multiphase operation with multiple LTM4603HV devices

in parallel will lower the effective output ripple current

due to the interleaving operation of the regulators. For

example, each LTM4603HV’s inductor current in a 12V

to 2.5V multiphase design can be read from the Inductor

Ripple Current vs Duty Cycle graph (Figure 3). The large

ripple current at low duty cycle and high output voltage

can be reduced by adding an external resistor from f to

SET

ground which increases the frequency. If we choose the

duty cycle of DC = 2.5V/12V = 0.21, the inductor ripple

currentfor2.5Voutputat21%dutycycleis~2AinFigure3.

4

0.6

2.5V OUTPUT

5V OUTPUT

0.5

3

2

1

0

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

1-PHASE

0.4

2-PHASE

3-PHASE

4-PHASE

0.3

3.3V OUTPUT WITH

82.5k ADDED FROM

6-PHASE

V

TO f

OUT

SET

0.2

5V OUTPUT WITH

150k ADDED FROM

f

TO GND

0.1

SET

0

0.2

DUTY CYCLE (V /V )

OUT IN

0.4

0.6

0.8

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY CYCLE (V /V

)

OUT IN

4603HV F02

4603HV F03

Figure 2. Normalized Input RMS Ripple Current

vs Duty Cycle for One to Six Modules (Phases)

Figure 3. Inductor Ripple Current vs Duty Cycle

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1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY CYCLE (V /V

)

IN

4603HV F04

O

Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = V_OT/L_I

Figure 4 providesa ratio of peak-to-peak output ripple cur-

Fault Conditions: Current Limit and Overcurrent

Foldback

rent to the inductor current as a function of duty cycle and

the number of paralleled phases. Pick the corresponding

dutycycleandthenumberofphasestoarriveatthecorrect

output ripple current ratio value. If a 2-phase operation is

chosen at a duty cycle of 21%, then 0.6 is the ratio. This

0.6 ratio of output ripple current to inductor ripple of 2A

equals 1.2A of effective output ripple current. Refer to

Application Note 77 for a detailed explanation of output

ripple currentreductionas a functionofparalleled phases.

The LTM4603HV has a current mode controller, which

inherently limits the cycle-by-cycle inductor current not

only in steady-state operation, but also in response to

transients.

To furtherlimitcurrentintheeventofanoverloadcondition,

the LTM4603HV provides foldback current limiting. If the

output voltage falls by more than 50%, then the maximum

output current is progressively lowered to about one sixth

of its full current limit value.

The output ripple voltage has two components that are

related to the amount of bulk capacitance and effective

series resistance (ESR) of the output bulk capacitance.

Therefore, the output ripple voltage can be calculated with

the known effective output ripple current. The equation:

Soft-Start and Tracking

The TRACK/SS pin provides a means to either soft-start

the regulator or track it to a different power supply. A

capacitor on this pin will program the ramp rate of the

output voltage. A 1.5µA current source will charge up the

external soft-start capacitor to 80% of the 0.6V internal

ΔV

≈ (ΔI /(8ꢀ•ꢀfꢀ•ꢀmꢀ•ꢀC ) + ESRꢀ•ꢀΔI ), where f

OUT(P-P)

L OUT L

is frequency and m is the number of parallel phases. This

calculation process can be easily accomplished by using

LTpowerCAD™.

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LTM4603HV

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voltagereferenceminusanymargindelta.Thiswillcontrol

the ramp of the internal reference and the output voltage.

The total soft-start time can be calculated as:

Run Enable

The RUN pin is used to enable the power module. The

pin has an internal 5.1V Zener to ground. The pin can be

driven with a logic input not to exceed 5V.

C_SS

t_SOFTSTART= 0.8 • 0.6V± V

•

(

)

1.5µA

OUT(MARGIN)

The RUN pin can also be used as an undervoltage lock out

(UVLO) function by connecting a resistor divider from the

input supply to the RUN pin:

When the RUN pin falls below 1.5V, then the TRACK/SS

pin is reset to allow for proper soft-start control when the

regulator is enabled again. Current foldback and forced

continuous mode are disabled during the soft-start pro-

cess. The soft-start function can also be used to control

the output ramp up time, so that another regulator can

be easily tracked to it.

R1+R2

V_UVLO

=

•1.5V

R2

See the Simplified Block Diagram (Figure 1).

Power Good

Output Voltage Tracking

The PGOOD pin is an open-drain pin that can be used to

monitor valid output voltage regulation. This pin monitors

a 10% window around the regulation point and tracks

with margining.

Output voltage tracking can be programmed externally

usingtheTRACK/SSpin. Theoutputcanbetrackedupand

downwithanotherregulator.Themasterregulator’soutput

is divided down with an external resistor divider that is the

same as the slave regulator’s feedback divider. Figure 5

shows an example of coincident tracking. Ratiometric

modes of tracking can be achieved by selecting different

resistor values to change the output tracking ratio. The

master output must be greater than the slave output for

the tracking to work. Figure 6 shows the coincident output

tracking characteristics.

COMP Pin

This pin is the external compensation pin. The module has

already been internally compensated for most output volt-

ages.Table2isprovidedformostapplicationrequirements.

LTpowerCAD is available for control loop optimization.

PLLIN

The power module has a phase-locked loop comprised

of an internal voltage controlled oscillator and a phase

detector. This allows the internal top MOSFET turn-on

MASTER

OUTPUT

R2

60.4k

TRACK CONTROL

V

IN

R1

40.2k

60.4k FROM

TO V

100k

V

IN

PLLIN TRACK/SS

MASTER OUTPUT

V

OUT

FB

SLAVE OUTPUT

PGOOD

V

OUT

MPGM

RUN

COMP

V

C

OUT

FB

MARG0

MARG1

V

OUT_LCL

SLAVE OUTPUT

OUTPUT

VOLTAGE

LTM4603HV

C

IN

INTV

CC

DRV

DIFFV

V

OUT

+

OSNS

–

OSNS

f

SGND PGND

SET

R

SET

40.2k

4603HV F06

4603HV F05

TIME

Figure 6. Coincident Output Tracking Characteristics

Figure 5. Coincident Tracking Schematic

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to be locked to the rising edge of the external clock. The

frequency range is 30% around the operating frequency

of 1MHz. A pulse detection circuit is used to detect a clock

on the PLLIN pin to turn on the phase-locked loop. The

pulse width of the clock has to be at least 400ns and the

amplitudeatleast2V. ThePLLINpinmustbedrivenfroma

lowimpedancesourcesuchasalogicgatelocatedcloseto

the pin. During start-up of the regulator, the phase-locked

loop function is disabled.

Parallel Operation of the Module

The LTM4603HV device is an inherently current mode

controlled device. Parallel modules will have very good

current sharing. This will balance the thermals on the

design. The voltage feedback equation changes with the

variable n as modules are paralleled:

60.4k

+R_SET

n

V_OUT= 0.6V

R_SET

INTV and DRV Connection

CC

n is the number of paralleled modules.

Thermal Considerations and Output Current Derating

An internal low dropout regulator produces an internal

5V supply that powers the control circuitry and DRV

for driving the internal power MOSFETs. Therefore, if the

system does not have a 5V power rail, the LTM4603HV

can be directly powered by Vin. The gate driver current

through the LDO is about 20mA. The internal LDO power

dissipation can be calculated as:

CC

The power loss curves in Figures 7 and 8 can be used

in coordination with the load current derating curves in

Figures 9 to 12, and Figures 13 to 16 for calculating an

approximate θ for the module with various heat sinking

JA

methods. Thermal models are derived from several tem-

peraturemeasurementsatthebenchandthermalmodeling

analysis.ThermalApplicationNote103providesadetailed

explanation of the analysis for the thermal models and the

derating curves. Tables 3 and 4 provide a summary of the

P

= 20mAꢀ•ꢀ(V – 5V)

IN

LDO_LOSS

The LTM4603HV also provides the external gate driver

voltage pin DRV . If there is a 5V rail in the system, it is

CC

recommended to connect DRV pin to the external 5V

CC

rail. This is especially true for higher input voltages. Do

equivalent θ for the noted conditions. These equivalent

JA

not apply more than 6V to the DRV pin. A 5V output can

θ

parameters are correlated to the measured values,

JA

CC

be used to power the DRV pin with an external circuit

and are improved with air flow. The case temperature is

maintained at 100°C or below for the derating curves.

CC

as shown in Figure 18.

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

6

5

24V LOSS

12V LOSS

2.5

2.0

1.5

1.0

0.5

4

3

12V LOSS

5V LOSS

2

1

0

5V , 1.5V , 0LFM

IN

OUT

5V , 1.5V , 200LFM

IN

OUT

5V , 1.5V , 400LFM

0

4

OUTPUT CURRENT (A)

6

7

0

1

2

3

5

4

OUTPUT CURRENT (A)

6

7

0

1

2

3

5

75

80

85

90

95

AMBIENT TEMPERATURE (C)

4603HV F07

4603HV F08

4603HV F09

Figure 7. 1.5V Power Loss

Figure 8. 3.3V Power Loss

Figure 9. No Heat Sink

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6

5

6

5

4

3

4

3

4

3

2

1

0

2

1

0

2

1

0

12V , 1.5V , 0LFM

5V , 1.5V , 0LFM

IN

OUT

IN

OUT

12V , 1.5V , 0LFM

IN

OUT

12V , 1.5V , 200LFM

5V , 1.5V , 200LFM

IN

OUT

IN

OUT

12V , 1.5V , 200LFM

IN

OUT

12V , 1.5V , 400LFM

5V , 1.5V , 400LFM

12V , 1.5V , 400LFM

IN OUT

70

75

80

85

90

95

70

75

80

85

90

95

75

80

85

90

95

AMBIENT TEMPERATURE (C)

4603HV F11

4603HV F12

4603HV F10

Figure 10. BGA Heat Sink

Figure 11. No Heat Sink

Figure 12. BGA Heat Sink

6

5

6

5

4

3

4

3

2

1

12V , 3.3V , 0LFM

IN OUT

1

0

IN

OUT

12V , 3.3V , 200LFM

IN OUT

IN

OUT

12V , 3.3V , 400LFM

IN OUT

0

70

75

80

85

90

95

70

75

80

85

90

95

AMBIENT TEMPERATURE (C)

4603HV F13

4603HV F14

Figure 13. No Heat Sink

Figure 14. BGA Heat Sink

6

5

6

5

4

3

2

1

0

4

3

2

1

0

24V , 3.3V , 0LFM

IN

OUT

IN

OUT

24V , 3.3V , 200LFM

IN

OUT

24V , 3.3V , 400LFM

IN

60

65

70

75

80

85

60

70

75

80

85

90

65

AMBIENT TEMPERATURE (C)

4603HV F15

1635 G24

Figure 15. No Heat Sink

Figure 16. BGA Heat Sink

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Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 20)

TYPICAL MEASURED VALUES

C

VENDORS

PART NUMBER

C

OUT2

VENDORS

PART NUMBER

OUT1

TAIYO YUDEN

TDK

JMK316BJ226ML-T501 (22µF, 6.3V)

JMK325BJ476MM-T (47µF, 6.3V)

C3225X5R0J476M (47µF, 6.3V)

SANYO POSCAP

6TPE220MIL (220µF, 6.3V)

2R5TPE330M9 (330µF, 2.5V)

4TPE330MCL (330µF, 4V)

V

C

V

(V)

DROOP

(mV)

PEAK TO

PEAK (mV)

RECOVERY

TIME (µs)

LOAD STEP

(A/µs)

R

SET

OUT

IN

OUT1

OUT2

IN

(V)

1.2

1.5

1.8

2.5

3.3

5

(CERAMIC)

(BULK)

(CERAMIC)

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

1 × 22µF 6.3V

1 × 47µF 6.3V

2 × 47µF 6.3V

4 × 47µF 6.3V

(BULK)

330µF 4V

330µF 2.5V

220µF 6.3V

NONE

(kW)

60.4

40.2

30.1

19.1

13.3

8.25

2 × 10µF 35V 150µF 35V

5

34

22

68

40

30

26

24

18

30

26

24

18

30

26

30

26

37

30

26

37

30

26

40

34

28

12

40

34

28

18

40

32

28

14

40

32

28

22

20

3

5

20

40

5

32

60

330µF 4V

330µF 2.5V

220µF 6.3V

NONE

12

5

34

68

22

40

20

39

29.5

35

55

330µF 4V

330µF 2.5V

220µF 6.3V

NONE

70

5

25

48

5

24

47.5

68

5

36

330µF 4V

330µF 2.5V

220µF 6.3V

NONE

12

5

35

70

25

48

24

45

32.6

38

61.9

76

330µF 4V

330µF 2.5V

220µF 6.3V

NONE

5

29.5

28

57.5

55

5

43

80

330µF 4V

330µF 2.5V

220µF 6.3V

NONE

12

5

38

76

28

55

27

52

36.4

38

70

330µF 4V

220µF 6.3V

NONE

78

5

37.6

39.5

66

74

5

78.1

119

78

5

330µF 4V

220µF 6.3V

NONE

12

7

38

34.5

35.8

50

66.3

68.8

98

330µF 4V

220µF 6.3V

NONE

42

86

7

47

89

7

50

94

7

75

141

86

330µF 4V

220µF 6.3V

NONE

12

15

20

42

47

88

50

94

69

131

215

217

NONE

110

5

NONE

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LTM4603HV

applicaTions inForMaTion

Table 3. 1.5V Output

DERATING CURVE

Figures 9, 11

Figures 10, 12

V

(V)

POWER LOSS CURVE

Figure 7

AIR FLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

IN

5, 12

0

15.2

14

Figure 7

200

400

0

None

5, 12

Figure 7

None

12

5, 12, 20

Figure 7

BGA Heat Sink

13.9

11.3

10.25

Figure 7

200

400

Figure 7

Table 4. 3.3V Output

DERATING CURVE

Figures 13, 15

V

(V)

POWER LOSS CURVE

Figure 8

AIR FLOW (LFM)

HEAT SINK

None

θ

(°C/W)

JA

IN

12, 24

0

15.2

14.6

13.4

13.9

11.1

10.5

Figures 13, 15

Figure 8

200

400

0

None

Figures 13, 15

Figure 8

None

Figures 14, 16

Figure 8

BGA Heat Sink

Figures 14, 16

Figure 8

200

400

Figures 14, 16

Figure 8

Heat Sink Manufacturer

Aavid Thermalloy

Part No: 375424B00034G

Phone: 603-224-9988

4603hvfa

18

For more information www.linear.com/LTM4603HV

LTM4603HV

applicaTions inForMaTion

This allows for 4W maximum power dissipation in the

total module with top and bottom heat sinking, and 2W

power dissipation through the top of the module with an

•ꢀ To minimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

approximate θ between 6°C/W to 9°C/W. This equates

JC

•ꢀ Do not put vias directly on pads.

to a total of 124°C at the junction of the device.

•ꢀ If vias are placed onto the pads, the the vias must be

Safety Considerations

capped.

TheLTM4603HVmodulesdonotprovidegalvanicisolation

•ꢀ Interstitialvia placement can also beused ifnecessary.

from V to V . There is no internal fuse. If required,

IN

OUT

•ꢀ Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to PGND underneath the unit.

a slow blow fuse with a rating twice the maximum input

current needs to be provided to protect each unit from

catastrophic failure.

Figure17givesagoodexampleoftherecommendedlayout.

Layout Checklist/Example

Frequency Adjustment

The high integration of LTM4603HV makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

The LTM4603HV is designed to typically operate at 1MHz

across most input conditions. The f

pin is typically

SET

left open. The switching frequency has been optimized

for maintaining constant output ripple noise over most

operating ranges. The 1MHz switching frequency and the

400nsminimumoff-timecanlimitoperationathigherduty

•ꢀ Use large PCB copper areas for high current path, in-

cluding V , PGND and V . It helps to minimize the

IN

OUT

PCB conduction loss and thermal stress.

cycles like 5V to 3.3V , and produce excessive induc-

IN

OUT

•ꢀ Place high frequency ceramic input and output capaci-

tor ripple currents for lower duty cycle applications like

tors next to the V , PGND and V

pins to minimize

28V to 5V . The 5V

and 3.3V

drop out curves

IN

OUT

IN

OUT

high frequency noise.

are modified by adding an external resistor on the f pin

SET

to allow for wider input voltage operation.

•ꢀ Place a dedicated power ground layer underneath the

unit.

V

IN

C

IN

C

IN

GND

SIGNAL

GND

C

OUT

V

OUT

4603HV F17

Figure 17. Recommended Layout

4603hvfa

19

For more information www.linear.com/LTM4603HV

LTM4603HV

applicaTions inForMaTion

Example for 5V Output

Example for 3.3V Output

LTM4603HV minimum on-time = 100ns

t

= ((V ꢀ•ꢀ10pf)/I ), for V

> 4.8V use 4.8V

t

= ((3.3Vꢀ•ꢀ10pF)/I

)

ON

OUT

fSET

OUT

ON

fSET

LTM4603HV minimum off-time = 400ns

= t– t , where t = 1/Frequency

LTM4603HV minimum off-time = 400ns

t = t – t , where t = 1/Frequency

OFF

t

OFF

ON

Duty Cycle = t /t or V /V

Duty Cycle (DC) = t /t or V /V

ON OUT IN

ON

OUT IN

Equations for setting frequency:

= (V /(3ꢀ•ꢀR )), for 28V input operation, I

Equations for setting frequency:

= (V /(3ꢀ•ꢀR )), for 28V input operation, I

I

=

I

=

fSET

IN

fSET

IN

fSET

281µA, t = ((4.8Vꢀ•ꢀ10pF)/I

), t = 171ns, where

281µA, t = ((3.3Vꢀ•ꢀ10pf)/I ), t = 117ns, where the

ON

fSET ON

ON fSET ON

the internal R

is 33.2k. Frequency = (V /(V ꢀ•ꢀt ))

internal R is 33.2k. Frequency = (V /(V ꢀ•ꢀt )) =

fSET OUT IN ON

fSET

OUT IN ON

= (5V/(28Vꢀ•ꢀ171ns)) ~ 1MHz. The inductor ripple cur-

rent begins to get high at the higher input voltages due

to a larger voltage across the inductor. This is shown in

the Inductor Ripple Current vs Duty Cycle graph as over

4A at 18% duty cycle. The inductor ripple current can be

lowered at the higher input voltages by adding an external

(3.3V/(28Vꢀ•ꢀ117ns)) ~ 1MHz. The minimum on-time and

minimum off-time are within specification at 117ns and

883ns. But the 4.5V minimum input for converting 3.3V

output will not meet the minimum off-time specification

of 400ns. t = 733ns, Frequency = 1MHz, t = 267ns.

ON

OFF

Solution

resistor from f

to ground to increase the switching

SET

frequency. A 3A ripple current is chosen, and the total

peak current is equal to 1/2 of the 3A ripple current plus

the output current. The 5V output current is limited to 5A,

so total peak current is less than 6.5A. This is below the

8A peak specified value. A 150k resistor is placed from

Lower the switching frequency at lower input voltages to

allowforhigherdutycycles,andmeetthe400nsminimum

off-timeat4.5Vinputvoltage.Theoff-timeshouldbeabout

500ns with 100ns guard band included. The duty cycle

for (3.3V/4.5V) = ~73%. Frequency = (1 – DC)/t

or

OFF

f

to ground, and the parallel combination of 150k and

SET

(1 – 0.73)/500ns = 540kHz. The switching frequency

needs to be lowered to 540kHz at 4.5V input. t = DC/

33.2k equates to 27.2k. The I

and 28V input voltage equals 343µA. This equates to a t

calculation with 27.2k

fSET

ON

frequency, or 1.35µs. The f

pin voltage compliance

SET

of 140ns. This will increase the switching frequency from

1MHz to ~1.28MHz for the 28V to 5V conversion. The

minimum on time is above 100ns at 28V input. Since the

switching frequency is approximately constant over input

and output conditions, then the lower input voltage range

is limited to 10V for the 1.28MHz operation due to the

is 1/3 of V , and the I

current equates to 45µA with

IN

fSET

the internal 33.2k. The I

current needs to be 24µA for

fSET

540kHz operation. A resistor can be placed from V

to

OUT

f

to lower the effective I

current out of the f pin

SET

fSET SET

to 24µA. The f

pin is 4.5V/3 =1.5V and V

= 3.3V,

SET

OUT

therefore an 82.5k resistor will source 21µA into the f

SET

400ns minimum off-time. Equation: t = (V /V )ꢀ•ꢀ(1/

ON

OUT IN

node and lower the I

current to 24µA. This enables the

fSET

Frequency) equates to a 382ns on time, and a 400ns off-

540kHz operation and the 4.5V to 28V input operation for

down converting to 3.3V output as shown in Figure 19.

Thefrequencywillscalefrom540kHzto1.27MHzoverthis

input range. This provides for an effective output current

of 5A over the input range.

time. The V to V Step-Down Ratio curve reflects an

IN

OUT

operatingrangeof10Vto28Vfor1.28MHzoperationwitha

150kresistortoground(showninFigure18), andan8Vto

16V operating range for f floating. These modifications

SET

are made to provide wider input voltage ranges for the 5V

output designs while limiting the inductor ripple current,

and maintaining the 400ns minimum off-time.

4603hvfa

20

For more information www.linear.com/LTM4603HV

LTM4603HV

Typical applicaTions

V

OUT

TRACK/SS CONTROL

V

IN

10V TO 28V

REVIEW TEMPERATURE

DERATING CURVE

R2

R4

V

PLLIN TRACK/SS

V

5V

5A

IN

100k 100k

OUT

PGOOD

V

OUT

C6 100pF

MPGM

RUN

V

FB

REFER TO

MARG0

MARG1

V

OUT_LCL

TABLE 2

C3

100µF

6.3V

COMP

INTV

DRV

+

LTM4603HV

CC

5% MARGIN

DIFFV

SANYO POSCAP

CC

OUT

+

R1

392k

1%

V

OSNS

C2

–

OSNS

10μF

f

SGND PGND

SET

35V

C1

10µF

35V

R

SET

INTV

fSET

CC

8.25k

150k

MARGIN CONTROL

IMPROVE

EFFICIENCY

SOT-323

FOR 12V INPUT

DUAL

CMSSH-3C3

4603HV F18

Figure 18. 5V at 5A Design

V

OUT

TRACK/SS CONTROL

V

IN

4.5V TO 28V

REVIEW TEMPERATURE

DERATING CURVE

R2

R4

V

PLLIN TRACK/SS

V

3.3V

5A

IN

100k 100k

OUT

PGOOD

V

OUT

C6 100pF

PGOOD

MPGM

RUN

V

FB

C3

100µF

6.3V

MARG0

MARG1

V

OUT_LCL

+

COMP

INTV

DRV

LTM4603HV

CC

SANYO POSCAP

DIFFV

OUT

+

C2

V

OSNS

R1

392k

10µF

35V

–

OSNS

R

f

fSET

C1

10µF

35V

SGND PGND

SET

R

SET

82.5k

13.3k

5% MARGIN

MARGIN CONTROL

4603HV F19

Figure 19. 3.3V at 5A Design

4603hvfa

21

For more information www.linear.com/LTM4603HV

LTM4603HV

Typical applicaTions

CLOCK SYNC

C5

V

OUT

0.01µF

V

IN

4.5V TO 28V

REVIEW TEMPERATURE

R2

100k

R4

V

PLLIN TRACK/SS

V

1.5V

6A

IN

DERATING CURVE

C3 100pF

100k

OUT

PGOOD

V

OUT

+

C

22µF

6.3V

C

OUT2

470µF

6.3V

PGOOD

MPGM

RUN

V

OUT1

FB

MARG0

MARG1

V

OUT_LCL

MARGIN

CONTROL

ON/OFF

COMP

INTV

DRV

LTM4603HV

CC

DIFFV

V

OUT

+

C

IN

+

R1

392k

BULK

OPT.

OSNS

–

V

OSNS

C

IN

TABLE 2

f

10µF

SGND PGND

SET

R

REFER TO

TABLE 2

SET

35V

×2 CER

100k*

40.2k

V

IN

4603 F18

*100k NEEDED ONLY FOR

20V INPUT

5% MARGIN

Figure 20. Typical 4.5V-28V_IN, 1.5V at 6A Design

V

OUT

V

IN

4.5V TO 28V

0 PHASE

PLLIN

R3

R4

V

100k 100k

IN

C1

V

2.5V

12A

OUT

10µF

35V

×2

PGOOD

RUN

COMP

V

OUT

C8

C2

100µF

6.3V

C4

220µF

6.3V

V

FB

V

OUT_LCL

100pF

R

SET

9.53k

INTV

DIFFV

CC

OUT

LTM4603HV

+

DRV

V

CC

MPGM

OSNS

–

OSNS

R2

392k

f

MARG0

MARG1

MARGIN

CONTROL

SET

LTC6908-1

+

TRACK/SS

V

OUT1

GND OUT2

SET MOD

C3

0.33µF

SGND PGND

C3

0.1µF

R9

118k

2-PHASE

OSCILLATOR

180 PHASE

PLLIN

R7

100k

V

IN

PGOOD

RUN

COMP

V

OUT

C6

220µF

6.3V

C7

100µF

6.3V

V

FB

V

OUT_LCL

C5

INTV

DIFFV

LTM4603HV

CC

OUT

10µF

35V

×2

+

DRV

V

CC

OSNS

–

MPGM

OSNS

R6

392k

f

MARG0

MARG1

SET

TRACK/SS

SGND PGND

4603HV F21

5% MARGIN

Figure 21. 2-Phase, Parallel 2.5V at 12A Design

4603hvfa

22

For more information www.linear.com/LTM4603HV

LTM4603HV

Typical applicaTions

LTC6908-1

0 PHASE

+

V

OUT1

GND OUT2

SET MOD

C8

0.1µF

R9

118k

2-PHASE

OSCILLATOR

3.3V

V

IN

5V TO 28V

180 PHASE

PLLIN

R3

R4

R7

R8

V

IN

PGOOD

RUN

LTM4603HV

COMP

PLLIN

100k 100k

IN

100k 100k

C1

V

3.3V

6A

V

2.5V

6A

OUT1

OUT2

10µF

35V

×2

PGOOD

RUN

V

OUT

V

OUT

V

FB

C8

C9

C2

100µF

6.3V

C4

220µF

6.3V

C6

100µF

6.3V

C7

220µF

6.3V

V

FB

22pF

LTM4603HV

COMP

C5

R

SET2

19.1k

SET1

13.3k

V

OUT_LCL

DIFFV

OUT_LCL

10µF

35V

×2

INTV

DRV

DIFFV

INTV

DRV

CC

OUT

+

CC

OUT

+

3.3V

TRACK

V

CC

MPGM

OSNS

CC

MPGM

OSNS

–

OSNS

R16

60.4k

R2

392k

f

MARG0

MARG1

f

MARG0

MARG1

MARGIN

CONTROL

MARGIN

CONTROL

SET

392k

TRACK/SS

C3

0.15µF

R15

19.1k

SGND PGND

4603HV F22

Figure 22. 2-Phase, 3.3V and 2.5V at 6A with Tracking

LTC6908-1

+

0 PHASE

V

OUT1

GND OUT2

SET MOD

C8

0.1µF

R9

182k

2-PHASE

OSCILLATOR

1.8V

V

IN

4.5V TO 28V

180 PHASE

PLLIN

R3

R4

R7

R8

V

IN

PGOOD

RUN

LTM4603HV

COMP

PLLIN

100k 100k

IN

100k 100k

C1

V

1.8V

6A

V

1.5V

6A

OUT1

OUT2

10µF

35V

×2

PGOOD

RUN

V

OUT

V

OUT

V

FB

C8

C9

C2

100µF

6.3V

C4

220µF

6.3V

C6

C7

V

FB

100pF

100µF

220µF

LTM4603HV

COMP

6.3V

C5

R

SET2

40.2k

SET1

30.1k

V

OUT_LCL

DIFFV

OUT_LCL

10µF

35V

×2

INTV

DRV

DIFFV

INTV

DRV

CC

OUT

+

CC

OUT

+

1.8V

TRACK

V

CC

MPGM

OSNS

CC

MPGM

OSNS

–

OSNS

R16

60.4k

R6

R2

392k

f

MARG0

MARG1

f

MARG0

MARG1

MARGIN

CONTROL

MARGIN

CONTROL

SET

392k

TRACK/SS

C3

0.15µF

R15

40.2k

SGND PGND

4603HV F23

Figure 23. 2-Phase, 1.8V and 1.5V at 6A with Tracking

4603hvfa

23

For more information www.linear.com/LTM4603HV

LTM4603HV

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

Z

b b b

Z

6 . 9 8 5 0

5 . 7 1 5 0

4 . 4 4 5 0

3 . 1 7 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 0 0 0 0

0 . 6 3 5 0

1 . 9 0 5 0

3 . 1 7 5 0

4 . 4 4 5 0

5 . 7 1 5 0

6 . 9 8 5 0

a a a

Z

4603hvfa

24

For more information www.linear.com/LTM4603HV

LTM4603HV

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

6/14

Updated Absolute Maximum Ratings.

Updated the Order Information table.

Updated the Electrical Characteristics table.

Updated the Pin Functions information.

Updated the Output Voltage Programming and Margining section.

Updated the PLLIN section.

2

2-4

7-8

11

15

20

21

Updated the Applications Information section.

Updated Figure 18.

4603hvfa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

25

For more information www.linear.com/LTM4603HV

LTM4603HV

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC2900

Quad Supply Monitor with Adjustable Reset Timer

Power Supply Tracking Controller

Synchronous Isolated Flyback Controllers

10A DC/DC µModule

Monitors Four Supplies; Adjustable Reset Timer

Tracks Both Up and Down; Power Supply Sequencing

No Opto-Coupler Required; 3.3V, 12A Output; Simple Design

Fast Transient Response

LTC2923

LT3825/LT3837

LTM4600

LTM4601

12A DC/DC µModule

with PLL, Output Tracking and Margining, LTM4603HV Pin Compatible

Pin Compatible with the LTM4600

LTM4602

6A DC/DC µModule

LTM4603

6A DC/DC µModule with Tracking PLL/Margining

Pin Compatible with the LTM4601

4603hvfa

LT 0614 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

26

For more information www.linear.com/LTM4603HV

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4603HV

l

 LINEAR TECHNOLOGY CORPORATION 2007


型号：	LTM4603HVIV#PBF
厂家：	Linear
描述：	LTM4603HV - 6A, 28VIN DC/DC µModule (Power Module) with PLL, Output Tracking and Margining; Package: LGA; Pins: 118; Temperature Range: -40°C to 85°C 开关
文件：	总26页 (文件大小：338K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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