LTM4603IV-PBF [Linear]
6A DC/DC μModule with PLL, Output Tracking and Margining; 6A DC / DC微型模块与PLL ,输出跟踪和裕型号: | LTM4603IV-PBF |
厂家: | Linear |
描述: | 6A DC/DC μModule with PLL, Output Tracking and Margining |
文件: | 总24页 (文件大小:340K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM4603/LTM4603-1
6A DC/DC µModule
with PLL, Output Tracking
and Margining
U
DESCRIPTIO
FEATURES
The LTM®4603 is a complete 6A step-down switch mode
DC/DC power supply with onboard switching controller,
MOSFETs, inductor and all support components. The
µModuleTM is housed in a small surface mount 15mm ×
15mm × 2.8mm LGA package. Operating over an input
voltage range of 4.5 to 20V, the LTM4603 supports an
outputvoltagerangeof0.6Vto5Vaswellasoutputvoltage
tracking and margining. The high efficiency design deliv-
ers 6A continuous current (8A peak). Only bulk input and
output capacitors are needed to complete the design.
■
Complete Switch Mode Power Supply
■
Wide Input Voltage Range: 4.5V to 20V
■
6A DC Typical, 8A Peak Output Current
■
0.6V to 5V Output Voltage
■
Output Voltage Tracking and Margining
■
Remote Sensing for Precision Regulation
(LTM4603 Only)
■
Typical Operating Frequency: 1MHz
■
PLL Frequency Synchronization
■
1.5% Regulation
■
Current Foldback Protection (Disabled at Start-Up)
The low profile (2.8mm) and light weight (1.73g) package
easily mounts on the unused space on the back side of
PC boards for high density point of load regulation. The
µModule can be synchronized with an external clock for
reducing undesirable frequency harmonics and allows
PolyPhase® operation for high load currents.
■
Pin Compatible with the LTM4601
■
Pb-Free (e4) RoHS Compliant Package with Gold
Finish Pads
■
Ultrafast Transient Response
■
Current Mode Control
■
Up to 93% Efficiency at 5V , 3.3V
IN
OUT
A high switching frequency and adaptive on-time current
mode architecture deliver a very fast transient response
to line and load changes without sacrificing stability. An
onboard remote sense amplifier can be used to accurately
regulate an output voltage independent of load current.
The onboard remote sense amplifier is not available in the
LTM4603-1.TheLTM4603/LTM4603-1arepincompatible
with the 12A LTM4601/LTM4601-1.
■
■
■
Programmable Soft-Start
Output Overvoltage Protection
Small Footprint, Low Profile (15mm × 15mm ×
2.8mm) SurfaceUMount LGA Package
APPLICATIO S
■
Telecom and Networking Equipment
■
Servers
, LT, LTC, LTM and PolyPhase are registered trademarks of Linear Technology
Corporation. µModule is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
Industrial Equipment
Point of Load Regulation
■
U
TYPICAL APPLICATIO
Efficiency vs Load Current with 12VIN
1.5V/6A Power Supply with 4.5V to 20V Input
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
CLOCK SYNC
TRACK/SS CONTROL
V
IN
4.5V TO 20V
V
IN
PLLIN TRACK/SS
V
1.5V
6A
OUT
PGOOD
V
OUT
100pF
V
FB
ON/OFF
RUN
MARG0
MARG1
MARGIN
CONTROL
COMP
12V , 1.2V
IN
C
OUT
OUT
OUT
OUT
OUT
OUT
LTM4603
0.60
0.55
0.50
0.45
0.40
C
IN
12V , 1.5V
INTV
V
IN
CC
OUT_LCL
12V , 1.8V
IN
13.3k
DRV
DIFFV
CC
OUT
+
12V , 2.5V
IN
MPGM
SGND PGND
V
V
OSNS
12V , 3.3V
IN
–
12V , 5V
IN
OSNS
OUT
392k
f
SET
0
2
3
4
5
6
7
1
5% MARGIN
OUTPUT CURRENT (A)
4603 TA01a
4603 TA01b
4603f
1
LTM4603/LTM4603-1
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
INTV , DRV , V
, V
(V
≤ 3.3V
CC
CC OUT_LCL OUT OUT
with Remote Sense Amp) ............................ –0.3V to 6V
PLLIN, TRACK/SS, MPGM, MARG0, MARG1,
PGOOD, f ..............................–0.3V to INTV + 0.3V
SET
CC
V
f
IN
SET
RUN ............................................................. –0.3V to 5V
MARG0
MARG1
DRV
V , COMP................................................ –0.3V to 2.7V
FB
CC
V ............................................................. –0.3V to 20V
IN
OSNS
V
FB
+
–
PGND
V
, V
..................................0V to INTV – 1V
OSNS CC
PGOOD
SGND
+
Operating Temperature Range (Note 2) ... –40°C to 85°C
Junction Temperature ........................................... 125°C
Storage Temperature Range................... –55°C to 125°C
V
/NC2*
OSNS
DIFFV /NC3*
OUT
V
V
V
OUT
OUT_LCL
–
/NC1*
OSNS
LGA PACKAGE
118-LEAD (15mm 15mm 2.8mm)
T
= 125°C, θ = 15°C/W, θ = 6°C/W,
JA JC
JMAX
θ
JA
DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS, WEIGHT = 1.7g
*LTM4603-1 Only
ORDER PART NUMBER
LGA PART MARKING*
LTM4603EV#PBF
LTM4603IV#PBF
LTM4603EV-1#PBF
LTM4603IV-1#PBF
LTM4603V
LTM4603V
LTM4603V-1
LTM4603V-1
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the –40°C to 85°C
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application (front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
V
Input DC Voltage
Output Voltage
4.5
20
V
IN(DC)
V
C
= 10µF ×2, C
= 2×, 100µF/X5R/
OUT(DC)
IN
OUT
Ceramic
●
●
V
IN
V
IN
= 5V, V
= 1.5V, I = 0A
OUT
1.478
1.478
1.5
1.5
1.522
1.522
V
V
OUT
OUT
= 12V, V
= 1.5V, I
= 0A
OUT
Input Specifications
V
Undervoltage Lockout Threshold
Input Inrush Current at Startup
I
I
= 0A
3.2
4
V
IN(UVLO)
OUT
I
= 0A. V
= 1.5V
INRUSH(VIN)
OUT
OUT
V
V
= 5V
= 12V
0.6
0.7
A
A
IN
IN
I
Input Supply Bias Current
V
V
= 12V, V
= 12V, V
= 1.5V, No Switching
= 1.5V, Switching
3.8
25
mA
mA
Q(VIN,NOLOAD)
IN
IN
OUT
OUT
Continuous
V
V
= 5V, V
= 5V, V
= 1.5V, No Switching
= 1.5V, Switching
2.5
43
mA
mA
IN
IN
OUT
OUT
Continuous
Shutdown, RUN = 0, V = 12V
22
µA
IN
4603f
2
LTM4603/LTM4603-1
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the –40°C to 85°C
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application (front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input Supply Current
V
IN
V
IN
V
IN
= 12V, V
= 12V, V
= 1.5V, I
= 3.3V, I
= 6A
= 6A
0.85
1.78
2.034
A
A
A
S(VIN)
OUT
OUT
OUT
OUT
= 5V, V
= 1.5V, I
= 6A
OUT
OUT
INTV
V
= 12V, RUN > 2V
IN
No Load
4.7
0
5
5.3
6
V
CC
Output Specifications
I
Output Continuous Current Range
(See Output Current Derating Curves
for Different V , V
V
= 12V, V
= 1.5V
OUT
A
OUTDC
IN
and T )
A
IN OUT
●
V
– V
Line Regulation Accuracy
V
V
= 1.5V, I
= 1.5V, I
IN
IN
= 0A, V = 4.5V to 20V
0.3
%
OUT(NOM)
OUT(ΔLINE)
OUT
OUT
OUT
IN
V
OUT(NOM)
V
– V
Load Regulation Accuracy
= 0A to 6A
= 12V, with Remote Sense Amp
= 12V, LTM4603-1
OUT(NOM)
OUT(ΔLOAD)
OUT
V
V
●
●
0.25
0.5
%
%
V
OUT(NOM)
V
Output Ripple Voltage
I
I
= 0A, C
= 2×, 100µF/X5R/Ceramic
OUT
OUT(AC)
OUT
V
V
= 12V, V
= 1.5V
10
10
mV
mV
IN
IN
OUT
P-P
P-P
= 5V, V
= 1.5V
OUT
f
Output Ripple Voltage Frequency
= 3A, V = 12V, V = 1.5V
OUT
1000
kHz
S
OUT
IN
ΔV
Turn-On Overshoot,
TRACK/SS = 10nF
C
V
= 2×, 100µF/X5R/Ceramic,
OUT(START)
OUT
OUT
= 1.5V, I
= 12V
= 5V
= 0A
OUT
V
IN
V
IN
20
20
mV
mV
t
Turn-On Time, TRACK/SS = Open
Peak Deviation for Dynamic Load
C
V
= 2×, 100µF/X5R/Ceramic,
START
OUT
OUT
= 1.5V, I
= 12V
= 5V
= 1A Resisitive Load
OUT
V
IN
V
IN
0.5
0.7
ms
ms
ΔV
Load: 0% to 50% to 0% of Full Load,
= 2 × 22µF/Ceramic, 470µF, 4V
OUTLS
C
OUT
Sanyo POSCAP
V
IN
V
IN
= 12V
= 5V
35
35
mV
mV
t
I
Settling Time for Dynamic Load Step Load: 0% to 50% to 10% of Full Load
SETTLE
V
= 12V
25
µs
IN
Output Current Limit
C
= 2×, 100µF/X5R/Ceramic
OUTPK
OUT
V
IN
V
IN
= 12V, V
= 1.5V
8
8
A
A
OUT
= 5V, V
= 1.5V
OUT
Remote Sense Amp (LTM4603 Only, Not Supported in the LTM4603-1) (Note 3)
+
–
V
, V
Common Mode Input Voltage Range
V
= 12V, RUN > 2V
0
0
INTV – 1
V
OSNS
OSNS
IN
CC
CM Range
DIFFV
Range
Output Voltage Range
Input Offset Voltage Magnitude
Differential Gain
V
= 12V, DIFF OUT Load = 100k
INTV
V
mV
OUT
IN
CC
V
OS
1.25
AV
1
3
V/V
MHz
V/µs
kΩ
GBP
SR
Gain Bandwidth Product
Slew Rate
2
+
R
Input Resistance
V
OSNS
to GND
20
100
IN
CMRR
Common Mode Rejection Ratio
dB
4603f
3
LTM4603/LTM4603-1
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the –40°C to 85°C
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application (front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Control Stage
●
V
Error Amplifier Input Voltage
Accuracy
I
= 0A, V = 1.5V
OUT
0.594
0.6
0.606
V
FB
OUT
V
RUN Pin On/Off Threshold
Soft-Start Charging Current
Minimum On Time
1
1.5
–1.5
50
1.9
–2
V
µA
ns
RUN
I
t
t
V
= 0V
–1
SS/TRACK
ON(MIN)
OFF(MIN)
SS/TRACK
(Note 4)
(Note 4)
100
400
Minimum Off Time
250
50
ns
R
PLLIN Input Resistance
kΩ
mA
PLLIN
I
Current into DRV Pin
V
OUT
= 1.5V, I = 1A,
OUT
18
25
DRVCC
CC
Frequency = 1MHz, DRV = 5V
CC
R
Resistor Between V
and V
FB
60.098
60.4
1.18
1.4
60.702
kΩ
V
FBHI
OUT
V
V
Margin Reference Voltage
MPGM
, V
MARG0, MARG1 Voltage Thresholds
V
MARG0 MARG1
PGOOD Output
ΔV
ΔV
ΔV
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
V
V
V
Rising
7
10
–10
1.5
13
–13
3
%
%
%
V
FBH
FB
Falling
–7
FBL
FB
Returning
FB(HYS)
FB
V
PGL
PGOOD Low Voltage
I
= 5mA
0.15
0.4
PGOOD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4603E/LTM4603-1 are guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LTM4603E/LTM4603-1
are guaranteed and tested over the –40°C to 85°C temperature range.
Note 3: Remote sense amplifier recommended for ≤3.3V output.
Note 4: 100% tested at wafer level only.
4603f
4
LTM4603/LTM4603-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS (See Figure 18 for all curves)
Efficiency vs Load Current
with 20VIN
Efficiency vs Load Current
with 5VIN
Efficiency vs Load Current
with 12V
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
5V , 0.6V
12V , 1.2V
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
20V , 1.5V
5V , 1.2V
IN
12V , 1.5V
IN
IN
OUT
OUT
OUT
OUT
20V , 1.8V
IN
5V , 1.5V
IN
12V , 1.8V
IN
20V , 2.5V
IN
5V , 1.8V
IN
12V , 2.5V
IN
20V , 3.3V
5V , 2.5V
IN
12V , 3.3V
IN
IN
20V , 5V
5V , 3.3V
IN
12V , 5V
IN
OUT
IN
OUT
0
2
3
4
5
6
7
1
0
2
3
4
5
7
1
6
0
2
3
4
5
6
7
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4603 G01
4603 G03
4603 G02
1.2V Transient Response
1.5V Transient Response
1.8V Transient Response
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
V
V
V
OUT
OUT
OUT
50mV/DIV
50mV/DIV
50mV/DIV
4603 G05
4603 G04
4603 G06
25µs/DIV
25µs/DIV
25µs/DIV
1.5V AT 3A/µs LOAD STEP
1.2V AT 3A/µs LOAD STEP
1.8V AT 3A/µs LOAD STEP
C
: 1x 22µF, 6.3V CERAMIC
C
: 1x 22µF, 6.3V CERAMIC
C
: 1x 22µF, 6.3V CERAMIC
OUT
OUT
OUT
1x 330µF, 4V SANYO POSCAP
1x 330µF, 4V SANYO POSCAP
1x 330µF, 4V SANYO POSCAP
2.5V Transient Response
3.3V Transient Response
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
V
V
OUT
OUT
50mV/DIV
50mV/DIV
4603 G08
4603 G07
25µs/DIV
25µs/DIV
3.3V AT 3A/µs LOAD STEP
2.5V AT 3A/µs LOAD STEP
C
: 1x 22µF, 6.3V CERAMIC
C
: 1x 22µF, 6.3V CERAMIC
OUT
OUT
1x 330µF, 4V SANYO POSCAP
1x 330µF, 4V SANYO POSCAP
4603f
5
LTM4603/LTM4603-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS (See Figure 18 for all curves)
Start-Up, IOUT = 6A
(Resistive Load)
Short-Circuit Protection,
IOUT = 0A
Start-Up, IOUT = 0A
V
V
OUT
0.5V/DIV
V
OUT
OUT
0.5V/DIV
0.5V/DIV
I
IN
I
0.5A/DIV
IN
I
IN
2A/DIV
0.5A/DIV
4603 G10
4603 G11
4603 G09
1ms/DIV
100µs/DIV
1ms/DIV
V
V
C
= 12V
OUT
OUT
V
V
C
= 12V
IN
OUT
OUT
V
V
C
= 12V
OUT
OUT
IN
IN
= 1.5V
= 1.5V
= 1.5V
= 1x 22µF, 6.3V CERAMIC
= 1x 22µF, 6.3V CERAMIC
= 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
1x 330µF, 4V SANYO POSCAP
1x 330µF, 4V SANYO POSCAP
SOFT-START = 3.9nF
SOFT-START = 3.9nF
SOFT-START = 3.9nF
Short-Circuit Protection,
IOUT = 6A
VIN to VOUT Step-Down Ratio
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.3V OUTPUT WITH
82.5k FROM V
OUT
TO f
SET
V
OUT
5V OUTPUT WITH
150k RESISTOR
0.5V/DIV
ADDED FROM f
TO GND
SET
5V OUTPUT WITH
NO RESISTOR ADDED
FROM f TO GND
I
IN
SET
2A/DIV
2.5V OUTPUT
1.8V OUTPUT
1.5V OUTPUT
1.2V OUTPUT
4603 G12
100µs/DIV
V
V
C
= 12V
OUT
OUT
IN
= 1.5V
= 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
0
2
4
6
8
10 12 14 16 18 20
SOFT-START = 3.9nF
INPUT VOLTAGE (V)
4603 G13
4603f
6
LTM4603/LTM4603-1
U
U
U
PI FU CTIO S
(See Package Description for Pin Assignment)
V (Bank 1): Power Input Pins. Apply input voltage be-
INTV (Pin A7): This pin is for additional decoupling of
IN
CC
tween these pins and PGND pins. Recommend placing
the 5V internal regulator.
input decoupling capacitance directly between V pins
IN
PLLIN (Pin A8): External Clock Synchronization Input to
the Phase Detector. This pin is internally terminated to
SGND with a 50k resistor. Apply a clock above 2V and
and PGND pins.
V
(Bank 3): Power Output Pins. Apply output load
OUT
between these pins and PGND pins. Recommend placing
outputdecouplingcapacitancedirectlybetweenthesepins
and PGND pins. Review the figure below.
below INTV . See Applications Information.
CC
TRACK/SS (Pin A9): Output Voltage Tracking and Soft-
Start Pin. When the module is configured as a master
output, then a soft-start capacitor is placed on this pin
to ground to control the master ramp rate. A soft-start
capacitor can be used for soft-start turn on as a stand
alone regulator. Slave operation is performed by putting
a resistor divider from the master output to the ground,
and connecting the center point of the divider to this pin.
See Applications Information.
PGND (Bank 2): Power ground pins for both input and
output returns.
–
V
OSNS
(PinM12):(–)InputtotheRemoteSenseAmplifier.
This pin connects to the ground remote sense point. The
remote sense amplifier is used for V ≤3.3V.
OUT
NC1 (Pin M12): No Connect on the LTM4603-1.
+
V
(PinJ12):(+)InputtotheRemoteSenseAmplifier.
OSNS
MPGM (Pin A12): Programmable Margining Input. A re-
sistor from this pin to ground sets a current that is equal
to 1.18V/R. This current multiplied by 10kΩ will equal a
value in millivolts that is a percentage of the 0.6V refer-
ence voltage. See Applications Information. To parallel
LTM4603s, each requires an individual MPGM resistor.
Do not tie MPGM pins together.
This pin connects to the output remote sense point. The
remote sense amplifier is used for V ≤3.3V.
OUT
NC2 (Pin J12): No Connect on the LTM4603-1.
DIFFV (Pin K12): Output of the Remote Sense Ampli-
OUT
fier. This pin connects to the V
pin.
OUT_LCL
NC3 (Pin K12): No Connect on the LTM4603-1.
f
(Pin B12): Frequency Set Internally to 1MHz. An
SET
DRV (Pin E12): This pin normally connects to INTV
external resistor can be placed from this pin to ground
to increase frequency. This pin can be decoupled with a
1000pF capacitor. See Applications Information for fre-
quency adjustment.
CC
CC
for powering the internal MOSFET drivers. This pin can
be biased up to 6V from an external supply with about
50mA capability, or an external circuit shown in Figure
16. This improves efficiency at the higher input voltages
by reducing power dissipation in the modules.
V
(Pin F12): The Negative Input of the Error Ampli-
FB
fier. Internally, this pin is connected to V
with a
OUT_LCL
60.4k precision resistor. Different output voltages can be
TOP VIEW
A
B
C
D
E
V
IN
f
SET
BANK 1
MARG0
MARG1
DRV
CC
PGND
BANK 2
F
V
FB
G
H
J
PGOOD
SGND
+
V
(NC2, LTM4603-1)
(NC3, LTM4603-1)
OSNS
K
L
M
DIFFV
V
OUT
OUT
BANK 3
V
V
OUT_LCL
–
(NC1, LTM4603-1)
OSNS
1
2 3 4 5 6 7 8 9 10 11 12
4603f
7
LTM4603/LTM4603-1
U
U
U
PI FU CTIO S
(See Package Description for Pin Assignment)
programmed with an additional resistor between V and
ranges from 0V to 2.4V with 0.7V corresponding to zero
sense voltage (zero current).
FB
SGND pins. See Applications Information.
MARG0 (Pin C12): This pin is the LSB logic input for the
margining function. Together with the MARG1 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.
PGOOD (Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within 10% of the regulation point,
after a 25µs power bad mask timer expires.
RUN (Pin A10): Run Control Pin. A voltage above 1.9V
will turn on the module, and when below 1.9V, will turn
off the module. A programmable UVLO function can be
MARG1 (Pin D12): This pin is the MSB logic input for the
margining function. Together with the MARG0 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.
accomplished with a resistor from V to this pin that has
IN
a 5.1V zener to ground. Maximum pin voltage is 5V.
V
(Pin L12): V
connects directly to this pin
OUT_LCL
OUT
SGND (Pin H12): Signal Ground. This pin connects to
PGND at output capacitor point.
to bypass the remote sense amplifier, or DIFFV
con-
OUT
nects to this pin when remote sense amplifier is used.
V
V
can be connected to V
is internally connected to V
on the LTM4603-1.
OUT_LCL
OUT_LCL
OUT
OUT
COMP (Pin A11): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
through 50Ω in
the LTM4603-1.
W
W
SI PLIFIED BLOCK DIAGRA
V
1M
OUT_LCL
V
OUT
>2V = ON
<0.9V = OFF
MAX = 5V
RUN
PGOOD
COMP
V
IN
4.5V TO 28V
+
5.1V
ZENER
1.5µF
C
IN
60.4k
INTERNAL
COMP
POWER CONTROL
Q1
Q2
SGND
V
2.5V
6A
OUT
MARG1
MARG0
22µF
V
FB
50k 50k
+
f
SET
R
FB
40.2k
C
OUT
33.2k
PGND
INTV
CC
MPGM
TRACK/SS
PLLIN
10k
–
10k
V
V
OSNS
–
C
SS
+
10k
+
OSNS
50k
10k
INTV
DRV
CC
DIFFV
4.7µF
OUT
CC
4603 F01
Figure 1. Simplified LTM4603/LTM4603-1 Block Diagram
4603f
8
LTM4603/LTM4603-1
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DECOUPLI G REQUIRE E TS
TA = 25°C, VIN = 12V. Use Figure 1 configuration.
CONDITIONS MIN
20
SYMBOL
PARAMETER
TYP
MAX
UNITS
C
External Input Capacitor Requirement
I
I
= 6A
= 6A
µF
IN
OUT
OUT
(V = 4.5V to 20V, V
= 1.5V)
IN
OUT
C
External Output Capacitor Requirement
100
200
µF
OUT
(V = 4.5V to 20V, V
= 1.5V)
IN
OUT
U
OPERATIO
Power Module Description
and bottom FET Q2 is turned on and held on until the
overvoltage condition clears.
TheLTM4603isastandalonenonisolatedswitchingmode
DC/DC power supply. It can deliver up to 6A of DC output
current with few external input and output capacitors.
This module provides precisely regulated output voltage
Pulling the RUN pin below 1V forces the controller into its
shutdown state, turning off both Q1 and Q2. At low load
current, the module works in continuous current mode by
default to achieve minimum output voltage ripple.
programmable via one external resistor from 0.6V to
DC
5.0V over a 4.5V to 20V wide input voltage. The typical
DC
When DRV pin is connected to INTV an integrated
CC
CC
application schematic is shown in Figure 18.
5V linear regulator powers the internal gate drivers. If a
The LTM4603 has an integrated constant on-time current
5V external bias supply is applied on the DRV pin, then
CC
mode regulator, ultralow R
FETs with fast switching
an efficiency improvement will occur due to the reduced
powerlossintheinternallinearregulator.Thisisespecially
true at the higher input voltage range.
DS(ON)
speedandintegratedSchottkydiodes.Thetypicalswitching
frequency is 1MHz at full load. With current mode control
and internal feedback loop compensation, the LTM4603
modulehassufficientstabilitymarginsandgoodtransient
performance under a wide range of operating conditions
andwithawiderangeofoutputcapacitors,evenallceramic
output capacitors.
The LTM4603 has a very accurate differential remote
sense amplifier with very low offset. This provides for
very accurate remote sense voltage measurement. The
MPGM pin, MARG0 pin and MARG1 pin are used to sup-
port voltage margining, where the percentage of margin
is programmed by the MPGM pin, and the MARG0 and
MARG1 select margining.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limit. Besides, foldback current limiting is provided in an
overcurrentconditionwhileV drops.Internalovervoltage
andundervoltagecomparatorspulltheopen-drainPGOOD
output low if the output feedback voltage exits a 10%
window around the regulation point. Furthermore, in an
overvoltage condition, internal top FET Q1 is turned off
FB
The PLLIN pin provides frequency synchronization of the
device to an external clock. The TRACK/SS pin is used for
power supply tracking and soft-start programming.
4603f
9
LTM4603/LTM4603-1
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APPLICATIO S I FOR ATIO
The typical LTM4603 application circuit is shown in
Figure 18. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 2 for specific external capacitor
requirements for a particular application.
where%V isthepercentageofV youwanttomargin,
OUT
OUT
and V
is the margin quantity in volts:
OUT(MARGIN)
VOUT
1.18V
•10k
RPGM
=
•
0.6V VOUT(MARGIN)
where RPGM is the resistor value to place on the MPGM
pin to ground.
V to V
Step-Down Ratios
IN
OUT
There are restrictions in the maximum V and V
step
IN
OUT
The output margining will be margining of the value.
This is controlled by the MARG0 and MARG1 pins. See
the truth table below:
down ratio that can be achieved for a given input voltage.
These constraints are shown in the Typical Performance
Characteristics curves labeled V to V
Step-Down
IN
OUT
Ratio.Notethatadditionalthermalderatingmayapply.See
the Thermal Considerations and Output Current Derating
section of this data sheet.
MARG0
LOW
MARG1
LOW
MODE
NO MARGIN
MARGIN UP
MARGIN DOWN
NO MARGIN
LOW
HIGH
LOW
HIGH
HIGH
Output Voltage Programming and Margining
HIGH
The PWM controller has an internal 0.6V reference volt-
age. As shown in the Block Diagram, a 1M and a 60.4k
Input Capacitors
0.5%internalfeedbackresistorconnectsV andFBpins
OUT
LTM4603moduleshouldbeconnectedtoalowACimped-
anceDCsource. Inputcapacitorsarerequiredtobeplaced
adjacent to the module. In Figure 18, the 10µF ceramic
input capacitors are selected for their ability to handle
the large RMS current into the converter. An input bulk
capacitorof100µFisoptional.This100µFcapacitorisonly
needed if the input source impedance is compromised by
long inductive leads or traces.
together. The V
pin is connected between the 1M
OUT_LCL
and the 60.4k resistor. The 1M resistor is used to protect
against an output overvoltage condition if the V
OUT_LCL
pin is not connected to the output, or if the remote sense
amplifier output is not connected to V . The output
OUT_LCL
voltage will default to 0.6V. Adding a resistor R
the FB pin to SGND pin programs the output voltage:
from
SET
For a buck converter, the switching duty-cycle can be
estimated as:
60.4k +RSET
VOUT = 0.6V
RSET
VOUT
D=
Table 1. Standard 1% Resistor Values
V
IN
R
SET
Open 60.4
0.6 1.2
40.2
1.5
30.1
1.8
25.5
2
19.1
2.5
13.3
3.3
8.25
5
(kΩ)
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
V
OUT
(V)
IOUT(MAX)
The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference
offset for margining. A 1.18V reference divided by the
RPGM resistor on the MPGM pin programs the current.
ICIN(RMS)
=
• D• 1–D
(
)
η%
In the above equation, η% is the estimated efficiency of
the power module. C can be a switcher-rated electrolytic
IN
Calculate V
:
OUT(MARGIN)
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitor. Note the capacitor ripple current rat-
ings are often based on temperature and hours of life. This
makes it advisable to properly derate the input capacitor,
%VOUT
100
VOUT(MARGIN)
=
• VOUT
4603f
10
LTM4603/LTM4603-1
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APPLICATIO S I FOR ATIO
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
Output Capacitors
The LTM4603 is designed for low output voltage ripple.
The bulk output capacitors defined as C are chosen
OUT
In Figure 18, the 10µF ceramic capacitors are together
used as a high frequency input decoupling capacitor. In a
typical 6A output application, two very low ESR, X5R or
X7R, 10µF ceramic capacitors are recommended. These
decoupling capacitors should be placed directly adjacent
to the module input pins in the PCB layout to minimize
the trace inductance and high frequency AC noise. Each
10µF ceramic is typically good for 2A to 3A of RMS ripple
current. Refer to your ceramics capacitor catalog for the
RMS current ratings.
with low enough effective series resistance (ESR) to meet
theoutputvoltagerippleandtransientrequirements. C
OUT
can be a low ESR tantalum capacitor, a low ESR polymer
capacitororaceramiccapacitor.Thetypicalcapacitanceis
200µF if all ceramic output capacitors are used. Additional
output filtering may be required by the system designer,
if further reduction of output ripple or dynamic transient
spikeisrequired.Table2showsamatrixofdifferentoutput
voltages and output capacitors to minimize the voltage
droop and overshoot during a 2.5A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to maximize transient performance.
Multiphase operation with multiple LTM4603 devices in
parallelwilllowertheeffectiveinputRMSripplecurrentdue
to the interleaving operation of the regulators. Application
Note 77 provides a detailed explanation. Refer to Figure 2
fortheinputcapacitorripplecurrentrequirementasafunc-
tion of the number of phases. The figure provides a ratio
of RMS ripple current to DC load current as a function of
duty cycle and the number of paralleled phases. Pick the
corresponding duty cycle and the number of phases to
arrive at the correct ripple current value. For example, the
2-phase parallel LTM4603 design provides 10A at 2.5V
output from a 12V input. The duty cycle is DC = 2.5V/12V
= 0.21. The 2-phase curve has a ratio of ~0.25 for a duty
cycle of 0.21. This 0.25 ratio of RMS ripple current to a
DC load current of 10A equals ~2.5A of input RMS ripple
current for the external input capacitors.
Multiphase operation with multiple LTM4603 devices in
parallel will lower the effective output ripple current due
to the interleaving operation of the regulators. For ex-
ample, each LTM4603’s inductor current of a 12V to 2.5V
multiphase design can be read from the “Inductor Ripple
versus Duty Cycle” (Figure 3). The large ripple current at
low duty cycle and high output voltage can be reduced
by adding an external resistor from f to ground which
SET
increases the frequency. If we choose the duty cycle of
DC = 2.5V/12V = 0.21, the inductor ripple current for 2.5V
output at 21% duty cycle is ~2.5A in Figure 3.
5
0.6
2.5V OUTPUT
5V OUTPUT
0.5
4
1.8V OUTPUT
1.5V OUTPUT
1-PHASE
0.4
2-PHASE
3
2
1
0
1.2V OUTPUT
3-PHASE
4-PHASE
3.3V OUTPUT WITH
82.5k ADDED FROM
0.3
6-PHASE
V
OUT
TO f
SET
0.2
5V OUTPUT WITH
150k ADDED FROM
f
TO GND
0.1
SET
0
0
20
DUTY CYCLE (V /V )
OUT IN
40
60
80
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V /V
)
OUT IN
4603 F02
4603 F03
Figure 3. Inductor Ripple Current vs Duty Cycle
Figure 2. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Modules (Phases)
4603f
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LTM4603/LTM4603-1
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APPLICATIO S I FOR ATIO
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
IN
4603 F04
O
Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI
Figure4providesaratioofpeak-to-peakoutputripplecur-
Fault Conditions: Current Limit and Overcurrent
rent to the inductor current as a function of duty cycle and
the number of paralleled phases. Pick the corresponding
dutycycleandthenumberofphasestoarriveatthecorrect
output ripple current ratio value. If a 2-phase operation is
chosen at a duty cycle of 21%, then 0.6 is the ratio. This
0.6 ratio of output ripple current to inductor ripple of 2.5A
equals 1.5A of effective output ripple current. Refer to Ap-
plicationNote77foradetailedexplanationofoutputripple
current reduction as a function of paralleled phases.
Foldback
The LTM4603 has a current mode controller, which inher-
ently limits the cycle-by-cycle inductor current not only in
steady-state operation, but also in transient.
To further limit current in the event of an overload condi-
tion,theLTM4603providesfoldbackcurrentlimiting.Ifthe
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to about one sixth
of its full current limit value.
The output voltage ripple has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
Therefore, the output voltage ripple can be calulated with
the known effective output ripple current. The equation:
Soft-Start and Tracking
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A
capacitor on this pin will program the ramp rate of the
output voltage. A 1.4µA current source will charge up the
external soft-start capacitor to 80% of the 0.6V internal
voltagereferenceminusanymargindelta.Thiswillcontrol
ΔV
≈ (ΔI /(8 • f • m • C ) + ESR • ΔI ), where f
OUT(P-P)
L OUT L
is frequency and m is the number of parallel phases. This
calclation process can be easily fulfilled using our Excel
tool (refer to??).
4603f
12
LTM4603/LTM4603-1
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APPLICATIO S I FOR ATIO
Run Enable
the ramp of the internal reference and the output voltage.
The total soft-start time can be calculated as:
The RUN pin is used to enable the power module. The
pin has an internal 5.1V zener to ground. The pin can be
driven with a logic input not to exceed 5V.
CSS
1.5µA
tSOFTSTART = 0.8V • 0.6V – V
•
(
)
OUT(MARGIN)
The RUN pin can also be used as an undervoltage lock out
(UVLO) function by connecting a resistor divider from the
input supply to the RUN pin:
WhentheRUNpinfallsbelow1.5V, thentheSSpinisreset
to allow for proper soft-start control when the regulator
is enabled again. Current foldback and force continuous
mode are disabled during the soft-start process. The
soft-start function can also be used to control the output
ramp up time, so that another regulator can be easily
tracked to it.
R1+R2
VUVLO
=
•1.5V
R2
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point and tracks
with margining.
Output Voltage Tracking
Output voltage tracking can be programmed externally
usingtheTRACK/SSpin. Theoutputcanbetrackedupand
downwithanotherregulator.Themasterregulator’soutput
is divided down with an external resistor divider that is the
same as the slave regulator’s feedback divider. Figure 5
shows an example of coincident tracking. Ratiometric
modes of tracking can be achieved by selecting different
resistor values to change the output tracking ratio. The
master output must be greater than the slave output for
the tracking to work. Figure 6 shows the coincident output
tracking characteristics.
COMP Pin
This pin is the external compensation pin. The module
has already been internally compensated for most output
voltages. Table 2 is provided for most application require-
ments. A spice model will be provided for other control
loop optimization.
PLLIN
MASTER
OUTPUT
Thepowermodulehasaphase-lockedloopcomprisedofan
internal voltage controlled oscillator and a phase detector.
This allows the internal top MOSFET turn-on to be locked
R2
60.4k
TRACK CONTROL
V
IN
R1
40.2k
60.4k FROM
TO V
100k
V
PLLIN TRACK/SS
V
IN
OUT
FB
MASTER OUTPUT
SLAVE OUTPUT
PGOOD
V
OUT
MPGM
RUN
COMP
V
C
FB
OUT
MARG0
MARG1
V
OUT_LCL
SLAVE OUTPUT
OUTPUT
VOLTAGE
LTM4603
C
IN
INTV
CC
DRV
DIFFV
CC
OUT
+
V
V
OSNS
–
OSNS
f
SGND PGND
SET
R
SET
40.2k
4603 F05
4603 F06
TIME
Figure 6
Figure 5
4603f
13
LTM4603/LTM4603-1
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APPLICATIO S I FOR ATIO
to the rising edge of the external clock. The frequency
range is 30% around the operating frequency of 1MHz.
A pulse detection circuit is used to detect a clock on the
PLLIN pin to turn on the phase lock loop. The pulse width
of the clock has to be at least 400ns and 2V in amplitude.
During the start-up of the regulator, the phase-lock loop
function is disabled.
sharing. This will balance the thermals on the design. The
voltage feedback equation changes with the variable η as
modules are paralleled:
60.4k
η
+RFB
VOUT = 0.6V
RFB
η is the number of paralleled modules.
INTV and DRV Connection
CC
CC
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRV
for driving the internal power MOSFETs. Therefore, if
the system does not have a 5V power rail, the LTM4603
can be directly powered by Vin. The gate driver current
through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:
Thermal Considerations and Output Current Derating
CC
The power loss curves in Figures 7 and 8 can be used
in coordination with the load current derating curves in
Figures 9 to 12, and Figures 13 to 14 for calculating an
approximate θ for the module with various heat sinking
JA
methods. Thermal models are derived from several tem-
peraturemeasurementsatthebenchandthermalmodeling
analysis.ThermalApplicationNote103providesadetailed
explanation of the analysis for the thermal models and the
derating curves. Tables 3 and 4 provide a summary of the
P
= 20mA • (V – 5V)
IN
LDO_LOSS
The LTM4603 also provides the external gate driver volt-
age pin DRV . If there is a 5V rail in the system, it is
CC
equivalent θ for the noted conditions. These equivalent
JA
recommended to connect DRV pin to the external 5V
CC
θ
JA
parameters are correlated to the measured values,
rail. This is especially true for higher input voltages. Do
and are improved with air flow. The case temperature is
maintained at 100°C or below for the derating curves.
This allows for 4W maximum power dissipation in the
total module with top and bottom heatsinking, and 2W
power dissipation through the top of the module with an
not apply more than 6V to the DRV pin. A 5V output can
CC
be used to power the DRV pin with an external circuit
CC
as shown in Figure 16.
Parallel Operation of the Module
approximate θ between 6°C/W to 9°C/W. This equates
JC
The LTM4603 device is an inherently current mode con-
trolleddevice.Parallelmoduleswillhaveverygoodcurrent
to a total of 124°C at the junction of the device.
3.5
6
3.5
3.0
3.0
5
20V LOSS
20V LOSS
2.5
2.0
1.5
1.0
0.5
2.5
2.0
1.5
1.0
0.5
12V LOSS
5V LOSS
4
3
12V LOSS
2
5V , 1.5V , 0LFM
IN
OUT
1
0
5V , 1.5V , 200LFM
IN
IN
OUT
OUT
5V , 1.5V , 400LFM
0
0
4
6
7
0
1
2
3
5
75
80
85
90
95
4
6
7
0
1
2
3
5
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
OUTPUT CURRENT (A)
4603 F07
4603 F09
4603 F08
Figure 7. 1.5V Power Loss
Figure 8. 3.3V Power Loss
Figure 9. No Heat Sink
4603f
14
LTM4603/LTM4603-1
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APPLICATIO S I FOR ATIO
6
6
5
6
5
5
4
3
4
3
4
3
2
1
0
2
2
1
0
12V , 1.5V , 0LFM
5V , 1.5V , 0LFM
1
0
IN
OUT
IN
OUT
12V , 1.5V , 200LFM
5V , 1.5V , 200LFM
IN
IN
OUT
OUT
IN
IN
OUT
OUT
12V , 1.5V , 400LFM
5V , 1.5V , 400LFM
70
75
80
85
90
95
70
75
80
85
90
95
75
80
85
90
95
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4603 F11
4603 F12
4603 F10
12V , 1.5V , 0LFM
IN
OUT
12V , 1.5V , 200LFM
IN
OUT
Figure 10. BGA Heat Sink
Figure 12. BGA Heat Sink
12V , 1.5V , 400LFM
IN
OUT
Figure 11. No Heat Sink
6
5
6
5
4
3
4
3
2
2
1
0
12V , 3.3V , 0LFM
1
0
IN
OUT
12V , 3.3V , 0LFM
IN
IN
OUT
OUT
OUT
12V , 3.3V , 200LFM
IN
IN
OUT
OUT
12V , 3.3V , 200LFM
12V , 3.3V , 400LFM
12V , 3.3V , 400LFM
IN
70
75
80
85
90
95
70
75
80
85
90
95
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4603 F13
4603 F14
Figure 14. BGA Heat Sink
Figure 13. No Heat Sink
4603f
15
LTM4603/LTM4603-1
Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 18)
TYPICAL MEASURED VALUES
C
VENDORS
PART NUMBER
C
OUT2
VENDORS
PART NUMBER
OUT1
TAIYO YUDEN
TAIYO YUDEN
TDK
JMK316BJ226ML-T501 (22µF, 6.3V)
JMK325BJ476MM-T (47µF, 6.3V)
C3225X5R0J476M (47µF, 6.3V)
SANYO POSCAP
SANYO POSCAP
SANYO POSCAP
6TPE220MIL (220µF, 6.3V)
2R5TPE330M9 (330µF, 2.5V)
4TPE330MCL (330µF, 4V)
V
C
C
C
C
V
(V)
DROOP
(mV)
PEAK TO
PEAK (mV)
RECOVERY
TIME (µs)
LOAD STEP
(A/µs)
R
SET
OUT
IN
IN
OUT1
OUT2
IN
(V)
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5
(CERAMIC)
(BULK)
(CERAMIC)
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
4 × 47µF 6.3V
4 × 47µF 6.3V
(BULK)
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
(kΩ)
60.4
60.4
60.4
60.4
60.4
60.4
60.4
60.4
40.2
40.2
40.2
40.2
40.2
40.2
40.2
40.2
30.1
30.1
30.1
30.1
30.1
30.1
30.1
30.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
13.3
13.3
13.3
13.3
13.3
13.3
13.3
13.3
8.25
8.25
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
2 × 10µF 25V 150µF 35V
5
34
22
68
40
30
26
24
18
30
26
24
18
30
30
26
26
30
30
26
26
37
30
26
26
37
30
26
26
40
34
28
12
40
34
28
18
40
32
28
14
40
32
28
22
20
20
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
5
20
40
5
32
60
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
12
12
12
12
5
34
68
22
40
20
39
29.5
35
55
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
70
5
25
48
5
24
47.5
68
5
36
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
12
12
12
12
5
35
70
25
48
24
45
32.6
38
61.9
76
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
5
29.5
28
57.5
55
5
5
43
80
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
12
12
12
12
5
38
76
28
55
27
52
36.4
38
70
330µF 4V
330µF 4V
220µF 6.3V
NONE
78
5
37.6
39.5
66
74
5
78.1
119
78
5
330µF 4V
330µF 4V
220µF 6.3V
NONE
12
12
12
12
7
38
34.5
35.8
50
66.3
68.8
98
330µF 4V
330µF 4V
220µF 6.3V
NONE
42
86
7
47
89
7
50
94
7
75
141
86
330µF 4V
330µF 4V
220µF 6.3V
NONE
12
12
12
12
15
20
42
47
88
50
94
69
131
215
217
NONE
110
110
5
NONE
4603f
16
LTM4603/LTM4603-1
U
W U U
APPLICATIO S I FOR ATIO
Table 3. 1.5V Output
DERATING CURVE
Figures 9, 11
V
(V)
POWER LOSS CURVE
Figure 7
AIR FLOW (LFM)
HEAT SINK
None
θ
JA
(°C/W)
IN
5, 12
5, 12
0
15.2
14
Figures 9, 11
Figure 7
200
400
0
None
Figures 9, 11
5, 12
Figure 7
None
12
Figures 10, 12
Figures 10, 12
Figures 10, 12
5, 12, 20
5, 12, 20
5, 12, 20
Figure 7
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
13.9
11.3
10.25
Figure 7
200
400
Figure 7
Table 4. 3.3V Output
DERATING CURVE
Figure 13
V
IN
(V)
POWER LOSS CURVE
Figure 8
AIR FLOW (LFM)
HEAT SINK
None
θ
JA
(°C/W)
12
0
15.2
14.6
13.4
13.9
11.1
10.5
Figure 13
12
12
12
12
12
Figure 8
200
400
0
None
Figure 13
Figure 8
None
Figure 14
Figure 8
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 14
Figure 8
200
400
Figure 14
Figure 8
Heat Sink Manufacturer
Wakefield Engineering
Part No: 20069
Phone: 603-635-2800
4603f
17
LTM4603/LTM4603-1
U
W U U
APPLICATIO S I FOR ATIO
Safety Considerations
• Do not put vias directly on pads.
TheLTM4603modulesdonotprovideisolationfromV to
OUT
with a rating twice the maximum input current needs to be
provided to protect each unit from catastrophic failure.
• If vias are placed onto the pads, the the vias must be
capped.
IN
V
.Thereisnointernalfuse.Ifrequired,aslowblowfuse
• Interstitialvia placementcan also beused if necessary.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
Layout Checklist/Example
The high integration of LTM4603 makes the PCB board
layoutverysimpleandeasy.However,tooptimizeitselectri-
cal and thermal performance, some layout considerations
are still necessary.
Figure 15 gives a good example of the recommended
layout.
Frequency Adjustment
• Use large PCB copper areas for high current path, in-
The LTM4603 is designed to typically operate at 1MHz
cluding V , PGND and V . It helps to minimize the
IN
OUT
across most input conditions. The f pin is typically left
PCB conduction loss and thermal stress.
SET
open or decoupled with an optional 1000pF capacitor. The
switching frequency has been optimized for maintaining
constant output ripple noise over most operating ranges.
The 1MHz switching frequency and the 400ns minimum
off time can limit operation at higher duty cycles like 5V to
3.3V, and produce excessive inductor ripple currents for
lower duty cycle applications like 20V to 5V. The 5V and
3.3V drop out curves are modified by adding an external
• Place high frequency ceramic input and output capaci-
tors next to the V , PGND and V
pins to minimize
IN
OUT
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
resistor on the f
pin to allow for lower input voltage
SET
operation, or higher input voltage operation.
V
IN
C
C
IN
IN
GND
SIGNAL
GND
C
C
OUT
OUT
V
OUT
4603 F15
Figure 15. Recommended Layout
4603f
18
LTM4603/LTM4603-1
U
W U U
APPLICATIO S I FOR ATIO
Example for 5V Output
Example for 3.3V Output
LTM4603 minimum on-time = 100ns;
= ((3.3 • 10pF)/I
LTM4603 minimum on-time = 100ns;
t
= ((4.8 • 10pf)/I
)
t
)
fSET
ON
fSET
ON
LTM4603 minimum off-time = 400ns; t = t – t ,
LTM4603 minimum off-time = 400ns;
= t – t , where t = 1/Frequency
OFF
ON
where t = 1/Frequency
t
OFF
ON
Duty Cycle = t /t or V /V
Duty Cycle (DC) = t /t or V /V
OUT IN
ON
OUT IN
ON
Equations for setting frequency:
=(V /(3•R )),for20Voperation,I =201µA,t
Equations for setting frequency:
I
I
t
= (V /(3 • R )), for 20V operation, I
= 201µA,
fSET
IN
fSET
SET
ON
fSET
IN
fSET
fSET
=((4.8•10pF)/I ), t =239ns, wheretheinternalR
= ((3.3 • 10pf)/I ), t = 164ns, where the internal
fSET ON
fSET
ON
fSET ON
is33.2k.Frequency=(V /(V •t ))=(5V/(20•239ns))
R
is 33.2k. Frequency = (V /(V • t )) = (3.3V/(20
OUT IN ON
fSET OUT IN ON
~1MHz.Theinductorripplecurrentbeginstogethighatthe
higher input voltages due to a larger voltage across the in-
ductor.Thisisnotedinthe“TypicalInductorRippleCurrent
verses Duty Cycle graph” at ~4.5A at 25% duty cycle. The
inductor ripple current can be lowered at the higher input
• 164ns)) ~ 1MHz. The minimum on-time and minimum-
off time are within specification at 164ns and 836ns. The
4.5V minimum input for converting 3.3V output will not
meet the minimum off-time specification of 400ns. t
=
ON
733ns, Frequency = 1MHz, t = 267ns.
OFF
voltagesbyaddinganexternalresistorfromf toground
SET
Solution
to increase the switching frequency. A 3A ripple current is
chosen, and the total peak current is equal to 1/2 of the 3A
ripplecurrentplustheoutputcurrent.The5Voutputcurrent
islimitedto5A,sototalpeakcurrentislessthan6.5A.Thisis
belowthe7Apeakspecifiedvalue.A150kresistorisplaced
Lower the switching frequency at lower input voltages to
allow for higher duty cycles, and meet the 400ns mini-
mum off-time at 4.5V input voltage. The off-time should
be about 500ns with 100ns guard band. The duty cycle
from f to ground, and the parallel combination of 150k
SET
for (3.3V/4.5) = ~73%. Frequency = (1 – DC)/t , or
OFF
and33.2kequatesto27.2k.TheI
and 20V input voltage equals 245µA. This equates to a t
calculationwith27.2k
fSET
(1–0.73)/500ns=540kHz.Theswitchingfrequencyneeds
ON
tobeloweredto540kHzat4.5Vinput. t =DC/frequency,
ON
of 196ns. This will increase the switching frequency from
1MHz to ~1.28MHz for the 20V to 5V conversion. The
minimum on time is above 100ns at 20V input. Since
the switching frequency is approximately constant over
input and output conditions, then the lower input voltage
range is limited to 10V for the 1.28MHz operation due to
or 1.35µs. The f
pin voltage compliance is 1/3 of V ,
SET
IN
and the I
current equates to 45µA with the internal
fSET
33.2k. The I
current needs to be 24µA for 540kHz
fSET
operation. A resistor can be placed from V
to f
to
OUT
SET
SET
lower the effective I
current out of the f pin to 24µA.
fSET
The f
pin is 4.5V/3 =1.5V and V
= 3.3V, therefore
OUT
node and lower the
SET
the 400ns minimum off time. Equation: t = (V /V )
ON
OUT IN
82.5k will source 21µA into the f
SET
• (1/Frequency) equates to a 382ns on time, and a 400ns
I
current to 24µA. This enables the 540kHz operation
fSET
off time. The “V to V Step Ratio Curve” reflects an
IN
OUT
and the 4.5V to 20V input operation for down converting
to 3.3V output. The frequency will scale from 540kHz to
1.2MHzoverthisinputrange.Thisprovidesforaneffective
output current of 5A over the input range.
operating range of 10V to 20V for 1.28MHz operation with
a 150k resistor to ground, and an 8V to 16V operation for
f
floating. These modifications are made to provide
SET
wider input voltage ranges for the 5V output designs while
limiting the inductor ripple current, and maintaining the
400ns minimum off time.
4603f
19
LTM4603/LTM4603-1
U
W U U
APPLICATIO S I FOR ATIO
V
OUT
TRACK/SS CONTROL
V
IN
10V TO 20V
REVIEW TEMPERATURE
DERATING CURVE
R2
R4
V
PLLIN TRACK/SS
V
5V
5A
IN
100k 100k
OUT
PGOOD
V
OUT
C3
C6 100pF
+
100µF
6.3V
MPGM
RUN
V
FB
REFER TO
MARG0
MARG1
SANYO POSCAP TABLE 2
COMP
INTV
DRV
LTM4603-1
V
CC
CC
OUT_LCL
NC3
5% MARGIN
R1
392k
1%
INTV
NC1
NC2
CC
C2
10µF
f
SGND PGND
SET
25V
C1
10µF
R
R
SET
8.25k
fSET
150k
25V
MARGIN CONTROL
IMPROVE
EFFICIENCY
SOT-323
FOR ≥12V INPUT
DUAL
CMSSH-3C3
4603 F16
Figure 16. 5V at 5A Design Without Differential Amplifier
V
OUT
TRACK/SS CONTROL
V
IN
4.5V TO 20V
REVIEW TEMPERATURE
DERATING CURVE
R2
R4
V
PLLIN TRACK/SS
V
3.3V
5A
IN
100k 100k
OUT
PGOOD
V
OUT
C6 100pF
PGOOD
MPGM
RUN
V
FB
C3
MARG0
MARG1
V
OUT_LCL
+
100µF
COMP
INTV
DRV
LTM4603
6.3V
CC
CC
SANYO POSCAP
DIFFV
OUT
+
C2
V
V
OSNS
R1
392k
10µF
25V
–
OSNS
R
f
fSET
C1
10µF
25V
SGND PGND
SET
R
SET
82.5k
13.3k
5% MARGIN
MARGIN CONTROL
4603 F17
Figure 17. 3.3V at 5A Design
4603f
20
LTM4603/LTM4603-1
U
W U U
APPLICATIO S I FOR ATIO
CLOCK SYNC
C5
V
OUT
0.01µF
V
IN
4.5V TO 20V
REVIEW TEMPERATURE
DERATING CURVE
R2
100k
R4
100k
V
IN
PLLIN TRACK/SS
V
OUT
1.5V
6A
PGOOD
V
OUT
C3 100pF
+
C
C
OUT2
PGOOD
MPGM
RUN
COMP
V
OUT1
FB
22µF
470µF
MARG0
MARG1
V
OUT_LCL
MARGIN
CONTROL
6.3V
6.3V
ON/OFF
LTM4603
INTV
DRV
CC
CC
DIFFV
V
OUT
+
C
IN
+
R1
392k
BULK
OPT.
OSNS
–
V
OSNS
C
IN
TABLE 2
f
10µF
25V
SGND PGND
SET
R
SET
40.2k
REFER TO
TABLE 2
×2 CER
4603 F18
5% MARGIN
Figure 18. Typical 4.5V-20VIN, 1.5V at 6A Design
CLOCK SYNC 0° PHASE
2.5V
R10
60.4k
1.2V
R9
19.1k
4.5V TO 16V
R1
R2
V
PLLIN TRACK/SS
IN
1.2V AT 6A
100k 100k
C10
10µF
25V
C1
10µF
25V
PGOOD
V
OUT
C6 100pF
C4
22µF
6.3V
MPGM
RUN
V
FB
MARG0
MARG1
V
OUT_LCL
MARGIN
CONTROL
COMP
INTV
DRV
LTM4603
+
C5
CC
CC
C12
0.1µF
470µF
DIFFV
OUT
+
6.3V
V
V
OSNS
LTC6908-1
+
–
OSNS
1
2
3
4
5
6
V
OUT1
R5
392k
f
SGND PGND
SET
R7
60.4k
R11
118k
GND OUT2
SET MOD
2-PHASE
CLOCK SYNC 180° PHASE
2.5V
R4
OSCILLATOR
C3
0.01µF
4.5V TO 16V
R3
V
PLLIN TRACK/SS
IN
2.5V AT 6A
100k 100k
C11*
100µF
25V
C2
10µF
25V
+
PGOOD
V
OUT
C6 100pF
C7
22µF
6.3V
MPGM
RUN
V
FB
MARG0
MARG1
MARGIN
CONTROL
COMP
LTM4603
+
C8
INTV
V
OUT_LCL
CC
CC
470µF
DRV
DIFFV
OUT
+
6.3V
V
V
OSNS
–
OSNS
R6
392k
f
SGND PGND
SET
R8
19.1k
4603 F19
*C11 OPTIONAL TO REDUCE LC RINGING.
NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTIONS
Figure 19. 2-Phase, 2.5V and 1.2V at 6A with Tracking
4603f
21
LTM4603/LTM4603-1
U
TYPICAL APPLICATIO
4603f
22
LTM4603/LTM4603-1
U
PACKAGE DESCRIPTIO
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
4603f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTM4603/LTM4603-1
TYPICAL APPLICATION
3.3V at 5A, LTM4603-1 (No Remote Sense Amplifier)
V
IN
TRACK/SS CONTROL
PLLIN TRACK/SS
4.5V TO 20V
REVIEW TEMPERATURE
DERATING CURVE
R2
R4
V
V
3.3V
5A
IN
100k 100k
OUT
PGOOD
V
OUT
C6
100pF
PGOOD
MPGM
RUN
COMP
V
+
C3
100µF
FB
MARG0
MARG1
6.3V
LTM4603-1
INTV
V
CC
CC
OUT_LCL
NC3
DRV
R
R1
392k
R
fSET
SET
C2
NC2
NC1
82.5k
13.3k
10µF
35V
f
C1
10µF
35V
SGND PGND
SET
4603 TA05
5% MARGIN
MARGIN CONTROL
RELATED PARTS
PART NUMBER
LTC2900
DESCRIPTION
COMMENTS
Quad Supply Monitor with Adjustable Reset Timer
Power Supply Tracking Controller
Synchronous Isolated Flyback Controllers
10A DC/DC µModule
Monitors Four Supplies; Adjustable Reset Timer
LTC2923
Tracks Both Up and Down; Power Supply Sequencing
No Optocoupler Required; 3.3V, 12A Output; Simple Design
Basic 10A Power Supply
LT3825/LT3837
LTM4600
LTM4601
12A DC/DC µModule
with PLL, Output Tracking and Margining, LTM4603 Pin Compatible
Basic 6A Power Supply
LTM4602
6A DC/DC µModule
4603f
LT 0307 • PRINTED IN USA
24 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号:
LTM4604EV#PBF
LTM4604 - Low Voltage, 4A DC/DC µModule (Power Module) Regulator with Tracking; Package: LGA; Pins: 66; Temperature Range: -40°C to 85°C
Linear
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