LTM8049IY#PBF_技术文档

LTM8049

Dual SEPIC or Inverting

µModule DC/DC Converter

FEATURES

DESCRIPTION

TheLTM^®8049isaDualSEPIC/InvertingµModule^®(power

module) DC/DC Converter. Each of the two outputs can

be easily configured as a SEPIC or Inverting converter by

simplygroundingtheappropriateoutputrail.TheLTM8049

includes power devices, inductors, control circuitry and

passive components. All that is needed to complete the

design are input and output caps, and small resistors to

set the output voltages and switching frequency. Other

components may be used to control the soft-start and

undervoltage lockout.

n

Two Complete Switch Mode Power Supplies

n

SEPIC or Inverting Topology

n

Wide Input Voltage Range: 1.6V to 10V

n

1.5V to 14V or –1.5V to –14V Output Voltage

n

±A at 5V

from ±1V

OUT

IN

n

Selectable Switching Frequency: 100kHz to 1.5MHz

Power Good Outputs for Event Based Sequencing

User Configurable Undervoltage Lockout

(e4) RoHS Compliant Package with Gold Pad Finish

Low Profile 15mm × 9mm × 2.42mm Surface Mount

BGA Package

The LTM8049 is packaged in a thermally enhanced, com-

pact (15mm × 9mm) over-molded Ball Grid Array (BGA)

package suitable for automated assembly by standard

surface mount equipment. The LTM8049 is available with

SnPb (BGA) or RoHS compliant terminal finish.

APPLICATIONS

n

Battery Powered Regulator

n

Local Negative Voltage Regulator

n

All registered trademarks and trademarks are the property of their respective owners.

Low Noise Amplifier Power

TYPICAL APPLICATION

±±1V_OUTfrom 1.7V_INto 10V_IN

Maximum Load Current vs V_IN

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8049 ꢀꢁ0ꢂa

8049 ꢀꢁ0ꢂ

8049fa

1

For more information www.linear.com/LTM8049

LTM8049

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note ±)

ꢀꢁꢂ ꢃꢄꢅꢆ

V

, RUNn, PGn.......................................................20V

INn

ꢇꢉꢘꢋ ꢕ

SYNCn, FBXn ..............................................................5V

SSn..........................................................................2.5V

SHAREn ......................................................................2V

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V

(V

= 0V)..................................................25V

= 0V)................................................–25V

OUTP OUTN

ꢜꢝꢘꢊꢑ

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ꢇꢉꢘꢋ ꢡ

ꢊꢎꢋꢁꢛꢀꢑ

ꢜꢞꢉꢚꢅꢕ

(V

OUTN OUTP

ꢃ

ꢁꢛꢀꢑꢘ

Maximum Internal Temperature............................ 125°C

Maximum Solder Temperature..............................260°C

Storage Temperature.............................. –55°C to 125°C

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ꢌꢌꢍꢎꢅꢉꢏ ꢐꢑꢒꢓꢓ ꢔ 9ꢓꢓ ꢔ ꢕꢖ4ꢕꢓꢓꢗ

T

= 125°C, θ = 16.2°C/W, θ = 3.8°C/W, θ

= 8.8°C/W,

JMAX

θ

JA

JB

JCtop

= 3.8°C/W, θ

= 4.6°C/W, WEIGHT = 0.8g,

JCbottom

JCboard

θ VALUES DETERMINED PER JEDEC 51-9, 51-12

http://www.linear.com/product/LTM8049#orderinfo

ORDER INFORMATION

PART MARKING*

PACKAGE

MSL

TEMPERATURE RANGE

(SEE NOTE 1)

PART NUMBER

LTM8049EY#PBF

LTM8049IY#PBF

LTM8049IY

PAD OR BALL FINISH

SAC305 (RoHS)

SnPb (63/37)

DEVICE

LTM8049Y

LTM8049

FINISH CODE

TYPE

RATING

e1

BGA

3

–40°C to 125°C

e0

* Device temperature grade is indicated by a label on the shipping container. • Recommended BGA PCB Assembly and Manufacturing Procedures:

www.linear.com/BGA-assy

• Pad or ball finish code is per IPC/JEDEC J-STD-609.

• BGA Package and Tray Drawings: www.linear.com/packaging

• Terminal Finish Part Marking: www.linear.com/leadfree

• This product is moisture sensitive. For more information, go to:

• This product is not recommended for second side reflow. For more

www.linear.com/BGA-assy

information, go to www.linear.com/BGA-assy

8049fa

2

For more information www.linear.com/LTM8049

LTM8049

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

temperature range (Notes 1, 3), otherwise specifications are at T_A= 15°C. RUN = 1V unless otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Minimum Input Operating Voltage

Positive Output DC Voltage

2.6

V

I

= 50mA, R = 15.4k, V

Grounded

OUTN

Grounded

OUTN

2.5

24

V

OUT

FB

= 50mA, R = 274k, V

FB

Negative Output DC Voltage

I

= 50mA, R = 30.1k, V

Grounded

OUTP

Grounded

OUTP

–2.5

–24

V

OUT

FB

= 50mA, R = 287k, V

FB

Maximum Continuous Output DC Current

V

= 12V, V

= 5V or –5V

= 24 or –24V

1

0.25

A

IN

OUT

V

IN

Quiescent Current

V

RUN

V

RUN

= 0V

= 2V, No Load

0

10

2

µA

mA

Line Regulation

4 ≤ V ≤ 20V, I

= 0.6A

0.1

0.3

%

IN

OUT

Load Regulation

Switching Frequency

0 ≤ I

≤ 1A

OUT

l

R = 31.6k

2100

160

2500

200

2900

240

kHz

T

R = 412k

T

l

Voltage at FBX Pin

Positive Output

Negative Output

1.185

2

1.204

7

1.22

16

V

mV

l

Current into FBX Pin

RUN pin Threshold Voltage

RUN Pin Current

Positive Output

Negative Output

81

83.3

85.6

µA

RUN Pin Rising

RUN Pin Falling

1.31

1.27

1.4

V

1.21

10.1

V

RUN

V

RUN

V

RUN

= 3V

= 1.3V

= 0V

45

12.1

0

65

14.1

0.1

µA

SS Sourcing Current

SS = 0V

5.7

8.8

11.7

2500

0.4

µA

kHz

V

Synchronization Frequency Range

SYNC Input Low Threshold

SYNC Input High Threshold

CLKOUT1 Duty Cycle

200

1.3

V

(Note 5)

50

%

CLKOUT Output Voltage (Low)

CLKOUT Output Voltage (High)

PG Threshold for Positive Feedback Voltage

PG Threshold for Negative Feedback Voltage

PG Output Voltage Low

2k Pull-Up to 2V

0.2

V

2k Pull-Down to GND

FBX Rising

1.9

1.09

20

V

1.2

120

150

1

V

FBX Falling

mV

µA

100µA into PG, FBX = 1V

PG = 20V, Run = 0V

PG Leakage Current

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 1: The LTM8049E is guaranteed to meet performance specifications

from 0°C to 125°C. Specifications over the –40°C to 125°C internal

temperature range are assured by design, characterization and correlation

with statistical process controls. LTM8049I is guaranteed to meet

specifications over the full –40°C to 125°C internal operating temperature

range. Note that the maximum internal temperature is determined by

specific operating conditions in conjunction with board layout, the rated

package thermal resistance and other environmental factors.

Note 3: This μModule regulator includes overtemperature protection that

is intended to protect the device during momentary overload conditions.

Internal temperature will exceed 125°C when overtemperature protection

is active. Continuous operation above the specified maximum internal

operating junction temperature may impair device reliability.

Note 4: CLKOUTn is intended to drive other circuitry. Do not apply a

positive or negative voltage or current source to CLKOUT, otherwise

permanent damage may occur.

Note 5: The duty cycle of CLKOUT2 is dependent upon the internal

temperature. See the Applications Information section for more details.

8049fa

3

For more information www.linear.com/LTM8049

LTM8049

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency, V_OUT±2.5V

Efficiency, V_OUT±3.3V

Efficiency, V_OUT±5V

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8049 ꢀ0ꢁ

Efficiency, V_OUT±8V

Efficiency, V_OUT±12V

Efficiency, V_OUT±15V

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8049 ꢀ04

8049 ꢀ0ꢁ

Efficiency, V_OUT±18V

Efficiency, V_OUT±24V

Input vs Load Current, V_OUT±2.5V

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8049 ꢀ0ꢁ

8049 ꢀ08

8049 ꢀ09

8049fa

4

For more information www.linear.com/LTM8049

LTM8049

TYPICAL PERFORMANCE CHARACTERISTICS

Input vs Load Current, V_OUT±3.3V

Input vs Load Current, V_OUT±5V

Input vs Load Current, V_OUT±8V

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8049 ꢀꢁ0

8049 ꢀꢁꢁ

8049 ꢀꢁꢂ

Input vs Load Current, V_OUT±12V

Input vs Load Current, V_OUT±15V

Input vs Load Current, V_OUT±18V

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0

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ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢂꢋ

8049 ꢀꢁ4

8049 ꢀꢁꢂ

Input vs Load Current, V_OUT±24V

Maximum Load Current vs V_IN

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0

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0ꢀꢁ

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8049 ꢀꢁꢂ

8049 ꢀꢁ8

8049fa

5

For more information www.linear.com/LTM8049

LTM8049

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Load Current vs V_IN

Derating Curve, V_OUT±2.5V_OUT

Derating Curve, V_OUT±3.3V_OUT

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ꢀꢁ

8049 ꢀꢁ9

8049 ꢀꢁ0

8049 ꢀꢁꢂ

Derating Curve, V_OUT±5V_OUT

Derating Curve, V_OUT±8V_OUT

Derating Curve, V_OUT±12V_OUT

ꢀꢁ00

ꢀꢁꢂ0

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0ꢀꢁ0

0

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0

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8049 ꢀꢁꢁ

8049 ꢀꢁꢂ

8049 ꢀꢁ4

Derating Curve, V_OUT±15V_OUT

Derating Curve, V_OUT±18V_OUT

Derating Curve, V_OUT±24V_OUT

ꢀꢁ00

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0

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8049 ꢀꢁꢂ

8049fa

6

For more information www.linear.com/LTM8049

LTM8049

TYPICAL PERFORMANCE CHARACTERISTICS

Output Ripple, DC2244A Board

800mA Load, 12V_IN

Measured Across C5, C6

CLKOUT2 Duty Cycle

vs Temperature

80

f

ꢀ ꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂ

ꢃꢄꢅ

ꢀ0ꢁꢂꢃꢄꢅꢂ

ꢀ0

40

ꢀ0

ꢀꢁꢂꢃ

ꢄꢅꢆ

ꢀ0ꢁꢂꢃꢄꢅꢂ

8049 ꢀꢁ9

ꢀ00ꢁꢂꢃꢄꢅꢆ

ꢀꢁ0 ꢀꢁꢂ

0

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ꢀ0

ꢀꢁ ꢀ00 ꢀꢁꢂ

ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ

8049 ꢀꢁ8

PIN FUNCTIONS

GND (Bank 1): Tie these GND pins to a local ground plane

RUN1,RUN2(PinsB7,K7):Thesepinsareusedtoenable/

disable the chip and restart the soft-start sequence. Drive

below 1.21V to stop the LTM8049 from switching. Drive

above 1.4V to activate the device and restart the soft-start

sequence. Do not float this pin.

below the LTM8049 and the circuit components. GND

MUST BE CONNECTED EITHER TO V

OR V

FOR

OUTP

OUTN

PROPER OPERATION. In most applications, the bulk of

the heat flow out of the LTM8049 is through these pads,

so the printed circuit design has a large impact on the

thermal performance of the part. See the PCB Layout and

Thermal Considerations sections for more details. Return

the feedback divider (RFB) to this net.

RT1,RT2(PinsE7,G7):TheRTnpinsareusedtoprogram

the switching frequency of the LTM8049 by connecting a

resistor from this pin to ground. The switching frequency

of the LTM8049 is determined by the equation RTn =

V

, V (Banks 2, 3): The V pins supply current to

IN1 IN2

(81.6/f )-1, wherethef

istheswitchingfrequencyin

INn

OSC

theLTM8049’sinternalregulatorandtotheinternalpower

switch. Thispinmustbelocallybypassedwithanexternal,

low ESR capacitor.

MHz. This pin must have a resistor to GND. Do not apply

a voltage to this pin.

SS1, SS2 (Pins C7, J7): Connect a soft-start capacitor

from this pin to GND. Upon start-up, the SSn pins will be

charged by an internal current source to about 2V.

V

, V

(Banks 4, 5): V

is the positive out-

OUTnP

OUT1P OUT2P

put of the LTM8049. Apply an external capacitor between

V

and V . Tie this net to GND to configure the

OUTnP

OUTnN

SYNC1, SYNC2(PinsD7, H7):Tosynchronizetheswitch-

ingfrequencytoanoutsideclock,simplydrivethispinwith

a clock signal. The high voltage level of the clock needs

to exceed 1.3V, and the low level must be less than 0.4V.

Drive this pin to less than 0.4V to revert to the internal

free running clock. Ground these pins if synchronization

is not required. See the Applications Information section

for more information.

LMT8049 as a negative output Inverting regulator.

V

, V (Banks 6, 7): V is the negative out-

OUT1N OUT2N

put of the LTM8049. Apply an external capacitor between

OUTnP

OUTnN

V

and V . Tie this net to GND to configure the

OUTnN

LTM8049 as a positive output SEPIC regulator.

8049fa

7

For more information www.linear.com/LTM8049

LTM8049

PIN FUNCTIONS

FBX1, FBX2 (Pins C1, J1): If configured as a SEPIC, the

LTM8049 regulates its FBX pin to 1.204V. Apply a resis-

CLKOUT1, CLKOUT2 (Pins E6, G6): Use these pins to

synchronize devices to either channel of the LTM8049.

ThesepinsoscillateatthesamefrequencyastheLTM8049

internaloscillatoror, ifactive, theSYNCpin. TheCLKOUT1

signal is about 180° out of phase with the oscillator of

channel1anddutycycleisabout50%.TheCLKOUT2signal

is in phase with the internal oscillator of channel 2 and its

duty cycle varies linearly with the internal temperature of

theLTM8049. PleaserefertotheApplicationsInformation

section for detailed information on using CLKOUT2 as an

indication of the LTM8049 internal temperature. Do not

apply a voltage to this pin or use this pin to drive capaci-

tive loads greater than 120pF.

tor between FBX and V

. Its value should be R

=

OUTP

FB

[(V

– 1.204)/0.0833]k. If the LTM8049 is configured

OUTP

as an inverting converter, the LTM8049 regulates the FBX

pin to 7mV. Apply a resistor between FBX and V of

OUTN

value R = [(|V

| + 0.007)/0.0833]k. The LTM8049

OUTN

FB

features frequency foldback to protect the power switches

during a fault or output current overload. During start-up,

frequency foldback also limits the current the LTM8049

delivers to the load. The user must evaluate the start-up

behavior of the LTM8049 to ensure that it properly pow-

ers up the load.

PG1, PG2 (Pins D6, H6): These active high pins indicates

that the FBn pin voltage for the corresponding channel

is within 4% of its regulation voltage These open drain

outputsrequiresapull-upresistortoindicatepowergood.

Also, the status of these pins is valid only when RUN >

SHARE1, 2 (pins F3, F4): Connect these pins together if

thetwooutputsoftheLTM8049areparalleled. Otherwise,

leave these pins floating.

1.4V and V > 2.6V.

IN

8049fa

8

For more information www.linear.com/LTM8049

LTM8049

BLOCK DIAGRAM

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ꢁꢂꢃ

0ꢀꢁꢂꢃ

4ꢀꢁꢂꢃ

ꢀ

ꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃ

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ꢀꢁꢂ

8049 ꢀꢁ

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8049fa

9

For more information www.linear.com/LTM8049

LTM8049

OPERATION

The LTM8049 contains two stand-alone switching DC/

DC converters; either one may be configured as a SEPIC

(single-ended primary inductance converter) or inverting

The LTM8049 also features RUN and SS pins to control

the start-up behavior of the device. The RUN pin may also

be used to implement an accurate undervoltage lockout

function by applying a resistor network to the RUN pin.

power supply simply by tying V

or V

to GND,

OUTN

OUTP

respectively. It accepts an input voltage up to 20VDC. The

output is adjustable between 2.5V and 24V for the SEPIC,

and between –2.5V and –24V for the inverting configura-

The LTM8049 features frequency foldback to protect the

power switches during a fault or output current overload.

Duringstart-up, frequencyfoldbackalsolimitsthecurrent

the LTM8049 delivers to the load. The user must evaluate

the start-up behavior of the LTM8049 to ensure that it

properly powers up the load.

tion. The LTM8049 can provide 1.5A at V = 12V when

IN

V

OUT

= 5V or –5V at ambient room temperature.

As shown in the Block Diagram, the LTM8049 contains a

current mode controller, power switching element, power

coupled inductor, power Schottky diode and a modest

amount of input and output capacitance. The LTM8049

is a fixed frequency PWM regulator.

The LTM8049 is equipped with a thermal shutdown to

protectthedeviceduringmomentaryoverloadconditions.

It is set above the 125°C absolute maximum internal tem-

perature rating to avoid interfering with normal specified

operation, so internal device temperatures will exceed

the absolute maximum rating when the overtemperature

protection is active. Therefore, continuous or repeated

activation of the thermal shutdown may impair device

reliability.

TheLTM8049switchingcanfreerunbyapplyingaresistorto

theRTpinorsynchronizetoanexternalsourceatafrequency

between 200kHz and 2.5MHz. To synchronize to an external

source, drive a valid signal source into the SYNC pin. See

SynchronizationintheApplicationsSectionformoredetails.

APPLICATIONS INFORMATION

For most applications, the design process is straight

forward, summarized as follows:

optimal efficiency over the given input condition is given

in the f

column. Running the LTM8049 faster than

OPTIMAL

the recommended frequency may reduce the usable input

voltage range.

1. Look at Table 1 and find the row that has the desired

input range and output voltage.

2. ApplytherecommendedC , C , R andR values.

Capacitor Selection Considerations

IN OUT ADJ

T

While these component combinations have been tested

for proper operation, it is incumbent upon the user to

verify proper operation over the intended system’s line,

load and environmental conditions. Bear in mind that the

maximum output current is limited by junction tempera-

ture, therelationshipbetweentheinputandoutputvoltage

magnitude and polarity and other factors. Please refer to

the graphs in the Typical Performance Characteristics

section for guidance.

The C and C

capacitor values in Table 1 are the

IN

OUT

minimum recommended values for the associated oper-

ating conditions. Applying capacitor values below those

indicated in Table 1 is not recommended, and may result

in undesirable operation. Using larger values is generally

acceptable, and can yield improved dynamic response, if

it is necessary. Again, it is incumbent upon the user to

verify proper operation over the intended system’s line,

load and environmental conditions.

Table 1 gives the recommended component values and

configuration for a single channel. Each channel may be

configured independently. The maximum frequency (and

Ceramic capacitors are small, robust and have very low

ESR. However, not all ceramic capacitors are suitable.

X5R and X7R types are stable over temperature and ap-

plied voltage and give dependable service. Other types,

including Y5V and Z5U have very large temperature and

attendant R value) at which the LTM8049 should be al-

T

lowed to switch is given in Table 1 in the f

column,

MAX

while the recommended frequency (and R value) for

voltage coefficients of capacitance. In an application

T

8049fa

10

For more information www.linear.com/LTM8049

LTM8049

APPLICATIONS INFORMATION

Table 1. Recommended Component Values and Configuration (T_A= 25°C)

V

IN

RANGE (V)

V

OUT

(V)

C

IN

C

OUT

R

FB

(Ω)

f

R

(Ω)

f

R

TMIN

(Ω)

OPTIMAL

TOPTIMAL

MAX

2.6V to 11.5V

2.6V to 9.5V

2.5V

4.7µF 25V 0603 X5R

100µF 4V 0805 X5R

15.4k

30.1k

600kHz

137k

2MHz

38.3k

–2.5V

100µF 4V 0805 X5R

+ 47µF 6.3V 0805 X5R

137k

2.6V to 18V

2.6V to 12V

3.3V

4.7µF 25V 0603 X5R

100µF 4V 0805 X5R

25.5k

39.2k

650kHz

124k

2.3MHz

33.2k

–3.3V

100µF 4V 0805 X5R

+ 47µF 6.3V 0805 X5R

2.7V to 20V

2.7V to 15V

5V

4.7µF 25V 0603 X5R

47µF 6.3V 0805 X5R

45.3k

60.4k

750k

107k

2.5MHz

31.6k

–5V

100µF 6.3V 1206 X5R

+ 47µF 10V 1206 X5R

2.7V to 20V

2.7 to 18.5V

2.7V to 20V

3V to 20V

8V

4.7µF 25V 0603 X5R

22µF 10V 1206 X5R

2x 47µF 10V 1206 X5R

22µF 16V 1210 X5R

47µF 16V 1210 X5R

22µF 16V 1210 X5R

47µF 16V 1210 X5R

22µF 16V 1210 X7R

22µF 25V 1206 X5R

82.5k

95.3k

130k

143k

165k

178k

200k

215k

274k

287k

1MHz

80.6k

73.2k

53.6k

2.5MHz

1.9MHz

1.8MHz

31.6k

41.2k

45.3k

–8V

12V

1MHz

–12V

15V

1MHz

1.1MHz

1.5MHz

–15V

18V

3V to 20V

–18V

24V

3.7V to 18V

–24V

Note: An input bulk capacitor is required.

circuit they may have only a small fraction of their nominal

capacitanceresultinginmuchhigheroutputvoltageripple

than expected.

Switching Frequency Trade-Offs

ItisrecommendedthattheuserapplytheoptimalR value

T

given in Table 1 for the corresponding input and output

operatingcondition. Systemlevelorotherconsiderations,

however, may necessitate another operating frequency.

While the LTM8049 is flexible enough to accommodate

a wide range of operating frequencies, a haphazardly

chosen one may result in undesirable operation under

certain operating or fault conditions. A frequency that is

too high can reduce efficiency, reduce the usable input

voltage range, generate excessive heat or even damage

the LTM8049 in some fault conditions. A frequency that

is too low can result in a final design that has too much

output ripple or too large of an output capacitor. Note that

the Maximum Output Current vs Input Voltage curves

given in the Typical Characteristics section are for the

recommended operating conditions in Table 1. Using a

different operating frequency may result in a different

maximum output current.

A final precaution regarding ceramic capacitors concerns

the maximum input voltage rating of the LTM8049. A

ceramic input capacitor combined with trace or cable

inductance forms a high Q (underdamped) tank circuit.

If the LTM8049 circuit is plugged into a live supply, the

input voltage can ring to twice its nominal value, possi-

bly exceeding the device’s rating. This situation is easily

avoided; see the Hot-Plugging Safely section.

Programming Switching Frequency

TheLTM8049hasanoperationalswitchingfrequencyrange

between 200kHz and 2.5MHz. The free running frequency

is programmed with an external resistor from the RT pin

to ground. Do not leave this pin open under any condition.

When the SYNC pin is driven low (<0.4V), the frequency

of operation is set by a resistor from RT to ground. The

R value is calculated by the following equation:

T

81.6

R =

T

– 1, where f

is in MHz and R is in kΩ

T

OSC

f

OSC

8049fa

11

For more information www.linear.com/LTM8049

LTM8049

APPLICATIONS INFORMATION

Soft-Start

The RUN pin has a voltage hysteresis with typical thresh-

olds of 1.31V (rising) and 1.27V (falling). Resistor R

UVLO2

The soft-start circuitry provides for a gradual ramp-up of

the switch current in each channel. When the channel is

enabled, the external SS capacitor is first discharged. This

resets the state of the logic circuits in the channel. Then

an integrated resistor pulls the channel’s SS pin to about

1.8V. The LTM8049 has a built-in soft-start characteristic,

but a slower ramp rate may be implemented by adding

capacitance to the SS pin. Typical values are between

0.1µF and 1µF.

is optional. R

can be included to reduce the overall

UVLO2

UVLO voltage variation caused by variations in the RUN

pin current (see the Electrical Characteristics). A good

choice for R

UVLO2 UVLO1

following:

is ≤10k + 1%. After choosing a value

can be determined from either of the

UVLO2

, R

for R

V

– 1.31V

IN(RISING)

R

=

UVLO1

1.32V

+ 12.1µA

R

UVLO2

Configurable Undervoltage Lockout

or

Figure 1 shows how to configure an undervoltage lock-

out (UVLO) for the LTM8049. Typically, UVLO is used in

situations where the input supply is current-limited, has

a relatively high source resistance, or ramps up/down

slowly. A switching regulator draws constant power from

the source, so source current increases as source voltage

drops. This looks like a negative resistance load to the

source and can cause the source to current-limit or latch

low under low source voltage conditions. UVLO prevents

the regulator from operating at source voltages where

these problems might occur.

V

_IN(FALLING)– 1.27V

R_UVLO1

=

1.29V

+ 11.6µA

R_UVLO2

where V

and V

are the V threshold

IN(FALLING) IN

IN(RISING)

voltages when rising or falling respectively.

For example, to disable the LTM8049 for V voltages

below3.5Vusingthesingleresistorconfiguration,choose:

IN

3.5V – 1.27V

1.29V

R_UVLO1

=

≅ 191k

ꢀꢁꢂ8049

+ 11.6µA

∞

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ꢁ

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To activate the LTM8049 for V greater than 4.5V using

the two resistor configuration, choose R

IN

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= 10k and:

UVLO2

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4.5V – 1.31V

1.32V

10k

R_UVLO1

=

≅ 22.1k

ꢀꢁꢂ

+ 12.1µA

8049 ꢀ0ꢁ

Figure 1. The RUN Pin May Be Used to Implement

an Accurate UVLO

Internal Undervoltage Lockout

The LTM8049 monitors the V supply voltage in case V

IN

The RUN pin sinks 12.1µA at the 1.31V rising threshold

voltage and about 11.6µA at the 1.27V falling threshold.

This makes it easy to set up an input voltage UVLO thresh-

drops below a minimum operating level (typically about

2.3V). When V is detected low, the power switch is

IN

deactivated, and while sufficient V voltage persists, the

IN

old with just a single resistor. For a desired V threshold,

IN

soft-start capacitor is discharged. After V is sufficiently

IN

choose R

using the equation:

UVLO1

high,theLTM8049willreactivateandthesoft-startcapaci-

V

IN

– 1.31V

tor will begin charging.

R

=

UVLO1

12.1µA

8049fa

12

For more information www.linear.com/LTM8049

LTM8049

APPLICATIONS INFORMATION

Frequency Foldback

that internal temperatures will exceed the 125°C absolute

maximum rating when the overtemperature protection is

active, possibly impairing the device’s reliability.

The frequency foldback function reduces the switching

frequency for that channel when the output is about 15%

below the target regulation point. This feature lowers the

operatingfrequency,thuscontrollingthemaximumoutput

current during start-up. When the FBX voltage is pulled

abovetheabovementionedrangeinapositiveoutputvolt-

age application, the switching frequency for that channel

PCB Layout

Most of the headaches associated with PCB layout have

been alleviated or even eliminated by the high level of

integration of the LTM8049. The LTM8049 is neverthe-

less a switching power supply, and care must be taken to

minimize EMI and ensure proper operation. Even with the

high level of integration, you may fail to achieve specified

operation with a haphazard or poor layout. See Figure 2

for a suggested layout. Ensure that the grounding and

heat-sinking are acceptable.

runs that the rate set by the R resistor value. Note that

T

the maximum output current at start-up is a function of

many variables including load profile, output capacitance,

target V , V , switching frequency, so the user must

OUT IN

evaluate the performance of the LTM8049 to ensure that

it properly powers up its load.

A few rules to keep in mind are:

Thermal Shutdown

1. Place the R and R resistors as close as possible to

FBX

T

If the part is too hot, the LTM8049 engages its thermal

shutdown and terminates switching and discharges the

soft-startcapacitor.Whentheparthascooled,thepartauto-

maticallyrestarts.Thisthermalshutdownissettoengageat

temperaturesabovethe125°Cabsolutemaximuminternal

operating rating to ensure that it does not interfere with

functionality in the specified operating range. This means

their respective pins.

2. Place the C capacitor as close as possible to the V

IN

and GND connection of the LTM8049.

3. Place the C

capacitor as close as possible to the

OUT

V

and GND connection of the LTM8049.

OUT

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ꢑꢒꢂꢁ

ꢍ

ꢑꢒꢂꢐ

ꢑꢒꢂꢁ

ꢊꢋꢌ

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ꢓꢋꢄꢊꢇꢂꢎꢍꢄ ꢑꢒꢂꢔꢒꢂꢕ

8049 ꢀ0ꢁ

ꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢌ ꢍꢎꢇꢏ

Figure 2. Layout Showing Suggested External Components, GND Plane and Thermal Vias

8049fa

13

For more information www.linear.com/LTM8049

LTM8049

APPLICATIONS INFORMATION

4. Place the C and C

capacitors such that their

Thermal Considerations

IN

OUT

ground current flow directly adjacent or underneath

The LTM8049 output current may need to be derated if

it is required to operate in a high ambient temperature or

deliver a large amount of continuous power. The amount

of current derating is dependent upon the input voltage,

output power and ambient temperature. The temperature

rise curves given in the Typical Performance Character-

istics section can be used as a guide. These curves were

the LTM8049.

5. Connect all of the GND connections to as large a copper

pour or plane area as possible on the top layer. Avoid

breaking the ground connection between the external

components and the LTM8049.

6. Use vias to connect the GND copper area to the board’s

internal ground planes. Liberally distribute these GND

vias to provide both a good ground connection and

thermal path to the internal planes of the printed circuit

board. Pay attention to the location and density of the

thermal vias in Figure 2. The LTM8049 can benefit from

theheat-sinkingaffordedbyviasthatconnecttointernal

GND planes at these locations, due to their proximity

to internal power handling components. The optimum

number of thermal vias depends upon the printed

circuit board design. For example, a board might use

very small via holes. It should employ more thermal

vias than a board that uses larger holes.

2

generated by a LTM8049 mounted to a 58cm 4-layer FR4

printedcircuitboard. Boardsofothersizesandlayercount

can exhibit different thermal behavior, so it is incumbent

upon the user to verify proper operation over the intended

system’sline,loadandenvironmentaloperatingconditions.

The thermal resistance numbers listed in Page 2 of the

data sheet are based on modeling the µModule package

mounted on a test board specified per JESD51-9 (Test

Boards for Area Array Surface Mount Package Thermal

Measurements). The thermal coefficients provided in this

page are based on JESD 51-12 (Guidelines for Reporting

and Using Electronic Package Thermal Information).

Forincreasedaccuracyandfidelitytotheactualapplication,

many designers use FEA to predict thermal performance.

To that end, Page 2 of the data sheet typically gives four

thermal coefficients:

Hot-Plugging Safely

The small size, robustness and low impedance of ceramic

capacitors make them an attractive option for the input

bypass capacitor of LTM8049. However, these capacitors

can cause problems if the LTM8049 is plugged into a live

input supply (see Application Note 88 for a complete dis-

cussion). The low loss ceramic capacitor combined with

stray inductance in series with the power source forms an

θ : Thermal resistance from junction to ambient

JA

θ

: Thermal resistance from junction to the bottom

JCbottom

of the product case

θ

: Thermal resistance from junction to top of the

JCtop

underdamped tank circuit, and the voltage at the V pin

IN

product case

of the LTM8049 can ring to more than twice the nominal

inputvoltage,possiblyexceedingtheLTM8049’sratingand

damaging the part. If the input supply is poorly controlled

or the user will be plugging the LTM8049 into an energized

supply,theinputnetworkshouldbedesignedtopreventthis

overshoot. This can be accomplished by installing a small

θ :Thermalresistancefromjunctiontotheprintedcircuit

JB

board.

While the meaning of each of these coefficients may seem

to be intuitive, JEDEC has defined each to avoid confusion

and inconsistency. These definitions are given in JESD

51-12, and are quoted or paraphrased below:

resistor in series to V , but the most popular method of

IN

controlling input voltage overshoot is to add an electrolytic

θ

is the natural convection junction-to-ambient air

JA

bulkcapacitortotheV net. Thiscapacitor’srelativelyhigh

IN

thermal resistance measured in a one cubic foot sealed

enclosure. This environment is sometimes referred to as

equivalentseriesresistancedampsthecircuitandeliminates

the voltage overshoot. The extra capacitor improves low

frequency ripple filtering and can slightly improve the ef-

ficiency of the circuit, though it is physically large.

8049fa

14

For more information www.linear.com/LTM8049

LTM8049

APPLICATIONS INFORMATION

stillairalthoughnaturalconvectioncausestheairtomove.

This value is determined with the part mounted to a JESD

51-9 defined test board, which does not reflect an actual

application or viable operating condition.

Giventhesedefinitions,itshouldnowbeapparentthatnone

of these thermal coefficients reflects an actual physical

operating condition of a µModule converter. Thus, none

of them can be individually used to accurately predict the

thermal performance of the product. Likewise, it would

be inappropriate to attempt to use any one coefficient to

correlate to the junction temperature vs load graphs given

in the product’s data sheet. The only appropriate way to

use the coefficients is when running a detailed thermal

analysis, such as FEA, which considers all of the thermal

resistances simultaneously.

θ

is the thermal resistance between the junction

JCbottom

andbottomofthepackagewithallofthecomponentpower

dissipation flowing through the bottom of the package. In

the typical µModule converter, the bulk of the heat flows

out the bottom of the package, but there is always heat

flow out into the ambient environment. As a result, this

thermal resistance value may be useful for comparing

packages but the test conditions don’t generally match

the user’s application.

A graphical representation of these thermal resistances

is given in Figure 3.

θ

isdeterminedwithnearlyallofthecomponentpower

The blue resistances are contained within the µModule

converter, and the green are outside.

JCtop

dissipation flowing through the top of the package. As the

electricalconnectionsofthetypicalµModuleconverterare

on the bottom of the package, it is rare for an application

to operate such that most of the heat flows from the junc-

The die temperature of the LTM8049 must be lower than

the maximum rating of 125°C, so care should be taken in

the layout of the circuit to ensure good heat sinking of the

LTM8049. The bulk of the heat flow out of the LTM8049

is through the bottom of the μModule converter and the

BGA pads into the printed circuit board. Consequently a

poor printed circuit board design can cause excessive

heating, resulting in impaired performance or reliability.

Please refer to the PCB Layout section for printed circuit

board design suggestions.

tion to the top of the part. As in the case of θ , this

JCbottom

value may be useful for comparing packages but the test

conditions don’t generally match the user’s application.

θ

JB

is the junction-to-board thermal resistance where

almost all of the heat flows through the bottom of the

µModule converter and into the board, and is really the

sum of the θ

and the thermal resistance of the

JCbottom

bottom of the part through the solder joints and through a

portion of the board. The board temperature is measured

a specified distance from the package, using a two sided,

two layer board. This board is described in JESD 51-9.

ꢌꢆꢍꢋꢎꢊꢄꢍꢏꢎꢄꢏꢐꢃꢖꢊꢈꢍꢎ ꢕꢈꢑꢊꢑꢎꢐꢍꢋꢈ ꢒꢌꢈꢑꢅ ꢗꢘꢏ9 ꢅꢈꢀꢊꢍꢈꢅ ꢖꢄꢐꢕꢅꢔ

ꢌꢆꢍꢋꢎꢊꢄꢍꢏꢎꢄꢏꢋꢐꢑꢈ ꢒꢎꢄꢓꢔ

ꢕꢈꢑꢊꢑꢎꢐꢍꢋꢈ

ꢋꢐꢑꢈ ꢒꢎꢄꢓꢔꢏꢎꢄꢏꢐꢃꢖꢊꢈꢍꢎ

ꢕꢈꢑꢊꢑꢎꢐꢍꢋꢈ

ꢌꢆꢍꢋꢎꢊꢄꢍꢏꢎꢄꢏꢖꢄꢐꢕꢅ ꢕꢈꢑꢊꢑꢎꢐꢍꢋꢈ

ꢌꢆꢍꢋꢎꢊꢄꢍ

ꢐꢃꢖꢊꢈꢍꢎ

ꢌꢆꢍꢋꢎꢊꢄꢍꢏꢎꢄꢏꢋꢐꢑꢈ

ꢒꢖꢄꢎꢎꢄꢃꢔ ꢕꢈꢑꢊꢑꢎꢐꢍꢋꢈ

ꢋꢐꢑꢈ ꢒꢖꢄꢎꢎꢄꢃꢔꢏꢎꢄꢏꢖꢄꢐꢕꢅ

ꢕꢈꢑꢊꢑꢎꢐꢍꢋꢈ

ꢖꢄꢐꢕꢅꢏꢎꢄꢏꢐꢃꢖꢊꢈꢍꢎ

ꢕꢈꢑꢊꢑꢎꢐꢍꢋꢈ

8049 ꢀ0ꢁ

ꢂꢃꢄꢅꢆꢇꢈ ꢅꢈꢉꢊꢋꢈ

Figure 3. Graphical Representation of JESD51-12 Thermal Coefficients

8049fa

15

For more information www.linear.com/LTM8049

LTM8049

TYPICAL APPLICATIONS

±±5V Converve

MaximumVLCadV ueevorVnsV5_IN

ꢀꢁ0

ꢀꢁꢂ

ꢀꢁ0

0ꢀꢁ

0

ꢀ

ꢁꢂꢃꢄꢅ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃꢄ

ꢁꢂ

ꢃꢄꢅꢀ ꢆꢇ ꢈꢉꢀ

ꢅꢀ

4ꢀꢁꢂꢃ

ꢀꢁꢂꢃ

×ꢄ

4ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ

4ꢀꢁꢂ

ꢁꢂꢃꢄꢅ

ꢀ0ꢁꢂ

ꢁꢃ0ꢂꢄꢅ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢂ8049

ꢀ0ꢁꢂ

ꢁꢃ0ꢂꢄꢅ

ꢀ

ꢁꢂꢃꢄꢅ

ꢁꢂꢃ

ꢀ4ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀ0ꢁ4ꢂ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁꢂꢃꢄ

ꢀ

ꢁꢂꢃꢄꢅ

ꢅꢆꢀ

0

ꢀ

ꢀ0

ꢀꢁ

ꢀꢁꢂꢃ ꢂꢄꢅ ꢆꢃꢇꢈꢉ ꢃꢃꢊꢋ ꢃꢃꢌꢋ ꢀꢍꢊꢋ ꢀꢍꢌꢋ ꢎꢏꢐꢄꢆꢅꢌꢋ ꢃꢑꢒꢓꢇꢊꢋ ꢃꢑꢒꢓꢇꢌ

8049 ꢀꢁ0ꢂa

ꢀ

ꢀꢁꢂ

ꢀꢁ

8049 ꢀꢁ0ꢂꢃ

PaeallvlV85VOurpursVfCeVIocevasvdV ueevor

MaximumVLCadV ueevorVnsV5_IN

ꢀ

ꢁꢂꢃꢄꢅ

ꢁꢂꢃ

ꢀ

ꢁꢂ

ꢀꢁꢂ

0ꢀꢁ

ꢃꢄꢅꢀ ꢆꢇ ꢃ0ꢀ

4ꢀꢁꢂꢃ

ꢀꢁꢂꢃ

×ꢄ

8ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ

ꢁꢂꢃꢄꢅ

80ꢀꢁꢂ

ꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

8ꢀ

ꢀꢁꢂ8049

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂ

80ꢀꢁꢂ

ꢃꢄꢅꢆ

ꢀ

ꢁꢂꢃꢄꢅ

ꢁꢂꢃ

ꢀꢁꢂꢃ

8ꢀꢁꢂꢃ

4ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀ

ꢁꢂꢃꢄꢅ

0

ꢀ

ꢀ0

ꢀꢁꢂ

ꢀꢁ

ꢀ0

ꢀ

ꢀꢁ

8049 ꢀꢁ0ꢂꢃ

ꢀꢁꢂꢃ ꢂꢄꢅ ꢆꢃꢇꢈꢉ ꢃꢃꢊꢋ ꢃꢃꢌꢋ ꢀꢍꢊꢋ ꢀꢍꢌꢋ ꢎꢏꢐꢄꢆꢅꢌ

8049 ꢀꢁ0ꢂa

8049fa

16

For more information www.linear.com/LTM8049

LTM8049

PACKAGE DESCRIPTION

PioVAssigomvorVTablv

(AeeaogvdVbyVPioVNumbve)

PINVNAME

F1 GND

A1

A2

V

OUT1P

V

OUT1P

B1

B2

V

C1 FBX1

D1

D2

V

E1

E2

V

OUT1P

OUT1N

C2

V

F2 GND

OUT1N

A3 GND

A4 GND

B3 GND

B4 GND

B5 GND

B6 GND

B7 RUN1

C3 GND

C4 GND

C5 GND

C6 GND

C7 SS1

D3 GND

D4 GND

D5 GND

D6 PG1

D7 SYNC1

E3 GND

E4 GND

E5 GND

F3 SHARE1

F4 SHARE2

F5 GND

A5

A6

A7

V

IN1

V

IN1

V

IN1

E6 CLKOUT1 F6 GND

E7 RT1 F7 GND

PINVNAME

J1 FBX2

J2

PINVNAME

G1

G2

V

H1

H2

V

K1

K2

V

OUT2P

V

OUT2P

L1

L2

V

OUT2N

OUT2P

V

OUT2N

G3 GND

G4 GND

G5 GND

H3 GND

H4 GND

H5 GND

J3 GND

J4 GND

J5 GND

J6 GND

J7 SS2

K3 GND

K4 GND

K5 GND

K6 GND

K7 RUN2

L3 GND

L4 GND

L5

L6

L7

V

IN2

V

IN2

V

IN2

G6 CLKOUT2 H6 PG2

G7 RT2 H7 SYNC2

PACKAGE PHOTO

8049fa

17

For more information www.linear.com/LTM8049

LTM8049

PACKAGE DESCRIPTION

PlvasvVevfveVrCVhrrp://www.liovae.cCm/peCducr/LTM8049#packagiogVfCeVrhvVmCsrVevcvorVpackagvVdeawiogs.

BGA Package

77-Lead (15.00mm × 9.00mm × 2.42mm)

ꢓꢏꢔfꢔꢕꢔꢖꢗꢔ ꢘꢆꢂ ꢙꢊꢄꢚ 0ꢛꢜ08ꢜꢍ9ꢝ4 ꢏꢔꢞ ꢟꢠ

ꢡꢅꢅ ꢋꢇꢆꢅꢡ

ꢝ

ꢁ

ꢙꢅꢆꢁꢉꢘ ꢁ

aaa

ꢒ

ꢅ

ꢐ

ꢄ

ꢁꢥ

ꢑ

ꢡꢅꢅ ꢋꢇꢆꢅꢡ

ꢧ

ꢀꢉꢋ ꢍ

ꢁꢍ

ꢁ

ꢟ

ꢂ

ꢙ

ꢅ

ꢨ

ꢗꢗꢗ

ꢒ

ꢀꢉꢋ ꢌꢁꢍꢎ

ꢂꢇꢏꢋꢅꢏ

4

ꢭꢍ

ꢭ

ꢤꢇꢘꢙ

ꢂꢁꢀ

ꢡꢪꢟꢡꢆꢏꢁꢆꢅ

ꢫꢍ

ꢙ

ꢨ

ꢫꢥ

ꢄ

ꢫ

ꢦ

ꢙꢅꢆꢁꢉꢘ ꢟ

ꢔ

ꢬꢭ ꢓꢮꢮ ꢀꢘꢁꢂꢅꢡꢠ

ꢃ

ꢘ

ꢯꢯꢯ

ꢔꢔꢔ

ꢤ

ꢒ

ꢑ ꢐ

aaa

ꢒ

ꢮ

ꢝ

ꢛ

4

ꢧ

ꢥ

ꢍ

ꢀꢁꢂꢃꢁꢄꢅ ꢆꢇꢀ ꢈꢉꢅꢊ

ꢀꢁꢂꢃꢁꢄꢅ ꢟꢇꢆꢆꢇꢤ ꢈꢉꢅꢊ

ꢙꢅꢆꢁꢉꢘ ꢟ

ꢀꢁꢂꢃꢁꢄꢅ ꢡꢉꢙꢅ ꢈꢉꢅꢊ

ꢋꢇꢆꢅꢡꢢ

ꢍꢣ ꢙꢉꢤꢅꢋꢡꢉꢇꢋꢉꢋꢄ ꢁꢋꢙ ꢆꢇꢘꢅꢏꢁꢋꢂꢉꢋꢄ ꢀꢅꢏ ꢁꢡꢤꢅ ꢐꢍ4ꢣꢛꢤꢜꢍ994

ꢙꢅꢆꢁꢉꢘ ꢁ

ꢥꢣ ꢁꢘꢘ ꢙꢉꢤꢅꢋꢡꢉꢇꢋꢡ ꢁꢏꢅ ꢉꢋ ꢤꢉꢘꢘꢉꢤꢅꢆꢅꢏꢡ

ꢧ

4

ꢟꢁꢘꢘ ꢙꢅꢡꢉꢄꢋꢁꢆꢉꢇꢋ ꢀꢅꢏ ꢦꢅꢡꢙ ꢤꢡꢜ0ꢥ8 ꢁꢋꢙ ꢦꢅꢀ9ꢛ

DIMENSIONS

ꢙꢅꢆꢁꢉꢘꢡ ꢇꢨ ꢀꢉꢋ ꢚꢍ ꢉꢙꢅꢋꢆꢉꢨꢉꢅꢏ ꢁꢏꢅ ꢇꢀꢆꢉꢇꢋꢁꢘꢩ

ꢟꢪꢆ ꢤꢪꢡꢆ ꢟꢅ ꢘꢇꢂꢁꢆꢅꢙ ꢊꢉꢆꢫꢉꢋ ꢆꢫꢅ ꢒꢇꢋꢅ ꢉꢋꢙꢉꢂꢁꢆꢅꢙꢣ

ꢆꢫꢅ ꢀꢉꢋ ꢚꢍ ꢉꢙꢅꢋꢆꢉꢨꢉꢅꢏ ꢤꢁꢐ ꢟꢅ ꢅꢉꢆꢫꢅꢏ ꢁ ꢤꢇꢘꢙ ꢇꢏ

ꢤꢁꢏꢃꢅꢙ ꢨꢅꢁꢆꢪꢏꢅ

SYMBOL

ꢁ

ꢁꢍ

ꢁꢥ

ꢭ

ꢭꢍ

ꢙ

ꢅ

ꢔ

ꢨ

ꢄ

ꢫꢍ

ꢫꢥ

aaa

ꢭꢭꢭ

ꢗꢗꢗ

ꢯꢯꢯ

ꢔꢔꢔ

MIN

ꢥꢣꢥꢥ

0ꢣꢛ0

ꢍꢣꢮꢥ

0ꢣꢝ0

NOM

ꢥꢣ4ꢥ

0ꢣꢝ0

ꢍꢣ8ꢥ

0ꢣꢮꢛ

0ꢣꢝꢧ

ꢍꢛꢣ00

9ꢣ00

ꢍꢣꢥꢮ

ꢍꢥꢣꢮ0

ꢮꢣꢝꢥ

0ꢣꢧꢥ

ꢍꢣꢛ0

MAX

ꢥꢣꢝꢥ

0ꢣꢮ0

ꢍꢣ9ꢥ

0ꢣ90

0ꢣꢝꢝ

NOTES

0ꢣꢝꢧ0 0ꢣ0ꢥꢛ ꢬ ꢮꢮꢴ

ꢝꢣꢧꢛ0

ꢛꢣ080

ꢧꢣ8ꢍ0

ꢥꢣꢛ40

ꢍꢣꢥꢮ0

0ꢣ000

ꢍꢣꢥꢮ0

ꢥꢣꢛ40

ꢧꢣ8ꢍ0

ꢛꢣ080

ꢝꢣꢧꢛ0

ꢟꢁꢘꢘ ꢫꢆ

ꢛꢣ ꢀꢏꢉꢤꢁꢏꢐ ꢙꢁꢆꢪꢤ ꢜꢒꢜ ꢉꢡ ꢡꢅꢁꢆꢉꢋꢄ ꢀꢘꢁꢋꢅ

ꢟꢁꢘꢘ ꢙꢉꢤꢅꢋꢡꢉꢇꢋ

ꢀꢁꢙ ꢙꢉꢤꢅꢋꢡꢉꢇꢋ

ꢝ

ꢀꢁꢂꢃꢁꢄꢅ ꢏꢇꢊ ꢁꢋꢙ ꢂꢇꢘꢪꢤꢋ ꢘꢁꢟꢅꢘꢉꢋꢄ ꢤꢁꢐ ꢈꢁꢏꢐ

ꢁꢤꢇꢋꢄ ꢰꢤꢱꢯꢲꢳꢔ ꢀꢏꢇꢙꢪꢂꢆꢡꢣ ꢏꢅꢈꢉꢅꢊ ꢅꢁꢂꢫ ꢀꢁꢂꢃꢁꢄꢅ

ꢘꢁꢐꢇꢪꢆ ꢂꢁꢏꢅꢨꢪꢘꢘꢐ

!

0ꢣꢥꢮ

ꢍꢣ4ꢛ

0ꢣꢧꢮ

ꢍꢣꢛꢛ

0ꢣꢍꢛ

0ꢣꢍ0

0ꢣꢥ0

0ꢣꢧ0

0ꢣꢍꢛ

ꢡꢪꢟꢡꢆꢏꢁꢆꢅ ꢆꢫꢃ

ꢤꢇꢘꢙ ꢂꢁꢀ ꢫꢆ

ꢘꢆꢤꢑꢑꢑꢑꢑꢑ

ꢰꢤꢱꢯꢲꢳꢔ

ꢂꢇꢤꢀꢇꢋꢅꢋꢆ

ꢀꢉꢋ ꢌꢁꢍꢎ

ꢡꢪꢄꢄꢅꢡꢆꢅꢙ ꢀꢂꢟ ꢘꢁꢐꢇꢪꢆ

ꢆꢇꢀ ꢈꢉꢅꢊ

ꢆꢏꢁꢐ ꢀꢉꢋ ꢍ

ꢟꢅꢈꢅꢘ

ꢆꢇꢆꢁꢘ ꢋꢪꢤꢟꢅꢏ ꢇꢨ ꢟꢁꢘꢘꢡꢢ ꢮꢮ

ꢀꢁꢂꢃꢁꢄꢅ ꢉꢋ ꢆꢏꢁꢐ ꢘꢇꢁꢙꢉꢋꢄ ꢇꢏꢉꢅꢋꢆꢁꢆꢉꢇꢋ

ꢟꢄꢁ ꢮꢮ 0ꢛꢍꢮ ꢏꢅꢈ ꢟ

8049fa

18

For more information www.linear.com/LTM8049

LTM8049

REVISION HISTORY

RE5

DATE

DES RIPTION

PAGEVNUMBER

A

12/17 Added SnPb BGA Package

1, 2

8049fa

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

19

For more information www.linear.com/LTM8049

LTM8049

TYPICAL APPLICATION

PaeallvlVOurpursVrCVIocevasvV–±5VOurpurV ueevor

MaximumVLCadV ueevorVnsV5_IN

4

ꢀ

ꢁꢂꢃꢄꢅ

ꢁꢂꢃ

ꢀ

ꢀ00ꢁꢂ

ꢃꢄ

ꢁꢂ

ꢃꢄꢅꢀ ꢆꢇ ꢈꢉꢀ

4ꢀꢁꢂꢃ

×ꢄ

ꢀꢁꢂꢃ

ꢀ0ꢁ4ꢂ

ꢀꢁꢂ

ꢀ

ꢁꢂꢃꢄꢅ

ꢀ0ꢁꢂ

ꢁꢃ0ꢂꢄꢅ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀ

0

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂ8049

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂ

ꢀ0ꢁꢂ

ꢁꢃ0ꢂꢄꢅ

ꢀ

ꢁꢂꢃ

ꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃ

ꢀ0ꢁ4ꢂ

ꢀ

ꢁꢂꢃ

ꢄꢅꢀ

ꢀꢁꢂꢃꢄ

ꢀ

ꢁꢂꢃꢄꢅ

0

ꢀ

ꢀ0

ꢀꢁꢂ

ꢀꢁ

ꢀ0

8049 ꢀꢁ04a

ꢀ

ꢀꢁ

ꢀꢁꢂꢃ ꢂꢄꢅ ꢆꢃꢇꢈꢉ ꢃꢃꢊꢋ ꢃꢃꢌꢋ ꢀꢍꢊꢋ ꢀꢍꢌꢋ ꢎꢏꢐꢄꢆꢅꢌ

8049 ꢀꢁ04ꢂ

DESIGN RESOURCES

SUBJE T

DES RIPTION

µModule Design and Manufacturing Resources

Design:

Manufacturing:

• Selector Guides

• Quick Start Guide

• Demo Boards and Gerber Files

• Free Simulation Tools

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

TechClip Videos

Quick videos detailing how to bench test electrical and thermal performance of µModule products.

Digital Power System Management

Analog Devices’ family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

RELATED PARTS

PARTVNUMBER DES RIPTION

OMMENT

LTM8045

LTM8046

Single. Inverting or SEPIC µModule DC/DC Convertor

2.8 ≤ V ≤ 18V. 2.5V ≤ V

≤ 15V. 6.25mm ꢀ 11.25mm ꢀ 4.92mm BGA

IN

OUT

2kVAC, 2.75W Isolated DC/DC µModule Converter

3.1V ≤ V ≤ 31V, 1.8V ≤ V

≤ 12V. 5V at 550mA from 24V ,

IN

OUT

IN

9mm ꢀ 15mm ꢀ 4.92mm BGA

LTM8047

LTM8048

725kVDC, 1.5W Isolated DC/DC µModule Converter

3.1V ≤ V ≤ 32V, 2.5V ≤ V

≤ 12V. 9mm ꢀ 11.25mm ꢀ 4.92mm BGA

OUT

IN

725kVDC, 1.5W Isolated DC/DC µModule Converter with 3.1V ≤ V ≤ 32V, 1.2V ≤ LDO V

Integrated LDO

≤ 12V. 9mm ꢀ 11.25mm ꢀ 4.92mm BGA

IN

OUT

LTM8067

LTM8068

2kVAC, 2.25W Isolated DC/DC µModule Converter

2.8V ≤ V ≤ 40V, 2.5V ≤ V

≤ 24V. 9mm ꢀ 11.25mm ꢀ 4.92mm BGA

IN

OUT

2kVAC, 2.25W Isolated DC/DC µModule Converter with

Integrated LDO

2.8V ≤ V ≤ 40V, 1.2V ≤ LDO V

≤ 18V. 9mm ꢀ 11.25mm ꢀ 4.92mm BGA

IN

OUT

LTM8023

LTM8053

36V , 2A, Step-Down DC/DC µModule Converter. Can Be 3.6V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V. 9mm x 11.25mm x 2.82mm LGA.

IN

OUT

Used for Inverting

9mm x 11.25mm x 3.52mm BGA

40V , 3.5A Step-Down DC/DC µModule Regulator. Can

3.4V ≤ V ≤ 40V. 0.97V ≤ V ≤ 15V. 6.25mm x 9mm x 3.32mm BGA.

IN

OUT

be used for inverting.

8049fa

LT 1217 REV A • PRINTED IN USA

www.linear.com/LTM8049

 ANALOG DEVICES, INC. 2016

20

For more information www.linear.com/LTM8049


型号：	LTM8049IY#PBF
厂家：	Linear
描述：	LTM8049 - Dual SEPIC or Inverting µModule DC/DC Converter; Package: BGA; Pins: 77; Temperature Range: -40°C to 85°C
文件：	总20页 (文件大小：1734K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM8049IY#PBF [Linear]

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