LTM8062/ [Linear]
Dual 13A or Single 26A DC/DC μModule Regulator; 双路13A或26A单DC / DC稳压器μModule
| 型号： | LTM8062/ |
| 厂家： | 
Linear |
| 描述： | Dual 13A or Single 26A DC/DC μModule Regulator |
| 文件： | 总36页 (文件大小：2967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4620
Dual 13A or Single 26A
DC/DC µModule Regulator
FeaTures
DescripTion
The LTM®4620 is a complete dual 13A output switching
mode DC/DC power supply. Included in the package are
the switching controller, power FETs, inductors, and all
supporting components. Operating from an input voltage
range of 4.5V to 16V, the LTM4620 supports two outputs
each with an output voltage range of 0.6V to 2.5V, set by a
single external resistor. Its high efficiency design delivers
up to 13A continuous current for each output. Only a few
input and output capacitors are needed.
n
Complete Standalone Dual Output Power Supply
n
Dual 13A or Single 26A Output
n
Wide Input Voltage Range: 4.5V to 16V
n
Output Voltage Range: 0.6V to 2.5V
n
1.5ꢀ Maꢁimum ꢂotal DC Output Error
n
Multiphase Current Sharing with Multiple
LꢂM4620s Up to 100A
n
Differential Remote Sense Amplifier
n
Current Mode Control/Fast Transient Response
n
Adjustable Switching Frequency
The device supports frequency synchronization, multi-
phaseoperation,BurstModeoperationandoutputvoltage
tracking for supply rail sequencing and has an onboard
temperaturediodefordevicetemperaturemonitoring.High
switchingfrequencyandacurrentmodearchitectureenable
a very fast transient response to line and load changes
without sacrificing stability.
n
Overcurrent Foldback Protection
n
Frequency Synchronization
n
Internal Temperature Sensing Diode Output
n
Output Overvoltage Protection
n
Low Profile (15mm × 15mm × 4.41mm) LGA Package
applicaTions
n
Fault protection features include overvoltage and overcur-
rentprotection.Thepowermoduleisofferedinaproprietary
space saving and thermally enhanced 15mm × 15mm ×
4.41mm LGA package with integrated top-side heat sink.
The LTM4620 is RoHS compliant with a PB-free finish.
Telecom and Networking Equipment
n
Storage and ATCA Cards
n
Industrial Equipment
ViDeo Tꢀꢁhcꢂꢃꢄ
Click and Learn
L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase are
registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All
other trademarks are the property of their respective owners.
100A and 26A ꢂhermal Performance
Current Sharing
Short-Circuit Protection
Typical applicaTion
26A, 1.2V Output DC/DC µModule® Regulator
1.2V Efficiency vs IOUꢂ
INTV
CC
4.7µF
5k
90
PGOOD
80
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
V
IN
4.5V TO 16V
V
V
IN
OUT1
+
22µF
×4
70
60
50
40
100µF
6.3V
470µF
6.3V
V
10k*
120k
OUTS1
25V
DIFFOUT
SW1
TEMP
RUN1
RUN2
V
V
FB1
FB2
LTM4620
TRACK1
TRACK2
60.4k
5V /500kHz
IN
COMP1
COMP2
5.1V*
12V /500kHz
IN
0.1µF
0
2
4
6
8
10 12 14 16 18 20 22 24 26
f
SET
V
OUTS2
OUTPUT CURRENT (A)
V
OUT
1.2V AT 26A
4620 TA01b
PHASMD
V
OUT2
SW2
+
121k
100µF
6.3V
470µF
6.3V
PGOOD2
SGND
GND
DIFFP
DIFFN
* PULL-UP RESISTOR AND
ZENER ARE OPTIONAL
PGOOD
4620 TA01a
4620f
1
LTM4620
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V (Note 8) ............................................... –0.3V to 18V
SW1 SW2
IN
V
TEMP
EXTV
CC
, V
................................................... –1V to 18V
M
L
PGOOD1, PGOOD2, RUN1, RUN2,
V
INTV , EXTV ........................................... –0.3V to 6V
IN
CC
CC
K
J
MODE_PLLIN, f , TRACK1, TRACK2,
SET
DIFFOUT, PHASMD................................ –0.3V to INTV
OUT1 OUT2 OUTS1 OUTS2
CC
CC
H
G
F
INTV
SW2
CC
CLKOUT
SW1
V
, V
, V
, V
...................... –0.3V to 6V
PGOOD1
PGOOD2
RUN2
DIFFP, DIFFN.......................................... –0.3V to INTV
PHASMD
RUN1
SGND
MODE_PLLIN
COMP1, COMP2, V , V (Note 6) ....... –0.3V to 2.7V
DIFFOUT
GND
COMP1 COMP2
FB1 FB2
DIFFP
E
DIFFN
TRACK1
INTV Peak Output Current ................................100mA
V
TRACK2
GND
SGND FB2
CC
V
FB1
D
C
B
A
V
Internal Operating Temperature Range
f
SGND OUTS2
SET
V
(Note 2) ............................................. –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Package Body Temperature .......................... 250°C
OUTS1
V
V
OUT1
OUT2
GND
1
2
3
4
5
6
7
8
9
10
11
12
LGA PACKAGE
144-LEAD (15mm × 15mm × 4.41mm)
T
JMAX
= 125°C, Θ = 7°C/W, Θ = 1.5°C/W,
JA
JCbottom
Θ
= 3.7°C/W, Θ + Θ ≅ 7°C/W
JCtop
JB BA
Θ VALUES DEFINED PER JESD 51-12
orDer inForMaTion
LEAD FREE FINISH
LTM4620EV#PBF
LTM4620IV#PBF
ꢂRAY
PARꢂ MARKING*
LTM4620V
PACKAGE DESCRIPꢂION
ꢂEMPERAꢂURE RANGE
–40°C to 125°C
LTM4620EV#PBF
LTM4620IV#PBF
144-Lead (15mm × 15mm × 4.41mm) LGA
144-Lead (15mm × 15mm × 4.41mm) LGA
LTM4620V
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
elecTrical cꢅaracTerisTics ꢂhe l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel. ꢂA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 23.
SYMBOL
PARAMEꢂER
CONDIꢂIONS
MIN
4.5
ꢂYP
MAX
16
UNIꢂS
l
l
l
V
V
Input DC Voltage
Output Voltage
V
V
V
IN
(Note 8)
0.6
2.5
OUT
V
V
,
Output Voltage, Total Variation with
Line and Load
1.477
1.5
1.523
C
= 22µF × 3, C
= 100µF × 1 Ceramic,
= 1.5V
OUT1(DC)
OUT2(DC)
IN
OUT
OUT
470µF POSCAP, V
Input Specifications
V
V
, V
RUN Pin On/Off Threshold
RUN Pin On Hysteresis
RUN Rising
1.1
1.25
150
1.40
V
RUN1 RUN2
, V
mV
RUN1HYS RUN2HYS
4620f
2
LTM4620
elecTrical cꢅaracTerisTics ꢂhe l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel. ꢂA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 23.
SYMBOL
PARAMEꢂER
CONDIꢂIONS
MIN
ꢂYP
MAX
UNIꢂS
I
Input Inrush Current at Start-Up
I
= 0A, C = 22µF ×3, C = 0.01µF,
1
A
INRUSH(VIN)
OUT
IN
SS
C
V
= 100µF ×3, V
= 1.5V, V
= 1.5V,
OUT2
OUT
OUT1
= 12V
IN
I
Input Supply Bias Current
Input Supply Current
V
V
V
= 12V, V
= 12V, V
= 1.5V, Burst Mode Operation
= 1.5V, Pulse-Skipping Mode
5
mA
mA
mA
µA
Q(VIN)
IN
IN
IN
OUT
OUT
15
65
50
= 12V, V = 1.5V, Switching Continuous
OUT
Shutdown, RUN = 0, V = 12V
IN
I
V
IN
V
IN
= 5V, V
= 1.5V, I = 13A
OUT
4.6
1.853
A
A
S(VIN)
OUT
= 12V, V
= 1.5V, I
= 13A
OUT
OUT
Output Specifications
, I
I
Output Continuous Current Range
Line Regulation Accuracy
V
V
= 12V, V
= 1.5V (Notes 7, 8)
0
13
A
OUT1(DC) OUT2(DC)
IN
OUT
l
l
ΔV
ΔV
/V
= 1.5V, V from 4.5V to 16V
0.01
0.5
15
0.025
%/V
OUT1(LINE) OUT1
OUT
IN
/V
I
= 0A for Each Output,
OUT
OUT2(LINE) OUT2
ΔV
ΔV
/V
Load Regulation Accuracy
Output Ripple Voltage
For Each Output, V
V = 12V (Note 7)
IN
= 1.5V, 0A to 13A
0.75
%
OUT1 OUT1
OUT
/V
OUT2 OUT2
V
, V
For Each Output, I
= 0A, C
= 100µF ×3/
mV
P-P
OUT1(AC) OUT2(AC)
OUT
OUT
X7R/Ceramic, 470µF POSCAP, V = 12V,
IN
V
OUT
= 1.5V, Frequency = 400kHz
f (Each Channel)
Output Ripple Voltage Frequency
SYNC Capture Range
V
IN
= 12V, V
= 1.5V, f = 1.25V (Note 4)
500
kHz
kHz
S
OUT
SET
f
400
780
SYNC
(Each Channel)
ΔV
Turn-On Overshoot
Turn-On Time
C
V
= 100µF/X5R/Ceramic, 470µF POSCAP,
10
5
mV
ms
OUTSTART
OUT
OUT
(Each Channel)
= 1.5V, I
= 0A V = 12V
OUT IN
t
C
= 100µF/X5R/Ceramic, 470µF POSCAP,
OUT
START
(Each Channel)
No Load, TRACK/SS with 0.01µF to GND,
V
= 12V
IN
ΔV
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
30
mV
OUT(LS)
(Each Channel)
C
= 22µF ×3/X5R/Ceramic, 470µF POSCAP
OUT
V
= 12V, V
= 1.5V
OUT
IN
t
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load,
20
20
µs
A
SETTLE
(Each Channel)
V
= 12V, C
= 100µF, 470µF POSCAP
IN
OUT
I
Output Current Limit
V
IN
= 12V, V
= 1.5V
OUT(PK)
OUT
(Each Channel)
Control Section
l
l
V
, V
Voltage at V Pins
I
= 0A, V = 1.5V
OUT
0.592
0.600
–5
0.606
–20
V
nA
V
FB1 FB2
FB
OUT
I
, I
(Note 6)
FB1 FB2
V
OVL
Feedback Overvoltage Lockout
0.64
1
0.66
1.25
0.68
1.5
TRACK1 (I),
TRACK2 (I)
Track Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V
µA
UVLO
Undervoltage Lockout
V
IN
V
IN
Falling
Rising
3.3
3.9
V
V
UVLO Hysteresis
0.6
90
V
ns
t
Minimum On-Time
(Note 6)
ON(MIN)
R
, R
Resistor Between V
, V
60.05
60.4
60.75
0.3
5
kΩ
FBHI1 FBHI2
OUTS1 OUTS2
and V , V Pins for Each Output
FB1 FB2
V
, V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
V
PGOOD1 PGOOD2
PGOOD
Low
I
PGOOD Leakage Current
V
µA
PGOOD
PGOOD
4620f
3
LTM4620
elecTrical cꢅaracTerisTics ꢂhe l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel. ꢂA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 23.
SYMBOL
PARAMEꢂER
CONDIꢂIONS
MIN
ꢂYP
MAX
UNIꢂS
V
PGOOD Trip Level
V
FB
V
FB
V
FB
with Respect to Set Output Voltage
Ramping Negative
Ramping Positive
PGOOD
–10
10
%
%
INꢂV Linear Regulator
CC
V
V
Internal V Voltage
6V < V < 16V
4.8
4.5
5
5.2
2
V
INTVCC
CC
IN
INTV Load Regulation
I
CC
= 0mA to 50mA
0.5
%
INTVCC
Load Regulation
CC
V
V
V
EXTV Switchover Voltage
EXTV Ramping Positive
4.7
50
V
mV
mV
EXTVCC
CC
CC
EXTV Dropout
I
CC
= 20mA, V = 5V
EXTVCC
100
EXTVCC(DROP)
EXTVCC(HYST)
CC
EXTV Hysteresis
200
CC
Oscillator and Phase-Locked Loop
Frequency Nominal Nominal Frequency
f
f
f
= 1.2V
450
210
700
9
500
250
780
10
550
290
860
11
kHz
kHz
kHz
µA
SET
SET
SET
Frequency Low
Frequency High
Lowest Frequency
= 0V (Note 5)
> 2.4V, Up to INTV
Highest Frequency
CC
f
Frequency Set Current
MODE_PLLIN Input Resistance
SET
R
250
kΩ
MODE_PLLIN
CLKOUT
Phase (Relative to V
)
PHASMD = GND
PHASMD = Float
PHASMD = INTV
60
90
120
Deg
Deg
Deg
OUT1
CC
CLK High
CLK Low
Clock High Output Voltage
Clock Low Output Voltage
2
V
V
0.2
3
Differential Amplifier
A Differential
Gain
1
V/V
V
Amplifier
R
Input Resistance
Measured at DIFFP Input
= V = 1.5V, I
80
kΩ
mV
dB
IN
V
OS
Input Offset Voltage
V
DIFFP
= 100µA
DIFFOUT
DIFFOUT
PSRR Differential
Amplifier
Power Supply Rejection Ratio
5V < V < 16V
90
2
IN
I
CL
Maximum Output Current
Maximum Output Voltage
Gain Bandwidth Product
Diode Connected PNP
Temperature Coefficient
mA
V
V
I
= 300µA
INTV – 1.4
CC
OUT(MAX)
DIFFOUT
GBW
3
MHz
V
V
Temp Diode
I = 100µA
0.6
–2.2
TEMP
TC
mV/°C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Two outputs are tested separately and the same testing condition
is applied to each output.
Note 4: The switching frequency is programmable from 400kHz to 750kHz.
Note 5: LTM4620 device is designed to operate from 400kHz to 750kHz
Note 6: These parameters are tested at wafer sort.
Note 2: The LTM4620 is tested under pulsed load conditions such that
T ≈ T . The LTM4620E is guaranteed to meet specifications from
J
A
Note 7: See output current derating curves for different V , V
and T .
A
IN OUT
0°C to 125°C internal temperature. Specifications over the –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM4620I is guaranteed over the full –40°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 8: Output current limitations. For 10V ≤ V ≤ 16V, the 2.5V output
IN
current needs to be limited to 10A/channel, switching frequency = 750kHz.
Derating curves apply. For 5V ≤ V ≤ 9V, the 2.5V output current needs
IN
to be limited to 12A/channel, switching frequency = 750kHz. Derating
curves apply. All other input and output combinations are 13A/channel
with recommended switching frequency included in the efficiency graphs.
Derating curves apply.
4620f
4
LTM4620
Typical perForMance cꢅaracTerisTics
Efficiency vs Output Current,
VIN = 5V
Efficiency vs Output Current,
VIN = 12V
Dual Phase Single Output Efficiency
vs Output Current, VIN = 12V
100
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
1V , f = 400kHz
1V , f = 400kHz
1V , f = 400kHz
OUT
OUT
OUT
1.2V , f = 500kHz
1.2V , f = 500kHz
1.2V , f = 500kHz
OUT
OUT
OUT
1.5V , f = 550kHz
1.5V , f = 550kHz
1.5V , f = 550kHz
OUT
OUT
OUT
1.8V , f = 600kHz
1.8V , f = 600kHz
1.8V , f = 600kHz
OUT
OUT
OUT
2.5V , f = 750kHz
2.5V , f = 750kHz
2.5V , f = 750kHz
OUT
OUT
OUT
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0
2
4
6
8
10 12 14 16 18 20 22 24 26
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4620 G01
4620 G02
4620 G03
Dual Phase Single Output
Load ꢂransient Response
Single Phase Single Output
Load ꢂransient Response
Single Phase Single Output
Load ꢂransient Response
V
V
V
OUT
100mV/DIV
OUT
OUT
100mV/DIV
100mV/DIV
I
I
I
LOAD
LOAD
LOAD
5A/DIV
10A/DIV
5A/DIV
4620 G06
4620 G04
4620 G05
50µs/DIV
50µs/DIV
50µs/DIV
12V , 1.2V
AT 13A/µs LOAD STEP
OUT
12V , 1.5V
AT 26A/µs LOAD STEP
12V , 1V
AT 13A/µs LOAD STEP
OUT
IN
IN
OUT
IN
C
= 2× 470µF, 4V POSCAP AND
1× 100µF, 6.3V CERAMIC
C
= 4× 470µF, 4V POSCAP AND
2× 100µF, 6.3V CERAMIC
C
= 2× 470µF, 4V POSCAP AND
1× 100µF, 6.3V CERAMIC
OUT
OUT
OUT
Single Phase Single Output
Load ꢂransient Response
Single Phase Single Output
Load ꢂransient Response
Single Phase Single Output
Load ꢂransient Response
V
V
V
OUT
OUT
OUT
100mV/DIV
100mV/DIV
100mV/DIV
I
I
I
LOAD
LOAD
LOAD
5A/DIV
5A/DIV
5A/DIV
4620 G07
4620 G08
4620 G09
50µs/DIV
50µs/DIV
50µs/DIV
12V , 1.5V
AT 13A/µs LOAD STEP
OUT
12V , 1.8V
AT 13A/µs LOAD STEP
OUT
12V , 2.5V
AT 13A/µs LOAD STEP
OUT
IN
IN
IN
C
= 2× 470µF, 4V POSCAP AND
1× 100µF, 6.3V CERAMIC
C
= 2× 470µF, 4V POSCAP AND
1× 100µF, 6.3V CERAMIC
C
= 2× 470µF, 4V POSCAP AND
1× 100µF, 6.3V CERAMIC
OUT
OUT
OUT
4620f
5
LTM4620
Typical perForMance cꢅaracTerisTics
Single Phase Single Output
Start-Up
Single Phase Single Output
Start-Up
V
V
OUT
0.5V/DIV
OUT
0.5V/DIV
I
I
OUT
5A/DIV
OUT
1A/DIV
4620 G10
4620 G11
2ms/DIV
2ms/DIV
12V , 1.5V
AT NO LOAD
12V , 1.5V AT 10A LOAD
OUT
OUT
IN
OUT
IN
C
= 2× 470µF, 4V SANYO POSCAP,
1× 100µF, 6.3V CERAMIC
C
= 2× 470µF, 4V SANYO POSCAP,
1× 100µF, 6.3V X5R CERAMIC
OUT
SOFT-START CAPACITOR = 0.01µF
SOFT-START CAPACITOR = 0.01µF
USE RUN PIN TO CONTROL START-UP
USE RUN PIN TO CONTROL START-UP
Current Limit and Current
Foldback
Load Regulation vs Current
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
= 12V
V
V
= 12V
IN
OUT
IN
OUT
1.0
0.8
0.6
0.4
0.2
0
= 1.5V
= 1.5V
0
5
10
15
20
25
0
5
10
15
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4620 G12
4620 G13
Short-Circuit Protection
Short-Circuit Protection
V
OUT
500mV/DIV
V
OUT
500mV/DIV
I
IN
I
IN
2A/DIV
2A/DIV
4620 G14
4620 G15
50µs/DIV
50µs/DIV
V
V
= 12V
V
V
= 12V
IN
OUT
OUT
IN
= 1.5V
= 1.5V
= 13A
OUT
OUT
I
= NO LOAD
I
4620f
6
LTM4620
(Recommended to Use ꢂest Points to Monitor Signal Pin Connections.)
pin FuncTions
V
(A1-A5, B1-B5, C1-C4): Power Output Pins. Apply
V
, V
(D5, D7): The Negative Input of the Error
OUꢂ1
FB1
FB2
outputloadbetweenthesepinsandGNDpins.Recommend
placing output decoupling capacitance directly between
these pins and GND pins. Review Table 4. See Note 8 in
the Electrical Characteristics section for output current
guideline.
Amplifier for Each Channel. Internally, this pin is con-
nected to V or V with a 60.4kΩ precision
OUTS1
OUTS2
resistor. Different output voltages can be programmed
with an additional resistor between V and GND pins. In
FB
PolyPhase® operation, tying the V pins together allows
FB
for parallel operation. See the Applications Information
section for details.
GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12,
F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1,
J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power
Ground Pins for Both Input and Output Returns.
ꢂRACK1, ꢂRACK2 (E5, D8): Output Voltage Tracking Pin
and Soft-Start Inputs. Each channel has a 1.3µA pull-up
current source. When one channel is configured to be
master of the two channels, then a capacitor from this pin
to ground will set a soft-start ramp rate. The remaining
channel can be set up as the slave, and have the master’s
output applied through a voltage divider to the slave out-
put’s track pin. This voltage divider is equal to the slave
output’s feedback divider for coincidental tracking. See
the Applications Information section.
V
(A8-A12, B8-B12, C9-C12): Power Output Pins.
OUꢂ2
Apply output load between these pins and GND pins.
Recommend placing output decoupling capacitance di-
rectly between these pins and GND pins. Review Table 4.
See Note 8 in the Electrical Characteristics section for
output current guideline.
V
, V
(C5, C8): This pin is connected to the top
OUꢂS1 OUꢂS2
of the internal top feedback resistor for each output. The
pin can be directly connected to its specific output, or
connected to DIFFOUT when the remote sense amplifier
COMP1, COMP2 (E6, E7): Current control threshold and
error amplifier compensation point for each channel. The
current comparator threshold increases with this control
voltage. Tie the COMP pins together for parallel operation.
The device is internal compensated.
is used. In paralleling modules, one of the V
pins is
OUTS
connectedtotheDIFFOUTpininremotesensingordirectly
to V with no remote sensing. It is very important to
connect these pins to either the DIFFOUT or V
this is the feedback path, and cannot be left open. See the
Applications Information section.
OUT
since
DIFFP (E8): Positive input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output voltage. See the Applications Information section.
OUT
f
(C6): Frequency Set Pin. A 10µA current is sourced
DIFFN (E9): Negative input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output GND. See the Applications Information section.
SEꢂ
from this pin. A resistor from this pin to ground sets a
voltage that in turn programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage
that can set the operating frequency. See the Applications
Information section.
MODE_PLLIN (F4): Force Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to SGND to force both channels into
SGND(C7, D6, G6-G7, F6-F7):SignalGroundPin. Return
ground path for all analog and low power circuitry. Tie a
single connection to the output capacitor GND in the ap-
plication. See layout guidelines in Figure 22.
force continuous mode of operation. Connect to INTV
CC
to enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force both channels into continuous mode of
operation and synchronized to the external clock applied
to this pin.
Heat Sink (ꢂop Eꢁposed Metal): The top exposed metal
is at ground potential.
4620f
7
LTM4620
pin FuncTions (Recommended to Use ꢂest Points to Monitor Signal Pin Connections.)
RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above
1.25V will turn on each channel in the module. A voltage
below 1.25V on the RUN pin will turn off the related chan-
nel. Each RUN pin has a 1µA pull-up current, once the
RUN pin reaches 1.2V an additional 4.5µA pull-up current
is added to this pin.
PGOOD1, PGOOD2 (G9, G8): Output Voltage Power
Good Indicator. Open drain logic output that is pulled to
ground when the output voltage is not within 10% of
the regulation point.
INꢂV (H8): Internal 5V Regulator Output. The control
CC
circuits and internal gate drivers are powered from this
DIFFOUꢂ (F8): Internal Remote Sense Amplifier Output.
voltage. Decouple this pin to PGND with a 4.7µF low ESR
Connect this pin to V
or V
depending on which
tantalumorceramic.INTV isactivatedwheneitherRUN1
OUTS1
OUTS2
CC
output is using remote sense. In parallel operation con-
nect one of the V pin to DIFFOUT for remote sensing.
or RUN2 is activated.
OUTS
ꢂEMP (J6): Onboard Temperature Diode for Monitoring
the VBE Junction Voltage Change with Temperature. See
the Applications Information section.
SW1, SW2 (G2, G11): Switching node of each channel
that is used for testing purposes. Also an R-C snubber
network can be applied to reduce or eliminate switch node
ringing, or otherwise leave floating. See the Applications
Information section.
EXꢂV (J7): External power input that is enabled through
CC
a switch to INTV whenever EXTV is greater than 4.7V.
CC
CC
Do not exceed 6V on this input, and connect this pin to
V when operating V on 5V. An efficiency increase will
PHASMD(G4):ConnectthispintoSGND,INTV ,orfloat-
CC
IN
IN
ing this pin to select the phase of CLKOUT to 60 degrees,
occur that is a function of the (V – INTV ) multiplied by
IN
CC
120 degrees, and 90 degrees respectively.
powerMOSFETdrivercurrent.Typicalcurrentrequirement
is 30mA. V must be applied before EXTV , and EXTV
CC
IN
CC
CLKOUꢂ (G5): Clock output with phase control using the
PHASMD pin to enable multiphase operation between
devices. See the Applications Information section.
must be removed before V .
IN
V (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11):
IN
Power Input Pins. Apply input voltage between these pins
and GND pins. Recommend placing input decoupling
capacitance directly between V pins and GND pins.
IN
ꢂop Heat Sink: Top heat sink is at ground potential.
4620f
8
LTM4620
siMpliFieD block DiagraM
PGOOD1
TRACK1
SS CAP
V
IN
C
22µF
25V
C
22µF
25V
IN1
IN2
1µF
GND
R
T
V
R
TEMP
CLKOUT
RUN1
IN
= 100µA
V
IN
MTOP1
MBOT1
T
SW1
V
0.33µH
OUT1
V
OUT1
1.5V/13A
+
MODE_PLLIN
PHASMD
2.2µF
C
OUT1
GND
V
OUTS1
COMP1
60.4k
V
FB1
INTERNAL
COMP
R
FB1
40.2k
SGND
POWER
CONTROL
PGOOD2
TRACK2
V
IN
INTV
CC
C
22µF
25V
C
22µF
25V
IN3
IN4
SS CAP
1µF
4.7µF
EXTV
GND
SW2
CC
MTOP2
MBOT2
0.33µH
V
OUT2
V
OUT2
1.2V/13A
+
RUN2
2.2µF
C
OUT2
GND
V
OUTS2
60.4k
COMP2
V
FB2
+
–
R
FB2
INTERNAL
COMP
60.4k
f
SET
R
fSET
INTERNAL
FILTER
121k
SGND
DIFFOUT
DIFFN
DIFFP
4620 BD
Figure 1. Simplified LꢂM4620 Block Diagram
ꢂA = 25°C. Use Figure 1 configuration.
CONDIꢂIONS
Decoupling requireMenTs
SYMBOL
PARAMEꢂER
MIN
ꢂYP
MAX
UNIꢂS
External Input Capacitor Requirement
C
C
C
(V = 4.5V to 16V, V
= 1.5V)
= 1.2V)
I
I
= 13A
= 13A (Note 8)
22
22
µF
µF
IN1, IN2
IN
OUT1
OUT2
OUT1
OUT2
C
(V = 4.5V to 16V, V
IN3, IN4
IN
External Output Capacitor Requirement
C
C
(V = 4.5V to 16V, V
= 1.5V)
= 1.2V)
I
I
= 13A
= 13A (Note 8)
300
300
µF
µF
OUT1
OUT2
IN
OUT1
OUT2
OUT1
OUT2
(V = 4.5V to 16V, V
IN
4620f
9
LTM4620
operaTion
Power Module Description
voltage tracking during start-up or used for soft-starting
the regulator. See the Applications Information section.
The LTM4620 is a dual-output standalone nonisolated
switching mode DC/DC power supply. It can provide two
13A outputs with few external input and output capacitors
and setup components. This module provides precisely
regulated output voltages programmable via external
The LTM4620 is internally compensated to be stable over
all operating conditions. Table 4 provides a guide line for
input and output capacitances for several operating con-
ditions. The LTpowerCAD™ will be provided for transient
resistors from 0.6V to 2.5V over 4.5V to 16V input
DC
DC
voltages. The typical application schematic is shown in
Figure 23. See Note 8 in the Electrical Characteristics
section for output current guideline.
and stability analysis. The V pin is used to program the
FB
output voltage with a single external resistor to ground.
A differential remote sense amplifier is available for sens-
ing the output voltage accurately on one of the outputs at
the load point, or in parallel operation sensing the output
voltage at the load point.
TheLTM4620hasdualintegratedconstant-frequencycur-
rent mode regulators and built-in power MOSFET devices
withfastswitchingspeed. Thetypicalswitchingfrequency
is 500kHz. For switching-noise sensitive applications, it
can be externally synchronized from 400kHz to 780kHz.
A resistor can be used to program a free run frequency
Multiphase operation can be easily employed with the
MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12
phases can be cascaded to run simultaneously with re-
spect to each other by programming the PHASMD pin to
different levels. See the Applications Information section.
on the f pin. See the Applications Information section.
SET
With current mode control and internal feedback loop
compensation, the LTM4620 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation or pulse-skipping opera-
tion using the MODE_PLLIN pin. These light load features
willaccommodatebatteryoperation.Efficiencygraphsare
providedforlightloadoperationintheTypicalPerformance
Characteristics section. See the Applications Information
section for details.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limitandfoldbackcurrentlimitinanovercurrentcondition.
Internal overvoltage and undervoltage comparators pull
the open-drain PGOOD outputs low if the output feedback
voltage exits a 10% window around the regulation point.
As the output voltage exceeds 10% above regulation, the
bottom MOSFET will turn on to clamp the output voltage.
ThetopMOSFETwillbeturnedoff.Thisovervoltageprotect
is feedback voltage referred.
Atemperaturediodeisincludedinsidethemoduletomoni-
tor the temperature of the module. See the Applications
Information section for details.
Theswitchingnodepinsareavailableforfunctionalopera-
tion monitoring and a resistor-capacitor snubber circuit
can be careful placed on the switching node pin to ground
to dampen any high frequency ringing on the transition
edges.SeetheApplicationsInformationsectionfordetails.
Pulling the RUN pins below 1.1V forces the regulators into
ashutdownstate,byturningoffbothMOSFETs.TheTRACK
pinsareusedforprogrammingtheoutputvoltagerampand
4620f
10
LTM4620
applicaTions inForMaTion
The typical LTM4620 application circuit is shown in
Figure 23. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 4 for specific external capacitor
requirements for particular applications.
resistors to the output. All of the V pins tie together with
FB
one programming resistor as shown in Figure 2.
Inparalleloperation,theV pinshaveanI currentof20nA
FB
FB
maximumeachchannel.Toreduceoutputvoltageerrordue
to this current, an additional V
pin can be tied to V
,
OUTS
OUT
andanadditionalR resistorcanbeusedtolowerthetotal
FB
V to V
Step-Down Ratios
IN
OUꢂ
Thevenin equivalent resistance seen by this current. For
exampleinFigure2,thetotalTheveninequivalentresistance
There are restrictions in the maximum V and V
step-
IN
OUT
down ratio that can be achieved for a given input voltage.
Each output of the LTM4620 is capable of 98% duty cycle,
of the V pin is (60.4k//R ), which is 30.2k where R is
FB
FB
FB
equal to 60.4k for a 1.2V output. Four phases connected
in parallel equates to a worse case feedback current of
but the V to V
minimum dropout is still shown as a
IN
OUT
function of its load current and will limit output current
capability related to high duty cycle on the top side switch.
4 • I = 80nA maximum. The voltage error is 80nA • 30.2k
FB
= 2.4mV. If V
is connected, as shown in Figure 2, to
OUTS2
Minimum on-time t
is another consideration in
V
, and another 60.4k resistor is connected from V
OUT
ON(MIN)
FB2
operating at a specified duty cycle while operating at a
certain frequency due to the fact that t < D/f
to ground, then the voltage error is reduced to 1.2mV. If
the voltage error is acceptable then no additional connec-
tions are necessary. The onboard 60.4k resistor is 0.5%
,
SW
ON(MIN)
where D is duty cycle and f is the switching frequency.
SW
t
is specified in the electrical parameters as 90ns.
See Note 8 in the Electrical Characteristics section for
accurate and the V resistor can be chosen by the user to
ON(MIN)
FB
be as accurate as needed. All COMP pins are tied together
for current sharing between the phases. The TRACK pins
can be tied together and a single soft-start capacitor can
be used to soft-start the regulator. The soft-start equa-
tion will need to have the soft-start current parameter
increased by the number of paralleled channels. See the
Output Voltage Tracking section.
output current guideline.
Output Voltage Programming
ThePWMcontrollerhasaninternal0.6Vreferencevoltage.
AsshownintheBlockDiagram,a60.4kΩinternalfeedback
resistor connects between the V
to V and V
OUTS1
FB1 OUTS2
to V . It is very important that these pins be connected
FB2
4 PARALLELED OUTPUTS
FOR 1.2V AT 50A
LTM4620
V
V
COMP1
COMP2
OUT1
OUT2
to their respective outputs for proper feedback regulation.
OvervoltagecanoccuriftheseV
andV
pinsare
OUTS1
OUTS2
60.4k
V
left floating when used as individual regulators, or at least
one of them is used in paralleled regulators. The output
voltage will default to 0.6V with no feedback resistor on
either V or V . Adding a resistor R from V pin to
OUTS1
OUTS2
V
OPTIONAL CONNECTION
V
FB1
60.4k
TRACK1
TRACK2
FB1
FB2
FB
FB
V
FB2
GND programs the output voltage:
OPTIONAL
60.4k + RFB
VOUT = 0.6V •
RFB
R
FB
60.4k
LTM4620
60.4k
V
COMP1
COMP2
OUT1
OUT2
V
USE TO LOWER
V
V
ꢂable 1. VFB Resistor ꢂable vs Various Output Voltages
OUTS1
OUTS2
TOTAL EQUIVALENT
RESISTANCE TO LOWER
V
0.6V
1.0V
1.2V
1.5V
1.8V
2.5V
OUꢂ
I
FB
VOLTAGE ERROR
V
FB1
R
Open
90.9k
60.4k
40.2k
30.2k
19.1k
FB
60.4k
TRACK1
TRACK2
For parallel operation of multiple channels the same feed-
back setting resistor can be used for the parallel design.
V
FB2
0.1µF
R
FB
4620 F02
60.4k
This is done by connecting the V
to the output as
OUTS1
shown in Figure 2, thus tying one of the internal 60.4k
Figure 2. 4-Phase Parallel Configurations
4620f
11
LTM4620
applicaTions inForMaTion
Input Capacitors
Output Capacitors
The LTM4620 module should be connected to a low ac-
impedance DC source. For the regulator input four 22µF
input ceramic capacitors are used for RMS ripple current.
A47µFto100µFsurfacemountaluminumelectrolyticbulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedanceiscompromisedbylonginductiveleads,traces
ornotenoughsourcecapacitance.Iflowimpedancepower
planes are used, then this bulk capacitor is not needed.
The LTM4620 is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as C
are chosen with low enough
OUT
effective series resistance (ESR) to meet the output volt-
age ripple and transient requirements. C can be a low
OUT
ESR tantalum capacitor, the low ESR polymer capacitor
or ceramic capacitor. The typical output capacitance range
for each output is from 200µF to 470µF. Additional output
filtering may be required by the system designer, if further
reduction of output ripples or dynamic transient spikes
is required. Table 4 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 7A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
tooptimizethetransientperformance.Stabilitycriteriaare
considered in the Table 4 matrix, and LTpowerCAD will be
provided for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the num-
ber of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
afunctionofstabilityandtransientresponse.LTpowerCAD
can calculate the output ripple reduction as the number of
implemented phases increases by N times. A small value
For a buck converter, the switching duty-cycle can be
estimated as:
VOUT
D =
V
IN
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
IOUT(MAX)
ICIN(RMS)
=
• D • 1− D
(
)
η%
In the above equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcher-
rated electrolytic aluminum capacitor, Polymer capacitor.
10Ω to 50Ω resistor can be placed in series from V
OUT
to the V
pin to allow for a bode plot analyzer to inject
OUTS
a signal into the control loop and validate the regulator
stability. The same resistor could be placed in series from
V
toDIFFPandabodeplotanalyzercouldinjectasignal
OUT
into the control loop and validate the regulator stability.
4620f
12
LTM4620
applicaTions inForMaTion
Burst Mode Operation
modewillmaintainhighereffectivefrequenciesthuslower
output ripple and lower noise than Burst Mode operation.
Eitherregulatorcanbeconfiguredforpulse-skippingmode.
The LTM4620 is capable of Burst Mode operation on each
regulator in which the power MOSFETs operate intermit-
tently based on load demand, thus saving quiescent cur-
rent. For applications where maximizing the efficiency at
very light loads is a high priority, Burst Mode operation
should be applied. Burst Mode operation is enabled with
the MODE_PLLIN pin floating. During this operation, the
peak current of the inductor is set to approximately one
third of the maximum peak current value in normal opera-
tion even though the voltage at the COMP pin indicates
a lower value. The voltage at the COMP pin drops when
the inductor’s average current is greater than the load
requirement. As the COMP voltage drops below 0.5V, the
burst comparator trips, causing the internal sleep line to
go high and turn off both power MOSFETs.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
outputrippleisdesired,forcedcontinuousoperationshould
be used. Forced continuous operation can be enabled by
tying the MODE_PLLIN pin to GND. In this mode, induc-
tor current is allowed to reverse during low output loads,
the COMP voltage is in control of the current comparator
thresholdthroughout,andthetopMOSFETalwaysturnson
witheachoscillatorpulse.Duringstart-up,forcedcontinu-
ous mode is disabled and inductor current is prevented
from reversing until the LTM4620’s output voltage is in
regulation. Either regulator can be configured for forced
continuous mode.
In sleep mode, the internal circuitry is partially turned off,
reducing the quiescent current to about 450µA for each
output. The load current is now being supplied from the
output capacitors. When the output voltage drops, caus-
ing COMP to rise above 0.5V, the internal sleep line goes
low, and the LTM4620 resumes normal operation. The
next oscillator cycle will turn on the top power MOSFET
and the switching cycle repeats. Either regulator can be
configured for Burst Mode operation.
Multiphase Operation
For output loads that demand more than 13A of current,
two outputs in LTM4620 or even multiple LTM4620s can
be paralleled to run out of phase to provide more output
currentwithoutincreasinginputandoutputvoltageripple.
The MODE_PLLIN pin allows the LTM4620 to synchronize
to an external clock (between 400kHz and 780kHz) and
the internal phase-locked loop allows the LTM4620 to
lock onto an incoming clock phase as well. The CLKOUT
signal can be connected to the MODE_PLLIN pin of the
followingstagetolineupboththefrequencyandthephase
Pulse-Skipping Mode Operation
In applications where low output ripple and high effi-
ciencyatintermediatecurrentsaredesired,pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4620 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
of the entire system. Tying the PHASMD pin to INTV ,
CC
SGND,or(floating)generatesaphasedifference(between
MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees,
or 90 degrees respectively. A total of 12 phases can be
cascadedtorunsimultaneouslywithrespecttoeachother
byprogrammingthePHASMDpinofeachLTM4620chan-
nel to different levels. Figure 3 shows a 2-phase design,
4-phase design and a 6-phase design example for clock
phasing with the PHASMD table.
the MODE_PLLIN pin to INTV enables pulse-skipping
CC
operation. At light loads the internal current comparator
may remain tripped for several cycles and force the top
MOSFETtostayoffforseveralcycles,thusskippingcycles.
The inductor current does not reverse in this mode. This
4620f
13
LTM4620
applicaTions inForMaTion
2-PHASE DESIGN
PHASMD SGND FLOAT INTV
CC
FLOAT
CONTROLLER1
CONTROLLER2
CLKOUT
0
0
0
CLKOUT
180
60
180
90
240
120
MODE_PLLIN
0 PHASE
180 PHASE
V
V
OUT2
OUT1
PHASMD
4-PHASE DESIGN
90 DEGREE
CLKOUT
CLKOUT
MODE_PLLIN
MODE_PLLIN
0 PHASE
FLOAT
180 PHASE
90 PHASE
270 PHASE
V
V
V
OUT1
V
OUT2
OUT1
OUT2
FLOAT
PHASMD
PHASMD
6-PHASE DESIGN
60 DEGREE
60 DEGREE
CLKOUT
MODE_PLLIN
CLKOUT
CLKOUT
MODE_PLLIN
MODE_PLLIN
0 PHASE
SGND
180 PHASE
60 PHASE
SGND
240 PHASE
120 PHASE
FLOAT
300 PHASE
V
OUT1
V
V
V
V
OUT1
V
OUT2
OUT2
OUT1
OUT2
PHASMD
PHASMD
PHASMD
4620 F03
Figure 3. Eꢁamples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD ꢂable
of phases used when all of the outputs are tied together
to achieve a single high output current design.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
thanthenumberofphasesusedtimestheoutputvoltage).
Theoutputrippleamplitudeisalsoreducedbythenumber
The LTM4620 device is an inherently current mode con-
trolled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Figure 26 shows an example of parallel operation
and pin connection.
4620f
14
LTM4620
applicaTions inForMaTion
Input RMS Ripple Current Cancellation
Frequency Selection and Phase-Locked Loop
(MODE_PLLIN and f Pins)
SEꢂ
Application Note 77 provides a detailed explanation of
multiphaseoperation.TheinputRMSripplecurrentcancel-
lationmathematicalderivationsarepresented,andagraph
isdisplayedrepresentingtheRMSripplecurrentreduction
asafunctionofthenumberofinterleavedphases. Figure4
shows this graph.
TheLTM4620deviceisoperatedoverarangeoffrequencies
toimprovepowerconversionefficiency.Itisrecommended
to operate the lower output voltages or lower duty cycle
conversions at lower frequencies to improve efficiency by
lowering power MOSFET switching losses. Higher output
voltages or higher duty cycle conversions can be operated
at higher frequencies to limit inductor ripple current. The
efficiencygraphswillshowanoperatingfrequencychosen
for that condition.
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
OUT IN
4620 F04
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
4620f
15
LTM4620
applicaTions inForMaTion
Minimum On-ꢂime
900
800
700
600
500
400
300
200
100
0
Minimum on-time t is the smallest time duration that
ON
the LTM4620 is capable of turning on the top MOSFET on
either channel. It is determined by internal timing delays,
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
VOUT
> tON(MIN)
V •FREQ
IN
0
0.5
1
1.5
2
2.5
f
PIN VOLTAGE (V)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple will increase. The on-time can be
increased by lowering the switching frequency. A good
rule of thumb is to keep on-time longer than 110ns.
SET
4620 F05
Figure 5. Operating Frequency vs fSEꢂ Pin Voltage
The LTM4620 switching frequency can be set with an
external resistor from the f
pin to SGND. An accurate
SET
10µA current source into the resistor will set a voltage
that programs the frequency or a DC voltage can be ap-
plied. Figure 5 shows a graph of frequency setting verses
programming voltage. An external clock can be applied to
Output Voltage ꢂracking
Output voltage tracking can be programmed externally
using the TRACK pins. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4620 uses an
accurate 60.4k resistor internally for the top feedback
resistor for each channel. Figure 6 shows an example of
coincident tracking.
the MODE_PLLIN pin from 0V to INTV over a frequency
CC
range of 400kHz to 780kHz. The clock input high thresh-
old is 1.6V and the clock input low threshold is 1V. The
LTM4620 has the PLL loop filter components on board.
The frequency setting resistor should always be present
to set the initial switching frequency before locking to an
external clock. Both regulators will operate in continuous
mode while being externally clocked.
60.4k
RTA
The output of the PLL phase detector has a pair of comple-
mentary current sources that charge and discharge the
internal filter network. When the external clock is applied,
SLAVE = 1+
• VTRACK
V
V
is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.6V, or the internal
TRACK
TRACK
thef frequencyresistorisdisconnectedwithaninternal
SET
switch, and the current sources control the frequency
adjustment to lock to the incoming external clock. When
no external clock is applied, then the internal switch is on,
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
thus connecting the external f
for free run operation.
frequency set resistor
SET
tracking is disabled when V
is more than 0.6V. R
TRACK
TA
in Figure 6 will be equal to the R for coincident tracking.
FB
Figure 7 shows the coincident tracking waveforms.
4620f
16
LTM4620
applicaTions inForMaTion
INTV
CC
C10
4.7µF
R2
10k
PGOOD
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
7V TO 16V INTERMEDIATE BUS
V
OUT1
V
V
OUT1
IN
1.5V AT 13A
C4
22µF
25V
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
C6
100µF
6.3V
C8
470µF
6.3V
R1*
10k
R6
10k
V
OUTS1
SW1
TEMP
RUN1
RUN2
V
V
FB1
FB2
LTM4620
R
FB
40.2k
COMP1
COMP2
60.4k
TRACK1
TRACK2
D1*
5.1V ZENER
MASTER
V
OUTS2
C
SS
R
R
TA
TB
SLAVE
V
0.1µF
OUT2
60.4k
V
60.4k
OUT2
SW2
f
SET
1.2V AT 13A
C5
C7
PGOOD
PHASMD
100µF
6.3V
470µF
6.3V
1.5V
R4
121k
PGOOD2
DIFFN DIFFOUT
INTV
SGND
GND
DIFFP
CC
R9
10k
RAMP TIME
SOFTSTART
t
= (C /1.3µA) • 0.6V
SS
* PULL-UP RESISTOR AND ZENER ARE OPTIONAL.
4620 F06
Figure 6. Eꢁample of Output ꢂracking Application Circuit
MASTER OUTPUT
SLAVE OUTPUT
TIME
4620 F07
Figure 7. Output Coincident ꢂracking Waveform
4620f
17
LTM4620
applicaTions inForMaTion
The TRACK pin can be controlled by a capacitor placed on
theregulatorTRACKpintoground.A1.3µAcurrentsource
will charge the TRACK pin up to the reference voltage
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then R is equal to R with V
=
FB
TA
FB
V
.ThereforeR =60.4k,andR =60.4kinFigure6.
TRACK
TB TA
and then proceed up to INTV . After the 0.6V ramp, the
CC
Inratiometrictracking, adifferentslewratemaybedesired
TRACK pin will no longer be in control, and the internal
voltage reference will control output regulation from the
feedback divider. Foldback current limit is disabled during
this sequence of turn-on during tracking or soft-starting.
The TRACK pins are pulled low when the RUN pin is below
1.2V. The total soft-start time can be calculated as:
for the slave regulator. R can be solved for when SR is
TB
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then
R
TB
= 76.8k. Solve for R to equal to 49.9k.
TA
CSS
tSOFT-START
=
• 0.6V
Each of the TRACK pins will have the 1.3µA current source
on when a resistive divider is used to implement tracking
on that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
1.3µA
RegardlessofthemodeselectedbytheMODE_PLLINpin,
the regulator channels will always start in pulse-skipping
mode up to TRACK = 0.5V. Between TRACK = 0.5V and
0.54V, it will operate in forced continuous mode and revert
totheselectedmodeonceTRACK>0.54V. Inordertotrack
with another channel once in steady state operation, the
LTM4620 is forced into continuous mode operation as
Power Good
soon as V is below 0.54V regardless of the setting on
FB
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. A resistor
can be pulled up to a particular supply voltage no greater
than 6V maximum for monitoring.
the MODE_PLLIN pin.
Ratiometric tracking can be achieved by a few simple
calculations and the slew rate value applied to the mas-
ter’s TRACK pin. As mentioned above, the TRACK pin has
a control range from 0 to 0.6V. The master’s TRACK pin
slew rate is directly equal to the master’s output slew rate
in Volts/Time. The equation:
Stability Compensation
The module has already been internally compensated for
all output voltages. Table 4 is provided for most applica-
tion requirements. LTpowerCAD will be provided for other
control loop optimization.
MR
SR
• 60.4k = RTB
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
Run Enable
tracking is desired, then MR and SR are equal, thus R
TB
is equal the 60.4k. R is derived from equation:
TheRUNpinshaveanenablethresholdof1.4Vmaximum,
typically1.25Vwith150mVofhysteresis. Theycontrolthe
TA
0.6V
RTA
=
turnoneachofthechannelsandINTV .Thesepinscanbe
CC
VTRACK
RTB
V
V
FB
FB
+
−
pulleduptoV for5Voperation,ora5VZenerdiodecanbe
IN
60.4k RFB
placedonthepinsanda10kto100kresistorcanbeplaced
up to higher than 5V input for enabling the channels. The
RUN pins can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tie together and
where V is the feedback voltage reference of the regula-
FB
tor, and V
is 0.6V. Since R is equal to the 60.4k top
TRACK
TB
4620f
18
LTM4620
applicaTions inForMaTion
controlled from a single control. See the Typical Applica-
tion circuits in Figure 23.
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usuallyeasiertopredict.Itcombinesthepowerpathboard
inductance in combination with the MOSFET interconnect
bond wire inductance.
INꢂV and EXꢂV
CC
CC
The LTM4620 module has an internal 5V low dropout
regulator that is derived from the input voltage. This regu-
lator is used to power the control circuitry and the power
MOSFET drivers. This regulator can source up to 70mA,
and typically uses ~30mA for powering the device at the
maximum frequency. This internal 5V supply is enabled
by either RUN1 or RUN2.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre-
quency can be measured for its value. The impedance Z
can be calculated:
Z
= 2πfL,
(L)
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
EXTV allowsanexternal5VsupplytopowertheLTM4620
andreducepowerdissipationfromtheinternallowdropout
5V regulator. The power loss savings can be calculated by:
CC
(V – 5V) • 30mA = PLOSS
IN
Calculated by: Z = 1/(2πfC). These values are a good
EXTV has a threshold of 4.7V for activation, and a
( )
C
CC
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss.
maximum rating of 6V. When using a 5V input, connect
this 5V input to EXTV also to maintain a 5V gate drive
CC
level. EXTV must sequence on after V , and EXTV
CC
IN
CC
must sequence off before V .
IN
ꢂemperature Monitoring
Differential Remote Sense Amplifier
Measuring the absolute temperature of a diode is pos-
sible due to the relationship between current, voltage
and temperature described by the classic diode equation:
Anaccuratedifferentialremotesenseamplifierisprovided
to sense low output voltages accurately at the remote
load points. This is especially true for high current loads.
The amplifier can be used on one of the two channels, or
on a single parallel output. It is very important that the
DIFFP and DIFFN are connected properly at the output,
and DIFFOUT is connected to either V
In parallel operation, the DIFFP and DIFFN are connected
properly at the output, and DIFFOUT is connected to
VD
η • V
ID = IS • e
T
or
or V
.
OUTS1
OUTS2
I
VD = η • VT • ln D
IS
one of the V
pins. Review the parallel schematics in
OUTS
where I is the diode current, V is the diode voltage, η is
D
D
Figure 24 and review Figure 2.
the ideality factor (typically close to 1.0) and I (satura-
S
tion current) is a process dependent parameter. V can
SW Pins
T
be broken out to:
The SW pins are generally for testing purposes by moni-
toring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combina-
tion is used called a snubber circuit. The resistor will
dampen the resonance and the capacitor is chosen to
only affect the high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
k • T
q
VT =
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. V is
T
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
4620f
19
LTM4620
applicaTions inForMaTion
temperature relationship that makes diodes suitable
To obtain a linear voltage proportional to temperature
temperature sensors. The I term in the equation above
we cancel the I variable in the natural logarithm term to
S
S
is the extrapolated current through a diode junction when
remove the I dependency from the following equation.
S
the diode has zero volts across the terminals. The I term
This is accomplished by measuring the diode voltage at
S
varies from process to process, varies with temperature,
two currents I , and I , where I = 10 • I ),
1
2
1
2
and by definition must always be less than I . Combining
D
Subtracting we get:
all of the constants into one term:
I1
IS
I2
IS
η • k
q
∆VD = T(KELVIN) •KD • ln − T(KELVIN) •KD • ln
KD =
Combining like terms, then simplifying the natural log
terms yields:
−5
where K = 8.62 •10 , and knowing ln(I /I ) is always
D
D S
positive because I is always greater than I , leaves us
with the equation that:
D
S
∆VD = T(KELVIN) •KD • ln(10)
and redefining constant
I
IS
VD = T(KELVIN) •KD • ln D
K’ = K • ln(10) = 198µV/k
D
D
yields
where V appears to increase with temperature. It is com-
D
∆VD = K'D • T(KELVIN)
mon knowledge that a silicon diode biased with a current
source has an approximately –2mV/°C temperature rela-
tionship (Figure 8), which is at odds with the equation. In
Solving for temperature:
fact, the I term increases with temperature, reducing the
∆VD
K'D
S
T(KELVIN) =
,
ln(I /I )absolutevalueyieldinganapproximately–2mV/°C
D S
composite diode voltage slope.
T(KELVIN) = [°C]+ 273.15,
[°C]= T(KELVIN)− 273.15
1.0
I
I
= 100µA
= 10µA
D
D
means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198µV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
0.8
∆V
D
The diode connected PNP transistor can be pulled up to
IN
0.6
0.4
V with a resistor to set the current to 100µA for using
this diode connected transistor as a general temperature
monitor by monitoring the diode voltage drop with tem-
perature, or a specific temperature monitor can be used
that injects two currents that are at a 10:1 ratio for very
accurate temperature monitoring. See Figure 24 for an
example.
–173
–73
27
127
TEMPERATURE (°C)
4620 F08
Figure 8. Diode Voltage VD vs ꢂemperature
ꢂ(°C) for Different Bias Currents
4620f
20
LTM4620
applicaTions inForMaTion
ꢂhermal Considerations and Output Current Derating
2. θ , the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule, the bulk
of the heat flows out the bottom of the package, but
there is always heat flow out into the ambient environ-
ment. As a result, this thermal resistance value may be
useful for comparing packages but the test conditions
don’t generally match the user’s application.
The thermal resistances reported in the Pin Configura-
tion section of the data sheet are consistent with those
parameters defined by JESD 51-12 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formed on a µModule package mounted to a hardware
test board defined by JESD 51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients is
foundinJESD51-12(“GuidelinesforReportingandUsing
Electronic Package Thermal Information”).
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap-
plicationatvariouselectricalandenvironmentaloperating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
As in the case of θ
, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
JCbottom
4. θ , the thermal resistance from junction to the printed
JB
circuitboard,isthejunction-to-boardthermalresistance
wherealmostalloftheheatflowsthroughthebottomof
the µModule and into the board, and is really the sum of
the θ
and the thermal resistance of the bottom
JCbottom
of the part through the solder joints and through a por-
tion of the board. The board temperature is measured a
specified distance from the package, using a two sided,
two layer board. This board is described in JESD 51-9.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
1. θ , the thermal resistance from junction to ambient, is
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure.Thisenvironmentissometimesreferredtoas“still
air”althoughnaturalconvectioncausestheairtomove.
This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
4620f
21
LTM4620
applicaTions inForMaTion
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 9; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
is used to accurately build the mechanical geometry of
the LTM4620 and the specified PCB with all of the cor-
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD 51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4620 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. An outcome of this
process and due diligence yields a set of derating curves
provided in other sections of this data sheet. After these
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
for θ
and θ , respectively. In practice, power
JCbottom
JCtop
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4620, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware
laboratory tests have been performed, then the θ and
JB
θ
BA
are summed together to correlate quite well with the
LTM4620modelwithnoairfloworheatsinkinginaproperly
define chamber. This θ + θ value is shown in the Pin
JB
BA
Configuration section and should accurately equal the θ
JA
value because approximately 100% of power loss flows
from the junction through the board into ambient with no
airflow or top mounted heat sink. Each system has its own
thermal characteristics, therefore thermal analysis must
be performed by the user in a particular system.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4620 F10
µMODULE DEVICE
Figure 9. Graphical Representation of JESD51-12 ꢂhermal Coefficients
4620f
22
LTM4620
applicaTions inForMaTion
The LTM4620 has been designed to effectively remove
heat from both the top and bottom of the package. The
bottomsubstratematerialhasverylowthermalresistance
to the printed circuit board and the exposed top metal is
thermally connected to the power devices and the power
inductors.Anexternalheatsinkcanbeappliedtothetopof
the device for excellent heat sinking with airflow. Basically
all power dissipating devices are mounted directly to the
substrate and the top exposed metal. This provides two
low thermal resistance paths to remove heat.
Figure 10 shows a modeled temperature plot of the
LTM4620 with BGA heat sink and 200LFM airflow with
4.7W of internal dissipation.
Figure 10. LꢂM4620 12V to 1.2V at 26A with
200LFM, Eꢁternal Heat Sink
Figure 11 shows a modeled temperature plot of the
LTM4620 with no heat sink and 200LFM airflow with 4.7W
of internal dissipation.
These plots equate to a paralleled 1.2V at 26A design
operating at 86% efficiency.
Safety Considerations
The LTM4620 modules do not provide isolation from V
IN
to V . There is no internal fuse. If required, a slow blow
OUT
fuse with a rating twice the maximum input current needs
tobeprovidedtoprotecteachunitfromcatastrophicfailure.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internaltopMOSFETfault. IftheinternaltopMOSFETfails,
then turning it off will not resolve the overvoltage, thus
the internalbottom MOSFETwillturn onindefinitely trying
to protect the load. Under this fault condition, the input
voltage will source very large currents to ground through
the failed internal top MOSFET and enabled internal bot-
tom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can
be used as a secondary fault protector in this situation.
Figure 11. LꢂM4620 12V to 1.2V at 26A with
200LFM, No Eꢁternal Heat Sink
Thedevicedoessupportovercurrentprotection.Atempera-
turediodeisprovidedformonitoringinternaltemperature,
and can be used to detect the need for thermal shutdown
that can be done by controlling the RUN pin.
4620f
23
LTM4620
applicaTions inForMaTion
Power Derating
the load current is derated to ~19A at ~80°C with no air
or heat sink and the power loss for the 12V to 1.0V at
19A output is a ~5.1W loss. The 5.1W loss is calculated
with the ~3.75W room temperature loss from the 12V to
1.0V power loss curve at 19A, and the 1.35 multiplying
factor at 125°C ambient. If the 80°C ambient temperature
is subtracted from the 120°C junction temperature, then
the difference of 40°C divided by 5.1W equals a 7.8°C/W
The 1.0V and 2.5V power loss curves in Figures 12 and 13
can be used in coordination with the load current derating
curves in Figures 14 to 21 for calculating an approximate
Θ thermal resistance for the LTM4620 with various heat
JA
sinking and airflow conditions. The power loss curves are
taken at room temperature, and are increased with a 1.35
to 1.4 multiplicative factor at 125°C. These factors come
fromthefact thatthe powerlossofthe regulatorincreases
about 45% from 25°C to 150°C, thus a 50% spread over
125°C delta equates to ~0.35%/°C loss increase. A 125°C
maximumjunctionminus25°Croomtemperatureequates
to a 100°C increase. This 100°C increase multiplied by
0.35%/°C equals a 35% power loss increase at the 125°C
junction, thus the 1.35 multiplier.
Θ
thermal resistance. Table 2 specifies a 6.5 to 7°C/W
JA
value which is pretty close. The airflow graphs are more
accurate due to the fact that the ambient temperature en-
vironment is controlled better with airflow. As an example
in Figure 15, the load current is derated to ~22A at ~90°C
with 200LFM of airflow and the power loss for the 12V to
1.0V at 22A output is a ~5.94W loss.
The 5.94W loss is calculated with the ~4.4W room tem-
perature loss from the 12V to 1.0V power loss curve at
22A, and the 1.35 multiplying factor at 125°C ambient. If
the90°Cambienttemperatureissubtractedfromthe120°C
junction temperature, then the difference of 30°C divided
The derating curves are plotted with V
and V
in
OUT2
OUT1
parallel single output operation starting at 26A of load
with low ambient temperature. The output voltages are
1.0V and 2.5V. These are chosen to include the lower and
higher output voltage ranges for correlating the thermal
resistance. Thermal models are derived from several
temperature measurements in a controlled temperature
chamber along with thermal modeling analysis.
by 5.94W equals a 5.1°C/W Θ thermal resistance. Table
JA
2 specifies a 5.5°C/W value which is pretty close. Tables 2
and 3 provide equivalent thermal resistances for 1.0V and
2.5V outputs with and without airflow and heat sinking.
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
The derived thermal resistances in Tables 2 and 3 for the
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
temperature.Roomtemperaturepowerlosscanbederived
from the efficiency curves and adjusted with the above
ambient temperature multiplicative factors. The printed
circuit board is a 1.6mm thick four layer board with two
ounce copper for the two outer layers and one ounce
copper for the two inner layers. The PCB dimensions are
101mm×114mm. TheBGAheatsinksarelistedinTable3.
The monitored junction temperature of 120°C minus the
ambient operating temperature specifies how much tem-
perature rise can be allowed. As an example in Figure 14,
4620f
24
LTM4620
applicaTions inForMaTion
ꢂable 2. 1.0V Output
DERAꢂING CURVE
Figures 14, 15
Figures 14, 15
Figures 14, 15
Figures 16, 17
Figures 16, 17
Figures 16, 17
V
(V)
POWER LOSS CURVE
Figure 12
AIRFLOW (LFM)
HEAꢂ SINK
None
Θ
(°C/W)
IN
JA
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
0
6.5 to 7
Figure 12
200
400
0
None
5.5
5
Figure 12
None
Figure 12
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
6.5
5
Figure 12
200
400
Figure 12
4
ꢂable 3. 2.5V Output
DERAꢂING CURVE
Figures 18, 19
V
(V)
POWER LOSS CURVE
Figure 13
AIRFLOW (LFM)
HEAꢂ SINK
None
Θ
(°C/W)
IN
JA
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
0
6.5 to 7
Figures 18, 19
Figure 13
200
400
0
None
5.5 to 6
4.5
Figures 18, 19
Figure 13
None
Figures 20, 21
Figure 13
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
6.5 to 7
4
Figures 20, 21
Figure 13
200
400
Figures 20, 21
Figure 13
3.5
HEAꢂ SINK MANUFACꢂURER
PARꢂ NUMBER
WEBSIꢂE
Aavid Thermalloy
Cool Innovations
375424B00034G
www.aavid.com
4-050503P to 4-050508P
www.coolinnovations.com
4620f
25
LTM4620
applicaTions inForMaTion
ꢂable 4. Output Voltage Response vs Component Matriꢁ (Refer to Figure 23) 0A to 7A Load Step ꢂypical Measured Values
VENDORS
VALUE
PARꢂ NUMBER
C4532X5R0J107MZ
GRM32ER60J107M
18126D107MAT
4TPF470ML
TDK, C
Ceramic
100µF 6.3V
100µF 6.3V
100µF 6.3V
470µF 4V
470µF 6.3V
56µF 25V
OUT1
Murata, C
Ceramic
OUT1
AVX, C
Ceramic
OUT1
Sanyo POSCAP, C
Sanyo POSCAP, C
Bulk
Bulk
OUT2
OUT2
6TPD470M
Sanyo, C Bulk
25SVP56M
IN
P-P
DEVIAꢂION RECOVERY LOAD
V
C
C
C
C
C
C
C
V
DROOP Aꢂ 7A LOAD
(mV)
65
ꢂIME
(µs)
SꢂEP
R
FB
OUꢂ
IN
IN
OUꢂ1
OUꢂ2
FF
BOꢂ
COMP
IN
(V) (CERAMIC) (BULK)** (CERAMIC) (BULK)
(pF)
(pF)
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
(pF)
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
(V)
SꢂEP (mV)
130
(A/µs) (kΩ) FREQ
1
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
100µF
100µF
470µF × 2 100
470µF × 2 100
5
30
30
30
30
30
30
35
30
35
30
30
30
15
18
20
20
30
30
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
90.9 400
90.9 400
90.9 400
90.9 400
60.4 500
60.4 500
60.4 500
60.4 500
40.2 550
40.2 550
30.2 600
30.2 600
30.2 600
30.2 600
19.1 750
19.1 750
19.1 750
19.1 750
1
12
5
65
130
1
100µF × 3 470µF × 2 100
100µF × 3 470µF × 2 100
100µF × 3 470µF × 2 100
100µF × 3 470µF × 2 100
60
120
1
12
5
60
120
1.2
1.2
1.2
1.2
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
65
130
12
5
65
130
100µF
100µF
470µF × 2 100
470µF × 2 100
470µF × 2 100
470µF × 2 100
68
136
12
5
68
136
100µF
70
140
100µF
12
5
70
140
100µF
470µF
470µF
None
None
None
None
470µF
470µF
100
100
150
150
220
220
150
150
75
150
100µF
12
5
75
150
100µF × 3
100µF × 3
100µF × 3
100µF × 3
100µF
100
100
100
100
85
200
12
5
200
200
12
5
200
170
100µF
12
85
170
**Bulk capacitance is optional if V has very low input impedance.
IN
4620f
26
LTM4620
applicaTions inForMaTion
6
9
8
7
6
5
4
3
2
1
0
5V , 2.5V
5V , 1V
IN
OUT
OUT
IN
OUT
OUT
12V , 2.5V
12V , 1V
IN
IN
5
4
3
2
1
0
4
12
20 22
4
12
18
20 22 24 26
0
2
6
8 10
14 16 18
24 26
0
2
6
8 10
14 16
LOAD CURRENT (A)
LOAD CURRENT (A)
4620 F12
4620 F13
Figure 12. 1.0V Power Loss Curve
Figure 13. 2.5V Power Loss Curve
26
24
22
20
18
16
14
12
10
8
26
24
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
80
AMBIENT TEMPERATURE (°C)
80
AMBIENT TEMPERATURE (°C)
0
20
40
60
100
120
0
20
40
60
100
120
4620 F14
4620 F15
Figure 15. 5V to 1V Derating
Curve, No Heat Sink
Figure 14. 12V to 1V Derating
Curve, No Heat Sink
26
24
22
20
18
16
14
12
10
8
26
24
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
80
AMBIENT TEMPERATURE (°C)
0
20
80
0
20
40
60
100
120
40
60
100
120
AMBIENT TEMPERATURE (°C)
4620 F16
4620 F17
Figure 16. 12V to 1V Derating
Curve, BGA Heat Sink
Figure 17. 5V to 1V Derating
Curve, BGA Heat Sink
4620f
27
LTM4620
applicaTions inForMaTion
26
24
22
20
18
16
14
12
10
8
26
24
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
80
0
20
40
60
100
120
80
AMBIENT TEMPERATURE (°C)
0
20
40
60
100
120
AMBIENT TEMPERATURE (°C)
4620 F19
4620 F18
Figure 18. 12V to 2.5V Derating
Curve, No Heat Sink
Figure 19. 5V to 2.5V Derating
Curve, No Heat Sink
26
24
22
20
18
16
14
12
10
8
26
24
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
80
AMBIENT TEMPERATURE (°C)
80
AMBIENT TEMPERATURE (°C)
0
20
40
60
100
120
0
20
40
60
100
120
4620 F20
4620 F21
Figure 20. 12V to 2.5V Derating
Curve, BGA Heat Sink
Figure 21. 5V to 2.5V Derating
Curve, BGA Heat Sink
4620f
28
LTM4620
applicaTions inForMaTion
Layout Checklist/Eꢁample
The high integration of LTM4620 makes the PCB board
layoutverysimpleandeasy.However,tooptimizeitselectri-
cal and thermal performance, some layout considerations
are still necessary.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
• Use large PCB copper areas for high current paths,
including V , GND, V
and V
. It helps to mini-
IN
OUT1
OUT2
• For parallel modules, tie the V , V , and COMP pins
OUT FB
mize the PCB conduction loss and thermal stress.
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Place high frequency ceramic input and output capaci-
tors next to the V , PGND and V
pins to minimize
IN
OUT
high frequency noise.
• Bring out test points on the signal pins for monitoring.
• Place a dedicated power ground layer underneath the
Figure22givesagoodexampleoftherecommendedlayout.
unit.
• Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
C
C
IN1
IN2
V
IN
M
L
K
J
GND
GND
H
G
F
SGND
C
C
OUT2
OUT1
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
V
GND
V
OUT2
OUT1
4620 F22
CNTRL
Figure 22. Recommended PCB Layout
4620f
29
LTM4620
Typical applicaTions
4620f
30
LTM4620
Typical applicaTions
4620f
31
LTM4620
Typical applicaTions
4620f
32
LTM4620
Typical applicaTions
INTV
CC
C10
4.7µF
R2
5k
CLK1
PGOOD1
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
INTERMEDIATE BUS
V
IN
5V TO 16V
V
IN
V
OUT1
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
C
C
+
+
OUT1
OUT2
R1*
10k
R6
10k
V
OUTS1
SW1
100µF
6.3V
470µF
6.3V
TEMP
V
V
FB1
FB
RUN
RUN1
V
R5
60.4k
FB2
LTM4620
RUN2
COMP1
COMP2
D1*
5.1V ZENER
TRACK1
TRACK1
TRACK2
COMP
V
OUTS2
f
V
SET
OUT2
SW2
C
C
OUT1
OUT2
PHASMD
100µF
6.3V
470µF
6.3V
R4
121k
PGOOD2
DIFFN DIFFOUT
PGOOD1
SGND
GND
DIFFP
V
OUT
1.2V AT 50A
C16
4.7µF
CLK1
PGOOD1
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
5V TO 16V INTERMEDIATE BUS
V
V
OUT1
IN
C12
22µF
25V
C15
22µF
25V
C5
22µF
25V
C
C
OUT2
+
+
OUT1
R9
V
OUTS1
SW1
100µF
6.3V
470µF
6.3V
10k
TEMP
RUN1
RUN1
V
V
V
FB
FB1
FB2
RUN2
LTM4620
TRACK1
COMP1
COMP2
COMP
TRACK1
TRACK2
C19
0.22µF
V
OUTS2
f
SET
V
OUT2
SW2
C
C
OUT1
OUT2
PHASMD
100µF
6.3V
470µF
6.3V
R10
121k
PGOOD2
DIFFN DIFFOUT
PGOOD1
SGND
GND
DIFFP
INTV
CC
4620 F26
* PULL-UP RESISTOR AND ZENER ARE OPTIONAL.
Figure 26. 4-Phase, 1.2V at 50A
4620f
33
LTM4620
package DescripTion
LꢂM4620 Component LGA Pinout
PIN ID FUNCꢂION PIN ID FUNCꢂION
PIN ID FUNCꢂION
PIN ID
B1
FUNCꢂION
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
GND
PIN ID
E1
FUNCꢂION
GND
PIN ID
F1
FUNCꢂION
GND
A1
A2
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
GND
C1
C2
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1S
D1
D2
GND
GND
B2
E2
GND
F2
GND
A3
B3
C3
D3
GND
E3
GND
F3
GND
A4
B4
C4
D4
GND
E4
GND
F4
MODE_PLLIN
RUN1
A5
B5
C5
D5
VFB1
SGND
VFB2
TRACK2
GND
E5
TRACK1
COMP1
COMP2
DIFFP
DIFFN
GND
F5
A6
B6
C6
f
D6
E6
F6
SGND
SET
A7
GND
B7
GND
C7
SGND
VOUT2S
VOUT2
VOUT2
VOUT2
VOUT2
D7
E7
F7
SGND
A8
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
B8
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
C8
D8
E8
F8
DIFFOUT
RUN2
A9
B9
C9
D9
E9
F9
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
GND
E10
E11
E12
F10
F11
F12
GND
GND
GND
GND
GND
GND
GND
PIN ID FUNCꢂION
PIN ID
H1
FUNCꢂION
GND
PIN ID
J1
FUNCꢂION PIN ID FUNCꢂION
PIN ID
L1
FUNCꢂION
GND
VIN
PIN ID
M1
FUNCꢂION
GND
VIN
G1
G2
GND
SW1
GND
VIN
K1
K2
GND
VIN
H2
GND
J2
L2
M2
G3
GND
H3
GND
J3
VIN
K3
VIN
L3
VIN
M3
VIN
G4
PHASMD
CLKOUT
SGND
SGND
PGOOD2
PGOOD1
GND
H4
GND
J4
VIN
K4
VIN
L4
VIN
M4
VIN
G5
H5
GND
J5
GND
TEMP
EXTVCC
GND
VIN
K5
GND
GND
GND
GND
VIN
L5
VIN
M5
VIN
G6
H6
GND
J6
K6
L6
VIN
M6
VIN
G7
H7
GND
J7
K7
L7
VIN
M7
VIN
G8
H8
INTVCC
GND
J8
K8
L8
VIN
M8
VIN
G9
H9
J9
K9
L9
VIN
M9
VIN
G10
G11
G12
H10
H11
H12
GND
J10
J11
J12
VIN
K10
K11
K12
VIN
L10
L11
L12
VIN
M10
M11
M12
VIN
SW2
GND
VIN
VIN
VIN
VIN
GND
GND
GND
GND
GND
GND
4620f
34
LTM4620
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LGA Package
144-Lead (15mm × 15mm × 4.41mm)
(Reference LTC DWG # 05-08-1844 Rev A)
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
4620f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTM4620
package pꢅoTo
4.41mm
15mm
15mm
relaTeD parTs
PARꢂ NUMBER DESCRIPꢂION
COMMENꢂS
LTM4628
Dual 8A, Single 16A µModule Regulator
Pin Compatible with LTM4620; 4.5V ≤ V ≤ 26.5V, 0.6V ≤ V
≤ 5.5V,
IN
OUT
15mm × 15mm × 4.32mm
LTM4627
LTM4611
LTM4619
LTM4615
LTM4616
LTM4627
15A µModule Regulator
Ultralow V , 15A µModule Regulator
4.5V ≤ V ≤ 20V, 0.6V ≤ V
≤ 5.5V, 15mm × 15mm × 4.32mm
OUT
IN
1.5V ≤ V ≤ 5.5V, 0.8V ≤ V ≤ 5V, 15mm × 15mm × 4.32mm
OUT
IN
IN
Dual 26V , 4A DC/DC µModule Regulator
4.5V ≤ V ≤ 26.5V; 0.8V ≤ V
≤ 5V
OUT
IN
IN
Triple Low V , 4A DC/DC µModule Regulator
2.375 ≤ V ≤ 5.5V; Two 4A and One 1.5A Output
IN
IN
Dual 8A, Low V , DC/DC µModule Regulator
2.7V ≤ V ≤ 5.5V; 0.6V ≤ V
≤ 5V
≤ 5V
IN
IN
OUT
OUT
15A DC/DC µModule Regulator
4.5V ≤ V ≤ 20V; 0.6V ≤ V
IN
LTM8062/
LTM8062A
32V , 2A µModule Battery Charger with Maximum Adjustable V
Up to 14.4V (18.8V for the LTM8062A), C/10 or Timer
IN
BATT
Peak Power Tracking (MPPT)
Termination, 9mm × 15mm × 4.32mm LGA Package
LTM8027
LTM4613
60V , 4A DC/DC Step-Down µModule Regulator
4.5V ≤ V ≤ 60V, 2.5V ≤ V ≤ 24V, 15mm × 15mm × 4.32mm LGA Package
IN
IN
OUT
EN55022B Compliant 36V , 8A Step-Down
5V ≤ V ≤ 36V, 3.3V ≤ V
≤ 15V, Synchronizable, Parallelable,
IN
IN
OUT
µModule Regulator
15mm × 15mm × 4.32mm LGA Package
4620f
LT 0712 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTM8062EV#PBF
LTM8062 - 32VIN, 2A µModule (Power Module) Power Tracking Battery Charger; Package: LGA; Pins: 77; Temperature Range: -40°C to 85°C
Linear
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