DS28E50QT [MAXIM]
DeepCover Secure SHA-3 Authenticator with ChipDNA PUF Protection;
| 型号： | DS28E50QT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | DeepCover Secure SHA-3 Authenticator with ChipDNA PUF Protection |
| 文件： | 总17页 (文件大小：446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Request DS28E50 Security User Guide
EVALUATION KIT AVAILABLE
Click here for production status of specific part numbers.
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
General Description
Benefits and Features
● Robust Countermeasures Protect Against Security
The DS28E50 secure authenticator combines FIPS202-
compliant secure hash algorithm (SHA-3) challenge
and response authentication with Maxim’s patented
ChipDNA™ technology, a physically unclonable function
(PUF) to provide a cost-effective solution with the ultimate
protection against security attacks. The ChipDNA imple-
mentation utilizes the random variation of semiconductor
device characteristics that naturally occur during wafer
fabrication. The ChipDNA circuit generates a unique
output value that is repeatable over time, temperature,
and operating voltage. Attempts to probe or observe
ChipDNA operation modifies the underlying circuit charac-
teristics thus preventing discovery of the unique value used
by the chip cryptographic functions. The DS28E50 utilizes
the ChipDNA output as key content to cryptographically
secure all device-stored data. With ChipDNA capability, the
device provides a core set of cryptographic tools derived
from integrated blocks including a SHA-3 engine, a FIPS/
NIST compliant true random number generator (TRNG),
2Kb of secured EEPROM, a decrement-only counter and
a unique 64-bit ROM identification number (ROM ID). The
unique ROM ID is used as a fundamental input parameter
for cryptographic operations and serves as an electronic
serial number within the application. The DS28E50 com-
municates over the single-contact 1-Wire® bus at both
standard and overdrive speeds. The communication fol-
lows the 1-Wire protocol with the ROM ID acting as node
address in the case of a multidevice 1-Wire network.
Attacks
• Patented Physically Unclonable Function Secures
Device Data
• Actively Monitored Die Shield Detects and Reacts
to Intrusion Attempts
• All Stored Data Cryptographically Protected from
Discovery
● Efficient Secure Hash Algorithm Authenticates
Peripherals
• FIPS 202-Compliant SHA-3 Algorithm for
Challenge/Response Authentication
• FIPS 198-Compliant Keyed-Hash Message
Authentication Code (HMAC)
• TRNG with NIST SP 800-90B Compliant Entropy
Source
● Supplemental Features Enable Easy Integration into
End Applications
• 17-Bit One-Time Settable, Nonvolatile Decrement-
Only Counter with Authenticated Read
• One GPIO Pin with Optional Authentication Control
• 2Kb of EEPROM for User Data, Key, and Control
Registers
• Unique and Unalterable Factory Programmed
64-Bit Identification Number (ROM ID)
• Single-Contact, 1-Wire Interface Communication
with Host at 11.7kbps and 62.5kbps
• Operating Range: 3.3V ±10%, -40°C to +85°C
• 6-Pin TDFN-EP Package (3mm x 3mm)
Applications
● Authentication of Medical Sensors and Tools
● Secure Management of Limited Use Consumables
● IoT Node Authentication
● Peripheral Authentication
● Reference Design License Management
● Printer Cartridge Identification and Authentication
Ordering Information appears at end of data sheet.
ChipDNA is a trademark and 1-Wire is a registered trademark
of Maxim Integrated Products, Inc.
19-100367; Rev 1; 9/18
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
Typical Application Circuit
V
CC
R
P
V
CC
V
CC
IO
2
I C
SDA
SCL
DS2477
GPIO
PORT
µC
IO
GND
IO
GND
IO
PIO
DS28E50
C
EXT
C
X
GND
Maxim Integrated
│ 2
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to GND..........-0.5V to 4.0V
Maximum Current into Any Pin........................... -20mA to 20mA
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -40°C to +125°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
6 TDFN-EP
Package Code
T633+2
21-0137
90-0058
Outline Number
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
)
55ºC/W
9ºC/W
JA
Junction to Case (θ
)
JC
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
42ºC/W
9ºC/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(Limits are 100% tested at T = +25ºC and T = +85ºC. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production
tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
R
System requirement
2.97
3.3
3.63
V
PUP
(Note 1)
1000
Ω
PUP
C
(Notes 1, 2)
0.1 + C
470
nF
nF
µA
IO
X
Capacitor External
C
System requirement, IO pin at V
399.5
540.5
360
X
PUP
Input Load Current
I
IO pin at V
10
L
PUP
High-to-Low Switching
Threshold
0.65 x
V
(Notes 3, 4)
(Note 5)
V
V
V
TL
V
PUP
0.10 x
VPUP
Input Low Voltage
V
IL
Low-to-High Switching
Threshold
0.75 x
V
(Notes 3, 6)
(Notes 3, 7)
TH
V
PUP
Switching Hysteresis
Output Low Voltage
V
V
0.3
V
V
HY
I
= 4mA (Note 8)
0.4
OL
OL
Maxim Integrated
│ 3
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25ºC and T = +85ºC. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production
tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire INTERFACE
Standard speed, R
= 1000Ω
25
5
PUP
Overdrive speed,
= 1000Ω,
T = -40°C to
A
+55°C
T = -40°C to
A
R
PUP
Recovery Time (Note 9)
t
t
μs
REC
Overdrive speed,
= 1000Ω
10
R
+85°C
PUP
Directly prior to reset pulse: R
= 1000Ω
100
PUP
Rising-Edge Hold-off (Note 10)
Applies to standard speed only
Standard speed
1
μs
μs
REH
85
16
Time Slot Duration (Note 11)
t
SLOT
Overdrive speed
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
System requirement, standard speed
480
48
480
48
65
7
640
80
Reset Low Time
t
μs
μs
μs
RSTL
System requirement, overdrive speed
Standard speed
Reset High Time (Note 21)
t
RSTH
Overdrive speed
Standard speed
75
10
Presence-Detect Sample Time
(Note 12)
t
MSP
Overdrive speed
IO PIN: 1-Wire WRITE
Standard speed
Overdrive speed
Standard speed
Overdrive speed
60
6
120
15.5
15
Write-Zero Low Time (Note 13)
t
t
μs
μs
W0L
0.25
0.25
Write-One Low Time (Note 13)
IO PIN: 1-Wire READ
W1L
2
Standard speed
Overdrive speed
Standard speed
Overdrive speed
0.25
0.25
15 - δ
2 - δ
15
Read Low Time (Note 14)
t
μs
μs
RL
t
+ δ
RL
Read Sample Time (Note 14)
t
MSR
t
+ δ
2
RL
PIO PIN
Output Low
PIOV
PIOI = 4mA (Note 8)
OL
0.4
V
V
OL
0.20
Input Low
Input High
PIOV
-0.3
0.7
IL
x V
PUP
V
+
PUP
0.3
PIOV
PIOI
V
IH
x V
PUP
Leakage Current
-1
+2
μA
L
STRONG PULLUP OPERATION
Strong Pullup Current
Strong Pullup Voltage
I
(Note 15)
(Note 15)
10
mA
V
SPU
V
2.8
SPU
Maxim Integrated
│ 4
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25ºC and T = +85ºC. Limits over the operating temperature range and relevant supply voltage
A
A
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production
tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
Read Memory
SYMBOL
CONDITIONS
MIN
TYP
MAX
50
UNITS
ms
t
RM
Write Memory
t
100
ms
WM
Page data changes limited to one of four
8-byte blocks (refer to the DS28E50 Security
User Guide)
Blockwise Write Memory
t
60
ms
WM_BL
Write State
t
60
25
50
5
ms
ms
ms
ms
WS
TRNG Generation
TRNG On-Demand Check
Computation Time (HMAC)
EEPROM
t
t
t
RNG
ODC
CMP
Write/Erase Cycles (Endurance)
Data Retention
N
(Notes 16, 17)
100K
10
CY
t
T
= +85ºC (Notes 18, 19, 20)
years
DR
A
Note 1: System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system
and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire
recovery times.
Note 2: Value represents the typical parasite capacitance when V
is first applied. Once the parasite capacitance is charged,
PUP
it does not affect normal communication. Typically, during normal communication, the parasite capacitance is effectively
~100pF.
Note 3:
V
, V , and V
are a function of the internal supply voltage, which is a function of V
, R
, 1-Wire timing, and
TL TH
HY
PUP PUP
capacitive loading on IO. Lower V
, higher R
, shorter t
, and heavier capacitive loading all lead to lower values
PUP
PUP
REC
of V , V , and V
.
TL TH
HY
Note 4: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 5: The voltage on IO must be less than or equal to V at all times the master is driving IO to a logic-zero level.
ILMAX
Note 6: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 7: After V is crossed during a rising edge on IO, the voltage on IO must drop by at least V
to be detected as logic-zero.
TH
HY
Note 8: The I-V characteristic is linear for voltages less than 1V.
Note 9: System requirement. Applies to a single device attached to a 1-Wire line.
Note 10: The earliest recognition of a negative edge is possible at t
after V has been previously reached.
REH
TH
Note 11: Defines maximum possible bit rate. Equal to 1/(t
+ t
).
W0LMIN
RECMIN
Note 12: System requirement. Interval after t
during which a bus master can read a logic 0 on IO if there is a DS28E50 present.
RSTL
The power-up presence detect pulse can be outside this interval, but completes within 2ms after power-up.
Note 13: System requirement. ε in Figure 4 represents the time required for the pullup circuitry to pull the voltage on IO up from V to
IL
V
. The actual maximum duration for the master to pull the line low is t
+ t - ε and t
+ t - ε, respectively.
TH
W1LMAX
F
W0LMAX F
Note 14: System requirement. δ in Figure 4 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is t
+ t .
RLMAX
F
Note 15: Current drawn from IO during a SPU operation interval. The pullup circuit on IO during the SPU operation interval should
be such that the voltage at IO is greater than or equal to V . A low-impedance bypass of R activated during the
SPUMIN
PUP
SPU operation is the recommended way to meet this requirement.
Note 16: Write-cycle endurance is tested in compliance with JESD47G.
Note 17: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 18: Data retention is tested in compliance with JESD47G.
Note 19: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 20: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated
temperatures is not recommended.
Note 21: An additional reset or communication sequence cannot begin until the reset high time has expired.
Maxim Integrated
│ 5
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
Pin Configuration
TOP VIEW
PIO 1
IO 2
+
6 C
EXT
5 DNC
4 DNC
DS28E50
GND 3
TDFN-EP
(3mm x 3mm)
Pin Description
PIN
1
NAME
PIO
FUNCTION
General-Purpose IO
1-Wire IO
2
IO
3
GND
DNC
Ground
4, 5
6
Do Not Connect
C
Input for External Capacitor
EXT
Exposed Pad (TDFN Only). Solder evenly to the board's ground plane for proper operation. Refer to
Application Note 3273: Exposed Pads: A Brief Introductionfor additional information.
—
E.P.
Maxim Integrated
│ 6
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
Functional Diagram
C
X
PARASITE
POWER
C
EXT
64-BIT ROM ID
BUFFER
1-WIRE
INFC
&
IO
SHA3-256
TRNG
CMD
2kb E2 ARRAY
USER MEMORY
SHA3 SECRET
DECREMENT COUNTER
REGISTERS
AUTHENTICATED
GPIO
PIO
ChipDNA
DS28E50
and control registers. One user page can optionally be
designated as a decrement-only counter. The PIO pin
can be independently operated under command control
and includes configurability supporting authenticated and
nonauthenticated operation. The device operates from
a 1-Wire interface with a parasitic supply by way of an
external capacitor.
Detailed Description
The DS28E50 integrates the Maxim ChipDNA capability
to protect all device stored data from invasive discovery.
In addition to the PUF and SHA-3 engines for signatures,
the device integrates a FIPS/NIST compliant TRNG,
2Kb EEPROM for user memory, SHA-3 secret storage,
Maxim Integrated
│ 7
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
or a coprocessor like the DS2477. The discussion of this
bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling
(signal types and timing). The 1-Wire protocol defines bus
transactions in terms of the bus state during specific time
slots that are initiated on the falling edge of sync pulses
from the bus master.
Design Resource Overview
Operation of the DS28E50 involves use of device
EEPROM and execution of device function commands.
The following section provides an overview including the
decrement counter. Refer to the DS28E50 Security User
Guide for details.
Memory
A 2Kb secured EEPROM array provides SHA-3 secret
storage, along with a decrement counter, and/or general-
purpose, user-programmable memory. Depending on the
memory space, there are either default or user-program-
mable options to set protection modes.
66h
N
FROM ROM FUNCTIONS
FLOW CHART
MASTER Tx
COMMAND START
COMMAND
START?
Y
MASTER Tx INPUT
LENGTH BYTE
General-Purpose I/O (GPIO)
MASTER Tx COMMAND BYTE
The open-drain PIO pin can be read and controlled in an
authenticated or nonauthenticated manner. Authenticated
operation includes measures to prevent replay attacks.
Upon power-up, the default state for the PIO pin is in high
impedance.
MASTER Tx
PARAMETER BYTE(S)
MASTER Rx CRC-16 (INVERTED
OF COMMAND START, LENGTH,
COMMAND, AND PARAMETERS)
Function Commands
MASTER Tx RELEASE BYTE
After a 1-Wire reset/presence cycle and ROM function
command sequence is successful, a command start
can be accepted and then followed by a device function
command. In general, these commands follow Figure 1.
Within this diagram, the data transfer is verified when writ-
ing and reading by a 16-bit CRC (CRC-16). The CRC-16
is computed as described in Maxim's Application Note 27:
Understanding and Using Cyclic Redundancy Checks
with Maxim 1-Wire and iButton Products..
N
SLAVE Rx AAh
RELEASE BYTE?
Y
DELAY WITH STRONG PULLUP
MASTER Rx FFh DUMMY BYTE
MASTER Rx OUTPUT
LENGTH BYTE
MASTER Rx RESULT BYTE
MASTER Rx DATA BYTE(S)
Decrement Counter
The optional 17-bit decrement counter can be written one
time on a dual-purpose page of memory. A dedicated
device function command is used to decrement the count
value by one with each call. Once the count value reach-
es a value of 0, no additional decrements are possible.
MASTER Rx CRC-16 (INVERTED
OF LENGTH, RESULT, AND DATA)
N
MASTER
Rx 1s
MASTER Tx
RESET?
Y
1-Wire Bus System
TO ROM FUNCTIONS
FLOW CHART
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS28E50 is a
slave device. The bus master is typically a microcontroller
Figure 1. Device Function Flow Chart
Maxim Integrated
│ 8
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
Hardware Configuration
Transaction Sequence
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus can drive it at the
appropriate time. To facilitate this, each device attached
to the 1-Wire bus must have open-drain or three-state
outputs. The 1-Wire port of the DS28E50 is open drain
with an internal circuit equivalent.
The protocol for accessing the DS28E50 through the
1-Wire port is as follows:
● Initialization
● ROM Function command
● Device Function command
● Transaction/data
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E50 supports both a standard
and overdrive communication speed of 11.7kbps (max)
and 62.5kbps (max), respectively. The value of the pullup
resistor primarily depends on the network size and load
conditions. The DS28E50 requires a pullup resistor of
1kΩ (max) at any speed.
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS28E50 is
on the bus and is ready to operate. For more details, see
the 1-Wire Signaling and Timing section.
The idle state for the 1-Wire bus is high. If for any reason
a transaction needs to be suspended, the bus must be left
in the idle state if the transaction is to resume. If this does
not occur and the bus is left low for more than 15.5μs
(overdrive speed) or more than 120μs (standard speed),
one or more devices on the bus could be reset.
V
PUP
*SEE NOTE
1-WIRE SLAVE PORT
BUS MASTER
C
X
Tx
PIOX
PIOY
CTL
Rx
R
PUP
Rx
Tx
DATA
I
L
Tx
Rx = RECEIVE
Tx = TRANSMIT
BIDIRECTIONAL
OPEN-DRAIN PORT
100Ω
MOSFET
*NOTE: USE A LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY
Figure 2. Hardware Configuration
Maxim Integrated
│ 9
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
and device function command. If the bus master uses
slew-rate control on the falling edge, it must pull down the
1-Wire Signaling and Timing
The DS28E50 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence
pulse, write-zero, write-one, and read-data. Except for the
presence pulse, the bus master initiates all falling edges.
The DS28E50 can communicate at two speeds: standard
and overdrive. If not explicitly set into the overdrive mode,
the DS28E50 communicates at standard speed. While in
overdrive mode, the fast timing applies to all waveforms.
line for t
+ t to compensate for the edge. A t
RSTL
F RSTL
duration of 480μs or longer exits the overdrive mode,
returning the device to standard speed. If the DS28E50 is
in overdrive mode and t
is no longer than 80μs,
RSTL
the device remains in overdrive mode. If the device is in
overdrive mode and t is between 80μs and 480μs,
RSTL
the device resets, but the communication speed is unde-
termined.
After the bus master has released the line, it goes into
To get from idle to active, the voltage on the 1-Wire line
receive mode. Now, the 1-Wire bus is pulled to V
PUP
needs to fall from V
below the threshold V . To get
PUP
TL
through the pullup resistor or, in the case of a special
driver chip, through the active circuitry. Now, the 1-Wire
from active to idle, the voltage needs to rise from V
ILMAX
past the threshold V . The time it takes for the voltage
TH
bus is pulled to V
through the pullup resistor. When
PUP
to make this rise is seen in Figure 3 as ε, and its dura-
the threshold V
is crossed, the DS28E50 waits and
TH
tion depends on the pullup resistor (R
) used and the
PUP
then transmits a presence pulse by pulling the line low. To
detect a presence pulse, the master must test the logical
capacitance of the 1-Wire network attached. The voltage
is relevant for the DS28E50 when determining a
V
ILMAX
state of the 1-Wire line at t
.
MSP
logical level, not triggering any events.
Immediately after t
has expired, the DS28E50 is
RSTH
Figure 3 shows the initialization sequence required to
begin any communication with the DS28E50. A reset
pulse followed by a presence pulse indicates that the
DS28E50 is ready to receive data, given the correct ROM
ready for data communication. In a mixed population net-
work, t should be extended to a minimum 480μs at
RSTH
standard speed and a 48μs at overdrive speed to accom-
modate other 1-Wire devices.
MASTER Tx RESET PULSE
MASTER Rx PRESENCE PULSE
t
MSP
ε
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
t
REC
RSTL
t
F
t
RSTH
MASTER
1-WIRE SLAVE
RESISTOR (R
)
PUP
Figure 3. Initialization Procedure: Reset and Presence Pulse
Maxim Integrated
│ 10
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
line low; its internal timing generator determines when this
pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28E50 does not hold the data
Read/Write Time Slots
Data communication with the DS28E50 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 4 illustrates the
definitions of the write and read time slots.
line low at all, and the voltage starts rising as soon as t
is over.
RL
The sum of t + δ (rise time) on one side and the internal
RL
timing generator of the DS28E50 on the other side define
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
the master sampling window (t
to t
), in
MSRMIN
MSRMAX
which the master must perform a read from the data line.
For the most reliable communication, t should be as
the threshold V , the DS28E50 starts its internal timing
TL
RL
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
short as permissible, and the master should read close
to, but no later than t . After reading from the data
MSRMAX
line, the master must wait until t
antees sufficient recovery time t
is expired. This guar-
for the DS28E50 to
SLOT
REC
Master to Slave
For a write-one time slot, the voltage on the data line must
get ready for the next time slot. Note that t
specified
REC
have crossed the V
threshold before the write-one low
herein applies only to a single DS28E50 attached to a
1-Wire line. For multidevice configurations, t must be
TH
time t
is expired. For a write-zero time slot, the
W1LMAX
REC
voltage on the data line must stay below the V
thresh-
extended to accommodate the additional 1-Wire device
input capacitance. Alternatively, an interface that performs
active pullup during the 1-Wire recovery time such as the
special 1-Wire line drivers can be used.
TH
old until the write-zero low time t
is expired. For
W0LMIN
the most reliable communication, the voltage on the data
line should not exceed V during the entire t or
ILMAX
W0L
t
window. After the V
threshold has been crossed,
W1L
TH
1-Wire ROM Commands
the DS28E50 needs a recovery time t
ready for the next time slot.
before it is
REC
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that the
DS28E50 supports.All ROM function commands are 8 bits
long. For operational details, see Figure 5 and Figure 6.
A descriptive list of these ROM function commands fol-
lows in the subsequent sections and the commands are
summarized in Table 1.
Slave to Master
A read-data time slot begins like a write-one time slot. The
voltage on the data line must remain below V until the
read low time t is expired. During the t window, when
responding with a 0, the DS28E50 starts pulling the data
TL
RL
RL
Table 1. 1-Wire ROM Commands Summary
ROM FUNCTION COMMAND
CODE
DESCRIPTION
Search for a device
Search ROM
Read ROM
F0h
33h
55h
CCh
A5h
3Ch
69h
Read ROM from device (single drop)
Select a device by ROM number
Select only device on 1-Wire
Match ROM
Skip ROM
Resume
Selected device with RC bit set
Put all devices in overdrive
Overdrive Skip ROM
Overdrive Match ROM
Put the device with the ROM in overdrive
Maxim Integrated
│ 11
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
WRITE-ONE TIME SLOT
t
W1L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
F
t
SLOT
MASTER
RESISTOR (R
)
PUP
WRITE-ZERO TIME SLOT
t
W0L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
t
F
REC
t
SLOT
MASTER
RESISTOR (R
)
PUP
READ-DATA TIME SLOT
t
MSR
t
RL
V
PUP
V
IHMASTER
V
TH
MASTER SAMPLING
WINDOW
V
TL
V
ILMAX
0V
δ
t
F
t
REC
t
SLOT
MASTER
1-WIRE SLAVE
RESISTOR (R
)
PUP
Figure 4. Read/Write Timing Diagrams
Maxim Integrated
│ 12
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
BUS MASTER Tx
RESET PULSE
FROM ROM FUNCTION FLOW PART 2
FROM DEVICE FUNCTIONS
FLOW CHART
N
OD
OD = 0
RESET PULSE?
Y
BUS MASTER Tx
SLAVE Tx
ROM FUNCTION COMMAND
PRESENCE PULSE
33h
55h
F0h
CCh
N
N
N
N
READ ROM
COMMAND?
MATCH ROM
COMMAND?
SEARCH ROM
COMMAND?
SKIP ROM
COMMAND?
TO ROM FUNCTION
FLOW PART 2
Y
Y
Y
Y
RC = 0
RC = 0
RC = 0
RC = 0
SLAVE Tx BIT 0
SLAVE Tx BIT 0
MASTER Tx BIT 0
SLAVE Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
N
N
BIT 0 MATCH?
Y
BIT 0 MATCH?
Y
SLAVE Tx BIT 1
SLAVE Tx BIT 1
MASTER Tx BIT 0
SLAVE Tx
SERIAL NUMBER
(6 BYTES)
MASTER Tx BIT 1
Y
N
N
BIT 1 MATCH?
Y
BIT 1 MATCH?
Y
SLAVE Tx BIT 63
SLAVE Tx BIT 63
MASTER Tx BIT 63
SLAVE Tx
CRC BYTE
MASTER Tx BIT 63
N
N
BIT 63 MATCH?
RC = 1
BIT 63 MATCH?
RC = 1
TO ROM FUNCTION
FLOW PART 2
FROM ROM FUNCTION FLOW PART 2
Figure 5. ROM Function Flow, Part 1
Maxim Integrated
│ 13
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
TO ROM FUNCTION FLOW PART 1
FROM ROM
FUNCTION
FLOW PART 1
A5h
3Ch
69h
N
N
N
RESUME
COMMAND?
OVERDRIVE-
SKIP ROM?
OVERDRIVE-
MATCH ROM?
Y
Y
Y
RC = 0; OD = 1
RC = 0; OD = 1
N
RC = 1?
MASTER Tx BIT 0
Y
N
MASTER Tx
RESET?
BIT 0 MATCH?
Y
OD = 0
N
MASTER Tx BIT 1
Y
MASTER Tx
RESET?
N
N
BIT 1 MATCH?
Y
OD = 0
SLAVE Tx BIT 63
N
BIT 63 MATCH?
RC = 1
OD = 0
FROM ROM FUNCTION
FLOW PART 1
TO ROM FUNCTION FLOW PART 1
Figure 6. ROM Function Flow, Part 2
www.maximintegrated.com
TO DEVICE FUNCTIONS
FLOW CHART
Maxim Integrated
│ 14
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
Search ROM[F0h]
Resume [A5h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a pro-
cess of elimination to identify the ID of all slave devices.
For each bit in the ID number, starting with the least sig-
nificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion, including an example.
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the device function commands, similar
to a Skip ROM command. The only way to set the RC
bit is through successfully executing the Match ROM,
Search ROM, or Overdrive-Match ROM command. Once
the RC bit is set, the device can repeatedly be accessed
through the Resume command. Accessing another device
on the bus clears the RC bit, preventing two or more
devices from simultaneously responding to the Resume
command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the device functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM command
sets the DS28E50 into the overdrive mode (OD = 1). All
communication following this command must occur at
overdrive speed until a reset pulse of minimum 480μs
duration resets all devices on the bus to standard speed
(OD = 0).
Read ROM[33h]
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search pro-
cess. If more than one slave supporting overdrive is pres-
ent on the bus and the Overdrive-Skip ROM command
is followed by a read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
drain pulldowns produce a wired-AND result).
The Read ROM command allows the bus master to read
the DS28E50’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
Match ROM[55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28E50 on a multidrop bus. Only the DS28E50 that
exactly matches the 64-bit ROM sequence responds
to the subsequent device function command. All other
slaves wait for a reset pulse. This command can be used
with a single device or multiple devices on the bus.
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-bit
ROM sequence transmitted at overdrive speed allows the
bus master to address a specific DS28E50 on a multi-
drop bus and to simultaneously set it in overdrive mode.
Only the DS28E50 that exactly matches the 64-bit ROM
sequence responds to the subsequent device function
command. Slaves already in overdrive mode from a previ-
ous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All overdrive-
capable slaves return to standard speed at the next reset
pulse of minimum 480μs duration. The Overdrive-Match
ROM command can be used with a single device or mul-
tiple devices on the bus.
Skip ROM [CCh]
This command can save time in a single-drop bus system
by allowing the bus master to access the device functions
without providing the 64-bit ROM ID. If more than one
slave is present on the bus and, for example, a read com-
mand is issued following the Skip ROM command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
Maxim Integrated
│ 15
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
The DS28E50’s 1-Wire front-end has the following features:
Improved Network Behavior (Switch-Point
Hysteresis)
● There is additional lowpass filtering in the circuit that
detects the falling edge at the beginning of a time
slot. This reduces the sensitivity to high-frequency
noise. This additional filtering does not apply at over-
drive speed.
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization with
the master and, consequently, result in a Search ROM
command coming to a dead end or cause a device-spe-
cific function command to abort. For better performance
in network applications, the DS28E50 uses a 1-Wire front
end that is less sensitive to noise.
● There is a hysteresis at the low-to-high switching
threshold V . If a negative glitch crosses V , but
TH
TH
does not go below V - V , it is not recognized
TH
HY
(Figure 7, Case A). The hysteresis is effective at any
1-Wire speed.
● There is a time window specified by the rising edge
hold-off time t
during which glitches are ignored,
REH
even if they extend below the V - V
thresh-
TH
HY
old (Figure 7, Case B, t < t
). Deep voltage
GL
REH
drops or glitches that appear late after crossing the
threshold and extend beyond the t window
V
TH
REH
cannot be filtered out and are taken as the beginning
of a new time slot (Figure 7, Case C, t ≥ t ).
GL
REH
t
REH
t
REH
V
PUP
V
TH
V
HY
CASE A
CASE B
CASE C
0V
t
t
GL
GL
Figure 7. Noise Suppression Scheme
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS28E50Q+T
-40°C to +85°C
6 TDFN (2.5k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Maxim Integrated
│ 16
www.maximintegrated.com
DS28E50
DeepCover Secure SHA-3 Authenticator
with ChipDNA PUF Protection
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
6/18
Initial release
Added Blockwise Write Memory parameter to Electrical Characteristics table
—
9/18
5
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2018 Maxim Integrated Products, Inc.
│ 17
相关型号：
©2020 ICPDF网 联系我们和版权申明