DS4424N+TR [MAXIM]
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC; 双/四通道， I²C ， 7位可吸入/源出电流DAC
| 型号： | DS4424N+TR |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC |
| 文件： | 总11页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4744; Rev 1; 7/09
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
/DS24
General Description
Features
♦ Two (DS4422) or Four (DS4424) Current DACs
2
The DS4422 and DS4424 contain two or four I C pro-
grammable current DACs that are each capable of
sinking and sourcing current up to 200µA. Each DAC
output has 127 sink and 127 source settings that are
♦ Full-Scale Current 50µA to 200µA
♦ Full-Scale Range for Each DAC Determined by
2
programmed using the I C interface. The current DAC
External Resistors
outputs power up in a high-impedance state.
♦ 127 Settings Each for Sink and Source Modes
2
♦ I C-Compatible Serial Interface
Applications
♦ Two Address Pins Allow Four Devices on Same
Power-Supply Adjustment
Power-Supply Margining
2
I C Bus
♦ Low Cost
Adjustable Current Sink or Source
♦ Small Package (14-Pin, 3mm x 3mm TDFN)
♦ -40°C to +85°C Temperature Range
♦ 2.7V to 5.5V Operating Range
Ordering Information
PIN-
PART
OUTPUTS TEMP RANGE
PACKAGE
DS4422N+
2
2
4
4
-40°C to +85°C 14 TDFN-EP
-40°C to +85°C 14 TDFN-EP
-40°C to +85°C 14 TDFN-EP
-40°C to +85°C 14 TDFN-EP
DS4422N+T&R
DS4424N+
Pin Configuration appears at end of data sheet.
DS4424N+T&R
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
EP = Exposed pad.
Typical Operating Circuit
V
CC
V
OUT0
V
OUT1
OUT
OUT
R
PU
R
PU
V
CC
SDA
SCL
A1
DC-DC
CONVERTER
DC-DC
CONVERTER
R
0A
R
1A
FB
FB
OUT0
OUT1
DS4422/
DS4424
A0
R
0B
R
1B
GND
FS0
FS1
R
FS0
R
FS1
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V , SDA, and SCL
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature ...............................Refer to the IPC/JEDEC
J-STD-020 Specification.
CC
Relative to Ground.............................................-0.5V to +6.0V
Voltage Range on A0, A1, FS0, FS1, FS2, FS3,
OUT0, OUT1, OUT2, and OUT3 Relative to
Ground ................-0.5V to (V
+ 0.5V) (Not to exceed 6.0V.)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.7
TYP
MAX
UNITS
/DS24
Supply Voltage
V
(Note 1)
(Note 2)
5.5
V
V
V
CC
Input Logic 1 (SDA, SCL, A0, A1)
Input Logic 0 (SDA, SCL, A0, A1)
V
0.7 x V
-0.3
V
+ 0.3
CC
IH
CC
V
0.3 x V
CC
IL
R
, R
FS0 FS1
,
Full-Scale Resistor Values
40
160
kꢀ
R
, R
FS2 FS3
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
DS4422
MIN
TYP
MAX
250
250
1
UNITS
V
= 5.5V
CC
Supply Current
I
μA
CC
(Note 3)
DS4424
Input Leakage (SDA, SCL)
Output Leakage (SDA)
I
V
CC
= 5.5V
μA
μA
IL
I
L
1
V
V
= 0.4V
= 0.6V
3
6
OL
OL
Output Current Low (SDA)
I
mA
OL
RFS Voltage
V
RFS
0.976
V
I/O Capacitance
C
I/O
10
pF
OUTPUT CURRENT SOURCE CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage for Sinking Current
V
(Note 4)
(Note 4)
0.5
3.5
V
OUT:SINK
Output Voltage for Sourcing
Current
V
CC
-
V
0
V
OUT:SOURCE
0.75
200
-50
Full-Scale Sink Output Current
Full-Scale Source Output Current
I
(Notes 1, 4)
(Notes 1, 4)
50
μA
μA
OUT:SINK
I
-200
OUT:SOURCE
Output Current Full-Scale
Accuracy
+25°C, V = 3.3V; using 0.1% R
CC FS
I
6
%
OUT:FS
OUT:TC
resistor (Note 2), V
= V
= 1.2V
OUT1
OUT0
Output Current Temperature
Coefficient
I
(Note 5)
75
ppm/°C
2
_______________________________________________________________________________________
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
/DS24
OUTPUT CURRENT SOURCE CHARACTERISTICS (continued)
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.32
0.42
0.16
0.16
MAX
UNITS
DC source
DC sink
Output Current Variation Due to
Power-Supply Change
%/V
DC source, V
measure at 1.2V
OUT
Output Current Variation Due to
Output-Voltage Change
%/V
μA
DC sink, V
measure at 1.2V
OUT
Output Leakage Current at Zero
Current Setting
I
-1
+1
ZERO
Output Current Differential
Linearity
DNL
INL
(Notes 6, 7)
-0.5
-1
+0.5
+1
LSB
LSB
Output Current Integral Linearity
(Notes 7, 8)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 9)
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
μs
μs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
μs
μs
μs
ns
μs
ns
ns
μs
LOW
t
HIGH
t
t
t
0
0.9
DH:DAT
SU:DAT
SU:STA
Data Setup Time
100
START Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Setup Time
0.6
t
(Note 10)
(Note 10)
20 + 0.1C
20 + 0.1C
0.6
300
300
R
B
t
F
B
t
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 10)
400
pF
B
Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Input resistors (R ) must be between the speciifed values to ensure the device meets its accuracy and linearity specifications.
FS
Note 3: Supply current specified with all outputs set to zero current setting. A0 and A1 are connected to GND. SDA and SCL are con-
nected to V . Excludes current through R resistors (I
). Total current including I
is I + (2 x I
).
RFS
CC
FS
RFS
RFS
CC
Note 4: The output-voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 5: Temperature drift excludes drift caused by external resistor.
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 127.
Note 7: Guaranteed by design.
Note 8: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
2
Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I C standard-mode timing.
Note 10: C —total capacitance of one bus line in pF.
B
_______________________________________________________________________________________
3
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
VOLTCO (SOURCE)
-150
-175
-200
-225
-250
250
250
200
150
100
50
40kΩ LOAD ON FS0, FS1, FS2, AND FS3
V
= 5.0V
CC
200
150
V
CC
= 3.3V
V
= 2.7V
CC
100
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0, FS1, FS2,
OR FS3
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0, FS1, FS2,
OR FS3
/DS24
50
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-20
0
20
40
60
80
V
OUT
(V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE COEFFICIENT
vs. SETTING (SOURCE)
TEMPERATURE COEFFICIENT
vs. SETTING (SINK)
VOLTCO (SINK)
250
225
200
175
150
200
150
100
50
50
0
FOR THE 50μA TO 200μA CURRENT SOURCE
RANGE
40kΩ LOAD ON FS0, FS1, FS2, AND FS3
+25°C TO -40°C
-50
+25°C TO -40°C
+25°C TO +85°C
+25°C TO +85°C
-100
-150
-200
-250
0
-50
-100
FOR THE 50μA TO 200μA CURRENT SINK
RANGE
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
25
50
75
100
125
0
25
50
75
100
125
V
OUT
(V)
SETTING (DEC)
SETTING (DEC)
INTEGRAL LINEARITY
DIFFERENTIAL LINEARITY
1.00
0.75
0.50
0.25
0
1.0
0.8
FOR THE 50μA TO 200μA CURRENT SOURCE
AND SINK RANGE
FOR THE 50μA TO 200μA CURRENT SOURCE
AND SINK RANGE
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.25
-0.50
-0.75
-1.00
0
25
50
75
100
125
0
25
50
75
100
125
SETTING (DEC)
SETTING (DEC)
4
_______________________________________________________________________________________
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
/DS24
Pin Description
PIN
NAME
FUNCTION
I C Serial Data. Input/output for I C data.
DS4424
DS4422
2
2
1
2
1
2
SDA
SCL
2
2
I C Serial Clock. Input for I C clock.
Ground
3
3
GND
FS3
4
—
—
6
Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale
current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (The DS4422 has
only two inputs: FS0 and FS1.)
5
FS2
6
FS1
7
7
FS0
8
8
OUT0
OUT1
OUT2
OUT3
2
10
12
14
10
—
—
Current Output. Sinks or sources the current determined by the I C interface and the
resistance connected to FSx. (The DS4422 has only two outputs: OUT0 and OUT1.)
2
Address Select Inputs. Determines the I C slave address by connecting V or GND.
CC
9, 11
13
9, 11
13
A0, A1
See the Detailed Description section for the available device addresses.
V
CC
Power Supply
4, 5, 12,
14
—
N.C.
EP
No Connection
—
—
Exposed Pad. Connect to GND or leave unconnected.
Block Diagram
SDA SCL A1 A0
V
CC
2
I C-COMPATIBLE
DS4422/DS4424
SERIAL INTERFACE
V
CC
FBh
F8h
F9h
FAh
SOURCE OR
SINK MODE
127 POSITIONS
EACH FOR SINK
AND SOURCE
MODE
CURRENT
DAC3
CURRENT
DAC0
CURRENT
DAC1
CURRENT
DAC2
GND
FS0
FS1
FS2
FS3
OUT0
OUT1
OUT2
OUT3
R
R
FS1
R
FS2
R
FS3
FS0
DS4424 ONLY
_______________________________________________________________________________________
5
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
2
I C Slave Address
Detailed Description
2
The DS4422/DS4424 respond to one of four I C slave
2
The DS4422/DS4424 contain two or four I C adjustable
addresses determined by the two address inputs, A0
and A1. The address inputs should be connected to
current sources that are each capable of sinking and
sourcing current. Each output (OUT0, OUT1, OUT2, and
OUT3) has 127 sink and 127 source settings that can be
either V
or ground. Table 1 lists the slave addresses
CC
determined by the address input combinations.
Table 1. Slave Addresses
SLAVE ADDRESS
2
controlled by the I C interface. The full-scale ranges
and corresponding step sizes of the outputs are deter-
mined by external resistors, connected to pins FS0, FS1,
FS2, and FS3, that can adjust the output current over a
4:1 range. Pins OUT2, OUT3, FS2, and FS3 are only
available on the DS4424.
A1
A0
(HEX)
GND
GND
GND
20h
60h
A0h
E0h
The formula to determine R (connected to the FSx
FS
pins) to attain the desired full-scale current range is:
V
CC
V
GND
CC
CC
Equation 1:
V
V
CC
/DS24
V
16 × I
RFS
R
=
× 127
FS
FS
Memory Organization
To control the DS4422/DS4424’s current sources, write
to the memory addresses listed in Table 2.
Where I is the desired full-scale current value, V
is
FS
RFS
the R voltage (see the DC Electrical Characteristics
FS
table), and R is the external resistor value.
FS
Table 2. Memory Addresses
To calculate the output current value (I
) based on the
OUT
corresponding DAC value (see Table 1 for corresponding
memory addresses), use equation 2.
MEMORY ADDRESS
CURRENT SOURCE
(HEX)
Equation 2:
F8h
OUT0
OUT1
OUT2*
OUT3*
F9h
FAh*
DAC Value(dec)
I
=
× I
FS
OUT
127
FBh*
On power-up the DS4422/DS4424 output zero current.
This is done to prevent them from sinking or sourcing an
incorrect amount of current before the system host con-
troller has had a chance to modify the device’s setting.
*Only for DS4424.
The format of each output control register is given by:
As a source for biasing instrumentation or other circuits,
the DS4422/DS4424 provide a simple and inexpensive
MSB
LSB
2
S
D
D
D
D
D
D
D
0
6
5
4
3
2
1
current source with an I C interface for control. The
adjustable full-scale range allows the application to get
the most out of its 7-bit sink or source resolution.
Where:
When used in adjustable power-supply applications
(see Typical Operating Circuit), the DS4422/DS4424 do
not affect the initial power-up voltage of the supply
because they default to providing zero output current on
power-up. As the devices source or sink current into the
feedback-voltage node, they change the amount of out-
put voltage required by the regulator to reach its steady-
POWER-ON
DEFAULT
BIT NAME
FUNCTION
Determines if DAC sources or
sinks current. For sink
S = 0; for source S = 1.
Sign
Bit
S
0b
7-Bit Data Controlling DAC
Output. Setting 0000000b
outputs zero current regardless
of the state of the sign bit.
state operating point. Using the external resistor, R , to
FS
set the output current range, the DS4422/DS4424 pro-
vide some flexibility for adjusting the impedances of the
feedback network or the range over which the power
supply can be controlled or margined.
D
Data
0000000b
X
6
_______________________________________________________________________________________
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
/DS24
Example: R
= 80kΩ and register 0xF8h is written to
STOP Condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition. See Figure 1 for applicable timing.
FS0
a value of 0xAAh. Calculate the output current.
I
FS
= (0.976V/80kΩ) x (127/16) = 96.838µA
The MSB of the output register is 1, so the output is
sourcing the value corresponding to position 2Ah (42
decimal). The magnitude of the output current is equal to:
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTs are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition. See Figure 1 for applicable timing.
96.838µA x (42/127) = 32.025µA
2
I C Serial Interface Description
2
I C Definitions
The following terminology is commonly used to describe
2
I C data transfers:
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL, plus the
setup and hold time requirements (Figure 1). Data is
shifted into the device during the rising edge of the SCL.
2
I C Slave Address: The slave address of the
DS4422/DS4424 is determined by the state of the A0
and A1 pins (see Table 1).
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Bit Read: At the end of a write operation, the master must
release the SDA bus line for the proper amount of setup
time (Figure 1) before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data bit
is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock puls-
es, including when it is reading bits from the slave.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
ninth bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmit-
ting a zero during the ninth bit. A device performs a
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 1 for
applicable timing.
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCED TO V
AND V
.
IL(MAX)
IH(MIN)
2
Figure 1. I C Timing Diagram
_______________________________________________________________________________________
7
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
2
TYPICAL I C WRITE TRANSACTION
MSB
LSB
R/W
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
A1 A0
1
0
0
0
0
READ/
WRITE
REGISTER/MEMORY ADDRESS
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
SLAVE
ADDRESS*
DATA
2
EXAMPLE I C TRANSACTIONS (WHEN A0 AND A1 ARE GROUNDED)
20h
F9h
A) SINGLE BYTE WRITE
-WRITE REGISTER
F9h TO 00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
0 0 1 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1
START
START
STOP
20h
F8h
21h
DATA
B) SINGLE BYTE READ
-READ REGISTER F8h
MASTER
NACK
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 0
STOP
1 1 1 1 1 0 0 0
/DS24
2
Figure 2. I C Communication Examples
NACK by transmitting a one during the ninth bit. Timing
for the ACK and NACK is identical to all other bit writes
(Figure 2). An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
state of the A0 and A1 address pins. Table 1 describes
the addresses corresponding to the state of A0 and A1.
When the R/W bit is 0 (such as in A0h), the master is
indicating that it will write data to the slave. If R/W = 1
(A1h in this case), the master is indicating that it wants
to read from the slave. If an incorrect slave address is
written, the DS4422/DS4424 assume the master is com-
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most significant
bit first) plus a 1-bit acknowledgement from the slave to
the master. The 8 bits transmitted by the master are
done according to the bit-write definition, and the
acknowledgement is read using the bit-read definition.
2
municating with another I C device and ignore the
communication until the next START condition is sent.
2
Memory Address: During an I C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit-read definition above, and the master transmits an
ACK using the bit write definition to receive additional
data bytes. The master must NACK the last byte read to
terminated communication so the slave will return con-
trol of SDA to the master.
2
I C Communication
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and gener-
ate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
2
Slave Address Byte: Each slave on the I C bus
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
responds to a slave address byte sent immediately fol-
lowing a START condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit. The
DS4422/DS4424 slave address is determined by the
8
_______________________________________________________________________________________
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
/DS24
V
CC
V
OUT
* = 2.0V
OUT
FB
4.7kΩ
4.7kΩ
V
CC
SDA
SCL
A1
DC-DC
CONVERTER
I
I
0A
R
= 4.00kΩ
= 2.67kΩ
0A
OUT0
DS4422/
DS4424
V
* = 0.8V
FB
A0
R
0B
GND
0B
FS0
R
I
OUT0
= 80kΩ
FS0
*V
AND V VALUES ARE DETERMINED BY THE DC-DC CONVERTER AND SHOULD NOT BE CONFUSED WITH V
AND V OF THE DS4422/DS4424.
OUT RFS
OUT
FB
Figure 3. Example Application Circuit
And:
Applications Information
V
− V
FB
OUT
R
Example Calculations
for an Adjustable Power Supply
I
=
R0A
0A
In this example, the Typical Operating Circuit is used
as a base to create Figure 3, a DC-DC output voltage
of 2.0V with 20ꢀ margin. The adjustable power sup-
To create a 20ꢀ margin in the supply voltage, the value
of V
is set to 2.4V. With these values in place, R
OUT
0B
is calculated to be 2.67kΩ, and R is calculated to be
0A
ply has a DC-DC converter output voltage, V
, of
OUT
4.00kΩ. The current DAC in this configuration allows
the output voltage to be moved linearly from 1.6V to
2.4V using 127 settings. This corresponds to a resolu-
tion of 6.3mV/step.
2.0V and a DC-DC converter feedback voltage, V , of
FB
and R
0.8V. To determine the relationship of R
start with the equation:
,
0B
0A
R
0B
R
V
=
× V
OUT
FB
V
CC
Decoupling
+
R
0A
0B
To achieve the best results when using the DS4422/
DS4424, decouple the power supply with a 0.01µF or
0.1µF capacitor. Use a high-quality ceramic surface-
mount capacitor if possible. Surface-mount compo-
nents minimize lead inductance, which improves
performance, and ceramic capacitors tend to have
adequate high-frequency response for decoupling
applications.
Substituting V = 0.8V and V
= 2.0V, the relation-
FB
OUT
ship between R and R is determined to be:
0A
0B
R
≈ 1.5 x R
0A
0B
I
is chosen to be 100µA (midrange source/sink
OUT0
current for the DS4422/DS4424). Summing the currents
into the feedback node produces the following:
I
= I
- I
OUT0
R0B R0A
Power Rail Considerations
Where:
Given that the absolute maximum rating for the OUT
pins is V
+ 0.5V, it is recommended that the DS4424
power rail be brought up before or at the same time as
the power rail of the source it is controlling.
V
R
CC
FB
I
=
R0B
0B
_______________________________________________________________________________________
9
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
Pin Configuration
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
TOP VIEW
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
14 OUT3 (N.C.)
SDA
1
2
3
4
5
6
7
14 TDFN-EP
T1433+2
21-0137
13
12 OUT2 (N.C.)
11
10 OUT1
SCL
GND
V
CC
FS3 (N.C.)
FS2 (N.C.)
FS1
A1
DS4422/
DS4424
9
8
A0
*EP
FS0
OUT0
/DS24
( ) INDICATES DS4422 ONLY.
*EXPOSED PAD
10 ______________________________________________________________________________________
2
Two-/Four-Channel, I C, 7-Bit Sink/Source
Current DAC
/DS24
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
3/08
Initial release.
Added the Power Rail Considerations section.
—
9
7/09
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
DS4432U+T&R
D/A Converter, 1 Func, Serial Input Loading, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8
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