MAX1003CAX-T [MAXIM]
ADC, Flash Method, 6-Bit, 2 Func, 1 Channel, Parallel, 6 Bits Access, PDSO36, 0.300 INCH, 0.80 MM PITCH, SSOP-36;
| 型号： | MAX1003CAX-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Flash Method, 6-Bit, 2 Func, 1 Channel, Parallel, 6 Bits Access, PDSO36, 0.300 INCH, 0.80 MM PITCH, SSOP-36 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1236; Rev 0; 6/97
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
MAX103
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Two Matched 6-Bit ADCs
The MAX1003 is a dual, 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The dual parallel ADCs are
designed to convert in-phase (I) and quadrature (Q)
analog signals into two 6-bit, offset-binary-coded digital
outputs at sampling rates up to 90Msps. The ability to
directly interface with baseband I and Q signals makes
the MAX1003 ideal for use in direct-broadcast satellite,
VSAT, and QAM16 demodulation applications.
♦ High Sampling Rate: 90Msps per ADC
♦ Low Power Dissipation: 350mW
♦ Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
♦ ±1/4LSB INL and DNL (typ)
♦ Internal Bandgap Voltage Reference
♦ Internal Oscillator with Overdrive Capability
The MAX1003 input amplifiers feature true differential
inputs, a -0.5dB analog bandwidth of 55MHz, and user-
programmable input full-scale ranges of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled input
signal, matching performance between input channels
is typically better than 0.1dB gain, 1/4LSB offset, and
0.5° phase. Dynamic performance is 5.85 effective
number of bits (ENOB) with a 20MHz analog input sig-
nal, or 5.7 ENOB with a 50MHz signal.
♦ 55MHz (-0.5dB) Bandwidth Input Amplifiers with
True Differential Inputs
♦ User-Selectable Input Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
♦ 1/4LSB Channel-to-Channel Offset Matching (typ)
♦ 0.1dB Gain and 0.5° Phase Matching (typ)
♦ Single-Ended or Differential Input Drive
The MAX1003 operates with +5V analog and +3.3V digi-
tal supplies for easy interfacing to +3.3V-logic-compati-
ble digital signal processors and microprocessors. It
comes in a 36-pin SSOP package.
♦ Flexible, 3.3V, CMOS-Compatible Digital Outputs
________________________Ap p lic a t io n s
Direct Broadcast Satellite (DBS) Receivers
VSAT Receivers
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
PIN-PACKAGE
Wide Local Area Networks (WLANs)
Cable Television Set-Top Boxes
MAX1003CAX
0°C to +70°C
36 SSOP
Pin Configuration appears at end of data sheet.
_________________________________________________________Fu n c t io n a l Dia g ra m
IOCC+
IOCC-
IIN+
IIN-
INPUT
AMP
I
6
6
ADC
I
VREF
DI0–DI5
DCLK
DATA
BUFFER
I
OFFSET
CORREC-
TION I
CLOCK
OUT
TNK+
TNK-
GAIN
BANDGAP
REFERENCE
CLOCK
DRIVER
OFFSET
CORREC-
TION Q
MAX1003
QIN+
QIN-
VREF
ADC
6
DATA
BUFFER
Q
INPUT
AMP
Q
6
DQ0–DQ5
Q
QOCC+
QOCC-
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ............................................................-0.3V to 6.5V
Continuous Power Dissipation (T = +70°C)
A
V
to OGND ........................................................-0.3V to 6.5V
SSOP (derate 11.8mW/°C above +70°C) ...................941mW
Operating Temperature Range ...............................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
CCO
GND to OGND ........................................................-0.3V to 0.3V
Digital and Clock Output Pins to OGND...-0.3V to V (10sec)
All Other Pins to GND...............................................-0.3V to V
CCO
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX103
DC ELECTRICAL CHARACTERISTICS
(V = +5V ±5%, V
= 3.3V ±300mV, T = T
to T
, unless otherwise noted.)
CC
CCO
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
RES
INL
6
Bits
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
-0.5
±0.25
±0.25
125
0.5
0.5
DNL
No missing codes over temperature
-0.5
V
FSH
GAIN = V (high gain)
CC
118.75
237.5
475
131.25
262.5
525
Full-Scale Input Range
V
FSM
GAIN = open (mid gain)
GAIN = GND (low gain)
250
mVp-p
V
FSL
500
INVERTING AND NONINVERTING ANALOG INPUTS
Input Open-Circuit Voltage
Input Resistance
V
2.25
13
2.35
20
3
2.45
29
5
V
AOC
R
C
kΩ
pF
IN
IN
Input Capacitance
Guaranteed by design
Other analog input driven with external source
(Note 2)
Common-Mode Voltage Range
V
1.75
4.8
2.75
V
CM
OSCILLATOR INPUTS
Oscillator Input Resistance
R
Other oscillator input tied to V + 0.3V
8
12.1
kΩ
OSC
CC
DIGITAL OUTPUTS (DI0–DI5, DQ0–DQ5)
Digital Outputs Logic-High
Voltage
V
I
= 50µA
0.7V
CCO
V
V
OH
SOURCE
Digital Outputs Logic-Low
Voltage
V
OL
I
= 400µA
0.5
SINK
POWER SUPPLY
Supply Current
I
63
104
-40
mA
dB
CC
Power-Supply Rejection Ratio
PSRR
V
CC
= 4.75V to 5.25V (Note 3)
-75
20MHz, full-scale I and Q analog inputs,
= 15pF (Note 4)
Digital Outputs Supply Current
Power Dissipation
I
21
mA
CCO
C
L
PD
350
mW
2
_______________________________________________________________________________________
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
MAX103
AC ELECTRICAL CHARACTERISTICS
(V = +5V ±5%, V
= 3.3V ±300mV, T = +25°C, unless otherwise noted.)
CC
CCO
A
PARAMETER
SYMBOL
CONDITIONS
MIN
= 20MHz sine, amplitude -1dB below
INQ
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), V = V
INI
full scale, unless otherwise noted.)
Maximum Sample Rate
f
90
Msps
MAX
Analog Input -0.5dB Bandwidth
BW
GAIN = GND, open, V
55
MHz
CC
GAIN = open (mid gain)
5.6
5.85
ENOB
M
GAIN = open (mid gain), f = 50MHz,
IN
-1dB below full scale
5.7
Effective Number of Bits
Bits
ENOB
GAIN = V (high gain)
CC
5.8
H
ENOB
GAIN = GND (low gain)
5.85
L
Signal-to-Noise plus Distortion
Ratio
SINAD
OFF
GAIN = open (mid gain)
35.5
37
dB
I channel
-0.5
-0.5
0.5
0.5
Input Offset (Note 5)
LSB
Q channel
Crosstalk Between ADCs
XTLK
OMM
-55
dB
Offset Mismatch Between ADCs
(Note 5)
-0.5
-0.2
-2
±0.25
0.5
0.2
2
LSB
Amplitude Match Between
ADCs
AM
PM
±0.1
±0.5
dB
Phase Match Between ADCs
degrees
TIMING CHARACTERISTICS (Data outputs: R = 1MΩ, C = 15pF)
L
L
Clock to Data Propagation
Delay
t
(Note 6)
3.6
ns
PD
Data Valid Skew
Input to DCLK Delay
Aperture Delay
t
(Note 6)
1.5
5.3
7.5
ns
ns
ns
SKEW
t
TNK+ to DCLK (Note 6)
Figure 8
DCLK
t
AD
clock
cycle
Pipeline Delay
PD
Figure 8
1
Note 1: Best-fit straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3: PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in V
supply voltage,
CC
expressed in decibels.
Note 4: The current in the V
supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
CCO
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2 and 3).
Note 6: t and t
are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
PD
SKEW
data bit. t
DCLK
itive load on the outputs is 15pF.
_______________________________________________________________________________________
3
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V ±5%, V
= 3.3V ±300mV, f
= 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, T = +25°C, unless
A
CC
CCO
CLK
otherwise noted.)
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
EFFECTIVE NUMBER OF BITS
vs. SAMPLING/CLOCK FREQUENCY
ANALOG INPUT BANDWIDTH
6.0
5.8
6.0
5.9
5.8
5.7
5.6
5.5
0
-0.2
-0.4
-0.6
-0.8
MAX103
5.6
5.4
5.2
5.0
f
= 90Msps
f = 20MHz
IN
CLK
-1.0
10
100
1
10
100
1
10
CLOCK FREQUENCY (MHz)
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
OSCILLATOR OPEN-LOOP PHASE NOISE
vs. FREQUENCY OFFSET
FFT PLOT
-50
-70
0
f
= 19.9512MHz
= 90.000MHz
IN
f
CLK
1024 POINTS
AC COUPLED
SINGLE ENDED
AVERAGED
-20
-90
-110
-130
-40
-60
1k
10k
100k
1M
0
9
18
27
36
45
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY (MHz)
DIFFERENTIAL NONLINEARITY
vs. CODE
INTEGRAL NONLINEARITY
vs. CODE
0.50
0.25
0
0.50
0.25
0
-0.25
-0.50
-0.25
-0.50
0
10
20
30
40
50
60 64
0
10
20
30
40
50
60 64
CODE
CODE
4
_______________________________________________________________________________________
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
MAX103
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1
GAIN
Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).
Positive I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
2
3
IOCC+
IOCC-
Negative I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
4
5
6
IIN+
IIN-
I-Channel Noninverting Analog Input
I-Channel Inverting Analog Input
V
CC
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 7).
7, 11, 12,
18, 19
GND
Analog Ground
8
V
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 11).
Positive Oscillator/Clock Input
CC
9
TNK+
TNK-
10
13
14
15
Negative Oscillator/Clock Input
V
CC
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 12).
Q-Channel Inverting Analog Input
QIN-
QIN+
Q-Channel Noninverting Analog Input
Negative Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
16
17
QOCC-
Positive Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
QOCC+
20–25
26, 28
27
DQ5–DQ0
Q-Channel Digital Outputs 0–5. DQ5 is the most significant bit (MSB).
Digital Output Supply, +3.3V ±300mV. Bypass each with a 47pF capacitor to OGND (pin 27).
Digital Output Ground
V
CCO
OGND
DCLK
29
Digital Clock Output. Frames the output data.
30–35
36
DI0–DI5
I-Channel Digital Outputs 0–5. DI5 is the most significant bit (MSB).
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 19).
V
CC
P ro g ra m m a b le In p u t Am p lifie rs
_______________De t a ile d De s c rip t io n
The MAX1003 has two (I and Q) programmable-gain
input amplifiers with a -0.5dB bandwidth of 55MHz and
true differential inputs. To maximize performance in
high-speed systems, each amplifier has less than 5pF
of input capacitance. The input amplifier gain is pro-
grammed, via the GAIN pin, to provide three possible
input full-scale ranges (FSRs) as shown in Table 1.
Co n ve rt e r Op e ra t io n
The MAX1003 contains two 6-bit analog-to-digital con-
verters (ADCs), a buffered voltage reference, and oscil-
la tor c irc uitry. The ADCs us e a fla s h c onve rs ion
technique to convert an analog input signal into a 6-bit
parallel digital output code. The MAX1003’s unique
design includes 63 fully differential comparators and a
proprietary encoding scheme that ensures no more
than 1LSB dynamic encoding error. The control logic
inte rfa c e s e a s ily to mos t d ig ita l s ig na l p roc e s s ors
(DSPs) and microprocessors (µPs) with +3.3V CMOS-
c omp a tib le log ic inte rfa c e s . Fig ure 1 s hows the
MAX1003 in a typical application.
Table 1. Input Amplifier Programming
INPUT FULL-SCALE RANGE
GAIN
(mVp-p)
GND
500
250
125
Open
V
CC
_______________________________________________________________________________________
5
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
Single-ended and differential AC-coupled input circuits
are shown in Figures 2 and 3. Each of the amplifier
inputs is internally biased to a 2.35V reference through
a 20kΩ resistor, eliminating external DC bias circuits. A
series 0.1µF capacitor is required at each amplifier
input for AC-coupled signals.
compensation capacitor is required to set the dominant
p ole of the offs e t-c orre c tion a mp lifie r’s fre q ue nc y
response (Figures 2 and 3). The compensation capaci-
tor will determine the low-frequency corner of the ana-
log input response according to the following formula:
f = 1 / (0.1 x C)
c
Whe n op e ra ting with AC-c oup le d inp uts , the inp ut
amplifiers’ DC offset voltage is nulled to within ±1/2LSB
by an on-chip offset-correction amplifier. An external
where C is the value of the compensation capacitor in
µF, and f is the corner frequency in Hz.
c
MAX103
LNB
75Ω CABLE
950MHz TO 2150MHz
F-CONNECTOR
INPUT
KU BAND
OR
VARACTOR-TUNED
PRESELECTION FILTER
FROM TANK VOLTAGE
V
CC
AGC
AGC
RFIN
RFIN
DATA
BUFFER
IIN
6 BITS
6 BITS
IOUT
CLK IN
0
90Msps
90
MAX2102
DSP
DATA
BUFFER
QIN
EXTERNAL
VCO
QOUT
LO
LO
DIV
ADC CLOCK
MAX1003
SYNTHESIZER
MODCTL FIN CAR
TANK
OR
MOD GND
TANK
TSA5055
or EQUIV.
Figure 1. Commercial Satellite Receiver System
_______________________________________________________________________________________
6
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
MAX103
0.22µF
0.22µF
_OCC+
_OCC-
_OCC+
_OCC-
OFFSET
CORREC-
TION
OFFSET
CORREC-
TION
0.1µF
0.1µF
_IN+
_IN+
INPUT
AMP
INPUT
AMP
V
SOURCE
V
SOURCE
_IN-
20k
_IN-
20k
0.1µF
0.1µF
MAX1003
MAX1003
20k
20k
2.35V INTERNAL REFERENCE
2.35V INTERNAL REFERENCE
Figure 2. Single-Ended AC-Coupled Input
Figure 3. Differential AC-Coupled Input
OFFSET CORRECTION DISABLED
OFFSET CORRECTION DISABLED
_OCC+
_OCC-
_OCC+
_OCC-
OFFSET
CORREC-
TION
OFFSET
CORREC-
TION
_IN+
_IN+
INPUT
AMP
INPUT
AMP
V
SOURCE
V
SOURCE
_IN-
20k
_IN-
20k
MAX1003
MAX1003
20k
20k
DIFFERENTIAL SOURCE
WITH COMMON MODE
FROM 1.75V TO 2.75V.
V
REF
1.75V TO 2.75V
2.35V INTERNAL REFERENCE
2.35V INTERNAL REFERENCE
Figure 4. Single-Ended DC-Coupled Input
Figure 5. Differential DC-Coupled Input
For applications where a DC component of the input
signal is present, Figures 4 and 5 show single-ended
and differential DC-coupled input circuits. The ampli-
fiers’ input common-mode voltage range extends from
1.75V to 2.75V. To prevent attenuation of the input
signal’s DC component in this mode, disable the offset-
c orre c tion a mp lifie r b y g round ing the _OCC+ a nd
_OCC- pins for the I and Q blocks (Figures 4 and 5).
ADCs
The I and Q ADC blocks receive the analog signals
from the respective I and Q input amplifiers. The ADCs
use flash conversion with 63 fully differential compara-
tors to digitize the analog input signal into a 6-bit output
in offset binary format.
_______________________________________________________________________________________
7
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
The MAX1003 features a proprietary encoding scheme
Os c illa t o r Circ u it
The MAX1003 includes a differential oscillator, which is
controlled by an external parallel resonant (tank) net-
work as shown in Figure 6. Alternatively, the oscillator
may be overdriven with an external clock source as
shown in Figure 7.
that ensures no more than 1LSB dynamic encoding
e rror. Dyna mic e nc od ing e rrors re s ulting from
metastable states may occur when the analog input
voltage, at the time the sample is taken, falls close to
the decision point for any one of the input comparators.
The resulting output code for typical converters can be
incorrect, including false full- or zero-scale outputs. The
MAX1003’s unique design reduces the magnitude of
this type of error to 1LSB.
Internal Clock Operation (Tank)
If the tank circuit is used, the resonant inductor should
have a sufficiently high Q and a self-resonant frequen-
cy (SRF) of at least twice the intended oscillator fre-
q ue nc y. Coilc ra ft’s 1008HS-221, with a n SRF of
700MHz and a Q of 45, works well for this application.
Generate different clock frequency ranges by adjusting
varactor and tank elements.
MAX103
In t e rn a l Vo lt a g e Re fe re n c e
An internal buffered bandgap reference is included on
the MAX1003 to drive the ADCs’ reference ladders. The
on-chip reference and buffer eliminate any external
(high-impedance) connections to the reference ladder,
minimizing the potential for noise coupling from exter-
nal circuitry while ensuring that the voltage reference,
input amplifier, and reference ladder track well with
variations of temperature and power supplies.
An internal clock-driver buffer is included to provide
sharp clock edges to the internal flash comparators.
The buffer ensures that the comparators are simultane-
ously clocked, maximizing the ADCs’ effective number
of bits (ENOB) performance.
47k
V
CLK
= 300mV TO 1.25V
p-p p-p
47pF
TNK+
0.1µF
50Ω
10k
Z = 50Ω
0
CLK
DRIVER
220nH
5pF
V
TUNE
TNK+
TNK-
50Ω
V
CLK
TNK-
CLK
DRIVER
47pF
MAX1003
0.1µF
50Ω
47k
MAX1003
V
TUNE
= 0V TO 8V
f
= 70MHz TO 110MHz
OSC
VARACTOR DIODE PAIR IS M/A-COM MA4ST079CK-287 (SOT23 PACKAGE)
INDUCTOR COILCRAFT 1008HS-221.
Figure 6. Tank Resonator Oscillator
Figure 7. External Clock Drive Circuit
8
_______________________________________________________________________________________
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
MAX103
N
N + 1
ANALOG
INPUT
N + 2
t
AD
50%
TNK+
(INPUT CLOCK)
t
DCLK
1.4V
t
PD
DCLK
t
SKEW
DATA VALID N - 1
DATA VALID N
1.4V
DATA OUT
Figure 8. MAX1003 Timing Diagram
External Clock Operation
To accommodate designs that use an external clock,
the MAX1003’s internal oscillator can be overdriven by
an external clock source as shown in Figure 7. The
external clock source should be a sinusoid to minimize
clock phase noise and jitter, which can degrade the
ADCs’ ENOB performance. AC couple the clock source
(recommended voltage level is approximately 1Vp-p) to
the oscillator inputs as shown in Figure 7.
111111
111110
111101
100001
100000
011111
011110
Ou t p u t Da t a Fo rm a t
The conversion results are output on a dual, 6-bit-wide
data bus. Data is latched into the ADC output latch fol-
lowing a pipeline delay of one clock cycle, as shown in
Figure 8. Output data is clocked out of the respective
ADC’s data output pins (D_0 through D_5) on the rising
edge of the clock output (DCLK), with a DCLK-to-data
000011
000010
000001
000000
propagation delay (t ) of 3.6ns. The MAX1003 outputs
PD
are +3.3V CMOS-logic compatible.
0
-FSR
2
FSR
2
1LSB
INPUT VOLTAGE (_IN+ TO _IN-)
Tra n s fe r Fu n c t io n
Figure 9 shows the MAX1003’s nominal transfer function.
Output coding is offset binary with 1LSB = FSR / 63.
Figure 9. Ideal Transfer Function
_______________________________________________________________________________________
9
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
__________Ap p lic a t io n s In fo rm a t io n
_____________Dyn a m ic P e rfo rm a n c e
The MAX1003 is designed with separate analog and
digital power-supply and ground connections to isolate
high-current digital noise spikes from the more sensi-
tive analog circuitry. The high-current digital output
ground (OGND) and analog ground (GND) should be
at the same DC level, connected at only one location
on the board. This will provide best noise immunity and
imp rove d c onve rs ion a c c ura c y. Us e of s e p a ra te
ground planes is strongly recommended.
Signal-to-noise and distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to all
other ADC output signals. The output spectrum is limit-
ed to frequencies above DC and below one-half the
ADC sample rate.
The the ore tic a l minimum a na log -to-d ig ita l nois e is
caused by quantization error, and results directly from
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where
N is the number of bits of resolution. Therefore, a per-
fect 6-bit ADC can do no better than 38dB.
MAX103
The entire board needs good DC bypassing for both
analog and digital supplies. Place the power-supply
bypass capacitors close to where the power is routed
onto the board, i.e., close to the connector. 10µF elec-
trolytic capacitors with low-ESR ratings are recom-
mended. For best effective bits performance, minimize
capacitive loading at the digital outputs. Keep the digi-
tal output traces as short as possible.
The FFT Plot (see Typical Operating Characteristics)
shows the result of sampling a pure 20MHz sinusoid at
a 90MHz clock rate. This FFT plot of the output shows
the output level in various spectral bands. The plot has
been averaged to reduce the quantization noise floor
and reveal the low-amplitude spurs. This emphasizes
the e xc e lle nt s p urious -fre e d yna mic ra ng e of the
MAX1003.
The MAX1003 requires a +5V ±5% power supply for
the analog supply (V ) and a +3.3V ±300mV power
CC
The effective resolution (or effective number of bits) the
ADC provides can be measured by transposing the
e q ua tion tha t c onve rts re s olution to SINAD: N =
(SINAD - 1.76) / 6.02 (s e e Typ ic a l Op e ra ting
Characteristics).
s up p ly c onne c te d to V
for the log ic outp uts .
CCO
Bypass each of the V
supply pins to its respective
CC_
GND with high-quality ceramic capacitors located as
close to the package as possible (Table 2). Consult the
e va lua tion kit ma nua l for a s ug g e s te d la yout a nd
bypassing scheme.
Table 2. Bypassing
BYPASS
SUPPLY
FUNCTION
V
/
TO
GND/
OGND
CAPACITOR
VALUE
CC
V
CCO
Analog Inputs
Oscillator/Clock
Converter
6
7
0.01µF
0.01µF
0.01µF
47pF
8
11
12
27
27
19
13
26
28
36
Digital Q-Output
Digital I-Output
Buffer
47p F
0.01µF
10 ______________________________________________________________________________________
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
MAX103
__________________P in Co n fig u ra t io n
TOP VIEW
GAIN
1
2
3
4
5
6
7
8
9
36 V
CC
IOCC+
IOCC-
IIN+
35 DI5
34 DI4
33 DI3
32 DI2
31 DI1
30 DI0
IIN-
MAX1003
V
CC
GND
V
CC
DCLK
29
28
TNK+
V
CCO
TNK- 10
GND 11
GND 12
27 OGND
26
V
CCO
25 DQ0
24 DQ1
23 DQ2
22 DQ3
21 DQ4
20 DQ5
19 GND
V
CC
13
QIN- 14
QIN+ 15
QOCC- 16
QOCC+ 17
GND 18
SSOP
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 6097
______________________________________________________________________________________ 11
Lo w -P o w e r, 9 0 Ms p s , Du a l 6 -Bit ADC
________________________________________________________P a c k a g e In fo rm a t io n
MAX103
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
©2020 ICPDF网 联系我们和版权申明