MAX11904ETP+ [MAXIM]
ADC, Successive Approximation,;
| 型号： | MAX11904ETP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 转换器 |
| 文件： | 总29页 (文件大小：750K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
General Description
Features and Benefits
● High DC/AC Accuracy Provides Better Measurement
The MAX11904 is a 20-bit, 1Msps, single-channel, fully
differential SAR ADC with internal reference buffers. The
MAX11904 provides excellent static and dynamic perfor-
mance with best-in-class power consumption that directly
scales with throughput. The device has a unipolar differ-
Quality
•
•
•
•
20-Bit Resolution with No Missing Codes
±6 LSB INL and ±0.9 LSB DNL at 20 Bits
99.2dB SNR and 99.2dB SINAD at f = 10kHz
IN
ential ±V
input range. Supplies include a 3.3V supply
REF
125dB SFDR and -123dB THD at f = 10kHz
IN
for the reference buffers, a 1.8V analog supply, a 1.8V
digital supply, and a 1.5V to 3.6V digital interface supply.
● High Sampling Rate SAR Architecture Enables Fast
Settling and Acquisition
This ADC achieves 99.2dB SNR and -123dB THD, guar-
antees 20-bit resolution with no-missing codes and 6 LSB
INL (max).
•
1Msps Throughput with No Pipeline Delay
● Integration Simplifies Design
•
•
Integrated Reference Buffers
±V Unipolar Differential Analog Input Range
The MAX11904 communicates data using a SPI-
compatible serial interface. The MAX11904 is offered in a
20-pin, 4mm x 4mm, TQFN package and is specified over
the -40°C to +85°C operating temperature range.
REF
● Scalable Ultra-Low Power Supply Reduces Power
Consumption
•
•
6.7mW at 1Msps
Applications
Scale as 6.7µW/ksps
● Test and Measurement
● Automatic Test Equipment
● Medical Instrumentation
● Process Control and Industrial Automation
● Data Acquisition Systems
● Telecommunications
● Flexible Low-Voltage Supplies Save Cost
•
•
•
1.8V Analog and Digital Core Supply
1.5V to 3.6V Digital Interface Supply
3.3V REFVDD Reference Buffer Supply
● Flexible, Industry-Standard Serial Interface and Small
Package Reduce Size
•
•
SPI-/QSPI™-/MICROWIRE®/DSP-Compatible
● Battery-Powered Equipment
20-Pin, 4mm x 4mm, TQFN Package
Ordering Information and Selector Guide appears at end of
data sheet.
Application Diagram
16-Bit to 20-Bit SAR ADC Family
1.5 TO
1.8V 1.8V 3.6V
16-BIT
18-BIT
20-BIT
3.3V
3.6V
1.6Msps
1Msps
MAX11901
MAX11900
MAX11903
MAX11902
MAX11905
MAX11904
REFVDD AVDD DVDD OVDD
DIN
10Ω
REFIN
AIN+
0 TO 3.3V
3.3V TO 0
4-WIRE
SPI
INTERFACE
SCLK
MAX11904
DOUT
2nF
C0G
CNVST
AIN-
10Ω
REF
A
D
REF REF GND GND GND
QSPI is a trademark of Motorola, Inc.
10µF
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
19-7449; Rev 1; 4/15
MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Application Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
16-Bit to 20-Bit SAR ADC Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Settling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Voltage Reference Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Conversion Result Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chip ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Single-Ended Unipolar Input to Differential Unipolar Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Single-Ended Bipolar Input to Differential Unipolar Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Layout, Grounding, and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Integral Nonlinearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Gain Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Signal-to-Noise Ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Signal-to-Noise Plus Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
TABLE OF CONTENTS (continued)
Effective Number of Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Spurious-Free Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Aperture Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Aperture Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Full-Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LIST OF FIGURES
Figure 1. Signal Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Simplified Model of Input Sampling Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. Conversion Frame, SAR Conversion, Track and Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. Ideal Transfer Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Read During Track Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Read During SAR Conversion Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Split Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. SPI Interface Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. DIN Timing for Register Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Timing Diagram for Data Out Reading After Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Mode Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Unipolar Single-Ended Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Bipolar Single-Ended Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Top Layer Sample Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LIST OF TABLES
Table 1. ADC Driver Amplifier Recommendation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2. Voltage Reference Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3. MAX11904 External Reference Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Transfer Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. DOUT Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Absolute Maximum Ratings
REFVDD, REF, REFIN, OVDD to GND ..................-0.3V to +4V
AVDD, DVDD to GND .............................................-0.3V to +2V
DGND to AGND, REFGND ..................................-0.3V to +0.3V
Continuous Power Dissipation (T = +70°C)
TQFN (derate 30.30mW/°C above +70°C).............2424.2mW
A
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
AIN+, AIN- to GND...... -0.3V to the lower of (V
+ 0.3V) and
REF
+4V or ±130mA
SCLK, DIN, DOUT, CNVST, to GND...........-0.3V to the lower of
(V + 0.3V) and +4V
OVDD
Maximum Current into Any Pin...........................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TQFN
Junction-to-Ambient Thermal Resistance (θ ).... ......33°C/W
JA
Junction-to-Case Thermal Resistance (θ ) ............... 2°C/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(f
T
= 1Msps, V
= 1.8V, V
= 1.8V, V
= 1.5V to 3.6V, V
= 3.6V, V
= 3.3V, Internal Ref Buffers On,
SAMPLE
AVDD
DVDD
OVDD
REFVDD
REF
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range (Note 3)
(AIN+) - (AIN-)
-V
+V
V
V
REF
REF
V
REF
0.1
+
Absolute Input Voltage Range
Common-Mode Input Range
AIN+, AIN- relative to AGND
-0.1
V
REF
0.1
/2 -
V
/2
REF
[(AIN+) + (AIN-)]/2
Acquisition phase
V
/2
V
REF
+ 0.1
Input Leakage Current
Input Capacitance
-1
0.001
32
+1
µA
pF
STATIC PERFORMANCE (Note 4)
Resolution
N
20
Bits
µV
Resolution
LSB
V
= 3.3V
6.3
REF
No Missing Codes
Offset Error (Note 4)
Offset Temperature Coefficient
Gain Error
20
Bits
-10
±1
+10
LSB
LSB/°C
LSB
±0.01
±20
Referred to REFIN reference input
Referred to REFIN reference input
Referred to REF pins
-175
-42
-6
+175
Gain Error Temperature
Coefficient (Note 5)
±0.2
±10
LSB/°C
LSB
Gain Error
+42
+6
Gain Error Temperature
Coefficient (Note 5)
Referred to REF pins
±0.12
±1.5
LSB/°C
LSB
Integral Nonlinearity
INL
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Electrical Characteristics (continued)
(f
= 1Msps, V
= 1.8V, V
= 1.8V, V
= 1.5V to 3.6V, V
= 3.6V, V
= 3.3V, Internal Ref Buffers On,
SAMPLE
AVDD
DVDD
OVDD
REFVDD
REF
T
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
±0.5
16
MAX
UNITS
LSB
Differential Nonlinearity
(Note 6)
DNL
-0.9
+0.9
Analog Input CMR
CMR
DC
LSB/V
LSB/V
Power-Supply Rejection
(Note 7)
PSR
PSR vs. AVDD
2
Power-Supply Rejection
(Note 7)
PSR
PSR vs. REFVDD
2
4
LSB/V
Transition Noise
LSB
RMS
EXTERNAL REFERENCE
REF Voltage Input Range
Load Current
V
2.5
2.5
3.3
350
1
3.6
V
REF
I
1Msps, V
= 3.3V
µA
nF
REF
REF
REF Input Capacitance
REFERENCE BUFFER
V
REFVDD
- 200mV
REFIN Input Voltage Range
REFIN Input Current
V
V
< (V - 200mV)
REFVDD
3
1
V
REFIN
REF
I
nA
ms
REFIN
C
C
= 10µF on REF pin,
EXT
Turn-On Settling Time
20
= 0.1µF on REFIN pin
REFIN
External Compensation
Capacitor
CEXT
REF pins
4.7
10
µF
DYNAMIC PERFORMANCE (Note 8)
Dynamic Range
Internal RefBuffer, -60dBFS input
99.4
99.2
dB
dB
Signal-to-Noise Ratio
SNR
Internal RefBuffer, f = 10kHz
98
98
IN
Internal RefBuffer, f = 10kHz,
IN
-0.1dBFs
Signal-to-Noise Plus Distortion
SINAD
99.2
dB
Spurious-Free Dynamic Range
Total Harmonic Distortion
Total Harmonic Distortion
Total Harmonic Distortion
SAMPLING DYNAMICS
Throughput
SFDR
THD
THD
THD
Internal RefBuffer, f = 10kHz
125
-123
-115
-107
dB
dB
dB
dB
IN
Internal RefBuffer, f = 10kHz
IN
Internal RefBuffer, f = 100kHz
IN
Internal RefBuffer, f = 250kHz
IN
0
1
Msps
MHz
ns
-3dB point
20
3
Full-Power Bandwidth
Acquisition Time
-0.1dB point
t
150
ACQ
Time delay from CNVST rising edge
to time at which sample is taken for
conversion
Aperture Delay
Aperture Jitter
1
3
ns
ps
RMS
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Electrical Characteristics (continued)
(f
= 1Msps, V
= 1.8V, V
= 1.8V, V
= 1.5V to 3.6V, V
= 3.6V, V
= 3.3V, Internal Ref Buffers On,
SAMPLE
AVDD
DVDD
OVDD
REFVDD
REF
T
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Analog Supply Voltage
Digital Supply Voltage
AVDD
DVDD
1.7
1.7
1.8
1.8
1.9
1.9
V
V
Reference Buffer Supply
Voltage
REFVDD
OVDD
2.7
1.5
3.3
3.6
V
Interface Supply Voltage
Analog Supply Current
Digital Supply Current
3.6
2.3
1.9
V
I
V
V
V
= 1.8V
1.75
1.5
mA
mA
AVDD
AVDD
I
= 1.8V
DVDD
DVDD
Reference Buffer Supply
Current
= 3.6V, internal buffers
REFVDD
I
I
3.3
0.2
3.55
mA
mA
REFVDD
REFVDD
enabled
Reference Buffer Supply
Current
V
REFVDD
powered down
= 3.6V, internal buffers
V
V
= 1.5V
= 3.6V
0.27
Interface Supply Current
(Note 9)
OVDD
I
mA
OVDD
1
1
1
OVDD
Shutdown Current
Shutdown Current
For AVDD, DVDD, REFVDD
For DVDD
µA
µA
V
V
= 1.8V, V
= 1.8V,
AVDD
DVDD
Power Dissipation
= 3.3V, internal reference
6.7
8.4
mW
REFVDD
buffers disabled
DIGITAL INPUTS (DIN, SCLK, CNVST)
0.7 x
Input Voltage High
Input Voltage Low
V
V
V
= 1.5V to 3.6V
= 1.5V to 3.6V
V
V
IH
OVDD
V
OVDD
0.3 x
V
IL
OVDD
V
OVDD
Input Capacitance
C
10
1
pF
µA
IN
Input Current
I
V
= 0V or V
OVDD
IN
IN
DIGITAL OUTPUTS (DOUT)
V
-
OVDD
0.4
Output Voltage High
Output Voltage Low
V
I
I
= 2mA
V
V
OH
SOURCE
V
= 2mA
SINK
0.4
OL
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Electrical Characteristics (continued)
(f
= 1Msps, V
= 1.8V, V
= 1.8V, V
= 1.5V to 3.6V, V
= 3.6V, V
= 3.3V, Internal Ref Buffers On,
SAMPLE
AVDD
DVDD
OVDD
REFVDD
REF
T
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING
DIN to SCLK Rising Edge
Setup
t1
t2
t3
4
ns
ns
ns
DIN to SCLK Rising Edge Hold
1
DOUT End-Of-Conversion
Low Time
15
DOUT to SCLK Rising
Edge Hold
t4
t5
2.5
1.5
ns
ns
DOUT to SCLK Rising
Edge Setup
100MHz SCLK
SCLK High
SCLK Period
SCLK Low
t6
t7
t8
4.5
10
ns
ns
ns
4.5
CNVST Rising Edge To SCLK
Rising Edge
t9
0
ns
ns
SCLK Rising Edge to CNVST
Rising Edge
t10
25
25
CNVST High
t11
t12
t13
ns
ns
ns
CNVST High to EOC
Conversion Period
850
1000
Note 2: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design
A
and device characterization.
Note 3: See the Analog Inputs section.
Note 4: See the Definitions section at the end of the data sheet.
Note 5: See the Definitions section at the end of the data sheet. Error contribution from the external reference not included.
Note 6: Parameter is guaranteed by design.
Note 7: Defined as the change in positive full-scale code transition caused by a ±5% variation in the supply voltage.
Note 8: Sine wave input, f = 10kHz, A = -0.1dB below full scale.
IN
IN
Note 9: C
= 10pF on DOUT. f
= 1Msps. All data is read out.
LOAD
CONV
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Typical Operating Characteristics
(V
= 1.8V, V
= 1.8V, V
= 1.8V, V
= 3.6V, f
= 1Msps, V
= 3.3V, Internal Ref Buffer On, T = T
to
MIN
AVDD
DVDD
OVDD
REFVDD
SAMPLE
REF
A
T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX
A
toc1
INL vs. TEMPERATURE
DNL vs. TEMPERATURE
toc3
toc4
6
4
MAX INL (LSB)
5
MAX DNL (LSB)
MIN DNL (LSB)
3
2
MIN INL (LSB)
4
3
2
1
1
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
TEMPERATURE (oC)
TEMPERATURE (oC)
DNL vs. AVDD SUPPLY VOLTAGE
INL vs. AVDD SUPPLY VOLTAGE
toc5
toc6
4
6
5
MAX DNL (LSB)
MIN DNL (LSB)
VREFVDD = 3.6V
VREF = 3.3V
VREFVDD = 3.6V
VREF = 3.3V
MAX INL (LSB)
MIN INL (LSB)
3
2
4
3
2
1
1
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
1.70
1.73
1.75
1.78
1.80
1.83
1.85
1.88
1.90
1.70
1.73
1.75
1.78
1.80
1.83
1.85
1.88
1.90
VAVDD (V)
VAVDD (V)
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Typical Operating Characteristics (continued)
(V
= 1.8V, V
= 1.8V, V
= 1.8V, V
= 3.6V, f
= 1Msps, V
= 3.3V, Internal Ref Buffer On, T = T
to
MIN
AVDD
DVDD
OVDD
REFVDD
SAMPLE
REF
A
T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX
A
DNL vs. REFVDD SUPPLY VOLTAGE
INL vs. REFVDD SUPPLY VOLTAGE
toc8
toc7
12
4
MAX DNL (LSB)
MIN DNL (LSB)
VAVDD = 1.8V
VREF = 2.5V
MAX INL (LSB)
MIN INL (LSB)
V
AVDD = 1.8V
10
8
3
2
VREF = 2.5V
6
4
1
2
0
0
-2
-4
-6
-8
-10
-12
-1
-2
-3
-4
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VREFVDD (V)
VREFVDD (V)
OFFSET AND GAIN ERROR vs. AVDD SUPPLY VOLTAGE
OFFSET AND GAIN ERROR vs. TEMPERATURE
toc9
toc10
20
16
12
8
2.0
1.5
12
10
8
VREF = 3.3V
VREFVDD = 3.6V
OFFEST ERROR (LSB)
GAIN ERROR (LSB)
Offset Error (LSB)
Gain Error (LSB)
VREF = 3.3V
VREFVDD = 3.6V
1.0
0.5
6
4
0
0.0
4
-4
-0.5
-1.0
-1.5
-2.0
2
-8
0
-12
-16
-20
-2
-4
-40
-25
-10
5
20
35
50
65
80
95
110 125
1.7
1.75
1.8
1.85
1.9
TEMPERATURE (°C)
VAVDD (V)
OFFSET AND GAIN ERROR vs. REFVDD VOLTAGE
OUTPUT NOISE HISTOGRAM
toc11
toc12
8
6
12
10
8
8000
7000
6000
5000
4000
3000
2000
1000
0
VREF = 2.5V
VAVDD = 1.8V
Offset Error (LSB)
Gain Error (LSB)
STDEV = 3.8 LSB
4
2
6
0
4
-2
-4
-6
-8
2
0
-2
-4
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VREFVDD (V)
OUTPUT CODE (DECIMAL)
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Typical Operating Characteristics (continued)
(V
= 1.8V, V
= 1.8V, V
= 1.8V, V
= 3.6V, f
= 1Msps, V
= 3.3V, Internal Ref Buffer On, T = T
A MIN
to
AVDD
DVDD
OVDD
REFVDD
SAMPLE
REF
T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX
A
OUTPUT NOISE HISTOGRAM
4 SAMPLES AVERAGE
OUTPUT NOISE HISTOGRAM
16 SAMPLES AVERAGE
toc14
toc13
14000
12000
24000
20000
16000
12000
8000
4000
0
STDEV = 2.0 LSB
STDEV = 1.1 LSB
10000
8000
6000
4000
2000
0
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
SFDR AND THD vs. TEMPERATURE
SNR AND SINAD vs. TEMPERATURE
toc18
toc17
135
102
101
100
99
-THD
SNR
133
131
129
127
125
123
121
119
117
115
SINAD
SFDR
98
97
96
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Maxim Integrated
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Typical Operating Characteristics (continued)
(V
= 1.8V, V
= 1.8V, V
= 1.8V, V
= 3.6V, f
= 1Msps, V
= 3.3V, Internal Ref Buffer On, T = T
A MIN
to
AVDD
DVDD
OVDD
REFVDD
SAMPLE
REF
T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX
A
SNR AND SINAD vs. REFERENCE VOLTAGE
THD AND SFDR vs. REFERENCE VOLTAGE
toc19
toc20
130
128
126
124
122
120
118
116
114
112
110
100
SINAD
SFDR
-THD
SNR
99
98
97
96
95
94
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3
VREF (V)
VREF (V)
SHUTDOWN CURRENT vs. TEMPERATURE
CURRENT vs. TEMPERATURE
toc21
toc22
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
30
25
20
15
10
5
IAVDD
IOVDD
IREFVDD
IDVDD
IOVDD
IREFVDD (BUFFER OFF)
IREFVDD
IDVDD
IAVDD
0
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
CURRENT vs. SAMPLING RATE
toc23
2.5
IDVDD
IOVDD
IAVDD
2.0
1.5
1.0
0.5
0.0
0.0
0.3
0.5
0.8
1.0
SAMPLING RATE (Msps)
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Pin Configuration
TOP VIEW
20
19
17
16
18
1
2
3
4
5
15 DGND
REF
REF
14
13
12
DIN
MAX11904
CNVST
SCLK
REFGND
REFGND
AIN-
DVDD
10
6
7
8
9
TQFN
4mm × 4mm
EXPOSED PAD IS GROUND. IT MUST BE SOLDERED TO PCB.
Pin Description
PIN
NAME
I/O
FUNCTION
Reference. REF is a bypass pin for the reference either driven by the internal reference buffers
or the external reference directly. Bypass these pins with 10µF capacitors to REFGND.
1, 2
REF
I/O
3, 4
5
REFGND
AIN-
I
I
I
I
Reference Ground
Negative Analog Input
Positive Analog Input
Analog Ground
6
AIN+
7
AGND
Digital Interface Supply. Nominally at 1.8V. Bypass to DGND with a 10µF capacitor in parallel
with a 0.1µF capacitor (10µF || 0.1µF).
8
OVDD
I
9
DOUT
DGND
O
I
Digital Output Data
Digital Ground
10
Digital Supply. Nominally at 1.8V. Bypass with a 10µF capacitor in parallel with a 0.1µF
capacitor (10µF || 0.1µF).
11
12
13
DVDD
SCLK
I
I
I
Serial Clock Input
Conversion Start. The analog inputs (AIN+, AIN-) are sampled at the rising edge and conversion
process is started.
CNVST
14
15
DIN
I
I
Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK.
Digital Ground
DGND
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Pin Description (continued)
PIN
16
NAME
REFVDD
AGND
I/O
FUNCTION
Reference Buffer Supply. Nominally at 3.3V. Bypass to AGND with a 10µF capacitor in parallel
with a 0.1µF capacitor (10µF || 100nF).
I
I
17, 18
Analog Ground.
Analog Supply. Nominally at 1.8V. Bypass to AGND with a 10µF capacitor in parallel with a
0.1µF capacitor (10µF || 100nF).
19
AVDD
I
Input for the Internal Reference Buffer. Voltage must be at least 200mV lower than
REFVDD voltage. If REFIN = 0V, reference buffer will be disabled.
20
—
REFIN
EP
I
—
Exposed Pad. Must be connected to the same plane as AGND.
Functional Diagram
REFIN
AVDD
DVDD
REFVDD
REFERENCE
BUFFER
REFERENCE
BUFFER
MAX11904
REFGND
REF
OVDD
REF
DIN
AIN+
SCLK
DOUT
CNVST
INTERFACE
20-BIT ADC
AIN-
AGND
DGND
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
The differential analog input must be centered around
Detailed Description
a signal common mode of V
±100mV.
/2, with a tolerance of
REF
The MAX11904 is a 20-bit, 1Msps maximum sampling
rate, fully differential input, single-channel SAR ADC with
SPI interface. This part features industry-leading sample
rate and resolution, while consuming very low power. The
MAX11904 has an integrated reference buffer to minimize
board space, component count, and system cost. An
internal oscillator drives the conversion and sets conver-
sion time, easing external timing considerations.
The reference voltage can range from 2.5V to the refer-
ence supply, REFVDD, if an external reference buffer
is used. When using the on-board reference buffer the
reference voltage can range from 2.5V to 200mV below
reference supply REFVDD. This will guarantee adequate
headroom for the internal reference buffers.
Figure 1 illustrates signal ranges for AIN+/AIN-, reference
Analog Inputs
Both analog inputs, AIN+ and AIN-, range from 0V to
voltage V
and reference supply voltage REFVDD.
REF
Figure 2 shows the input equivalent circuit of MAX11904.
The ADC samples both inputs, AIN+ and AIN-, with a fully
differential on-chip track-and-hold exhibiting no pipeline
delay or latency.
V
. Thus, the differential input interval V
= (AIN+)
REF
DIFF
- (AIN-) ranges from -V
range is:
to +V
, and the full-scale
REF
REF
FSR = 2 x V
REF
The MAX11904 has dedicated input clamps to protect
the inputs from overranging. Diodes D1 and D2 provide
ESD protection and act as a clamp for the input voltages.
Diodes D1/D2 can sustain a maximum forward current
of 100mA. The sampling switches connect inputs to the
sampling capacitors.
The nominal resolution step width of the least significant
bit (LSB) is:
FSR
LSB =
,N = 20
N
2
Figure3showsthetimingofthedigitizingcycle:Conversion
frame, SAR conversion, Track and Read operations.
V
VREF +200mV ≤ VREFVDD ≤ 3.6V
REFVDD
VREF
IF BUFFER IS ENABLED
200mV
VREF ≤ VREFVDD ≤ 3.6V
IF BUFFER IS DISABLED
AIN+
AIN-
0.5 x VREF
0V
time
Figure 1. Signal Ranges
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
REFVDD
D1
RON = 260Ω
AIN+
CIN = 30pF
D2
VDC
REFVDD
D1
RON = 260Ω
AIN-
CIN = 30pF
D2
Figure 2. Simplified Model of Input Sampling Circuit
1/Sample Rate
SAR Conversion
1/Sample Rate
SAR Conversion
Track
Track
Read Data
Read Data
Sample 1
Sample 2
CNVST
SCLK
Sample 1
Sample 2
MSB MSB-1
LSB+1
LSB
MSB MSB-1
LSB+1
LSB
DOUT
Reading sample1 during track
Reading sample 2 during track
Figure 3. Conversion Frame, SAR Conversion, Track and Read Operation
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
capacitor, PCB parasitic capacitor), and t
track time.
is the
Input Settling
TRACK
During track phase (Figure 3), the sample switches are
closed and the analog inputs are directly connected to the
sample capacitors. The charging of the sample capacitor
to the input voltage is determined by the source resis-
tance and sampling capacitor size. The rising edge of
CNVST is the sampling instant for the ADC. At this instant,
the track phase ends, the sample switch opens, and the
device enters into the successive approximation (SAR)
conversion phase. In the conversion phase, a differential
comparator compares the voltage on the sample capaci-
When an ADC driver is used, it is recommended to use
a series resistance (typically 5Ω to 50Ω) between the
amplifier and the ADC input, as shown in the Application
Diagram. Below are some of the requirements for the
ADC driver amplifier:
1) Fast settling time: For a multichannel multiplexed cir-
cuit the ADC driver amplifier must be able to settle with
an error less than 0.5 LSB during the minimum track
time when a full-scale step is applied.
tor against the CDAC value, which cycles through values
20
2) Low noise: It is important to ensure that the ADC driver
has a sufficiently low-noise density in the bandwidth
of interest of the application. When the MAX11904 is
used with its full bandwidth of 20MHz, it is preferable
to use an amplifier with an output noise spectral den-
sity of less than 3nV/√Hz, to ensure that the overall
SNR is not degraded significantly. It is recommended
to insert an external RC filter at the ADC input to
attenuate out-of-band input noise.
between V
/2 and V
/2
using the successive
REF
REF
approximation technique. The final result can be read via
the SPI bus. The ADC automatically goes back into track
phase at the end of SAR conversion and powers down its
active circuits. That is, the ADC consumes no static power
in track mode.
The conversion results will be accurate if the ADC tracks
the input signal for an interval longer than the input sig-
nal’s settling time. If the signal cannot settle within the
track time due to excessive source resistance, external
ADC drivers are required to achieve faster settling. Since
the MAX11904 has a fixed conversion time set by an
internal oscillator, track time can be increased by lowering
the sample rate for better settling.
3) To take full advantage of the ADC’s excellent dynamic
performance, Maxim recommends the use of an ADC
driver with equal or even better THD performance.
This will ensure that the ADC driver does not limit
distortion performance in the signal path. Table 1 sum-
marizes the most important features of the MAX9632
when used as an ADC driver.
The settling behavior is determined by the time constant
in the sampling network. The time constant depends upon
the total resistance (source resistance + switch resis-
tance) and total capacitance (sampling capacitor, external
input capacitor, PCB parasitic capacitors).
Input Filtering
Noisy input signals should be filtered prior to the ADC
driver amplifier input with an appropriate filter to minimize
noise. The RC network shown in the Application Diagram
is mainly designed to reduce the load transient seen by
the amplifier when the ADC starts the track phase. This
network also has to satisfy the settling time requirement
and provides the benefit of limiting the noise bandwidth.
Modeling the input circuit with a single pole network, the
time constant, R
× C
, of the input should not
TOTAL
LOAD
exceed t
/15, where R
is the total resistance
TOTAL
TRACK
(source resistance + switch resistance), C
total capacitance (sampling capacitor, external input
is the
LOAD
Table 1. ADC Driver Amplifier Recommendation
INPUT-NOISE
DENSITY (nV/√Hz)
SMALL-SIGNAL
BANDWIDTH (MHz)
SLEW RATE
(V/µs)
THD
(dB)
ICC
(mA)
AMPLIFIER
COMMENTS
Ultra-low noise, wide
GBWP, single ended
MAX9632
0.9
55
30
-128
-137
3.9mA
3.7mA
Ultra-low distortion, wide
GBWP, fully differential
MAX44205
3.1
180
180
Maxim Integrated
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
MAX11904. The MAX6126 and MAX6325 offer, respec-
tively, 0.02% and 0.04% initial accuracy and 3ppm/°C and
1ppm/°C (max) temperature coefficient for high-precision
applications. Maxim recommends bypassing REFIN and
REF with a 2.2µF capacitor close to the ADC pins.
Voltage Reference Configurations
The MAX11904 features internal reference buffers,
helping to reduce component count and board space.
Alternatively, the user may drive the reference nodes REF
with an external reference. To use the internal reference
buffers, drive the REFIN pin with an external reference
voltage source. It will appear on the REF pin as a buffered
reference output. The internal reference buffers can be
disabled by writing to a register (see the Mode Register
section) or tying REFIN to 0V. Once the on-chip reference
buffers are disabled, REF pins can be directly driven by
external reference buffers. A simplified diagram is shown
to clarify the required connections for external reference.
Transfer Function
Figure 4 shows the ideal transfer characteristics for the
MAX11904.
The default data format is two’s complement. However,
offset binary format can be chosen by setting mode regis-
ter BIT 1 (see the Mode Register section).
Table 4 shows the codes in terms of input voltage applied.
The data reported is with V
scale range of 6V.
of 3.0V, that gives a full-
A low-noise, low-temperature drift reference is required
to achieve high system accuracy. The MAX6126 and
MAX6325 are particularly well suited for use with the
REF
Table 2. Voltage Reference Configurations
REFERENCE
CONFIGURATION
INTERNAL
REFERENCE BUFFERS
REFIN
2.5V to V
V
V
REFVDD
REF
Internal Reference Buffer
ON
- 0.2V
2.5V to V
- 0.2V
2.7V to 3.6V
2.5V to 3.6V
REFVDD
REFVDD
External Reference
Buffer
Tie to 0V or disable
through serial interface
OFF
2.5V to V
REFVDD
Table 3. MAX11904 External Reference Recommendations
TEMPERATURE
COEFFICIENT
(ppm/°C, max)
INITIAL
ACCURACY
(%)
NOISE
(0.1Hz TO 10Hz)
PART
V
(V)
PACKAGE
OUT
(µV
)
P-P
MAX6126
MAX6325
2.5, 3
2.5
3
1
0.02
0.04
1.45
1.5
µMAX-8, SO-8
SO-8
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
OUTPUT CODE
(OFFSET
BINARY)
OUTPUT CODE
(TWO'S COMPLEMENT)
FS - 1.5 x LSB
FS - 1.5 x LSB
011...111
011...110
011...101
111...111
111...110
111...101
100...010
100...001
000...010
000...001
V
IN = (AIN+) - (AIN-)
DIFFERENTIAL
ANALOG INPUT
(LSB)
V
IN = (AIN+) - (AIN-)
DIFFERENTIAL
ANALOG INPUT
(LSB)
100...000
000...000
-219-219+1-219+2
219-2 219-1 219
219-2 219-1 219
-219-219+1-219+2
2 x VREF
2 X VREF
ZERO SCALE
(ZS)
VIN = -VREF
FULL SCALE
(FS)
VIN = +VREF
ZERO SCALE
(ZS)
VIN = -VREF
FULL SCALE
(FS)
VIN = +VREF
Figure 4. Ideal Transfer Characteristic
Table 4. Transfer Characteristic
DIFFERENTIAL ANALOG INPUT
FULL-SCALE RANGE = 6V (V)
HEXADECIMAL
TWO’S COMPLEMENT
HEXADECIMAL OFFSET
BINARY
MIDCODE VALUE
FS - 1 LSB
2.99999428
0.00000572
0.00000000
-0.00000572
-2.99999428
-3.00000000
0x7FFFF
0x00001
0x00000
0xFFFFF
0x80001
0x80000
0xFFFFF
0x80001
0x80000
0x7FFFF
0x00001
0x00000
Midscale + 1 LSB
Midscale
Midscale - 1 LSB
-FS + 1 LSB
-FS
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
The MAX11904 has three different modes to read the data:
● Reading during track phase (Figure 5)
● Reading during SAR conversion phase (Figure 6)
● Split reading (Figure 7)
Digital Interface
The MAX11904 has a SPI interface with CNVST control-
ling the sampling, and SCLK, DOUT, DIN forming the
standard SPI signals. The SAR conversion begins with
the rising edge of CNVST. The minimum CNVST high
time is 20ns and CNVST should be brought low before
DOUT goes low, which signals the completion of a SAR
conversion. The DOUT goes low for 10ns, followed by
the output of the MSB on the DOUT pin. The 20-bit con-
version result can then be read via the SPI interface by
sending 20 SCLK pulses. DOUT going low also signals
the start of the track phase. The ADC stays in track phase
until the next rising edge of CNVST.
When reading during track phase mode, the data is read
only while the ADC is in track mode. Figure 5 shows the
SPI signal for this reading mode.
In the reading during SAR conversion phase mode,
the data is read only in the SAR conversion phase.
Figure 6 illustrates all SPI signals for this mode. Note that
the data being read only during the SAR conversion phase
corresponds to the previous conversion frame.
1/Sample Rate
1/Sample Rate
SAR Conversion
SAR Conversion
Track
Track
Read Data
Read Data
Sample 1
Sample 2
CNVST
SCLK
Sample 1
Sample 2
MSB MSB-1
LSB+1 LSB
MSB MSB-1
LSB+1 LSB
DOUT
Reading sample1 during track
Reading sample 2 during track
Figure 5. Read During Track Phase
1/SAMPLE RATE
1/SAMPLE RATE
SAR CONVERSION
READ DATA
SAR CONVERSION
TRACK
TRACK
READ DATA
SAMPLE 1
SAMPLE 2
CNVST
SCLK
SAMPLE 0
SAMPLE 1
MSB
MSB-1
LSB+1
LSB
MSB
MSB-1
LSB+1
LSB
MSB
DOUT
READING SAMPLE 0 DURING SAR
CONVERSION
READING SAMPLE 1 DURING SAR
CONVERSION
Figure 6. Read During SAR Conversion Phase
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
In the split reading mode, the data is read during the track
phase and the following SAR conversion phase. Figure 7
shows the descriptive timing diagram.
SPI Timing Diagram
Figure 8 shows the typical digital SPI interface connection
between the MAX11904 and host processor.
At higher sampling rates, the track time may not be long
enough to allow reading all 20 bits of data. In this case,
the data read can be started in track mode, and then
continued in the subsequent SAR conversion phase. Note
that the read operation must be completed before DOUT
goes low, signaling the end of the SAR conversion phase.
Also note that no SCLK pulses should be applied close to
the sampling edge (rising edge of CNVST), to safeguard
the sampling edge from digital noise (see the Quiet Time
The dashed connections are optional.
Figure 9 shows the timing diagram for configuration reg-
isters.
Figure 10 shows the timing diagram for data output read-
ing after conversion.
specification t ). This split reading feature can be used
10
to accommodate slower SPI clocks.
1/Sample Rate
1/Sample Rate
SAR Conversion
SAR Conversion
Track
Track
Read Data
Read Data
Sample 2
Sample 1
CNVST
SCLK
Quiet Time
Sample 1
Sample 2
MSB MSB-1
LSB+1 LSB
MSB MSB-1
DOUT
Reading sample 1
Figure 7. Split Read Mode
MAX11904
Host Processor
DIN
DOUT
SCLK
SCLK
DIN
DOUT
IRQ
CNVST
CNVST
Figure 8. SPI Interface Connection
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
t1
0.7 x OVDD
SCLK
t2
0.7 x OVDD
0.3 x OVDD
DIN
Figure 9. DIN Timing for Register Write Operations
t13
t12
t11
0.7 x OVDD
0.7 x OVDD
CNVST
t6
t8
t7
t10
t9
0.7 x OVDD
0.3 x OVDD
0.7 x OVDD
SCLK
DOUT
t3
t5
t4
0.7 x OVDD
MSB-2
MSB-1
MSB
0.3 x OVDD
Figure 10. Timing Diagram for Data Out Reading After Conversion
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Register Write
All SPI operations start with a command word. The structure of the command word is shown below. If there is no start
bit, i.e. DIN is low, the part will output the conversion result and then go idle (see Figures 5, 6, and 7). The 16-bit mode
register is the only register that can be written to. Figure 11 shows the waveform for a mode register write operation.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Start
0
Adr 3
Adr 2
Adr 1
Adr 0
R/W
0
CNVST
DOUT
SCLK
DIN
ST
0
A3
A2
A1
A0
R/W
0
D15
D14
D1
D0
Figure 11. Mode Register Write
Register Read
A read operation is specified by setting the R/W bit high. Data will be output by the MAX11904 after the 8th rising SCLK
edge. Figure 12 shows the waveform for a mode register read.
CNVST
D7
D6
D1
D0
DOUT
SCLK
DIN
ST
0
0
A3
A2
A1
A0
R/W
Figure 12. Register Read
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Register Map
FUNCTION
ADDRESS
0001
R/W BITS
DATA WIDTH
DATA
Mode Register
Read or Write Mode Register
Read Conversion Result*
Read Chip ID
1 or 0
16
20
8
0010
1
1
Conversion Result
Chip ID
0100
Reserved, Do Not Use
All other
—
—
Reserved, Do Not Use
*Conversion result can also be read as shown in Figures 5, 6, and 7.
Mode Register
The reset state is: 0x0000. That is, the reference buffers are enabled if a valid reference voltage is applied at the REFIN
pin. If external reference buffers are used, tie REFIN low and the buffers will be automatically powered down.
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PD
POR
OTP
busy
PD
REF2
Reset
—
—
—
—
—
DD2
DD1
DD0
—
—
OB
REF1 pass
Reset:
Reset the part when high.
Program the driver strength on DOUT.
Power down the first reference buffer when set.
DD[2:0]:
PD REF1:
POR pass:
OTP busy:
OB:
High to indicate that POR was successful. If this bit is low, RESET should be asserted.
High to indicate that the device is powering up.
Output data format is offset binary when high. two’s complement when low.
Power down the second reference buffer when set.
PD REF2:
DD[2:0] program the driver strength on DOUT pin. Higher driver strengths are for systems that have larger capacitive
loads on DOUT. The lowest driver strength that works should be chosen to save power and improve performance.
The driver strength is ordered from 1 to 6. The driver strength 1 is the weakest while the driver strength 6 is the strongest.
Table 5 shows the mapping between the register value D[2:0] and the correspondent driver strength.
Table 5. DOUT Driver Strength
DD[2:0]
000
DRIVER STRENGTH
4
001
5
010
6
011
Not Valid
100
1
101
2
3
110
111
Not Valid
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Conversion Result Register
A 20-bit read-only register, can be read directly or via a command read sequence.
Chip ID Register
This register holds a 4-bit code that can be used to verify the silicon revision. The ID = 1001b.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
—
—
—
—
ID3
ID2
ID1
ID0
ration and drives the AIN+ input of the ADC. This ampli-
fier adds an offset to generate a signal with peak-to-peak
Typical Application Circuit
Real-world signals usually require conditioning before
they can be digitized by an ADC. The following outlines
common examples of analog signal processing circuits for
shifting, gaining, attenuating, and filtering signals.
amplitude of V
and common-mode output voltage
REF
of V
/2. The input impedance, seen by the signal
REF
source, depends on the input resistor of the first-stage
inverting amplifier. Input impedance must be chosen care-
fully based on the output source impedance of the signal
source.
Single-Ended Unipolar Input to Differential
Unipolar Output
The circuit in Figure 13 shows how a single-ended, uni-
polar signal can interface with the MAX11904. This signal
Layout, Grounding, and Bypassing
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines paral-
lel to one another (especially clock lines), and avoid run-
ning digital lines underneath the ADC package. A single
solid GND plane configuration with digital signals routed
from one direction and analog signals from the other pro-
vides the best performance. Connect the GND pin on the
MAX11904 to this ground plane. Keep the ground return
to the power supply for this ground low impedance and as
short as possible for noise-free operation.
conditioning circuit transforms a 0V to +V
single-end-
REF
ed input signal to a fully differential output signal with a
signal peak-to-peak amplitude of 2 x V and common-
REF
mode voltage (V
/2). In this case, the single-ended
REF
signal source drives the high-impedance input of the first
amplifier. This amplifier drives the AIN+ input of ADC and
the second stage amplifier with peak-to-peak amplitude
of V
and common-mode output voltage of V
/2.
REF
REF
The second amplifier inverts this input signal and adds
an offset to generate an inverted signal with peak-to-peak
amplitude of V
and common-mode output voltage of
REF
V
/2, which drives the AIN- input of ADC.
REF
A 2nF C0G ceramic chip capacitor should be placed
between AIN+ and AIN- as close as possible to the
MAX11904. This capacitor reduces the voltage transient
seen by the input source circuit.
Single-Ended Bipolar Input to Differential
Unipolar Output
The MAX11904 is a differential input ADC that accepts
a differential input signal with unipolar common mode.
Figure 14 shows a signal conditioning circuit that trans-
forms a -2 x V
input signal to a fully differential output signal with ampli-
tude peak-to-peak 2 x V and common-mode voltage
For best performance, connect the REF output to the
ground plane with a 16V, 10µF ceramic chip capacitor
with a X5R dielectric in a 1210 or smaller case size.
Ensure that all bypass capacitors are connected directly
into the ground plane with an independent via.
to +2 x V
single-ended bipolar
REF
REF
REF
V
/2.
Bypass AVDD, DVDD, and OVDD to the ground plane with
10µF ceramic chip capacitors on each pin as close as pos-
sible to the device to minimize parasitic inductance. For
best performance, bring the AVDD and DVDD power plane
in from the analog interface side of the MAX11904 and the
OVDD power plane from the digital interface side of the
device. Figure 15 shows the top layer of a sample layout.
REF
The single-ended bipolar input signal drives the inverting
input of the first amplifier. This amplifier inverts and adds
an offset to the input signal. It also drives the AIN- input
of ADC and the second stage amplifier with peak-to-peak
amplitude of V
and common-mode output voltage of
REF
V
REF
/2. The second amplifier is also in inverting configu-
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
2.7V
1.5V TO
TO
2.5V TO
VREFVDD - 0.2V
1.8V
1.8V
3.6V
3.6V
REFVDD AVDD DVDD OVDD
RS
REFIN
AIN+
VREF
0.5 x VREF
0V
DIN
DSP
R
R
CS
SCLK
DOUT
MAX11904
SPI
INTERFACE
COG
RS
CNVST
AIN-
REF
A
D
REF REF GND GND GND
VREF
2
+
-
10µF
Figure 13. Unipolar Single-Ended Input
2.7V
2.5V TO
VREFVDD - 0.2V
TO
1.5V TO
3.6V
3.6V
1.8V
1.8V
R
R
REFVDD AVDD DVDD OVDD
RS
REFIN
AIN+
R
DIN
DSP
SPI
+2 x VREF
4R
SCLK
+
-
CS
COG
VREF
2
MAX11904
0V
INTERFACE
DOUT
-2 x VREF
R
RS
CNVST
AIN-
REF
A
D
+
VREF
2
4R
REF REF GND GND GND
-
10µF
Figure 14. Bipolar Single-Ended Input
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Figure 15. Top Layer Sample Layout
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Effective Number of Bits
Definitions
The effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. For these
devices, this straight line is a line drawn between the end
points of the transfer function, once offset and gain errors
have been nullified.
SINAD -1.76
ENOB =
Differential Nonlinearity
6.02
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specification
of less than ±1 LSB guarantees no missing codes.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the power
contained in the first five harmonics of the converted data
to the power of the fundamental. This is expressed as:
P + P + P + P
2
3
4
5
Offset Error
THD = 10×log
P
1
The offset error is defined as the deviation between the
actual output and ideal output measured with 0V differen-
tial analog input voltage.
where P is the fundamental power and P through P is
1
2
5
Gain Error
the power of the 2nd- through 5th-order harmonics.
Gain error is defined as the difference between the
actual output range measured and the ideal output range
expected. It is measured with signal applied at the input
with an amplitude close to full-scale range.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
power of the fundamental (maximum signal component)
to the power of the next-largest frequency component.
Signal-to-Noise Ratio
Aperture Delay
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the full-
scale analog input power to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization noise error only
and results directly from the ADC’s resolution (N bits):
Aperture delay (t ) is the time delay from the sampling
AD
clock edge to the instant when an actual sample is taken.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
aperture delay.
SNR = (6.02 x N + 1.76)dB
Full-Power Bandwidth
In reality, there are other noise sources besides quantiza-
tion noise: thermal noise, reference noise, clock jitter, etc.
SNR is computed by taking the ratio of the signal power to
the noise power, which includes all spectral components
not including the fundamental, the first five harmonics,
and the DC offset.
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as full-power
input bandwidth frequency.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s power to the power of all
the other ADC output signals:
Signal
SINAD(dB) = 10×LOG
Noise + Distortion
Maxim Integrated
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Selector Guide
FULLY
DIFFERENTIAL
INPUT (MAX) (V)
SPEED
(ksps)
REFERENCE
BUFFERS
PART
BITS
PACKAGE
MAX11900
MAX11901
MAX11902
MAX11903
MAX11904
MAX11905
16
16
18
18
20
20
1000
1600
1000
1600
1000
1600
±3.6
±3.6
±3.6
±3.6
±3.6
±3.6
Internal/External
Internal/External
Internal/External
Internal/External
Internal/External
Internal/External
4mm x 4mm TQFN-20
4mm x 4mm TQFN-20
4mm x 4mm TQFN-20
4mm x 4mm TQFN-20
4mm x 4mm TQFN-20
4mm x 4mm TQFN-20
Package Information
Ordering Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
20 TQFN-EP*
MAX11904ETP+
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
Chip Information
PROCESS: CMOS
20 TQFN-EP
T2044+5
21-0139
90-0429
Maxim Integrated
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MAX11904
20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
9/14
Initial release
—
Removed future product references in the 16-Bit to 20-Bit SAR ADC Family table
and Selector Guide
1
4/15
1, 28
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
│ 29
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