MAX5972AETE+ [MAXIM]
IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET; 符合IEEE 802.3af / at兼容，供电设备接口控制器，集成功率MOSFET
| 型号： | MAX5972AETE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | IEEE 802.3af/at-Compliant, Powered Device Interface Controller with Integrated Power MOSFET |
| 文件： | 总13页 (文件大小：1215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4924; Rev 1; 2/10
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
General Description
Features
S IEEE 802.3af/at Compliant
The MAX5972A provides a complete interface for a
®
powered device (PD) to comply with the IEEE 802.3af/
S 2-Event Classification or an External Wall Adapter
at standard in a power-over-Ethernet (PoE) system. The
MAX5972A provides the PD with a detection signature,
classification signature, and an integrated isolation
power switch with inrush current control. During the
inrush period, the MAX5972A limits the current to less
than 180mA before switching to the higher current limit
(720mA to 880mA) when the isolation power MOSFET
is fully enhanced. The device features an input UVLO
with wide hysteresis and long deglitch time to compen-
sate for twisted-pair cable resistive drop and to assure
glitch-free transition during power-on/-off conditions. The
MAX5972A can withstand up to 100V at the input.
Indicator Output
S Simplified Wall Adapter Interface
S PoE Classification 0 to 5
S 100V Input Absolute Maximum Rating
S Inrush Current Limit of 180mA Maximum
S Current Limit During Normal Operation Between
720mA and 880mA
S Current Limit and Foldback
S Legacy UVLO at 36V
S Overtemperature Protection
The MAX5972A supports a 2-event classification method
as specified in the IEEE 802.3at standard and provides a
signal to indicate when probed by Type 2 power-sourcing
equipment (PSE). The device detects the presence of
a wall adapter power-source connection and allows a
smooth switch over from the PoE power source to the
wall power adapter.
S Thermally Enhanced, 5mm x 5mm, 16-Pin TQFN
Ordering Information
PIN-
PACKAGE
SLEEP
MODE
PART
TEMP RANGE
The MAX5972A also provides a power-good (PG) signal,
two-step current limit and foldback, overtemperature
protection, and di/dt limit.
MAX5972AETE+
-40NC to +85NC 16 TQFN-EP*
––
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
The MAX5972A is available in a 16-pin, 5mm x 5mm,
TQFN power package. This device is rated over the
-40NC to +85NC extended temperature range.
Pin Configuration
Applications
TOP VIEW
IEEE 802.3af/at-Powered Devices
16
15
14
13
IP Phones, Wireless Access Nodes, IP Security
Cameras
+
WiMAXK Base Station
CLS
11 2EC
12
N.C.
1
2
3
4
V
DD
MAX5972A
DET
I.C.
10
9
PG
EP*
5
WAD
6
7
8
TQFN
(5mm × 5mm)
WiMAX is a trademark of WiMAX Forum.
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
*EP = EXPOSED PAD. CONNECT TO V
.
SS
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
ABSOLUTE MAXIMUM RATINGS
V
to V ..........................................................-0.3V to +100V
Package Thermal Resistance (Note 2)
DD
SS
B
...............................................................................35NC/W
JA
.............................................................................2.7NC/W
JC
DET, RTN, WAD, PG, 2EC to V
-0.3V to +100V
SS .......................
B
CLS to V ..............................................................-0.3V to +6V
SS
Operating Temperature Range.......................... -40NC to +85NC
Maximum Junction Temperature.....................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) .............................. +300NC
Maximum Current on CLS (100ms maximum).................100mA
Continuous Power Dissipation (T = +70NC) (Note 1)
A
16-Pin TQFN (derate 28.6mW/NC above +70NC)
Multilayer Board .....................................................2285.7mW
Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = (V
IN
- V ) = 48V, R
= 24.9kω, R
= 615ω, and R = 60.4kω. RTN, WAD, PG, and 2EC unconnected, all voltages are
CLS SL
DD
SS
DET
referenced to V
(Note 3)
unless otherwise noted. T = T = -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.)
A J A
SS,
PARAMETER
DETECTION MODE
Input Offset Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
V
= 1.4V to 10.1V (Note 4)
10
FA
kI
OFFSET
dR
IN
Effective Differential Input
Resistance
V
V
= 1.4V up to 10.1V with 1V step,
= RTN = WAD = PG = 2EC (Note 5)
IN
23.95
22.0
25.00
25.50
DD
CLASSIFICATION MODE
Classification Disable
Threshold
V
V
IN
rising (Note 6)
22.8
0.2
23.6
V
TH,CLS
Classification Stability Time
ms
Class 0, R
Class 1, R
Class 2, R
Class 3, R
Class 4, R
Class 5, R
= 615I
= 117I
= 66.5I
= 43.7I
= 30.9I
= 21.3I
0
3.96
11.88
19.8
29.7
43.6
63.3
CLS
CLS
CLS
CLS
CLS
CLS
9.12
17.2
26.3
36.4
52.7
V
IN
= 12.5V to
20.5V, V
RTN = WAD =
=
DD
Classification Current
I
mA
CLASS
PG = 2EC
TYPE 2 (802.3at) CLASSIFICATION MODE
Mark Event Threshold
V
V
V
falling
10.1
10.7
0.84
11.6
V
V
THM
IN
Hysteresis on Mark Event
Threshold
falling to enter mark event, 5.2V P V
IN
IN
Mark Event Current
I
0.25
2.8
0.85
5.2
mA
V
MARK
P 10.1V
Reset Event Threshold
V
V
IN
falling
4
THR
POWER MODE
V
IN
V
IN
Supply Voltage Range
Supply Current
60
V
I
Q
0.27
0.55
mA
2
______________________________________________________________________________________
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
ELECTRICAL CHARACTERISTICS (continued)
(V = (V
IN
- V ) = 48V, R
= 24.9kω, R
= 615ω, and R = 60.4kω. RTN, WAD, PG, and 2EC unconnected, all voltages are
CLS SL
DD
SS
DET
referenced to V
(Note 3)
unless otherwise noted. T = T = -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.)
A J A
SS,
PARAMETER
Turn-On Voltage
Turn-Off Voltage
SYMBOL
CONDITIONS
MIN
34.3
30
TYP
MAX
UNITS
V
V
V
ON
V
rising
falling
35.4
36.6
V
V
IN
IN
V
OFF
V
IN
IN
V
Turn-On/-Off Hysteresis
Deglitch Time
V
(Note 7)
4.2
30
V
IN
HYST_UVLO
V
IN
t
V
IN
falling from 40V to 20V (Note 8)
120
Fs
OFF_DLY
Inrush to Operating Mode
Delay
t
= minimum PG current pulse width
DELAY
t
80
96
112
ms
DELAY
after entering into power mode
T = +25NC
0.7
0.9
1.1
1.5
J
Isolation Power MOSFET
On-Resistance
R
I
= 600mA
T = +85NC
J
I
ON_ISO
RTN
T = +125NC
J
1.15
RTN Leakage Current
I
V
RTN
= 12.5V to 30V
10
FA
RTN_LKG
CURRENT LIMIT
During initial turn-on period,
= 1.5V
Inrush Current Limit
I
90
135
800
180
mA
INRUSH
V
RTN
Current Limit During Normal
Operation
After inrush completed,
I
720
13
880
mA
V
LIM
V
RTN
= 1V
Foldback Threshold
V
RTN
(Note 9)
16.5
LOGIC
V
rising, V = 14V to 48V (referenced
IN
WAD
WAD Detection Threshold
V
8
9
10
WAD-REF
to RTN)
V
WAD Detection Threshold
Hysteresis
V
falling, V
= 0V, V
RTN SS
WAD
0.725
unconnected
WAD Input Current
I
V
= 10V (referenced to RTN)
3.5
2.25
1
FA
mA
FA
FA
FA
WAD-LKG
WAD
V
2EC
= 3.5V (referenced to RTN), V
SS
1
1.5
2EC Sink Current
unconnected
V
V
= 48V
2EC Off-Leakage Current
PG Sink Current
2EC
= 1.5V, V = 0.8V, during inrush
RTN
PG
125
230
375
1
period
V = 60V
PG
PG Off-Leakage Current
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
T
T rising
+140
+28
NC
NC
SD
J
T falling
J
Note 3: This device is 100% production tested at T = +25NC. Limits over temperature are guaranteed by design.
A
Note 4: The input offset current is illustrated in Figure 1.
Note 5: Effective differential input resistance is defined as the differential resistance between V
Note 6: Classification current is turned off whenever the device is in power mode.
Note 7: UVLO hysteresis is guaranteed by design, not production tested.
and V . See Figure 1.
SS
DD
Note 8: A 20V glitch on input voltage that takes V
below V
shorter than or equal to t
does not cause the MAX5972A
DD
ON
OFF_DLY
to exit power-on mode.
Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload
condition across V and RTN.
DD
_______________________________________________________________________________________
3
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
I
IN
(V
(I
- V
)
INi
1V
INi + 1
dR =
i
=
- I
)
(I
- I
)
INi + 1 INi
INi + 1 INi
V
INi
I
= I
INi
-
OFFSET
dR
i
I
INi + 1
dR
i
I
INi
I
OFFSET
V
IN
V
INi
1V
V
INi + 1
Figure 1. Effective Differential Input Resistance/Offset Current
Typical Operating Characteristics
(V = (V
- V ) = 54V, R
= 24.9kω, R
= 615ω, and R = 60.4kω. RTN, WAD, PG, and 2EC unconnected; all voltages are
IN
DD
SS
DET
CLS SL
referenced to V
)
SS.
DETECTION CURRENT
vs. INPUT VOLTAGE
SIGNATURE RESISTANCE
vs. INPUT VOLTAGE
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
26.0
4
2
0.5
I
R
= I
+ I
I
R
= I
+ I
IN VDD DET
IN VDD DET
= 24.9kI
= 24.9kI
DET
DET
RTN = 2EC = PG = WAD = V
RTN = 2EC = PG = WAD = V
-40°C P T P+85NC
DD
DD
0.4
0.3
0.2
0.1
0
T
A
= +85NC
25.5
25.0
24.5
24.0
A
T
A
= -40NC
T
A
= -40NC
0
T
= +25NC
A
T
A
= +25NC
-2
-4
T
A
= +85NC
0
2
4
6
8
10
0
2
4
6
8
10
0
2
4
6
8
10
V
(V)
V
(V)
IN
V
(V)
IN
IN
CLASSIFICATION CURRENT vs.
INPUT VOLTAGE
CLASSIFICATION SETTLING TIME
MAX5972A toc05
70
60
50
40
30
20
10
0
V
IN
CLASS 5
10V/div
0V
CLASS 4
CLASS 3
I
IN
0A
200mA/div
CLASS 2
CLASS 1
V
CLS
1V/div
0V
CLASS 0
R
CLS
= 30.9I
100Fs/div
0
5
10
15
(V)
20
25
30
V
IN
4
______________________________________________________________________________________
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
Typical Operating Characteristics (continued)
(V = (V
- V ) = 54V, R
= 24.9kω, R
= 615ω, and R = 60.4kω. RTN, WAD, PG, and 2EC unconnected; all voltages are
IN
DD
SS
DET
CLS SL
referenced to V
)
SS.
2EC SINK CURRENT vs. 2EC VOLTAGE
PG SINK CURRENT vs. PG VOLTAGE
2.0
1.6
1.2
0.8
0.4
0
300
250
200
150
100
50
T
= +25NC
T
A
= -40NC
A
T = +25NC
A
T
A
= -40NC
T
A
= +85NC
T
A
= +85NC
V
V
V
UNCONNECTED
REFERENCED TO RTN
= 14V
SS
2EC
WAD
0
10
20
30
(V)
40
50
60
0
10
20
30
40
50
60
V
V
(V)
PG
2EC
INRUSH CURRENT LIMIT
vs. RTN VOLTAGE
NORMAL OPERATION CURRENT LIMIT
vs. RTN VOLTAGE
150
130
110
90
900
800
700
600
500
400
300
200
100
70
50
0
10
20
30
(V)
40
50
60
0
10
20
30
40
50
60
V
V
(V)
RTN
RTN
ENTERING POWER MODE WITH
TYPE 2 CLASSIFICATION
INRUSH CONTROL WAVEFORM WITH
TYPE 2 CLASSIFICATION
MAX5972A toc11
MAX5972A toc10
V
PG
0V 10V/div
V
2EC
USING TYPICAL APPLICATION CIRCUIT
50V/div
2EC PULLED UP TO V WITH 10kI
DD
0V
0V
0A
USING TYPICAL APPLICATION CIRCUIT
V
2EC
2EC PULLED UP TO V WITH 10kI
DD
0V
40V/div
V
RTN
50V/div
V
RTN
0V 50V/div
I
RTN
I
RTN
100mA/div
0A 200mA/div
V
DD
V
DD
50V/div
0V 50V/div
0V
20ms/div
200µs/div
_______________________________________________________________________________________
5
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
Pin Description
PIN
NAME
FUNCTION
1, 13–16
N.C.
No Connection. Not internally connected.
Positive Supply Input. Connect a 68nF (min) bypass capacitor between V
2
3
4
V
DD
and V
.
DD
SS
DET
I.C.
Detection Resistor Input. Connect a signature resistor (R
Internally Connected. Leave unconnected.
= 24.9kI) from DET to V
.
DET
DD
Negative Supply Input. V connects to the source of the integrated isolation n-channel power
SS
MOSFET.
5, 6
V
SS
Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power
MOSFET. Connect RTN to the downstream DC-DC converter ground as shown in the Typical
Application Circuit.
7, 8
RTN
Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment V
- V crosses
SS
DD
the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V.
When a wall power adapter is present, the isolation n-channel power MOSFET turns off, 2EC current
sink turns on. Connect WAD directly to RTN when the wall power adapter or other auxiliary power
source is not used.
9
WAD
Open-Drain Power-Good Indicator Output. PG sinks 230FA to disable the downstream DC-DC con-
verter while turning on the hot-swap MOSFET switch. PG current sink is disabled during detection,
classification, and in the steady-state power mode. The PG current sink is turned on to disable the
downstream DC-DC converter when the device is in sleep mode.
10
PG
Active-Low 2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is
enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE,
the 2EC current sink is enabled after the isolation MOSFET is fully on until V drops below the UVLO
IN
11
2EC
threshold. 2EC is latched when powered by a Type 2 PSE until V drops below the reset threshold.
IN
2EC also asserts when a wall adapter supply, typically greater than 9V, is applied between WAD and
RTN. 2EC is not latched if asserted by WAD.
Classification Resistor Input. Connect a resistor (R ) from CLS to V to set the desired classification
CLS SS
12
––
CLS
EP
current. See the classification current specifications in the Electrical Characteristics table to find the
resistor value for a particular PD classification.
Exposed Pad. Do not use EP as an electrical connection to V . EP is internally connected to V
SS
SS
through a resistive path and must be connected to V externally. To optimize power dissipation, sol-
SS
der the exposed pad to a large copper power plane.
6
______________________________________________________________________________________
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
Simplified Block Diagram
V
DD
V
DD
EN
CLS
2EC
CLASSIFICATION
V
DD
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
5V REGULATOR
1.5mA
V
DD
5V
PG
46µA
DET
V
V
/V
ON OFF
230µA
V
DD
DD
THERMAL
SHUTDOWN
t
DELAY
WAD
R
S
Q
9V
I
SWITCH
V
SS
RTN
ISOLATION
SWITCH
K x I
SWITCH
MAX5972A
S
I0
1/K
I1
MUX
_______________________________________________________________________________________
7
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
Typical Operating Circuit
2-EVENT
CLASSIFICATION
DETECTION
GND
V
DD
2EC
IN+
ENABLE
RJ-45
AND
GND
PG
BRIDGE
RECTIFIER
R
DET
2EC/WAD
24.9kI
DC-DC
CONVERTER
DET
CLS
68nF
WAD
MAX5972A
1.5mA
SMAJ58A
24V/48V
BATTERY
R
CLS
IN-
V
SS
RTN
-54V
in detection mode. DET goes high impedance when the
input voltage exceeds 12.5V. In detection mode, most of
the MAX5972A internal circuitry is off and the offset cur-
rent is less than 10µA.
Detailed Description
Operating Modes
Depending on the input voltage (V = V
- V ), the
IN
DD
SS
MAX5972A operates in four different modes: PD detec-
tion, PD classification, mark event, and PD power. The
device enters PD detection mode when the input voltage
is between 1.4V and 10.1V. The device enters PD clas-
sification mode when the input voltage is between 12.6V
and 20V. The device enters PD power mode once the
If the voltage applied to the PD is reversed, install pro-
tection diodes at the input terminal to prevent internal
damage to the MAX5972A (see the Typical Application
Circuit). Since the PSE uses a slope technique (DV/DI) to
calculate the signature resistance, the DC offset due to
the protection diodes is subtracted and does not affect
the detection process.
input voltage exceeds V
.
ON
Detection Mode (1.4V ≤ V ≤ 10.1V)
In detection mode, the power source equipment (PSE)
IN
Classification Mode (12.6V ≤ V ≤ 20V)
IN
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD. This
allows the PSE to efficiently manage power distribution.
Class 0 to 5 is defined as shown in Table 1. (The IEEE
802.3af/at standard defines only Class 0 to 4 and Class 5
applies two voltages on V in the range of 1.4V to 10.1V
IN
(1V step minimum) and then records the current measure-
ments at the two points. The PSE then computes DV/DI
to ensure the presence of the 24.9kω signature resistor.
Connect the signature resistor (R
) from V
to DET for
DET
DD
for any special requirement.) An external resistor (R
)
CLS
proper signature detection. The MAX5972A pulls DET low
connected from CLS to V sets the classification current.
SS
8
______________________________________________________________________________________
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
Table 1. Setting Classification Current
IEEE 802.3at PD
CLASSIFICATION CURRENT
SPECIFICATION (mA)
MAXIMUM
POWER USED
BY PD
CLASS CURRENT SEEN AT
(mA)
R
(I)
V *
IN
(V)
CLS
V
CLASS
IN
(W)
MIN
0
MAX
4
MIN
0
MAX
5
0
1
2
3
4
5
0.44 to 12.95
0.44 to 3.94
3.84 to 6.49
6.49 to 12.95
12.95 to 25.5
> 25.5
615
117
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
9
12
20
30
44
64
8
13
21
31
45
68
66.5
43.7
30.9
21.3
17
26
36
52
16
25
35
51
*V is measured across the MAX5972A input V
to V .
SS
IN
DD
Power Mode (Wake Mode)
The MAX5972A enters power mode when V rises
The PSE determines the class of a PD by applying
a voltage at the PD input and measuring the current
sourced out of the PSE. When the PSE applies a volt-
age between 12.6V and 20V, the MAX5972A exhibits a
current characteristic with a value shown in Table 1. The
PSE uses the classification current information to classify
the power requirement of the PD. The classification cur-
IN
above the undervoltage lockout threshold (V ). When
ON
V
rises above V , the MAX5972A turns on the inter-
IN
ON
nal n-channel isolation MOSFET to connect V to RTN
SS
with inrush current limit internally set to 135mA (typ). The
isolation MOSFET is fully turned on when the voltage at
RTN is near V and the inrush current is reduced below
rent includes the current drawn by R
and the supply
SS
CLS
the inrush limit. Once the isolation MOSFET is fully turned
on, the MAX5972A changes the current limit to 800mA.
The open-drain power-good output (PG) remains low for
current of the MAX5972A so the total current drawn by
the PD is within the IEEE 802.3af/at standard figures. The
classification current is turned off whenever the device is
in power mode.
a minimum of t
until the power MOSFET fully turns
DELAY
on to keep the downstream DC-DC converter disabled
during inrush.
2-Event Classification and Detection
During 2-event classification, a Type 2 PSE probes PD
for classification twice. In the first classification event, the
PSE presents an input voltage between 12.6V and 20.5V
and the MAX5972A presents the programmed load
Undervoltage Lockout
The MAX5972A operates up to a 60V supply voltage with
a turn-on UVLO threshold (V ) at 35.4V and a turn-off
ON
I
. The PSE then drops the probing voltage below
CLASS
UVLO threshold (V
) at 31V. When the input voltage is
OFF
the mark event threshold of 10.1V and the MAX5972A
above V , the MAX5972A enters power mode and the
ON
presents the mark current (I ). This sequence is
MARK
repeated one more time.
internal MOSFET is turned on. When the input voltage
goes below V
turns off.
for more than t , the MOSFET
OFF_DLY
OFF
When the MAX5972A is powered by a Type 2 PSE, the
2-event identification output 2EC asserts low after the
internal isolation n-channel MOSFET is fully turned on.
Power-Good Output
An open-drain output (PG) is used to allow disabling
downstream DC-DC converter until the n-channel isola-
2EC current sink is turned off when V
goes below the
DD
UVLO threshold (V
above the UVLO threshold (V ), unless V
) and turns on when V
goes
goes
OFF
DD
tion MOSFET is fully turned on. PG is pulled low to V
SS
ON
DD
for a period of t
and until the internal isolation
DELAY
below V
to reset the latched output of the Type 2
THR
MOSFET is fully turned on. The PG is also pulled low
during sleep mode and coming out of thermal shutdown.
PSE detection flag.
Alternatively, the 2EC output also serves as a wall
adapter detection output when the MAX5972A is pow-
ered by an external wall power adapter. See the Wall
Power Adapter Detection and Operation section for more
information.
Thermal-Shutdown Protection
The MAX5972A includes thermal protection from exces-
sive heating. If the junction temperature exceeds the
thermal-shutdown threshold of +140NC, the MAX5972A
_______________________________________________________________________________________
9
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
turns off the internal power MOSFET and 2EC current
sink. When the junction temperature falls below +112NC,
the devices enter inrush mode and then return to power
mode. Inrush mode ensures the downstream DC-DC
converter is turned off as the internal power MOSFET is
turned on.
Applications Information
Operation with 12V Adapter
Layout Procedure
Careful PCB layout is critical to achieve high efficiency
and low EMI. Follow these layout guidelines for optimum
performance:
Wall Power Adapter Detection
and Operation
For applications where an auxiliary power source such
as a wall power adapter is used to power the PD,
the MAX5972A features wall power adapter detection.
The MAX5972A gives highest priority to the WAD and
smoothly switches the power supply to WAD when it is
1) Place the input capacitor, classification resistor, and
transient voltage suppressor as close as possible to
the MAX5972A.
2) Use large SMT component pads for power dissipat-
ing devices such as the MAX5972A and the external
diodes.
detected. Once the input voltage (V
- V ) exceeds
DD
SS
3) Use short and wide traces for high-power paths.
the mark event threshold, the MAX5972A enables wall
adapter detection. The wall power adapter is connected
from WAD to RTN. The MAX5972A detects the wall
power adapter when the voltage from WAD to RTN is
greater than 9V. When a wall power adapter is detected,
the internal n-channel isolation MOSFET turns off, 2EC
current sink turns on, and classification current is dis-
4) Use the MAX5972A evaluation kit layout as a refer-
ence.
5) Place enough vias in the pad for the EP of the
MAX5972A so that heat generated inside can be
effectively dissipated by the PCB copper. The rec-
ommended spacing for the vias is 1mm to 1.2mm
pitch. The thermal vias should be plated (1oz cop-
per) and have a small barrel diameter (0.3mm to
0.33mm).
abled if V is in the classification range.
IN
2-EVENT
CLASSIFICATION
(ASSERTED ON)
GND
V
2EC
DD
IN+
GND
ENABLE
RJ-45
AND
BRIDGE
PG
R
DET
2EC/WAD
RECTIFIER
24.9kI
DC-DC
CONVERTER
DET
CLS
68nF
WAD
MAX5972A
1.5mA
SMAJ58A
12V
BATTERY
R
CLS
IN-
V
SS
RTN
-54V
THIS CIRCUIT ACHIEVES
PROPER 2EC LOGIC WHEN
BATTERY IS < 12.5V
Figure 2. Typical Configuration When Using a 12V Wall Power Adapter
10 _____________________________________________________________________________________
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
Typical Application Circuit
ISOLATED 2-EVENT
CLASSIFICATION
OUTPUT
GND
GND
V
2EC
DD
PG
PG
V
AC
24.9kI
2EC/WAD
DET
68nF
WAD
MAX5972A
1.5mA
CLS
V
SMAJ58A
AC
24/48V
BATTERY
43.7I
RTN
V
RTN
SS
-54V
GND
33kI
249I
4.7µF
0.1µF
0.1µF
1.37MI
51.5kI
ISOLATED +5.3V/2A
ISOLATED RTN
GND
RTN
0.1µF
PG
ULVO/EN
IN
22µF
V
CC
UFLG
FB
V
CC
22.1I
NDRV
GND
RT
MAX15000
10kI
COMP
CS
CS
CS
649I
619I
8.2nF
1kI
0.1µF
18.1kI
0.75I
8.06kI
330pF
4.99kI
1kI
100pF
RTN
V
CC
4.99kI
33nF
8.06I
1kI
2.49kI
2.2nF
RTN
ISOLATED RTN
______________________________________________________________________________________ 11
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
Chip Information
Package Information
PROCESS: BiCMOS
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
16 TQFN-EP
T1655+4
21-0140
12 _____________________________________________________________________________________
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
8/09
Initial release
Removed the MAX5972B from the data sheet.
—
2/10
1–16
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
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13
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2010 Maxim Integrated Products
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