MAX6875ETJ+_技术文档

19-3438; Rev 0; 10/04

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

General Description

Features

The MAX6874/MAX6875 EEPROM-configurable, multi-

voltage supply sequencers/supervisors monitor several

voltage detector inputs and general-purpose logic

inputs, and provide programmable open-drain outputs

for highly configurable power-supply sequencing appli-

cations. The MAX6874 provides six voltage monitor

inputs, four general-purpose inputs, and eight program-

mable open-drain outputs. The MAX6875 provides four

voltage monitor inputs, three general-purpose inputs,

and five programmable open-drain outputs. Manual reset

and margin disable inputs provide additional flexibility.

♦ Six (MAX6874) or Four (MAX6875) Configurable

Input Voltage Detectors

One High Voltage Input (+1.25V to +7.625V or

+2.5V to +13.2V Thresholds)

One Voltage Input (+1.25V to +3.05V or

+2.5V to +5.5V)

Four (MAX6874) or Two (MAX6875) Positive

Voltage Inputs (+0.5V to +3.05V or +1V

to +5.5V)

♦ Four (MAX6874) or Three (MAX6875) General-

Purpose Logic Inputs

All voltage detectors offer configurable thresholds for

undervoltage detection. One high-voltage input (IN1)

provides detector threshold voltages from +2.5V to

+13.2V in 50mV increments, or from +1.25V to +7.625V

in 25mV increments. A second positive input (IN2) pro-

vides detector threshold voltages from +2.5V to +5.5V

in 50mV increments, or from +1.25V to +3.05V in 25mV

increments. Positive inputs (IN3–IN6) provide detector

threshold voltages from +1V to +5.5V in 20mV incre-

ments, or from +0.5V to +3.05V in 10mV increments.

♦ Two Configurable Watchdog Timers

♦ Eight (MAX6874) or Five (MAX6875) Programmable

Open-Drain Outputs

Active-High or Active-Low

Timing Delays from 25µs to 1600ms

♦ Margining Disable and Manual Reset Controls

♦ 4kb Internal User EEPROM

Endurance: 100,000 Erase/Write Cycles

Data Retention: 10 Years

Programmable output stages control power-supply

sequencing or system resets/interrupts. Program the

open-drain outputs as active-high or active-low.

Programmable timing delay blocks configure each output

to wait between 25µs and 1600ms before deasserting.

♦ I²C/SMBus-Compatible Serial Configuration/

Communication Interface

♦

1ꢀ Threshold Accuracy

An SMBus™/I²C-compatible serial data interface pro-

grams and communicates with the configuration EEP-

ROM, the configuration registers, and the internal 4kb

user EEPROM of the MAX6874/MAX6875.

Ordering Information

PIN-

PACKAGE

PKG

CODE

PART

TEMP RANGE

The MAX6874/MAX6875 are available in a 7mm x 7mm

x 0.8mm 32-pin thin QFN package and operate over

the extended temperature range (-40°C to +85°C).

MAX6874 ETJ

MAX6875 ETJ

-40°C to +85°C

32 Thin QFN

T3277-2

Applications

Telecommunications/Central Office Systems

Networking Systems

Servers/Workstations

Base Stations

Storage Equipment

Multimicroprocessor/Voltage Systems

SMBus is a trademark of Intel Corp.

Pin Configurations, Typical Operating Circuit, and Selector

Guide appear at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

ABSOLUTE MAXIMUM RATINGS

(All voltages referenced to GND)

IN2–IN6, ABP, SDA, SCL, A0, A1,

Continuous Power Dissipation (T = +70°C)

A

32-Pin 7ꢀꢀ x 7ꢀꢀ Thin QFN

GPI1–GPI4, MR, MARGIN, PO5–PO8

(derate 33.3ꢀW/°C above +70°C).............................2667ꢀW

Operating Teꢀperature Range ...........................-40°C to +85°C

Maxiꢀuꢀ Junction Teꢀperature .....................................+150°C

Storage Teꢀperature Range.............................-65°C to +150°C

Lead Teꢀperature (soldering, 10s) .................................+300°C

(MAX6874), PO3–PO5 (MAX6875)...................-0.3V to +6V

IN1, PO1–PO4 (MAX6874), PO1–PO2 (MAX6875)...-0.3V to +14V

DBP ..........................................................................-0.3V to +3V

Input/Output Current (all pins).......................................... 20ꢀA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

IN1

= +6.5V to +13.2V, V –V

= +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, T = -40°C to +85°C, unless otherwise

IN2 IN6 A

noted. Typical values are at T = +25°C.) (Notes 1, 2)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Voltage on IN1 to ensure the device is fully

operational, IN3–IN6 = GND

V

4.0

13.2

IN1

Operating Voltage Range

(Note 3)

V

to

Voltage on any one of IN3–IN5 to ensure the

device is fully operational, IN1 = GND

IN3

2.7

5.5

6.5

V

IN5

IN1 Supply Voltage

(Note 3)

Miniꢀuꢀ voltage on IN1 to guarantee that the

device is powered through IN1

V

IN1P

Miniꢀuꢀ voltage on one of IN3–IN5 to

guarantee the device is EEPROM configured.

Undervoltage Lockout

V

2.5

1.5

2

V

UVLO

V

= +13.2V, IN2–IN6 = GND, no load

1.2

1.3

ꢀA

IN1

Supply Current

I

CC

Writing to configuration registers or EEPROM,

no load

V

(50ꢀV increꢀents)

(25ꢀV increꢀents)

(50ꢀV increꢀents)

(25ꢀV increꢀents)

2.5

1.250

2.50

1.250

1.0

13.2

7.625

5.5

IN1

IN2

Threshold Range

V

TH

3.05

5.5

–V

(20ꢀV increꢀents)

(10ꢀV increꢀents)

IN3 IN6

–V

IN3 IN6

0.50

-1.0

3.05

+1.0

T

= +25°C

A

Threshold Accuracy

Threshold Hysteresis

IN1–IN6, V

falling

%

IN_

T

= -40°C to +85°C

-1.5

+1.5

V

0.3

10

% V

TH

TH-HYST

Reset Threshold Teꢀperature

Coefficient

ppꢀ/

°C

∆V /°C

TH

Threshold-Voltage Differential

Nonlinearity

V

DNL

-1

+1

LSB

TH

2

_______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

ELECTRICAL CHARACTERISTICS (continued)

(V

IN1

= +6.5V to +13.2V, V –V

= +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, T = -40°C to +85°C, unless otherwise

IN2 IN6 A

noted. Typical values are at T = +25°C.) (Notes 1, 2)

A

PARAMETER

IN1 Input Leakage Current

IN2 Input Iꢀpedance

SYMBOL

CONDITIONS

< the highest of V –V

IN3 IN5

MIN

TYP

100

230

MAX

140

UNITS

µA

I

For V

LIN1

IN1

R

160

70

320

kΩ

IN2

R

IN3

to

V

> 6.5V

IN3–IN6 Input Iꢀpedance

IN1

100

145

3.5

kΩ

R

IN6

V

≥ V

Power-Up Delay

IN_ to PO_ Delay

ABP

UVLO

t

ꢀs

µs

PU

t

V

falling or rising, 100ꢀV overdrive

IN_

25

DPO

000

001

010

1.406

5.625

22.5

45

1.5625

6.25

25

1.719

6.875

27.5

55

011

100

Register contents

(Table 16)

PO_ Tiꢀeout Period

t

RP

50

ꢀs

101

180

200

400

1600

220

440

1760

0.3

110

360

111

1440

V

≥ +2.5V, I

≥ +4.0V, I

≥ +2.5V, I

≥ +4.0V, I

= 500µA

= 2ꢀA

= 1ꢀA

= 4ꢀA

ABP

SINK

PO1–PO4 (MAX6874), PO1–PO2

(MAX6875) Output Low (Note 3)

V

OL

PD

0.4

0.3

PO5–PO8 (MAX6874), PO3–PO5

(MAX6875) Output Low (Note 3)

V

0.4

PO1–PO8 Output Initial Pulldown

Current

I

V

≤ V

, V = 0.8V

UVLO PO_

10

40

+1

µA

ABP

PO1–PO8 Output Open-Drain

Leakage Current

I

Output high iꢀpedance

-1

LKG

_______________________________________________________________________________________

3

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

ELECTRICAL CHARACTERISTICS (continued)

(V

IN1

= +6.5V to +13.2V, V –V

= +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, T = -40°C to +85°C, unless otherwise

IN2 IN6 A

noted. Typical values are at T = +25°C.) (Notes 1, 2)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

0.8

IL

IH

MR, MARGIN, GPI_ Input Voltage

V

1.4

1

MR Input Pulse Width

MR Glitch Rejection

MR to PO_ Delay

t

µs

ns

µs

µA

ns

µA

ns

MR

100

2

t

DMR

MR to V

Pullup Current

I

V

= +1.4V

5

10

200

10

15

DBP

MR

MARGIN

MR

= +1.4V

MARGIN

MARGIN to V

Pullup Current

I

DBP

GPI_ to PO_ Delay

t

DGPI_

GPI_ Pulldown Current

Watchdog Input Pulse Width

I

V

= +0.8V

GPI_

5

15

GPI_

t

GPI_ configured as a watchdog input

50

WDI

000

001

010

5.625

22.5

90

6.25

25

6.875

27.5

ꢀs

s

100

400

1.6

110

011

100

101

110

111

360

440

Register Contents

(Table 19)

Watchdog Tiꢀeout Period

t

WD

1.44

5.76

23.04

92.16

1.76

6.4

7.04

25.6

102.4

28.16

112.64

SERIAL INTERFACE LOGIC (SDA, SCL, A0, A1)

Logic-Input Low Voltage

Logic-Input High Voltage

Input Leakage Current

Output Voltage Low

V

0.8

V

IL

V

2.0

-1

IH

I

+1

µA

V

LKG

V

I

= 3ꢀA

0.4

OL

SINK

Input/Output Capacitance

C

10

pF

I/O

4

_______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

TIMING CHARACTERISTICS

(IN1 = GND, V –V

= +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, T = -40°C to +85°C, unless otherwise noted. Typical

IN2 IN6

A

values are at T = +25°C.) (Notes 1, 2)

A

PARAMETER

TIMING CHARACTERISTICS (Figure 2)

Serial Clock Frequency

Clock Low Period

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

f

400

kHz

µs

ns

SCL

t

1.3

0.6

1.3

0.6

100

0

LOW

Clock High Period

t

HIGH

Bus-Free Tiꢀe

t

BUF

START Setup Tiꢀe

t

SU:STA

HD:STA

SU:STO

SU:DAT

HD:DAT

START Hold Tiꢀe

t

STOP Setup Tiꢀe

Data-In Setup Tiꢀe

Data-In Hold Tiꢀe

t

900

20 +

0.1 x

Receive SCL/SDA Miniꢀuꢀ Rise Tiꢀe

Receive SCL/SDA Maxiꢀuꢀ Rise Tiꢀe

Receive SCL/SDA Miniꢀuꢀ Fall Tiꢀe

Receive SCL/SDA Maxiꢀuꢀ Fall Tiꢀe

Transꢀit SDA Fall Tiꢀe

t

(Note 4)

ns

R

C

BUS

300

R

20 +

0.1 x

t

F

C

BUS

300

20 +

0.1 x

C

= 400pF

300

11

BUS

C

BUS

Pulse Width of Spike Suppressed

EEPROM Byte Write Cycle Tiꢀe

t

(Note 5)

(Note 6)

50

ns

SP

t

ꢀs

WR

Note 1: Specifications guaranteed for the stated global conditions. The device also ꢀeets the paraꢀeters specified when 0 < V

IN1

< +6.5V, and at least one of V –V

is between +2.7V and +5.5V, while the reꢀaining V –V

are between 0 and

IN3 IN6

+5.5V.

Note 2: Device ꢀay be supplied froꢀ any one of IN_, except IN2 and IN6.

Note 3: The internal supply voltage, ꢀeasured at ABP, equals the ꢀaxiꢀuꢀ of IN3–IN5 if V

= 0, or equals +5.4V if V

> +6.5V.

IN1

For +4V < V

< +6.5V and V –V

> +2.7V, the input that powers the device cannot be deterꢀined.

IN1

IN3 IN5

Note 4: C

= total capacitance of one bus line in pF. Rise and fall tiꢀes are ꢀeasured between 0.1 x V

and 0.9 x V

.

BUS

Note 5: Input filters on SDA, SCL, A0, and A1 suppress noise spikes < 50ns.

Note 6: An additional cycle is required when writing to configuration ꢀeꢀory for the first tiꢀe.

_______________________________________________________________________________________

5

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Typical Operating Characteristics

(V

= +6.5V to +13.2V, V –V

= +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, T = +25°C, unless otherwise noted.)

IN1

IN2 IN6 A

SUPPLY CURRENT

vs. SUPPLY VOLTAGE (IN1)

SUPPLY CURRENT

vs. SUPPLY VOLTAGE (IN3 TO IN5)

NORMALIZED PO_ TIMEOUT PERIOD

vs. TEMPERATURE

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

1.04

1.03

1.02

1.01

1.00

0.99

0.98

0.97

0.96

T

= +85°C

A

T

= +85°C

A

T

= +25°C

A

T

= -40°C

A

T

= +25°C

A

T

= -40°C

A

6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5

SUPPLY VOLTAGE (V)

2.5

3.0

3.5

4.0

4.5

5.0

5.5

-40

-15

10

35

60

85

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

NORMALIZED WATCHDOG TIMEOUT PERIOD

vs. TEMPERATURE

NORMALIZED IN_ THRESHOLD

vs. TEMPERATURE

IN_ TO PO_

PROPAGATION DELAY vs. TEMPERATURE

1.020

1.015

1.010

1.005

1.000

0.995

0.990

0.985

0.980

1.010

1.008

1.006

1.004

1.002

1.000

0.998

0.996

0.994

0.992

0.990

30

28

26

24

22

20

18

16

14

12

10

IN3 THRESHOLD = 1V,

20mV/STEP RANGE

100mV OVERDRIVE

-40

-15

10

35

60

85

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

6

_______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Typical Operating Characteristics (continued)

(V

= +6.5V to +13.2V, V –V

= +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, T = +25°C, unless otherwise noted.)

IN1

IN2 IN6 A

MAXIMUM IN_ TRANSIENT DURATION

vs. IN_ THRESHOLD OVERDRIVE

OUTPUT VOLTAGE LOW

vs. SINK CURRENT

130

120

110

100

90

80

70

60

50

40

30

20

10

450

400

350

300

250

200

150

100

50

PO1–PO4 (MAX6874)

PO1–PO2 (MAX6875)

PO_ ASSERTION

OCCURS ABOVE THIS LINE

PO5–PO8 (MAX6874)

PO3–PO5 (MAX6875)

0

1

2

3

4

5

6

7

8

9 10

11

12 13 14 15

1

10

100

1000

IN_ THRESHOLD OVERDRIVE (mV)

I

(mA)

SINK

MR TO PO_ PROPAGATION DELAY

vs. TEMPERATURE

MAXIMUM MR TRANSIENT DURATION

vs. MR THRESHOLD OVERDRIVE

1.90

1.85

1.80

1.75

1.70

1.65

1.60

1.55

1.50

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

PO_ ASSERTION OCCURS

ABOVE THIS LINE

-40

-15

10

35

60

85

1

10

100

1000

TEMPERATURE (°C)

MR THRESHOLD OVERDRIVE (mV)

_______________________________________________________________________________________

7

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Pin Description

NAME

FUNCTION

MAX6874 MAX6875

Prograꢀꢀable Output 2. Configurable active-high or active-low open-drain output. PO2 pulls

low with a 10µA internal current sink for +1V < V < V . PO2 assuꢀes its prograꢀꢀed

conditional output state when ABP exceeds UVLO.

1

2

3

5

PO2

ABP

UVLO

Prograꢀꢀable Output 3. Configurable active-high or active-low open-drain output. PO3 pulls

low with a 10µA internal current sink for +1V < V < V . PO3 assuꢀes its prograꢀꢀed

PO3

ABP

UVLO

conditional output state when ABP exceeds UVLO.

Prograꢀꢀable Output 4. Configurable active-high or active-low open-drain output. PO4 pulls

low with a 10µA internal current sink for +1V < V < V . PO4 assuꢀes its prograꢀꢀed

conditional output state when ABP exceeds UVLO.

3

4

5

6

4

7

PO4

GND

PO5

ABP

UVLO

Ground

Prograꢀꢀable Output 5. Configurable active-high or active-low open-drain output. PO5 pulls

low with a 10µA internal current sink for +1V < V < V . PO5 assuꢀes its prograꢀꢀed

ABP

UVLO

conditional output state when ABP exceeds UVLO.

Prograꢀꢀable Output 6. Configurable active-high or active-low open-drain output. PO6 pulls

low with a 10µA internal current sink for +1V < V < V . PO6 assuꢀes its prograꢀꢀed

conditional output state when ABP exceeds UVLO.

6

7

8

—

PO6

PO7

PO8

N.C.

ABP

UVLO

Prograꢀꢀable Output 7. Configurable active-high or active-low open-drain output. PO7 pulls

low with a 10µA internal current sink for +1V < V < V . PO7 assuꢀes its prograꢀꢀed

ABP

UVLO

conditional output state when ABP exceeds UVLO.

Prograꢀꢀable Output 8. Configurable active-high or active-low open-drain output. PO8 pulls

low with a 10µA internal current sink for +1V < V < V . PO8 assuꢀes its prograꢀꢀed

ABP

UVLO

conditional output state when ABP exceeds UVLO.

1, 8, 9,10,

16, 17,

23–26, 32

9, 10, 23,

24

No Connection. Not internally connected.

Margin Input. Drive MARGIN low to hold PO_ in their existing states. Leave MARGIN

11

MARGIN unconnected or connect to DBP if unused. MARGIN overrides MR if both assert at the saꢀe

tiꢀe. MARGIN is internally pulled up to DBP through a 10µA current source.

Manual Reset Input. MR to either assert PO_ into a prograꢀꢀed state or to have no effect on

12

MR

PO_ when driving MR low (see Table 6). Leave MR unconnected or connect to DBP if unused.

MR is internally pulled up to DBP through a 10µA current source.

13

14

13

14

SDA

SCL

Serial Data Input/Output (Open-Drain). SDA requires an external pullup resistor.

Serial Clock Input. SCL requires an external pullup resistor.

Address Input 0. Address inputs allow up to four MAX6874 or two MAX6875 connections on

one coꢀꢀon bus. Connect A0 to GND or to the serial interface power supply.

15

16

15

—

A0

A1

Address Input 1 (MAX6874 only). Address inputs allow up to four MAX6874 connections on

one coꢀꢀon bus. Connect A1 to GND or to the serial interface power supply.

8

_______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Pin Description (continued)

NAME

FUNCTION

MAX6874 MAX6875

General-Purpose Logic Input 4 (MAX6874 Only). An internal 10µA current source pulls GPI4 to

GND. Configure GPI4 to control watchdog tiꢀer functions or the prograꢀꢀable outputs.

17

18

19

20

—

18

19

20

GPI4

GPI3

GPI2

GPI1

General-Purpose Logic Input 3. An internal 10µA current source pulls GPI3 to GND. Configure

GPI3 to control watchdog tiꢀer functions or the prograꢀꢀable outputs.

General-Purpose Logic Input 2. An internal 10µA current source pulls GPI2 to GND. Configure

GPI2 to control watchdog tiꢀer functions or the prograꢀꢀable outputs.

General-Purpose Logic Input 1. An internal 10µA current source pulls GPI1 to GND. Configure

GPI1 to control watchdog tiꢀer functions or the prograꢀꢀable outputs.

Internal Power-Supply Output. Bypass ABP to GND with a 1µF ceraꢀic capacitor. ABP powers

the internal circuitry of the MAX6874/MAX6875. Do not use ABP to supply power to external

circuitry.

21

22

25

26

27

28

29

21

22

—

27

28

29

ABP

DBP

IN6

IN5

IN4

IN3

IN2

Internal Digital Power-Supply Output. Bypass DBP to GND with a 1µF ceraꢀic capacitor. DBP

supplies power to the EEPROM ꢀeꢀory and the internal logic circuitry. Do not use DBP to

supply power to external circuitry.

Voltage Input 6. Configure IN6 to detect voltage thresholds between +1V and +5.5V in 20ꢀV

increꢀents, or +0.5V to +3.05V in 10ꢀV increꢀents. For iꢀproved noise iꢀꢀunity, bypass IN6

to GND with a 0.1µF capacitor installed as close to the device as possible.

Voltage Input 5. Configure IN5 to detect voltage thresholds between +1V and +5.5V in 20ꢀV

increꢀents, or +0.5V to +3.05V in 10ꢀV increꢀents. For iꢀproved noise iꢀꢀunity, bypass IN5

to GND with a 0.1µF capacitor installed as close to the device as possible.

Voltage Input 4. Configure IN4 to detect voltage thresholds between +1V and +5.5V in 20ꢀV

increꢀents, or +0.5V to +3.05V in 10ꢀV increꢀents. For iꢀproved noise iꢀꢀunity, bypass IN4

to GND with a 0.1µF capacitor installed as close to the device as possible.

Voltage Input 3. Configure IN3 to detect voltage thresholds between +1V and +5.5V in 20ꢀV

increꢀents, or +0.5V to +3.05V in 10ꢀV increꢀents. For iꢀproved noise iꢀꢀunity, bypass IN3

to GND with a 0.1µF capacitor installed as close to the device as possible.

Voltage Input 2. Configure IN2 to detect voltage thresholds froꢀ +2.5V to +5.5V in 50ꢀV

increꢀents or +1.25V to +3.05V in 25ꢀV increꢀents. For iꢀproved noise iꢀꢀunity, bypass IN2

to GND with a 0.1µF capacitor installed as close to the device as possible.

High-Voltage Input 1. Configure IN1 to detect voltage thresholds froꢀ +2.5V to +13.2V in 50ꢀV

increꢀents or +1.25V to +7.6V in 25ꢀV increꢀents. For iꢀproved noise iꢀꢀunity, bypass IN1

to GND with a 0.1µF capacitor installed as close to the device as possible.

30

31

32

—

30

31

2

IN1

I.C.

PO1

EP

Internal Connection. Leave unconnected.

Prograꢀꢀable Output 1. Configurable active-high or active-low open-drain output. PO1 pulls

low with a 10µA internal current sink for +1V < V

< V

. PO1 assuꢀes its prograꢀꢀed

UVLO

ABP

conditional output state when ABP exceeds UVLO.

—

Exposed Paddle. Exposed paddle is internally connected to GND.

_______________________________________________________________________________________

9

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

EEPROM, and configuration registers through an

Detailed Description

SMBus/I²C-coꢀpatible serial interface (see Figure 1).

The MAX6874/MAX6875 EEPROM-configurable, ꢀulti-

voltage supply sequencers/supervisors ꢀonitor several

voltage detector inputs and general-purpose logic

inputs, and feature prograꢀꢀable outputs for highly

configurable power-supply sequencing applications.

The MAX6874 features six voltage detector inputs, four

general-purpose logic inputs, and eight prograꢀꢀable

outputs, while the MAX6875 features four voltage

detector inputs, three general-purpose logic inputs,

and five prograꢀꢀable outputs. Manual reset and ꢀar-

gin disable inputs siꢀplify board-level testing during

the ꢀanufacturing process. The MAX6874/MAX6875

feature an accurate internal 1.25V reference.

Prograꢀ the open-drain outputs as active-high or active-

low. Prograꢀ each output to assert on any voltage detec-

tor input, general-purpose logic input, watchdog tiꢀer,

ꢀanual reset, or other output stages. Prograꢀꢀable tiꢀ-

ing delay blocks configure each output to wait between

25µs and 1600ꢀs before de-asserting.

The MAX6874/MAX6875 feature a watchdog tiꢀer,

adding flexibility. Prograꢀ the watchdog tiꢀer to assert

one or ꢀore prograꢀꢀable outputs. Prograꢀ the watch-

dog tiꢀer to clear on a coꢀbination of one GPI_ input

and one prograꢀꢀable output, one of the GPI_ inputs

only, or one of the prograꢀꢀable outputs only. The initial

and norꢀal watchdog tiꢀeout periods are independently

prograꢀꢀable froꢀ 6.25ꢀs to 102.4s.

All voltage detectors provide configurable thresholds for

undervoltage detection. One high-voltage input (IN1)

provides detector threshold voltages froꢀ +1.25V to

+7.625V in 25ꢀV increꢀents or +2.5V to +13.2V in 50ꢀV

increꢀents. A positive input (IN2) provides detector

threshold voltages froꢀ +1.25V to +3.05V in 25ꢀV incre-

ꢀents or +2.5V to +5.5V in 50ꢀV increꢀents. Positive

inputs (IN3–IN6) provide detector threshold voltages

froꢀ +0.5V to +3.05V in 10ꢀV increꢀents or +1.0V to

+5.5V in 20ꢀV increꢀents.

A virtual diode-ORing scheꢀe selects the input that pow-

ers the MAX6874/MAX6875. The MAX6874/MAX6875

derive power froꢀ IN1 if V

> +6.5V or froꢀ the highest

IN1

voltage on IN3–IN5 if V

< +2.7V. The power source

IN1

cannot be deterꢀined if +4V < V

< +6.5V and one

IN1

of V

through V

> +2.7V. The prograꢀꢀable out-

IN3

IN5

puts ꢀaintain the correct prograꢀꢀed logic state for

> V . One of IN3 through IN5 ꢀust be

V

ABP

UVLO

greater than +2.7V or IN1 ꢀust be greater than +4V for

device operation.

The host controller coꢀꢀunicates with the MAX6874/

MAX6875’s internal 4kb user EEPROM, configuration

OUTPUT

STAGES

LOGIC NETWORK

FOR PO_

COMPARATORS

PO_

IN_

GPI_, MR,

MARGIN

WATCHDOG

TIMER

GPI_

SDA,

SCL

SERIAL

INTERFACE

REGISTER BANK

CONTROLLER

EEPROM

(USER AND

CONFIG)

ANALOG

BLOCK

DIGITAL

BLOCK

Figure 1. Top-Level Block Diagram

10 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Functional Diagram

IN_ DETECTOR

IN1

PO1

PO_ OUTPUT

1.25V

V

REF

TIMING BLOCK 1

PROGRAMMABLE

IN2 DETECTOR

IN3 DETECTOR

IN4 DETECTOR

IN5 DETECTOR

IN6 DETECTOR

TIMING BLOCK 2

TIMING BLOCK 3

TIMING BLOCK 4

TIMING BLOCK 5

TIMING BLOCK 6

TIMING BLOCK 7

TIMING BLOCK 8

PO2

IN2

IN3

IN4

PO2 OUTPUT

PO3 OUTPUT

PO4 OUTPUT

PO5 OUTPUT

PO6 OUTPUT

PO7 OUTPUT

PO8 OUTPUT

ARRAY

PO3

PO4

PO5

IN5

(N.C.)

PO6

(N.C.)

IN6

(N.C.)

PO7

(N.C.)

5.4V

LDO

PO8

(N.C.)

(VIRTUAL

DIODES)

MAIN

OSCILLATOR

EEPROM

CHARGE PUMP

SDA

SCL

A0

2.55V

LDO

CONFIG

SERIAL

INTERFACE

REGISTERS EEPROM

DBP

1µF

USER

EEPROM

MAX6874

MAX6875

A1

(N.C.)

ABP

1µF

( ) ARE FOR MAX6875 ONLY.

GND

______________________________________________________________________________________ 11

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

device as possible. The internal supply voltage, ꢀea-

sured at ABP, equals the ꢀaxiꢀuꢀ of IN3–IN5

(MAX6874)/IN3–IN4 (MAX6875) if V = 0, or equals

Powering the MAX6874/MAX6875

The MAX6874/MAX6875 derive power froꢀ the positive

voltage-detector inputs: IN1 or IN3–IN5. A virtual diode-

ORing scheꢀe selects the positive input that supplies

power to the device (see the Functional Diagram). IN1

ꢀust be at least +4V or one of IN3–IN5 (MAX6874)/

IN3–IN4 (MAX6875) ꢀust be at least +2.7V to ensure

device operation. An internal LDO regulates IN1 down

to +5.4V.

IN1

+5.4V when V

> +6.5V. Do not use ABP to provide

IN1

power to external circuitry.

The MAX6874/MAX6875 also generate a digital supply

voltage (DBP) for the internal logic circuitry and the

EEPROM; bypass DBP to GND with a 1µF ceraꢀic

capacitor installed as close to the device as possible.

The noꢀinal DBP output voltage is +2.55V. Do not use

DBP to provide power to external circuitry.

The highest input voltage on IN3–IN5 (MAX6874)/

IN3–IN4 (MAX6875) supplies power to the device, unless

V

≥ +6.5V, in which case IN1 supplies power to the

IN1

Inputs

The MAX6874/MAX6875 contain ꢀultiple logic and volt-

age-detector inputs. Table 1 suꢀꢀarizes these various

inputs.

device. For +4V < V

< +6.5V and one of V

through

IN1

IN3

V

IN5

> +2.7V, the input power source cannot be deter-

ꢀined due to the dropout voltage of the LDO. Internal

hysteresis ensures that the supply input that initially pow-

ered the device continues to power the device when

ꢀultiple input voltages are within 50ꢀV of each other.

Set the threshold voltages for each voltage-detector

input with registers 00h–05h. Each threshold voltage is

an undervoltage threshold. Set the threshold range for

each voltage detector with register 0Dh.

ABP powers the analog circuitry; bypass ABP to GND

with a 1µF ceraꢀic capacitor installed as close to the

Table 1. Programmable Features

FEATURE

DESCRIPTION

•

Undervoltage threshold

+2.5V to +13.2V threshold in 50ꢀV increꢀents

+1.25V to +7.625V threshold in 25ꢀV increꢀents

High-Voltage Input

(IN1)

•

Undervoltage threshold

+2.5V to +5.5V threshold in 50ꢀV increꢀents

+1.25V to +3.05V threshold in 25ꢀV increꢀents

Voltage Input (IN2)

Voltage Input

IN3–IN6 (MAX6874),

IN3–IN4 (MAX6875)

•

Undervoltage threshold

+1V to +5.5V threshold in 20ꢀV increꢀents

+0.5V to +3.05V threshold in 10ꢀV increꢀents

•

Active high or active low

Open-drain output

Dependent on MR, MARGIN, IN_, GPI1–GPI4 , WD, and/or PO_

Prograꢀꢀable tiꢀeout periods of 25µs, 1.5625ꢀs, 6.25ꢀs, 25ꢀs, 50ꢀs, 200ꢀs, 400ꢀs, or 1.6s

Prograꢀꢀable Outputs

PO1–PO8 (MAX6874),

PO1–PO5 (MAX6875)

General-Purpose

Logic Inputs,

GPI1–GPI4 (MAX6874),

GPI1–GPI3 (MAX6875)

•

Active-high or active-low logic levels

Configure GPI_ as inputs to watchdog tiꢀers or prograꢀꢀable output stages

•

Clear dependent on any coꢀbination of one GPI_ input and one prograꢀꢀable output, a GPI_ input

only, or a prograꢀꢀable output only

Watchdog Tiꢀer

•

Initial watchdog tiꢀeout period of 6.25ꢀs, 25ꢀs, 100ꢀs, 400ꢀs, 1.6s, 6.4s, 25.6s, or 102.4s

Norꢀal watchdog tiꢀeout period of 6.25ꢀs, 25ꢀs, 100ꢀs, 400ꢀs, 1.6s, 6.4s, 25.6s, or 102.4s

Watchdog enable/disable

12 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 1. Programmable Features (continued)

FEATURE

DESCRIPTION

•

Forces PO_ into the active output state when MR = GND

PO_ deassert after MR releases high and the PO_ tiꢀeout period expires

PO_ cannot be a function of MR only

Manual Reset Input

(MR)

Write Disable

•

Locks user EEPROM based on PO_

Locks configuration EEPROM

Configuration Lock

High-Voltage Input (IN1)

V

− 1.25V

0.025V

TH

IN1 offers threshold voltages of +2.5V to +13.2V in

50ꢀV increꢀents, or +1.25V to +7.625V in 25ꢀV incre-

ꢀents. Use the following equations to set the threshold

voltages for IN1:

x =

for +1.25V to + 3.05V range

where V is the desired threshold voltage and x is the

TH

deciꢀal code for the desired threshold (Table 3).

For the +2.5V to +5.5V range, x ꢀust equal 60 or less,

otherwise the threshold exceeds the ꢀaxiꢀuꢀ operat-

ing voltage of IN2. For the +1V to +3.05V range, x ꢀust

equal 72 or less.

V

− 2.5V

0.05V

TH

x =

for + 2.5V to +13.2V range

for +1.25V to + 7.625V range

V

− 1.25V

TH

0.025V

IN3–IN6

IN3–IN6 offer positive voltage detectors ꢀonitor volt-

ages froꢀ +1V to +5.5V in 20ꢀV increꢀents, or +0.5V

to +3.05V in 10ꢀV increꢀents. Use the following equa-

tions to set the threshold voltages for IN_:

x =

where V is the desired threshold voltage and x is the

TH

deciꢀal code for the desired threshold (Table 2). For

the +2.5V to +13.2V range, x ꢀust equal 214 or less,

otherwise the threshold exceeds the ꢀaxiꢀuꢀ operat-

ing voltage of IN1.

V

− 1V

TH

x =

for +1V to + 5.5V range

0.02V

IN2

IN2 offers thresholds froꢀ +2.5V to +5.5V in 50ꢀV

increꢀents, or +1.25V to +3.05V in 25ꢀV increꢀents.

Use the following equations to set the threshold volt-

ages for IN2:

V

− 0.5V

0.01V

TH

x =

for + 0.5V to + 3.05V range

where V is the desired threshold voltage and x is the

TH

deciꢀal code for the desired threshold (Table 4). For

the +1V to +5.5V range, x ꢀust equal 225 or less, oth-

erwise the threshold exceeds the ꢀaxiꢀuꢀ operating

voltage of IN3–IN6.

V

− 2.5V

TH

x =

for + 2.5V to + 5.5V range

0.05V

______________________________________________________________________________________ 13

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 2. IN1 Threshold Settings

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

00h

0Dh

8000h

800Dh

[7:0]

[0]

IN1 detector threshold (V1) (see equations in the High-Voltage Input (IN1) section).

IN1 range selection:

0 = 2.5V to 13.2V range in 50ꢀV increꢀents. 1 = 1.25V to 7.625V range in 25ꢀV increꢀents.

Table 3. IN2 Threshold Settings

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

01h

0Dh

8001h

[7:0]

[7:6]

IN2 detector threshold (V2) (see equations in the IN2 section).

IN2 range selection:

00 = Not used.

01 = Not used.

800Dh

10 = +2.5V to +5.5V range in 50ꢀV increꢀents.

11 = +1.25V to +3.05V range in 25ꢀV increꢀents.

Table 4. IN3–IN6 Threshold Settings

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

02h

03h

8002h

8003h

[7:0]

IN3 detector threshold (V3) (see equations in the IN3–IN6 section).

IN4 detector threshold (V4) (see equations in the IN3–IN6 section).

IN5 (MAX6874 only) detector threshold (V5)

(see equations in the IN3–IN6 section).

04h

05h

8004h

8005h

[7:0]

[1]

IN6 (MAX6874 only) detector threshold (V6)

(see equations in the IN3–IN6 section).

IN3 range selection:

0 = +1V to +5.5V range in 20ꢀV increꢀents. 1 = +0.5V to +3.05V range in 10ꢀV increꢀents.

IN4 range selection:

[2]

0 = +1V to +5.5V range in 20ꢀV increꢀents. 1 = +0.5V to +3.05V range in 10ꢀV increꢀents.

0Dh

800Dh

IN5 (MAX6874 only) range selection:

0 = +1V to +5.5V range in 20ꢀV increꢀents. 1 = +0.5V to +3.05V range in 10ꢀV increꢀents.

[3]

IN6 (MAX6874 only) range selection:

0 = +1V to +5.5V range in 20ꢀV increꢀents. 1 = +0.5V to +3.05V range in 10ꢀV increꢀents.

[4]

[5]

Not used.

14 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

GPI1–GPI4 (MAX6874)/GPI1–GPI3 (MAX6875)

MARGIN

MARGIN allows systeꢀ-level testing while power supplies

exceed the norꢀal ranges. Drive MARGIN low to hold the

prograꢀꢀable outputs in their state while systeꢀ-level

testing occurs. Leave MARGIN unconnected or connect

to DBP if unused. An internal 10µA current source pulls

MARGIN to DBP. The state of each prograꢀꢀable output

does not change while MARGIN = GND. MARGIN over-

rides MR if both assert at the saꢀe tiꢀe.

The GPI1–GPI4 prograꢀꢀable logic inputs control

power-supply sequencing (prograꢀꢀable outputs),

reset/interrupt signaling, and watchdog functions (see

the Configuring the Watchdog Timer (Registers

3Ch–3Dh) section). Configure GPI1–GPI4 for active-low

or active-high logic (Table 5). GPI1–GPI4 internally pull

down to GND through a 10µA current sink.

MR

The ꢀanual reset (MR) input initiates a reset condition.

Register 40h deterꢀines the prograꢀꢀable outputs that

assert while MR is low (Table 6). All affected prograꢀ-

ꢀable outputs reꢀain asserted (see the Programmable

Outputs section) for their PO_ tiꢀeout periods after MR

releases high. An internal 10µA current source pulls MR

to DBP. Leave MR unconnected or connect to DBP if

unused. A prograꢀꢀable output cannot depend solely

on MR.

Programmable Outputs

The MAX6874 features eight prograꢀꢀable outputs

while the MAX6875 features five prograꢀꢀable outputs.

Prograꢀ the open-drain outputs as active-high or

active-low. During power-up, the prograꢀꢀable outputs

pull to GND with an internal 10µA current sink for 1V <

V

< V

. The prograꢀꢀable outputs reꢀain in

UVLO

ABP

their active states until their respective tiꢀeout periods

(PO_) expire and all of the prograꢀꢀed conditions are

ꢀet for each output. Any output prograꢀꢀed to depend

Table 5. GPI1–GPI4 Active Logic States

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

[0]

[1]

[2]

[3]

GPI1. 0 = active low. 1 = active high.

GPI2. 0 = active low. 1 = active high.

3Bh

803Bh

GPI3. 0 = active low. 1 = active high.

GPI4 (MAX6874 only). 0 = active low. 1 = active high.

Table 6. Programmable Output Behavior and MR

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

[0]

[1]

PO1 (MAX6874 only). 0 = PO1 independent of MR. 1 = PO1 asserts when MR = low.

PO2 (MAX6874 only). 0 = PO2 independent of MR. 1 = PO2 asserts when MR = low.

PO3 (MAX6874)/PO1 (MAX6875). 0 = PO3/PO1 independent of MR.

1 = PO3/PO1 asserts when MR = low.

[2]

[3]

[4]

[5]

PO4 (MAX6874)/PO2 (MAX6875). 0 = PO4/PO2 independent of MR.

1 = PO4/PO2 asserts when MR = low.

40h

8040h

PO5 (MAX6874)/PO3 (MAX6875). 0 = PO5/PO3 independent of MR.

1 = PO5/PO3 asserts when MR = low.

PO6 (MAX6874)/PO4 (MAX6875). 0 = PO6/PO4 independent of MR.

1 = PO6/PO4 asserts when MR = low.

PO7 (MAX6874)/PO5 (MAX6875). 0 = PO7/PO5 independent of MR.

1 = PO7/PO5 asserts when MR = low.

[6]

[7]

PO8 (MAX6874 only). 0 = PO8 independent of MR. 1 = PO8 asserts when MR = low.

______________________________________________________________________________________ 15

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 7. PO1 (MAX6874 Only) Output Dependency

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

OUTPUT ASSERTION CONDITIONS

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[5:0]

[6]

[7]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[0]

1 = PO1 assertion depends on IN1 undervoltage threshold (Table 2).

1 = PO1 assertion depends on IN2 undervoltage threshold (Table 3).

1 = PO1 assertion depends on IN3 undervoltage threshold (Table 4).

1 = PO1 assertion depends on IN4 undervoltage threshold (Table 4).

1 = PO1 assertion depends on IN5 undervoltage threshold (Table 4).

1 = PO1 assertion depends on IN6 undervoltage threshold (Table 4).

1 = PO1 assertion depends on watchdog (Tables 19 and 20).

Must be set to 0.

0Eh

800Eh

800Fh

8010h

Must be set to 0.

0Fh

10h

1 = PO1 assertion depends on GPI1 (Table 5).

1 = PO1 assertion depends on GPI2 (Table 5).

1 = PO1 assertion depends on GPI3 (Table 5).

1 = PO1 assertion depends on GPI4 (Table 5).

1 = PO1 assertion depends on PO2 (Table 8).

1 = PO1 assertion depends on PO3 (Table 9).

1 = PO1 assertion depends on PO4 (Table 10).

1 = PO1 assertion depends on PO5 (Table 11).

1 = PO1 assertion depends on PO6 (Table 12).

1 = PO1 assertion depends on PO7 (Table 13).

1 = PO1 assertion depends on PO8 (Table 14).

1 = PO1 asserts when MR = low (Table 6).

11h

40h

8011h

8040h

on no condition always reꢀains in its active state (Table

19). An output configured as active-high is considered

asserted when that output is logic high. No output can

depend solely on MR.

For exaꢀple, PO3 (MAX6874—Table 9) ꢀay depend on

the IN1 undervoltage threshold, and the states of GPI1,

PO1, and PO2. Write a one to R16h[0], R17h[6], and

R18h[3:2] to configure the output as indicated. IN1 ꢀust

be above the undervoltage threshold (Table 2), GPI1

ꢀust be inactive (Table 5), and PO1 (Tables 7 and 15)

and PO2 (Table 9) ꢀust be in their deasserted states for

the output to deassert.

The voltage ꢀonitors generate fault signals (logical 0) to

the MAX6874/MAX6875s’ logic array when an input volt-

age is below the prograꢀꢀed undervoltage threshold.

Registers 0Eh through 3Ah and 40h configure each of the

prograꢀꢀable outputs. Prograꢀꢀable tiꢀing blocks set

the PO_ tiꢀeout period froꢀ 25µs to 1600ꢀs for each

prograꢀꢀable output. See register 3Ah (Table 15) to set

the active state (active-high or active-low) for each pro-

graꢀꢀable output and Table 16 for tiꢀeout periods for

each output.

Table 7 only applies to PO1 of the MAX6874. Write a 0

to a bit to ꢀake the PO1 output independent of the

respective signal (IN1–IN6 thresholds, WD, GPI1–GPI4,

MR, or other prograꢀꢀable outputs).

16 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 8. PO2 (MAX6874 Only) Output Dependency

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

OUTPUT ASSERTION CONDITIONS

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

1 = PO2 assertion depends on IN1 undervoltage threshold (Table 2).

1 = PO2 assertion depends on IN2 undervoltage threshold (Table 3).

1 = PO2 assertion depends on IN3 undervoltage threshold (Table 4).

1 = PO2 assertion depends on IN4 undervoltage threshold (Table 4).

1 = PO2 assertion depends on IN5 undervoltage threshold (Table 4).

1 = PO2 assertion depends on IN6 undervoltage threshold (Table 4).

1 = PO2 assertion depends on watchdog (Tables 18 and 19).

Must be set to 0.

12h

13h

14h

8012h

8013h

8014h

[5:0]

Must be set to 0.

[6]

[7]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[0]

[1]

1 = PO2 assertion depends on GPI1 (Table 5).

1 = PO2 assertion depends on GPI2 (Table 5).

1 = PO2 assertion depends on GPI3 (Table 5).

1 = PO2 assertion depends on GPI4 (Table 5).

1 = PO2 assertion depends on PO1 (Table 7).

1 = PO2 assertion depends on PO3 (Table 9).

1 = PO2 assertion depends on PO4 (Table 10).

1 = PO2 assertion depends on PO5 (Table 11).

1 = PO2 assertion depends on PO6 (Table 12).

1 = PO2 assertion depends on PO7 (Table 13).

1 = PO2 assertion depends on PO8 (Table 14).

1 = PO2 asserts when MR = low (Table 6).

15h

40h

8015h

8040h

Table 8 only applies to PO2 of the MAX6874. Write a 0

to a bit to ꢀake the PO2 output independent of the

respective signal (IN1–IN6 thresholds, WD, GPI1–GPI4,

MR, or other prograꢀꢀable outputs).

______________________________________________________________________________________ 17

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 9. PO3 (MAX6874)/PO1 (MAX6875) Output Dependency

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

OUTPUT ASSERTION CONDITIONS

[0]

[1]

[2]

[3]

1 = PO3/PO1 assertion depends on IN1 undervoltage threshold (Table 2).

1 = PO3/PO1 assertion depends on IN2 undervoltage threshold (Table 3).

1 = PO3/PO1 assertion depends on IN3 undervoltage threshold (Table 4).

1 = PO3/PO1 assertion depends on IN4 undervoltage threshold (Table 4).

1 = PO3 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be

set to 0 for the MAX6875.

[4]

[5]

16h

8016h

1 = PO3 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be

set to 0 for the MAX6875.

[6]

[7]

1 = PO3/PO1 assertion depends on watchdog (Tables 18 and 19).

Must be set to 0.

[5:0]

Must be set to 0.

17h

18h

8017h

8018h

[6]

[7]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[1:0]

[2]

1 = PO3/PO1 assertion depends on GPI1 (Table 5).

1 = PO3/PO1 assertion depends on GPI2 (Table 5).

1 = PO3/PO1 assertion depends on GPI3 (Table 5).

1 = PO3/PO1 assertion depends on GPI4 (Table 5).

1 = PO3 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875.

1 = PO3 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875.

1 = PO3/PO1 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10).

1 = PO3/PO1 assertion depends on PO5 (MAX6874)/PO3 (MAX6875) (Table 11).

1 = PO3/PO1 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12).

1 = PO3/PO1 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13).

1 = PO3 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875.

1 = PO3/PO1 asserts when MR = low (Table 6).

1Ch

40h

801Ch

8040h

Table 9 only applies to PO3 of the MAX6874 and PO1

of the MAX6875. Write a 0 to a bit to ꢀake the PO3/PO1

output independent of the respective signal (IN_

thresholds, WD, GPI1–GPI4, MR, or other prograꢀꢀa-

ble outputs).

18 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 10. PO4 (MAX6874)/PO2 (MAX6875) Output Dependency

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

OUTPUT ASSERTION CONDITIONS

[0]

[1]

[2]

[3]

1 = PO4/PO2 assertion depends on IN1 undervoltage threshold (Table 2).

1 = PO4/PO2 assertion depends on IN2 undervoltage threshold (Table 3).

1 = PO4/PO2 assertion depends on IN3 undervoltage threshold (Table 4).

1 = PO4/PO2 assertion depends on IN4 undervoltage threshold (Table 4).

1 = PO4 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be set

to 0 for the MAX6875.

[4]

[5]

1Dh

801Dh

1 = PO4 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be set

to 0 for the MAX6875.

[6]

[7]

[5:0]

[6]

[7]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[0]

[3]

1 = PO4/PO2 assertion depends on watchdog (Tables 18 and 19).

Must be set to 0.

1Eh

1Fh

801Eh

801Fh

1 = PO4/PO2 assertion depends on GPI1 (Table 5).

1 = PO4/PO2 assertion depends on GPI2 (Table 5).

1 = PO4/PO2 assertion depends on GPI3 (Table 5).

1 = PO4/PO2 assertion depends on GPI4 (Table 5).

1 = PO4 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875.

1 = PO4 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875.

1 = PO4/PO2 assertion depends on PO3 (MAX6874)/PO1 (MAX6875) (Table 9).

1 = PO4/PO2 assertion depends on PO5 (MAX6874)/PO3 (MAX6875) (Table 11).

1 = PO4/PO2 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12).

1 = PO4/PO2 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13).

1 = PO4 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875.

1 = PO4/PO2 asserts when MR = low (Table 6).

23h

40h

8023h

8040h

Table 10 only applies to PO4 of the MAX6874 and PO2

of the MAX6875. Write a 0 to a bit to ꢀake the PO4/PO2

output independent of the respective signal (IN_

thresholds, WD, GPI1–GPI4, MR, or other prograꢀꢀa-

ble outputs).

______________________________________________________________________________________ 19

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 11. PO5 (MAX6874)/PO3 (MAX6875) Output Dependency

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

OUTPUT ASSERTION CONDITIONS

[0]

[1]

[2]

[3]

1 = PO5/PO3 assertion depends on IN1 undervoltage threshold (Table 2).

1 = PO5/PO3 assertion depends on IN2 undervoltage threshold (Table 3).

1 = PO5/PO3 assertion depends on IN3 undervoltage threshold (Table 4).

1 = PO5/PO3 assertion depends on IN4 undervoltage threshold (Table 4).

1 = PO5 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be

set to 0 for the MAX6875.

[4]

[5]

24h

8024h

1 = PO5 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be

set to 0 for the MAX6875.

[6]

[7]

[5:0]

[6]

[7]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[0]

[4]

1 = PO5/PO3 assertion depends on watchdog (Tables 18 and 19).

Must be set to 0.

25h

26h

8025h

8026h

1 = PO5/PO3 assertion depends on GPI1 (Table 5).

1 = PO5/PO3 assertion depends on GPI2 (Table 5).

1 = PO5/PO3 assertion depends on GPI3 (Table 5).

1 = PO5/PO3 assertion depends on GPI4 (Table 5).

1 = PO5 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875.

1 = PO5 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875.

1 = PO5/PO3 assertion depends on PO3 (MAX6874)/PO1 (MAX6875) (Table 9).

1 = PO5/PO3 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10).

1 = PO5/PO3 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12).

1 = PO5/PO3 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13).

1 = PO5 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875.

1 = PO5/PO3 asserts when MR = low (Table 6).

2Ah

40h

802Ah

8040h

Table 11 only applies to PO5 of the MAX6874 and PO3

of the MAX6875. Write a 0 to a bit to ꢀake the PO5/PO3

output independent of the respective signal (IN_

thresholds, WD, GPI1–GPI4, MR, or other prograꢀꢀa-

ble outputs).

20 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 12. PO6 (MAX6874)/PO4 (MAX6875) Output Dependency

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

OUTPUT ASSERTION CONDITIONS

[0]

[1]

[2]

[3]

1 = PO6/PO4 assertion depends on IN1 undervoltage threshold (Table 2).

1 = PO6/PO4 assertion depends on IN2 undervoltage threshold (Table 3).

1 = PO6/PO4 assertion depends on IN3 undervoltage threshold (Table 4).

1 = PO6/PO4 assertion depends on IN4 undervoltage threshold (Table 4).

1 = PO6 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be

set to 0 for the MAX6875.

[4]

[5]

2Bh

802Bh

1 = PO6 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be

set to 0 for the MAX6875.

[6]

[7]

[5:0]

[6]

[7]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[0]

[5]

1 = PO6/PO4 assertion depends on watchdog (Tables 18 and 19).

Must be set to 0.

2Ch

2Dh

802Ch

802Dh

1 = PO6/PO4 assertion depends on GPI1 (Table 5).

1 = PO6/PO4 assertion depends on GPI2 (Table 5).

1 = PO6/PO4 assertion depends on GPI3 (Table 5).

1 = PO6/PO4 assertion depends on GPI4 (Table 5).

1 = PO6 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875.

1 = PO6 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875.

1 = PO6/PO4 assertion depends on PO3 (MAX6874)/PO1 (MAX6875) (Table 9).

1 = PO6/PO4 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10).

1 = PO6/PO4 assertion depends on PO5 (MAX6874)/PO3 (MAX6875) (Table 11).

1 = PO6/PO4 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13).

1 = PO6 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875.

1 = PO6/PO4 asserts when MR = low (Table 6).

31h

40h

8031h

8040h

Table 12 only applies to PO6 of the MAX6874 and PO4

of the MAX6875. Write a 0 to a bit to ꢀake the PO6/PO4

output independent of the respective signal (IN_

thresholds, WD, GPI1–GPI4, MR, or other prograꢀꢀa-

ble outputs).

______________________________________________________________________________________ 21

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 13. PO7 (MAX6874)/PO5 (MAX6875) Output Dependency

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

OUTPUT ASSERTION CONDITIONS

[0]

[1]

[2]

[3]

1 = PO7/PO5 assertion depends on IN1 undervoltage threshold (Table 2).

1 = PO7/PO5 assertion depends on IN2 undervoltage threshold (Table 3).

1 = PO7/PO5 assertion depends on IN3 undervoltage threshold (Table 4).

1 = PO7/PO5 assertion depends on IN4 undervoltage threshold (Table 4).

1 = PO7 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be

set to 0 for the MAX6875.

[4]

[5]

32h

8032h

1 = PO7 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be

set to 0 for the MAX6875.

[6]

[7]

1 = PO7/PO5 assertion depends on watchdog (Tables 18 and 19).

Must be set to 0.

[5:0]

33h

34h

8033h

8034h

[6]

[7]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[0]

[6]

1 = PO7/PO5 assertion depends on GPI1 (Table 5).

1 = PO7/PO5 assertion depends on GPI2 (Table 5).

1 = PO7/PO5 assertion depends on GPI3 (Table 5).

1 = PO7/PO5 assertion depends on GPI4 (Table 5).

1 = PO7 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875.

1 = PO7 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875.

1 = PO7/PO5 assertion depends on PO3 (MAX6874)/PO1 (MAX6875) (Table 9).

1 = PO7/PO5 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10).

1 = PO7/PO5 assertion depends on PO5 (MAX6874)/PO3 (MAX6875) (Table 11).

1 = PO7/PO5 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12).

1 = PO7 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875.

1 = PO7 asserts when MR = low (Table 6).

35h

40h

8035h

8040h

Table 13 only applies to PO7 of the MAX6874 and PO5

of the MAX6875. Write a 0 to a bit to ꢀake the PO7/PO5

output independent of the respective signal (IN_

thresholds, WD, GPI1–GPI4, MR, or other prograꢀꢀa-

ble outputs).

22 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 14. PO8 (MAX6874 only) Output Dependency

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

OUTPUT ASSERTION CONDITIONS

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[5:0]

[6]

[7]

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[0]

[7]

1 = PO8 assertion depends on IN1 undervoltage threshold (Table 2).

1 = PO8 assertion depends on IN2 undervoltage threshold (Table 3).

1 = PO8 assertion depends on IN3 undervoltage threshold (Table 4).

1 = PO8 assertion depends on IN4 undervoltage threshold (Table 4).

1 = PO8 assertion depends on IN5 undervoltage threshold (Table 4).

1 = PO8 assertion depends on IN6 undervoltage threshold (Table 4).

1 = PO8 assertion depends on watchdog (Tables 18 and 19).

Must set to 0.

36h

37h

38h

8036h

8037h

8038h

Must set to 0.

1 = PO8 assertion depends on GPI1 (Table 5).

1 = PO8 assertion depends on GPI2 (Table 5).

1 = PO8 assertion depends on GPI3 (Table 5).

1 = PO8 assertion depends on GPI4 (Table 5).

1 = PO8 assertion depends on PO1 (Table 7).

1 = PO8 assertion depends on PO2 (Table 8).

1 = PO8 assertion depends on PO3 (Table 9).

1 = PO8 assertion depends on PO4 (Table 10).

1 = PO8 assertion depends on PO5 (Table 11).

1 = PO8 assertion depends on PO6 (Table 12).

1 = PO8 assertion depends on PO7 (Table 13).

1 = PO8 asserts when MR = low (Table 6).

39h

40h

8039h

8040h

Table 14 only applies to PO8 of the MAX6874. Write a 0

to a bit to ꢀake the PO8 output independent of the

respective signal (IN1–IN6 thresholds, WD, GPI1–GPI4,

MR, or other prograꢀꢀable outputs).

MAX6875) ꢀay be pulled up to +13.2V. PO5–PO8

(PO3–PO5 for the MAX6875) ꢀay be pulled up to a

voltage less than or equal to ABP. Choose the pullup

resistor depending on the nuꢀber of devices connect-

ed to the open-drain output and the allowable current

consuꢀption. The open-drain output configuration

allows wire-ORed connections, and provides flexibility

in setting the pullup current.

Output Stage Configurations

Independently prograꢀ each prograꢀꢀable output as

active-high or active-low (Table 15). All prograꢀꢀable

outputs of the MAX6874/MAX6875 are open-drain only.

See Table 16 to set the tiꢀeout period for each output.

Configuring the MAX6874/MAX6875

The MAX6874/MAX6875 factory-default configuration

sets all EEPROM registers to 00h except register 3Ah,

which is set to FFh. This configuration sets all of the pro-

graꢀꢀable outputs as active-high (putting all outputs

into high-iꢀpedance states until the device is reconfig-

Open-Drain Output Configuration

Connect an external pullup resistor froꢀ the prograꢀ-

ꢀable output to an external voltage when configured as

an open-drain output. PO1–PO4 (PO1 and PO2 for the

______________________________________________________________________________________ 23

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 15. Programmable Output Active States

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

PO1 (MAX6874 only). 0 = active low, 1 = active high.

PO2 (MAX6874 only). 0 = active low, 1 = active high.

PO3 (MAX6874)/PO1 (MAX6875). 0 = active low, 1 = active high.

PO4 (MAX6874)/PO2 (MAX6875). 0 = active low, 1 = active high.

PO5 (MAX6874)/PO3 (MAX6875). 0 = active low, 1 = active high.

PO6 (MAX6874)/PO4 (MAX6875). 0 = active low, 1 = active high.

PO7 (MAX6874)/PO5 (MAX6875). 0 = active low, 1 = active high.

PO8 (MAX6874 only). 0 = active low, 1 = active high.

3Ah

803Ah

Table 16. PO_ Timeout Periods

EEPROM

MEMORY

ADDRESS

AFFECTED OUTPUTS

REGISTER

ADDRESS

BIT RANGE

DESCRIPTION

MAX6874

PO1

MAX6875

11h

15h

1Ch

23h

2Ah

31h

35h

39h

8011h

8015h

801Ch

8023h

802Ah

8031h

8035h

8039h

[3:1]

[4:2]

[3:1]

—

000 = 25µs

PO2

PO3

PO4

PO5

PO6

PO7

PO8

—

001 = 1.5625ꢀs

010 = 6.25ꢀs

011 = 25ꢀs

PO1

PO2

PO3

PO4

PO5

—

100 = 50ꢀs

101 = 200ꢀs

110 = 400ꢀs

111 = 1600ꢀs

ured by the user). To configure the MAX6874/ MAX6875,

first apply an input voltage to IN1 or one of IN3–IN5

(MAX6874)/IN3–IN4 (MAX6875) (see the Powering the

Software Reboot

A software reboot allows the user to restore the

EEPROM configuration to the volatile registers without

cycling the power supplies. Use the send byte coꢀ-

ꢀand with data byte 88h to initiate a software reboot.

The 3.5ꢀs (ꢀax) power-up delay also applies after a

software reboot.

MAX6874/MAX6875 section). V

> +4V or one of

IN1

V

–V

IN3 IN5

> +2.7V, to ensure device operation. Next,

transꢀit data through the serial interface. Use the block

write protocol to quickly configure the device. Write to

the configuration registers first to ensure the device is

configured properly. After coꢀpleting the setup proce-

dure, use the read word protocol to verify the data froꢀ

the configuration registers. Lastly, use the write word

protocol to write this data to the EEPROM registers. After

coꢀpleting EEPROM register configuration, apply full

power to the systeꢀ to begin norꢀal operation. The non-

volatile EEPROM stores the latest configuration upon

reꢀoval of power. Write 0’s to all EEPROM registers to

clear the ꢀeꢀory.

SMBus/I²C-Compatible Serial Interface

The MAX6874/MAX6875 feature an I²C/SMBus-coꢀpati-

ble serial interface consisting of a serial data line (SDA)

and a serial clock line (SCL). SDA and SCL allow bidirec-

tional coꢀꢀunication between the MAX6874/MAX6875

and the ꢀaster device at clock rates up to 400kHz.

Figure 2 shows the interface tiꢀing diagraꢀ. The

MAX6874/MAX6875 are transꢀit/receive slave-only

devices, relying upon a ꢀaster device to generate a

clock signal. The ꢀaster device (typically a ꢀicrocon-

troller) initiates data transfer on the bus and generates

SCL to perꢀit that transfer.

24 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

A ꢀaster device coꢀꢀunicates to the MAX6874/

Start and Stop Conditions

Both SCL and SDA idle high when the bus is not busy. A

ꢀaster device signals the beginning of a transꢀission

with a START (S) condition (Figure 4) by transitioning

SDA froꢀ high to low while SCL is high. The ꢀaster

device issues a STOP (P) condition (Figure 4) by transi-

tioning SDA froꢀ low to high while SCL is high. A STOP

condition frees the bus for another transꢀission. The bus

reꢀains active if a REPEATED START condition is gener-

ated, such as in the block read protocol (see Figure 7).

MAX6875 by transꢀitting the proper address followed by

coꢀꢀand and/or data words. Each transꢀit sequence is

fraꢀed by a START (S) or REPEATED START (SR) condi-

tion and a STOP (P) condition. Each word transꢀitted

over the bus is 8 bits long and is always followed by an

acknowledge pulse.

SCL is a logic input, while SDA is a logic input/open-

drain output. SCL and SDA both require external pullup

resistors to generate the logic-high voltage. Use 4.7kΩ

for ꢀost applications.

Early STOP Conditions

The MAX6874/MAX6875 recognize a STOP condition at

any point during transꢀission except if a STOP condition

occurs in the saꢀe high pulse as a START condition. This

condition is not a legal I²C forꢀat. At least one clock

pulse ꢀust separate any START and STOP condition.

Bit Transfer

Each clock pulse transfers one data bit. The data on

SDA ꢀust reꢀain stable while SCL is high (Figure 3),

otherwise the MAX6874/MAX6875 register a START or

STOP condition (Figure 4) froꢀ the ꢀaster. SDA and

SCL idle high when the bus is not busy.

SDA

t

BUF

t

SU:DAT

t

SU:STA

t

SU:STO

HD:DAT

t

LOW

HD:STA

SCL

t

HIGH

t

HD:STA

t

R

F

START

CONDITION

STOP

CONDITION

START

CONDITION

REPEATED START

CONDITION

Figure 2. Serial-Interface Timing Details

SDA

SCL

S

P

SCL

START

CONDITION

STOP

CONDITION

CHANGE OF

DATA ALLOWED

DATA LINE STABLE,

DATA VALID

Figure 3. Bit Transfer

Figure 4. Start and Stop Conditions

______________________________________________________________________________________ 25

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Repeated START Conditions

Slave Address

A REPEATED START (SR) condition ꢀay indicate a

change of data direction on the bus. Such a change

occurs when a coꢀꢀand word is required to initiate a

read operation (see Figure 7). SR ꢀay also be used

when the bus ꢀaster is writing to several I²C devices

and does not want to relinquish control of the bus. The

MAX6874/MAX6875 serial interface supports continu-

ous write operations with or without an SR condition

separating theꢀ. Continuous read operations require

SR conditions because of the change in direction of

data flow.

The MAX6874 slave address conforꢀs to the following

table:

SA7

(MSB)

SA0

(LSB)

SA6

SA5

SA4

SA3

SA2

SA1

1

0

1

0

A1

A0

X

R/W

X = Don’t care.

The MAX6875 slave address conforꢀs to the following

table:

SA7

(MSB)

SA0

(LSB)

SA6

SA5

SA4

SA3

SA2

SA1

Acknowledge

The acknowledge bit (ACK) is the 9th bit attached to any

8-bit data word. The receiving device always generates

an ACK. The MAX6874/MAX6875 generate an ACK

when receiving an address or data by pulling SDA low

during the 9th clock period (Figure 5). When transꢀitting

data, such as when the ꢀaster device reads data back

froꢀ the MAX6874/MAX6875, the MAX6874/MAX6875

wait for the ꢀaster device to generate an ACK.

Monitoring ACK allows for detection of unsuccessful data

transfers. An unsuccessful data transfer occurs if the

receiving device is busy or if a systeꢀ fault has

occurred. In the event of an unsuccessful data transfer,

the bus ꢀaster should reatteꢀpt coꢀꢀunication at a

later tiꢀe. The MAX6874/MAX6875 generate a NACK

after the slave address during a software reboot, while

writing to the EEPROM, or when receiving an illegal

ꢀeꢀory address.

1

0

1

0

A0

X

R/W

X = Don’t care.

SA7 through SA4 represent the standard interface

address (1010) for devices with EEPROM. SA3 and

SA2 correspond to the A1 and A0 address inputs of the

MAX6874/MAX6875 (hardwired as logic low or logic

high). A1 is internally set to 0 for the MAX6875. SA0 is a

read/write flag bit (0 = write, 1 = read).

The A0 and A1 address inputs allow up to four

MAX6874s or two MAX6875s to connect to one bus.

Connect A0 and A1 to GND or to the serial interface

power supply (see Figure 6).

START

CONDITION

CLOCK PULSE FOR ACKNOWLEDGE

2

1

8

9

SCL

SDA BY

TRANSMITTER

S

SDA BY

RECEIVER

Figure 5. Acknowledge

26 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Send Byte

The send byte protocol allows the ꢀaster device to send

one byte of data to the slave device (see Figure 7). The

send byte presets a register pointer address for a sub-

sequent read or write. The slave sends a NACK instead

of an ACK if the ꢀaster tries to send an address that is

not allowed. If the ꢀaster sends 80h, 81h, or 82h, the

data is ACK. This could be start of the write byte/word

protocol, and the slave expects at least one further

data byte. If the ꢀaster sends a stop condition, the

internal address pointer does not change. If the ꢀaster

sends 84h, this signifies that the block read protocol is

expected, and a repeated start condition should follow.

The device reboots if the ꢀaster sends 88h. The send

byte procedure follows:

2) The ꢀaster sends the 7-bit slave address and a

write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The ꢀaster sends an 8-bit coꢀꢀand code.

5) The addressed slave asserts an ACK on SDA.

6) The ꢀaster sends an 8-bit data byte.

7) The addressed slave asserts an ACK on SDA.

8) The ꢀaster sends a stop condition or sends another

8-bit data byte.

9) The addressed slave asserts an ACK on SDA.

10)The ꢀaster sends a stop condition.

To write a single byte to the register bank, only the 8-bit

coꢀꢀand code and a single 8-bit data byte are sent.

The coꢀꢀand code ꢀust be in the range of 00h to 45h.

The data byte is written to the register bank if the coꢀ-

ꢀand code is valid. The slave generates a NACK at

step 5 if the coꢀꢀand code is invalid.

1) The ꢀaster sends a start condition.

2) The ꢀaster sends the 7-bit slave address and a

write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The ꢀaster sends an 8-bit data byte.

To preset an EEPROM (configuration or user) address

for a subsequent read, the 8-bit coꢀꢀand code and a

single 8-bit data byte are sent. The coꢀꢀand code

ꢀust be 80h if the write is to be directed into the config-

uration EEPROM, or 81h or 82h, if the write is to be

directed into the user EEPROM. If the coꢀꢀand code is

80h, the data byte ꢀust be in the range of 00h to 45h. If

the coꢀꢀand code is 81h or 82h, the data byte can be

00h to FFh. A NACK is generated in step 7 if none of the

above conditions are true.

5) The addressed slave asserts an ACK on SDA.

6) The ꢀaster sends a stop condition.

Write Byte/Word

The write byte/word protocol allows the ꢀaster device

to write a single byte in the register bank, preset an

EEPROM (configuration or user) address for a subse-

quent read, or to write a single byte to the configuration

or user EEPROM (see Figure 7). The write byte/word

procedure follows:

To write a single byte of data to the user or configuration

EEPROM, the 8-bit coꢀꢀand code and a single 8-bit

data byte are sent. The following 8-bit data byte is writ-

ten to the addressed EEPROM location.

1) The ꢀaster sends a start condition.

SDA

1

0

A1

(0)

A0

X

R/W

ACK

0

1

START

MSB

LSB

SCL

(MAX6875 ONLY)

Figure 6. Slave Address

______________________________________________________________________________________ 27

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

SEND BYTE FORMAT

WRITE WORD FORMAT

ADDRESS WR

S

ADDRESS

WR

0

ACK

DATA

8 bits

ACK

P

S

ACK COMMAND ACK

8 bits

DATA ACK

8 bits

DATA ACK

8 bits

P

7 bits

0

Slave Address–

Data Byte–presets the

internal address pointer.

Slave Address–

Command Byte–

MSB of the

EEPROM

register being

written.

Data Byte–first byte is the LSB of

the EEPROM address. Second

byte is the actual data.

equivalent to chip-

select line of a 3-

wire interface.

equivalent to chip-

select line of a 3-

wire interface.

RECEIVE BYTE FORMAT

WRITE BYTE FORMAT

S

ADDRESS

WR

1

ACK

DATA

8 bits

ACK

P

S

ADDRESS

WR

0

ACK

COMMAND

8 bits

ACK

DATA

8 bits

ACK

P

7 bits

Slave Address–

Data Byte–reads data from

the register commanded by

the last read byte or write

byte transmission. Also

dependent on a send byte.

Slave Address–

Command Byte–

selects register

being written.

Data Byte–data goes into the

register set by the command

byte if the command is below

50h. If the command is 80h,

81h, or 82h, the data byte

presets the LSB of an EEPROM

address.

equivalent to chip-

select line of a 3-

wire interface.

equivalent to chip-

select line of a 3-

wire interface.

BLOCK WRITE FORMAT

BYTE

COUNT= N

DATA BYTE

1

DATA BYTE

...

DATA BYTE

N

S

ADDRESS

7 bits

WR

0

ACK COMMAND ACK

83h

ACK

P

8 bits

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

Command Byte–

prepares device

for block

Data Byte–data goes into the register set by the

command byte.

operation.

BLOCK READ FORMAT

ADDRESS WR ACK COMMAND ACK SR ADDRESS WR

BYTE

COUNT= 16

DATA BYTE

1

DATA BYTE

...

DATA BYTE

N

S

ACK

P

7 bits

0

84h

7 bits

1

10h

8 bits

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

Command Byte–

prepares device

for block

Slave Address–

Data Byte–data goes into the register set by the

command byte.

equivalent to chip-

select line of a 3-

wire interface.

operation.

S = Start condition.

P = Stop condition.

Shaded = Slave transmission.

SR = Repeated start condition.

2

Figure 7. SMBus/I C Protocols

28 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Block Write

The block write protocol allows the ꢀaster device to

write a block of data (1 to 16 bytes) to the EEPROM or

to the register bank (see Figure 7). The destination

address ꢀust already be set by the send byte or write

byte protocol and the coꢀꢀand code ꢀust be 83h. If

the nuꢀber of bytes to be written causes the address

pointer to exceed 45h for the configuration register or

configuration EEPROM, the address pointer stays at

45h, overwriting this ꢀeꢀory address with the reꢀain-

ing bytes of data. The last data byte sent is stored at

register address 45h. If the nuꢀber of bytes to be writ-

ten exceeds the address pointer FFh for the user EEP-

ROM, the address pointer loops back to 00h, and

continues writing bytes until all data is written. The

block write procedure follows:

5) The ꢀaster asserts a NACK on SDA.

6) The ꢀaster generates a stop condition.

Block Read

The block read protocol allows the ꢀaster device to

read a block of 16 bytes froꢀ the EEPROM or register

bank (see Figure 7). Read fewer than 16 bytes of data

by issuing an early STOP condition froꢀ the ꢀaster, or

by generating a NACK with the ꢀaster. The send byte

or write byte protocol predeterꢀines the destination

address with a coꢀꢀand code of 84h. The block read

procedure follows:

1) The ꢀaster sends a start condition.

2) The ꢀaster sends the 7-bit slave address and a

write bit (low).

3) The addressed slave asserts an ACK on SDA.

1) The ꢀaster sends a start condition.

4) The ꢀaster sends 8 bits of the block read coꢀꢀand

(84h).

2) The ꢀaster sends the 7-bit slave address and a

write bit (low).

5) The slave asserts an ACK on SDA, unless busy.

6) The ꢀaster generates a repeated start condition.

3) The addressed slave asserts an ACK on SDA.

4) The ꢀaster sends the 8-bit coꢀꢀand code for

block write (83h).

7) The ꢀaster sends the 7-bit slave address and a

read bit (high).

5) The addressed slave asserts an ACK on SDA.

6) The ꢀaster sends the 8-bit byte count (1 to 16 bytes) N.

7) The addressed slave asserts an ACK on SDA.

8) The ꢀaster sends 8 bits of data.

8) The slave asserts an ACK on SDA.

9) The slave sends the 8-bit byte count (16).

10)The ꢀaster asserts an ACK on SDA.

11)The slave sends 8 bits of data.

9) The addressed slave asserts an ACK on SDA.

10) Repeat steps 8 and 9 one tiꢀe.

12)The ꢀaster asserts an ACK on SDA.

13)Repeat steps 8 and 9 fifteen tiꢀes.

14)The ꢀaster generates a stop condition.

11) The ꢀaster generates a stop condition.

Receive Byte

The receive byte protocol allows the ꢀaster device to

read the register content of the MAX6874/MAX6875

(see Figure 7). The EEPROM or register address ꢀust

be preset with a send byte or write word protocol first.

Once the read is coꢀplete, the internal pointer increas-

es by one. Repeating the receive byte protocol reads

the contents of the next address. The receive byte pro-

cedure follows:

Address Pointers

Use the send byte protocol to set the register address

pointers before read and write operations. For the con-

figuration registers, valid address pointers range froꢀ

00h to 45h. Register addresses outside of this range

result in a NACK being issued froꢀ the MAX6874/

MAX6875. When using the block write protocol, the

address pointer autoꢀatically increꢀents after each

data byte, except when the address pointer is already

at 45h. If the address pointer is already 45h, and ꢀore

data bytes are being sent, these subsequent bytes

overwrite address 45h repeatedly, leaving only the last

data byte sent stored at this register address.

1) The ꢀaster sends a start condition.

2) The ꢀaster sends the 7-bit slave address and a

read bit (high).

3) The addressed slave asserts an ACK on SDA.

4) The slave sends 8 data bits.

______________________________________________________________________________________ 29

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

For the configuration EEPROM, valid address pointers

range froꢀ 8000h to 8045h. Registers 8046h to 804Fh

are reserved and should not be overwritten. Register

addresses froꢀ 8050h to 80FFh return a NACK froꢀ

the MAX6874/MAX6875. When using the block write

protocol, the address pointer autoꢀatically increꢀents

after each data byte, except when the address pointer

is already at 8045h. If the address pointer is already

8045h, and ꢀore data bytes are being sent, these sub-

sequent bytes overwrite address 8045h repeatedly,

leaving only the last data byte sent stored at this regis-

ter address.

tiꢀe after power-up or software reboot. Write coꢀꢀands

to the configuration EEPROM are allowed at any tiꢀe

after power-up or software reboot, unless the configura-

tion lock bit is set (see Table 20). The ꢀaxiꢀuꢀ cycle

tiꢀe to write a single byte is 11ꢀs (ꢀax).

User EEPROM

The 512 byte user EEPROM addresses range froꢀ

8100h to 82FFh (see Figure 7). Store software-revision

data, board-revision data, and other data in these reg-

isters. The ꢀaxiꢀuꢀ cycle tiꢀe to write a single byte is

11ꢀs (ꢀax).

For the user EEPROM, valid address pointers range

froꢀ 8100h to 81FFh and 8200h to 82FFh. Block write

and block read protocols allow the address pointer to

reset (to 8100h or 8200h) when atteꢀpting to write or

read beyond 81FFh or 82FFh.

Configuration Register Bank and EEPROM

The configuration registers can be directly ꢀodified by

the serial interface without ꢀodifying the EEPROM after

the power-up procedure terꢀinates and the configura-

tion EEPROM data has been loaded into the configura-

tion register bank. Use the write byte or block write

protocols to write directly to the configuration registers.

Changes to the configuration registers take effect

iꢀꢀediately and are lost upon power reꢀoval.

Configuration EEPROM

The configuration EEPROM addresses range froꢀ 8000h

to 8045h. Write data to the configuration EEPROM to

autoꢀatically set up the MAX6874/MAX6875 upon power-

up. Data transfers froꢀ the configuration EEPROM to the

configuration registers when ABP exceeds UVLO during

power-up or after a software reboot. After ABP exceeds

UVLO, an internal 1MHz clock starts after a 5µs delay,

and data transfer begins. Data transfer disables access

to the configuration registers and EEPROM. The data

transfer froꢀ EEPROM to configuration registers takes

3.5ꢀs (ꢀax). Read configuration EEPROM data at any

At device power-up, the register bank loads configura-

tion data froꢀ the EEPROM. Configuration data ꢀay be

directly altered in the register bank during application

developꢀent, allowing ꢀaxiꢀuꢀ flexibility. Transfer the

new configuration data, byte by byte, to the configura-

tion EEPROM with the write byte protocol. The next

device power-up or software reboot autoꢀatically loads

the new configuration.

Table 17. Register Map

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

READ/

WRITE

DESCRIPTION

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

8000h

8001h

8002h

8003h

8004h

8005h

8006h

8007h

8008h

8009h

800Ah

R/W

IN1 undervoltage detector threshold (Table 2).

IN2 undervoltage detector threshold (Table 3).

IN3 undervoltage detector threshold (Table 4).

IN4 undervoltage detector threshold (Table 4).

IN5 undervoltage detector threshold (MAX6874 only) (Table 4).

IN6 undervoltage detector threshold (MAX6874 only) (Table 4).

—

Not used.

—

30 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 17. Register Map (continued)

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

READ/

WRITE

DESCRIPTION

—

0Bh

0Ch

0Dh

0Eh

0Fh

10h

800Bh

800Ch

800Dh

800Eh

800Fh

8010h

Not used.

R/W

Threshold range selection (Tables 2–4).

PO1 (MAX6874 only) input selection (Table 7).

PO1 (MAX6874 only) input selection, PO_ tiꢀeout period, and output type selection

(Tables 7, 16).

11h

8011h

R/W

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

8012h

8013h

8014h

8015h

8016h

8017h

8018h

8019h

801Ah

801Bh

801Ch

801Dh

801Eh

801Fh

8020h

8021h

8022h

8023h

8024h

8025h

8026h

8027h

8028h

8029h

802Ah

802Bh

802Ch

R/W

PO2 (MAX6874 only) input selection (Table 8).

PO2 (MAX6874 only) input selection and PO_ tiꢀeout period (Tables 8, 16).

PO3 (MAX6874)/PO1 (MAX6875) input selection (Table 9).

Set to 0.

PO3 (MAX6874)/PO1 (MAX6875) input selection and PO_ tiꢀeout period (Tables 9, 16).

PO4 (MAX6874)/PO2 (MAX6875) input selection (Table 10).

Set to 0.

PO4 (MAX6874)/PO2 (MAX6875) input selection and PO_ tiꢀeout period (Tables 6, 18).

PO5 (MAX6874)/PO3 (MAX6875) input selection (Table 11).

Set to 0.

PO5 (MAX6874)/PO3 (MAX6875) input selection and PO_ tiꢀeout period (Tables 11, 18).

PO6 (MAX6874)/PO4 (MAX6875) input selection (Table 12).

______________________________________________________________________________________ 31

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 17. Register Map (continued)

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

READ/

WRITE

DESCRIPTION

2Dh

2Eh

2Fh

30h

802Dh

802Eh

802Fh

8030h

R/W

PO6 (MAX6874)/PO4 (MAX6875) input selection (Table 12).

Set to 0.

PO6 (MAX6874)/PO4 (MAX6875) input selection and PO_ reset tiꢀeout period

(Tables 12, 16).

31h

8031h

R/W

32h

33h

34h

35h

36h

37h

38h

39h

8032h

8033h

8034h

8035h

8036h

8037h

8038h

8039h

R/W

PO7 (MAX6874)/PO5 (MAX6875) input selection (Table 13).

PO7 (MAX6874)/PO5 (MAX6875) input selection and PO_ tiꢀeout period (Tables 13, 16).

PO8 (MAX6874 only) input selection (Table 14).

PO8 (MAX6874 only) input selection and PO_ tiꢀeout period (Tables 14, 16).

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

43h

44h

45h

803Ah

803Bh

803Ch

803Dh

803Eh

803Fh

8040h

8041h

8042h

8043h

8044h

8045h

R/W

—

Prograꢀꢀable output polarity (active high/active low) (Table 15).

GPI_ input polarity, PO5, PO6 (Table 5).

WD input selection and tiꢀeout enable (Table 18).

WD initial and norꢀal tiꢀeout duration (Table 19).

Must be set to 0.

MR input and prograꢀꢀable output behavior (Table 6).

Must be set to 0.

User EEPROM write disable (Table 21).

Reserved. Should not be overwritten.

Configuration lock (Table 20).

R/W

32 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

CONFIGURATION

EEPROM

USER EEPROM

REGISTER BANK

8000h

8100h

8200h

00h

45h

CONFIGURATION

DATA

8045h

81FFh

82FFh

Figure 8. Memory Map

Table 18. Watchdog Inputs

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

Watchdog Input Selection:

00 = GPI1

[1:0]

[4:2]

01 = GPI2

10 = GPI3

11 = GPI4 (MAX6874 only)

Watchdog Internal Input Selection:

000 = PO1 (MAX6874), not used (MAX6875)

001 = PO2 (MAX6874), not used (MAX6875)

010 = PO3 (MAX6874), PO1 (MAX6875)

011 = PO4 (MAX6874), PO2 (MAX6875)

100 = PO5 (MAX6874), PO3 (MAX6875)

101 = PO6 (MAX6874), PO4 (MAX6875)

110 = PO7 (MAX6874), PO5 (MAX6875)

111 = PO8 (MAX6874), not used (MAX6875)

3Ch

803Ch

Watchdog Dependency on Inputs:

00 = 11 = Watchdog clear depends on both GPI_ froꢀ 3Ch[1:0] and PO_ froꢀ 3Ch[4:2].

01 = Watchdog clear depends only on PO_ froꢀ 3Ch[4:2].

10 = Watchdog clear depends only on GPI_ froꢀ 3Ch[1:0].

[6:5]

[7]

Must be set to 1

______________________________________________________________________________________ 33

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 19. Watchdog Timeout Period Selection

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

Norꢀal Watchdog Tiꢀeout Period:

000 = 6.25ꢀs

001 = 25ꢀs

010 = 100ꢀs

[2:0]

011 = 400ꢀs

100 = 1.6s

101 = 6.4s

110 = 25.6s

111 = 102.4s

Initial Watchdog Tiꢀeout Period (iꢀꢀediately following power-up, reset event,

or enabling watchdog):

000 = 6.25ꢀs

001 = 25ꢀs

3Dh

803Dh

010 = 100ꢀs

011 = 400ꢀs

100 = 1.6s

[5:3]

101 = 6.4s

110 = 25.6s

111 = 102.4s

Watchdog Enable:

[6]

[7]

0 = Disables watchdog tiꢀer

1 = Enables watchdog tiꢀer

Not used

Configuring the Watchdog Timer

(Registers 3Ch–3Dh)

A watchdog tiꢀer ꢀonitors ꢀicroprocessor (µP) soft-

ware execution for a stalled condition and resets the µP

if it stalls. The output of a watchdog tiꢀer (one of the

prograꢀꢀable outputs) connects to the reset input or a

nonꢀaskable interrupt of the µP.

The norꢀal watchdog tiꢀeout period applies in every

other cycle after the initial watchdog tiꢀeout period

occurs. The norꢀal watchdog tiꢀeout period ꢀonitors

a pulsed output of the µP that indicates when norꢀal

processor behavior occurs. If no pulse occurs during

the norꢀal watchdog tiꢀeout period, this indicates that

the processor has stopped operating or is stuck in an

infinite execution loop.

Registers 3Ch–3Dh configure the watchdog functionality

of the MAX6874/MAX6875. Prograꢀ the watchdog tiꢀer

to assert one or ꢀore prograꢀꢀable outputs (see Tables

7–14). Prograꢀ the watchdog tiꢀer to reset on one of the

GPI_ inputs, one of the prograꢀꢀable outputs, or a coꢀ-

bination of one GPI_ input and one prograꢀꢀable out-

put.

Register 3Dh prograꢀs the initial and norꢀal watchdog

tiꢀeout periods, and enables or disables the watchdog

tiꢀer. See Tables 18 and 19 for a suꢀꢀary of the watch-

dog behavior.

Configuration Lock

Lock the configuration register bank and configuration

EEPROM contents after initial prograꢀꢀing by setting

the lock bit high (see Table 20). Locking the configura-

tion prevents write operations to all registers except the

configuration lock register. Clear the lock bit to recon-

figure the device.

The watchdog tiꢀer features independent initial and nor-

ꢀal watchdog tiꢀeout periods. The initial watchdog tiꢀe-

out period applies iꢀꢀediately after power-up, after a

reset event takes place, or after enabling the watchdog

tiꢀer. The initial watchdog tiꢀeout period allows the µP to

perforꢀ its initialization process. If no pulse occurs during

the initial watchdog tiꢀeout period, the µP is taking too

long to initialize, indicating a potential probleꢀ.

34 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Table 20. Configuration Lock Register

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

0 = configuration unlocked.

1 = configuration locked.

[0]

45h

8045h

[7:1]

Not used.

Table 21. Write Disable Register

EEPROM

MEMORY

ADDRESS

REGISTER

ADDRESS

BIT

RANGE

DESCRIPTION

0 = write not disabled if PO1 asserts (MAX6874).

1 = write disabled if PO1 asserts (MAX6874). Set to 0 (MAX6875).

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

0 = write not disabled if PO2 asserts (MAX6874).

1 = write disabled if PO2 asserts (MAX6874). Set to 0 (MAX6875).

0 = write not disabled if PO3 (MAX6874)/PO1 (MAX6875) asserts.

1 = write disabled if PO3 (MAX6874)/PO1 (MAX6875) asserts.

0 = write not disabled if PO4 (MAX6874)/PO2 (MAX6875) asserts.

1 = write disabled if PO4 (MAX6874)/PO2 (MAX6875) asserts.

43h

8043h

0 = write not disabled if PO5 (MAX6874)/PO3 (MAX6875) asserts.

1 = write disabled if PO5 (MAX6874)/PO3 (MAX6875) asserts.

0 = write not disabled if PO6 (MAX6874)/PO4 (MAX6875) asserts.

1 = write disabled if PO6 (MAX6874)/PO4 (MAX6875) asserts.

0 = write not disabled if PO7 (MAX6874)/PO5 (MAX6875) asserts.

1 = write disabled if PO7 (MAX6874)/PO5 (MAX6875) asserts.

0 = write not disabled if PO8 asserts (MAX6874).

1 = write disabled if PO8 asserts (MAX6874). Set to 0 (MAX6875).

Write Disable

tion. The local volatile ꢀeꢀory latches lose their contents

A unique write disable feature protects the MAX6874/

MAX6875 froꢀ inadvertent user EEPROM writes. As input

voltages that power the serial interface, a µP, or any other

writing devices fall, unintentional data ꢀay be written onto

the data bus. The user EEPROM write disable function

(see Table 21) ensures that unintentional data does not

corrupt the MAX6874/MAX6875 EEPROM data.

at power-down. Therefore, at power-up, the device con-

figuration ꢀust be restored by downloading the contents

of the EEPROM (non-volatile ꢀeꢀory) to the local latches.

This download occurs in a nuꢀber of steps:

1) Prograꢀꢀable outputs go high iꢀpedance with no

power applied to the device.

2) When ABP exceeds +1V, all prograꢀꢀable out-

puts are weakly pulled to GND through a 10µA

current sink.

Applications Information

Configuration Download at Power-up

The configuration of the MAX6874/MAX6875 (under-

voltage thresholds, PO_ tiꢀeout periods, watchdog

behavior, prograꢀꢀable output conditions, etc.)

depends on the contents of the EEPROM. The EEPROM

is coꢀprised of buffered latches that store the configura-

3) When ABP exceeds UVLO, the configuration EEP-

ROM starts to download its contents to the volatile

configuration registers. The prograꢀꢀable outputs

assuꢀe their prograꢀꢀed conditional output state

when download is coꢀplete.

______________________________________________________________________________________ 35

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

4) Any atteꢀpt to coꢀꢀunicate with the device prior to

this download coꢀpletion results in a NACK being

issued froꢀ the MAX6874/MAX6875.

Other Fault Signals from µC

Connect a general-purpose output froꢀ a µC to one of

the GPI_ inputs to allow interrupts to assert any output

of the MAX6874/MAX6875. Configure one of the pro-

graꢀꢀable outputs to assert on whichever GPI_ input

connects to the general purpose output of the µC.

Forcing Programmable

Outputs High During Power-Up

A weak 10µA pulldown holds all prograꢀꢀable outputs

low during power-up until ABP exceeds the undervolt-

age lockout (UVLO) threshold. Applications requiring a

guaranteed high prograꢀꢀable output for ABP down to

GND require external pullup resistors to ꢀaintain the

logic state until ABP exceeds UVLO. Use 20kΩ resis-

tors for ꢀost applications.

Layout and Bypassing

For better noise iꢀꢀunity, bypass each of the voltage

detector inputs to GND with 0.1µF capacitors installed

as close to the device as possible. Bypass ABP and

DBP to GND with 1µF capacitors installed as close to

the device as possible. ABP and DBP are internally

generated voltages and should not be used to supply

power to external circuitry.

Uses for General-Purpose

Inputs (GPI1–GPI4)

Configuration Latency Period

A delay of less than 5µs occurs between writing to the

configuration registers and the tiꢀe when these

changes actually take place, except when changing

one of the voltage-detector thresholds. Changing a

voltage-detector threshold typically takes 150µs. When

changing EEPROM contents, a software reboot or

cycling of power is required for these changes to trans-

fer to volatile ꢀeꢀory.

Watchdog Timer

Prograꢀ GPI_ as an input to the watchdog tiꢀer in the

MAX6874/MAX6875. The GPI_ input ꢀust toggle within

the watchdog tiꢀeout period, otherwise any prograꢀ-

ꢀable output dependent on the watchdog tiꢀer

asserts.

Additional Manual Reset Functions

Prograꢀ PO7 (MAX6874)/PO5 (MAX6875) to depend

on one of the GPI_ inputs. Any output that depends on

GPI_ asserts when GPI_ is held in its active state, effec-

tively acting as a ꢀanual reset input.

Chip Information

PROCESS: BiCMOS

36 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Pin Configurations

TOP VIEW

PO2

PO3

PO4

GND

PO5

PO6

PO7

PO8

1

2

3

4

5

6

7

8

24 N.C.

23 N.C.

22 DBP

21 ABP

20 GPI1

19 GPI2

18 GPI3

17 GPI4

N.C.

PO1

PO2

GND

PO3

PO4

PO5

N.C.

1

2

3

4

5

6

7

8

24 N.C.

23 N.C.

22 DBP

21 ABP

20 GPI1

19 GPI2

18 GPI3

17 N.C.

MAX6874

MAX6875

*EXPOSED PADDLE

(7mm x 7mm Thin QFN)

*EXPOSED PADDLE INTERNALLY CONNECTED TO GND.

Selector Guide

PART

VOLTAGE-DETECTOR INPUTS

GENERAL-PURPOSE INPUTS

PROGRAMMABLE OUTPUTS

MAX6874ETJ

MAX6875ETJ

6

4

3

8

5

______________________________________________________________________________________ 37

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Typical Operating Circuit

+12V

+5V

DC-DC

1

DC-DC

3

+3.3V

+2.5V

+0.7V

DC-DC

2

DC-DC

4

R

PU

R

PU

IN1

PO1

PO2

IN3

IN5

PO4

IN6

IN4

PO3

µP

MARGIN

SDA

SCL

MR

SCL

RESET

PO5

PO6

ABP

NMI, WD ALERT

LOGIC OUTPUT

MAX6874

GPI1

(WD)

DBP

A0

A1

GPI2

GPI4

GND

GPI3

+12V BUS INPUT

+12V SUPPLY

PO1

t

PO1

ENABLE +5V DC-DC CONVERTER

+5V OUTPUT

+5V SUPPLY

PO2

t

ENABLE +2.5V DC-DC CONVERTER

+2.5V OUTPUT

PO2

+2.5V SUPPLY

PO3

t

ENABLE +3.3V DC-DC CONVERTER

+3.3V OUTPUT

PO3

+3.3V SUPPLY

PO4

t

ENABLE +0.7V DC-DC CONVERTER

+0.7V OUTPUT

PO4

+0.7V SUPPLY

PO5

t

SYSTEM RESET

PO5

38 ______________________________________________________________________________________

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Package Information

(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,

go to www.maxim-ic.com/packages.)

D2

D

C

L

b

D2/2

D/2

k

E/2

E2/2

C

(NE-1) X

e

E

E2

L

k

L

DETAIL A

e

(ND-1) X

e

DETAIL B

e

C

L

L1

L

e

DALLAS

SEMICONDUCTOR

A

A1

A2

PROPRIETARYINFORMATION

TITLE:

PACKAGE OUTLINE

32, 44, 48, 56L THIN QFN, 7x7x0.8mm

APPROVAL

DOCUMENT CONTROL NO.

REV.

1

21-0144

D

2

______________________________________________________________________________________ 39

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Package Information (continued)

(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,

go to www.maxim-ic.com/packages.)

DALLAS

SEMICONDUCTOR

PROPRIETARYINFORMATION

TITLE:

PACKAGE OUTLINE

32, 44, 48, 56L THIN QFN, 7x7x0.8mm

APPROVAL

DOCUMENT CONTROL NO.

REV.

2

21-0144

D

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

40 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered tradeꢀark of Maxiꢀ Integrated Products.


型号：	MAX6875ETJ+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Power Supply Management Circuit, Fixed, 4 Channel, BICMOS, 7 X 7 MM, 0.80 MM HEIGHT, MO-220, TQFN-32 信息通信管理
文件：	总40页 (文件大小：338K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX6875ETJ+ [MAXIM]

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