MAX8649EWET [MAXIM]
1.8A Step-Down Regulator with Remote Sense in 2mm x 2mm WLP; 1.8A降压型调节器，采用2mm x 2mm WLP封装遥感
| 型号： | MAX8649EWET |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1.8A Step-Down Regulator with Remote Sense in 2mm x 2mm WLP |
| 文件： | 总31页 (文件大小：1932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4504; Rev 4; 6/11
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
General Description
Features
o 1.8A Guaranteed Output Current
The MAX8649/MAX8649A high-efficiency DC-to-DC step-
down switching regulators deliver up to 1.8A of output cur-
rent. The device operates from a 2.5V to 5.5V input
voltage range, making it future proof for next-generation
battery technologies. The output voltage is I2C program-
mable from 0.75V to 1.38V. Remote sense ensures pre-
cise DC regulation at the load. Total output error is less
than 2% over load, line, and temperature.
2
o I C Programmable V
(750mV to 1.38V in 10mV
OUT
Steps)
o Operates from 2.5V to 5.5V Input Supply
o On-Chip FET and Synchronous Rectifier
o Fixed 3.25MHz PWM Switching Frequency
o Synchronizes to 13MHz, 19.2MHz, or 26MHz
System Clock when Available
o Small 1.0µH Inductor
The ICs operate at a 3.25MHz fixed frequency. The high
operating frequency minimizes the size of external com-
ponents. The switching frequency of the converter can be
synchronized to the master clock of the application. When
synchronizing to an external clock, the ICs measure the
frequency of the external clock to ensure that the clock is
stable before changing the switching frequency to the
external clock frequency.
o Initial Accuracy 0.5% at 1.25V Output
o 2% Output Accuracy Over Load, Line, and
Temperature
o Power-Save Mode Increases Light Load Efficiency
o Overvoltage and Overcurrent Protection
o Thermal Shutdown Protection
An on-board DAC allows adjustment of the output volt-
age in 10mV steps. The output voltage can be pro-
grammed directly through the I2C interface, or by
preloading a set of on-board registers and using the
two VID logic signals to select the appropriate register.
Other features include internal soft-start control circuitry
to reduce inrush current, output overvoltage, overcur-
rent, and overtemperature protection.
2
o 400kHz I C Interface
o < 1µA Shutdown Current
o 16-Bump, 2mm x 2mm WLP Package
Ordering Information
2
I C ADDRESS
PART
PIN-PACKAGE
2
The ICs feature different I C addresses so that devices
(WRITE/READ)
may be used in a system. For a 2.5A version of this
device, refer to the MAX8952 data sheet.
MAX8649EWE+T
16 WLP (0.5mm pitch)
0xC0/0xC1
MAX8649AEWE+T 16 WLP (0.5mm pitch)
0xC4/0xC5
Applications
+Denotes a lead(Pb)-free/RoHS-compliant package.
Note: All devices operate over the -40°C to +85°C temperature
range.
Cell Phones and Smartphones
PDAs and MP3 Players
Typical Operating Circuit
Bump Configuration
TOP VIEW
(BUMPS ON BOTTOM)
2.5V TO
5.5V
1.8V TO
3.6V
VID1
MAX8649
MAX8649A
IN1
A1
AGND
A2
IN2
A4
+
IN2
LX
V
DD
A3
10μF
0.1μF
0.1μF
1μH
10μF
2.5V TO
5.5V
V
OUT
(0.75V TO
1.38V)
SNS+
B1
EN
B2
LX
B3
LX
B4
SCL
SDA
0.1μF
11Ω
PGND
IN1
PGND
PGND
SNS-
C1
VID0
C2
2.2μF
0.1μF
FSYNC
SNS+
SNS-
C3
SCL
D3
C4
SYNC
D4
EN
VID0
VID1
CPU
V
SDA
D2
DD
AGND
D1
WLP 0.5mm PITCH
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
ABSOLUTE MAXIMUM RATINGS
IN1, IN2 to AGND..................................................-0.3V to +6.0V
to AGND.........................................................-0.3V to +4.0V
Continuous Power Dissipation (T = +70°C)
A
16-Bump WLP 0.5mm Pitch
V
DD
LX, SNS+, VID0, VID1, EN to AGND..........-0.3V to (V
SCL, SDA, SYNC to AGND.........................-0.3V to (V
PGND, SNS- to AGND...........................................-0.3V to +0.3V
RMS LX Current ..............................................................1800mA
+ 0.3V)
+ 0.3V)
(derate 13mW/°C above +70°C)............................1040mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
IN1
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
WLP
Junction to Ambient Thermal Resistance (θ )............76°C/W
JA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
/MX8649A
(V
= V
= 3.6V, V
= V
= 0V, V
= 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at
DD A
IN1
IN2
AGND
PGND
T
= +25°C.) (Note 2)
A
PARAMETER
IN1, IN2 Operating Range
CONDITIONS
MIN
2.5
TYP
MAX
5.5
UNITS
V
V
V
Operating Range
1.8
3.6
DD
V
Undervoltage Lockout
DD
V
falling
0.54
2.10
0.865
50
1.35
2.20
V
DD
(UVLO) Threshold
V
UVLO Hysteresis
mV
V
DD
IN_ Undervoltage Lockout
(UVLO) Threshold
V
V
falling
2.15
IN
IN_ UVLO Hysteresis
70
mV
µA
T
A
T
A
T
A
T
A
T
A
T
A
= +25°C
= +85°C
= +25°C
= +85°C
= +25°C
= +85°C
0.01
0.01
0.25
0.25
0.35
0.35
1
1
1
= V
= 5.5V,
IN2
IN1
V
Shutdown Supply Current
DD
EN = V
= AGND
DD
IN1, IN2 Shutdown Supply
Current
V
= V
= 5.5V,
IN1
IN2
µA
µA
EN = V
= AGND
DD
V
V
= V
= 5.5V, SCL = SDA =
IN1
IN2
IN1, IN2 Standby Supply Current
, EN = AGND, I2C ready
DD
V
= V
= V
= 3.6V,
DD
IN1
IN2
T
= +25°C
= +85°C
0.02
0.02
1
A
A
V
Standby Supply Current
µA
SCL = SDA = V , EN = AGND,
DD
DD
I2C ready
T
LOGIC INTERFACE
EN, VID0, VID1
SYNC, SCL, SDA
EN, VID0, VID1
SYNC, SCL, SDA
1.4
V
V
= V
= 2.5V to 5.5V,
IN2
IN1
DD
Logic Input High Voltage (V
)
IH
V
V
= 1.8V to 3.6V
0.7 x V
DD
0.4
V
V
= V = 2.5V to 5.5V,
= 1.8V to 3.6V
IN1
DD
IN2
Logic Input Low Voltage (V )
IL
0.3 x V
DD
T
A
T
A
= +25°C
= +85°C
-1
0.01
0.01
+1
SDA, SCL, SYNC Logic Input
Current
V
= 0V or V = 3.6V,
IL IH
µA
EN = AGND
2
_______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 3.6V, V
= V
= 0V, V
= 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T =
DD A A
IN1
IN2
AGND
PGND
+25°C.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Controlled by I2C command:
VID0_PD = 1
VID1_PD = 1
VID0, VID1, EN Logic Input
Pulldown Resistor
200
320
450
kΩ
EN_PD = 1
2
I C INTERFACE
SDA Output Low Voltage
I2C Clock Frequency
I
= 3mA
0.03
0.1
0.4
V
SDA
BUF
400
kHz
Bus-Free Time Between START
and STOP
t
t
1.3
0.6
µs
µs
Hold Time Repeated START
Condition
HD_STA
SCL Low Period
SCL High Period
t
t
1.3
0.6
0.2
0.2
µs
µs
LOW
HIGH
Setup Time Repeated START
Condition
t
0.6
0.1
µs
SU_STA
SDA Hold Time
t
t
t
0
-0.01
0.05
0.1
µs
µs
µs
HD_DAT
SU_DAT
SU_STO
SDA Setup Time
0.1
0.6
Setup Time for STOP Condition
STEP-DOWN DC-DC REGULATOR
OPERATION_MODE_ = 0, V
OPERATION_MODE_ = 1, V
= 1.27V, no switching
54
9
70
µA
OUT
OUT
IN1 + IN2
Supply Current
= 1.27V, f = 3.25MHz
mA
sw
Minimum Output Capacitance
Required for Stability
V
= 0.75V to 1.38V,
= 0 to 1.8A
OUT
10
µF
I
OUT
OUT Voltage Range
10mV steps
Rising, 50mV hysteresis (typ)
0.750
1.65
1.380
1.9
V
V
Output Overvoltage Protection
1.8
_______________________________________________________________________________________
3
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 3.6V, V
= V
= 0V, V
= 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T =
A A
IN1
IN2
AGND
PGND
DD
+25°C.) (Note 2)
PARAMETER
CONDITIONS
= 2.5V to 5.5V, V = 1.27V
MIN
TYP
MAX
UNITS
No load, V
IN_
OUT
-0.5
+0.5
OPERATION_MODE_ = 1
I
= no load, V = 2.5V to 5.5V, V
= 0.75V,
= 1.38V,
OUT
IN_
OUT
OUT
OUT Voltage Accuracy
Load Regulation
-1.0
-0.5
+1.0
+0.5
%
OPERATION_MODE_ = 1
I
= no load, V = 2.5V to 5.5V, V
OUT
IN_
OPERATION_MODE_ = 1
R is the resistance from LX to SNS+ (output)
L
R /25
L
V/A
RAMP[2:0] = 000
RAMP[2:0] = 001
RAMP[2:0] = 010
RAMP[2:0] = 011
RAMP[2:0] = 100
RAMP[2:0] = 101
RAMP[2:0] = 110
RAMP[2:0] = 111
32.50
16.25
8.125
4.063
2.031
1.016
0.508
0.254
RAMP Timer
mV/µs
/MX8649A
Peak Current Limit
(p-Channel MOSFET)
PWM and hysteretic mode
Hysteretic mode
2.3
1.8
2.0
2.8
2.4
2.5
3.2
3.0
3.0
A
A
A
Valley Current Limit
(n-Channel MOSFET)
Negative Current Limit
(n-Channel MOSFET)
PWM mode
n-Channel Zero-Crossing
Threshold
50
mA
Ω
LX pFET On-Resistance
IN2 to LX, I = -200mA
LX
0.08
0.06
0.16
0.12
+1
OPERATION_MODE = 0
LX nFET On-Resistance
Ω
LX to PGND, I = 200mA
LX
T
T
= +25°C
= +85°C
-1
0.03
0.05
3.25
A
LX Leakage
V
= 5.5V or 0V
µA
LX
A
Internal oscillator, PWM
2.82
2.43
3.56
4.06
Internal oscillator, power-save mode before entering
PWM mode
3.25
Operating Frequency
13MHz option
19.2MHz option
26MHz option
f
f
f
/4
MHz
SYNC
SYNC
SYNC
/6
/8
4
_______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 3.6V, V
= V
= 0V, V
= 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T =
DD A A
IN1
IN2
AGND
PGND
+25°C.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Forced PWM mode only, minimum duty cycle in
(OPERATION_MODE_ = 1) = 0%
Minimum Duty Cycle
Maximum Duty Cycle
16
%
60
30
%
ns
Ω
Minimum On- and Off-Time
OUT Discharge Resistance
40
50
During shutdown or UVLO, from SNS+ to PGND
650
600
SNS+, SNS- Input Impedance
V
= 0.75V (OUT_MODEx [5:0] = 0b000000)
400
850
kΩ
OUT
Time Delay from PWM
to Power-Save Mode
Time required for error amplifier to stabilize before
switching mode
70
µs
µs
Time Delay from Power-Save
Mode to PWM
Time required for error amplifier to stabilize before
switching mode
140
SYNCHRONIZATION (SYNC)
SYNC = 00 default
SYNC = 1X default
SYNC = 01 default
18.9
14.2
9.5
26.0
19.2
13.0
13
38.0
28.5
19.0
SYNC Capture Range
MHz
ns
SYNC Pulse Width
PROTECTION CIRCUITS
Thermal-Shutdown Hysteresis
Thermal Shutdown
20
°C
°C
+160
Note 2: All devices are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by
A
design.
_______________________________________________________________________________________
5
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Typical Operating Characteristics
(Typical Operating Circuit, V
= V
= 3.6V, V
= V
= 0V, V
= 1.1V, V = 1.8V, T = +25°C, unless otherwise noted.)
DD A
IN1
IN2
AGND
PGND
OUT
EFFICIENCY vs. LOAD CURRENT
(0.9V OUTPUT, SYNC OFF)
EFFICIENCY vs. LOAD CURRENT
(1.1V OUTPUT, SYNC OFF)
EFFICIENCY vs. LOAD CURRENT
(1.3V OUTPUT, SYNC OFF)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
POWER SAVE
POWER SAVE
POWER SAVE
90
80
70
60
V
= 3.2V
3.6V
V
IN
= 3.2V
3.6V
V
IN
= 3.2V
3.6V
IN
50
40
30
20
10
0
4.2V
4.2V
4.2V
FORCED PWM
FORCED PWM
FORCED PWM
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
/MX8649A
EFFICIENCY vs. LOAD CURRENT
(0.9V OUTPUT, 26MHz SYNC)
EFFICIENCY vs. LOAD CURRENT
(1.1V OUTPUT, 26MHz SYNC)
EFFICIENCY vs. LOAD CURRENT
(1.3V OUTPUT, 26MHz SYNC)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
POWER SAVE
POWER SAVE
POWER SAVE
V
= 3.2V
3.6V
V
IN
= 3.2V
3.6V
V
IN
= 3.2V
3.6V
IN
4.2V
4.2V
4.2V
FORCED PWM
FORCED PWM
FORCED PWM
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
SWITCHING FREQUENCY
vs. LOAD CURRENT
SWITCHING FREQUENCY
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT vs.
SUPPLY VOLTAGE (POWER SAVE)
3.6
3.5
3.4
3.3
3.2
3.1
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.6
0.5
0.4
0.3
0.2
0.1
FORCED PWM
26MHz SYNC
NO SYNC
TRANSITION TO PWM
POWER SAVE
NO SYNC
1.3V OUTPUT, 500mA LOAD
V
V
= 3.6V
IN
= 1.3V
OUT
3.0
-40
-15
10
35
60
85
0
0.3
0.6
0.9
1.2
1.5
1.8
2.5
3.5
4.5
5.5
TEMPERATURE (°C)
LOAD CURRENT (A)
SUPPLY VOLTAGE (V)
6
_______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
Typical Operating Characteristics (continued)
(Typical Operating Circuit, V
= V
= 3.6V, V
= V
= 0V, V
= 1.1V, V = 1.8V, T = +25°C, unless otherwise noted.)
DD A
IN1
IN2
AGND
PGND
OUT
NO-LOAD SUPPLY CURRENT vs.
SUPPLY VOLTAGE (FORCED PWM)
OUTPUT VOLTAGE vs. LOAD CURRENT
OUTPUT VOLTAGE vs. LOAD CURRENT
1.115
1.32
1.31
1.30
1.29
1.28
1.27
1.26
20
18
16
14
12
10
8
NO SYNC
T
= +85NC
T
A
= +25NC
A
1.110
FORCED PWM
1.105
1.100
26MHz SYNC
T
A
= -40NC
1.095
POWER SAVE
6
POWER SAVE
4
1.090
V
= 1.1V
1.5
2
V
= 1.3V
OUT
OUT
1.085
0
0
0.3
0.6
0.9
1.2
1.8
0
0.4
0.8
1.2
1.6
2.0
2.5
3.5
4.5
5.5
LOAD CURRENT (A)
LOAD CURRENT (A)
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE vs. LOAD CURRENT
LIGHT LOAD SWITCHING WAVEFORMS
MAX8649/49A toc14
0.910
0.905
0.900
0.895
0.890
0.885
0.880
FORCED PWM
V
OUT
20mV/div
2V/div
V
LX
POWER SAVE
I
L
200mA/div
V
= 0.9V
1.5
OUT
10mA LOAD, V
= 1.3V
OUT
0
0.3
0.6
0.9
1.2
1.8
2μs/div
LOAD CURRENT (A)
MEDIUM LOAD SWITCHING
WAVEFORMS
HEAVY LOAD SWITCHING WAVEFORMS
MAX8649/49A toc16
MAX8649/49A toc15
20mV/div
2V/div
V
V
20mV/div
2V/div
OUT
OUT
V
LX
V
LX
I
L
I
L
1A/div
1.8A LOAD
500mA LOAD
= 1.3V
500mA/div
V
OUT
= 1.3V
V
OUT
200ns/div
200ns/div
_______________________________________________________________________________________
7
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, V
= V
= 3.6V, V
= V
= 0V, V
= 1.1V, V
= 1.8V, T = +25°C, unless otherwise noted.)
IN1
IN2
AGND
PGND
OUT
DD A
LIGHT LOAD STARTUP WAVEFORMS
HEAVY LOAD STARTUP WAVEFORMS
MAX8649/49A toc17
MAX8649/49A toc18
10I LOAD
1V/div
1I LOAD
1V/div
V
OUT
V
OUT
100mA/div
200mA/div
I
IN
I
IN
500mA/div
5V/div
500mA/div
5V/div
I
L
I
L
V
V
EN
EN
200μs/div
200μs/div
/MX8649A
PREBIAS STARTUP WAVEFORMS
LINE TRANSIENT RESPONSE (4.2V TO
(FORCED PWM)
3.2V TO 4.2V) SYNC OFF
MAX8649/49A toc19
MAX8649/49A toc20
OUTPUT PREBIASED TO 1.3V
STARTUP TO 1.1V
1V/div
V
OUT
V
IN
500mV/div
V
OUT
20mV/div
I
L
1A/div
5V/div
200mA/div
I
L
300mA LOAD
20μs/div
V
EN
200μs/div
LINE TRANSIENT RESPONSE (4.2V TO
LOAD TRANSIENT RESPONSE
3.2V TO 4.2V) 26MHz SYNC
(1mA TO 1A)
MAX8649/49A toc21
MAX8649/49A toc22
1V/div
50mV/div
V
IN
V
OUT
V
OUT
20mV/div
500mA/div
1A/div
I
L
I
L
200mA/div
I
OUT
300mA LOAD
20μs/div
40μs/div
8
_______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
Typical Operating Characteristics (continued)
(Typical Operating Circuit, V
= V
= 3.6V, V
= V
= 0V, V
= 1.1V, V
= 1.8V, T = +25°C, unless otherwise noted.)
IN1
IN2
AGND
PGND
OUT
DD A
LOAD TRANSIENT RESPONSE
(1A to 1mA)
LOAD TRANSIENT RESPONSE
(5mA TO 1.8A)
MAX8649/49A toc23
MAX8649/49A toc24
50mV/div
1A/div
V
OUT
V
OUT
50mV/div
I
L
500mA/div
I
L
I
1A/div
I
1A/div
OUT
OUT
40μs/div
40μs/div
LOAD TRANSIENT RESPONSE
(1.8A to 5mA)
SYNCHRONIZATION RESPONSE
(26MHz SYNC)
MAX8649/49A toc26
MAX8649/49A toc25
FORCED PWM, NO LOAD
2V/div
V
SYNC
V
OUT
100mV/div
1A/div
V
OUT
20mV/div
2V/div
I
L
V
LX
I
OUT
I
L
200mA/div
1A/div
1μs/div
20μs/div
OUTPUT VOLTAGE CHANGE RESPONSE
MAX8649/49A toc27
10I LOAD,
POWER SAVE
32mV/μs RAMP
V
VID0
2V/div
1.3V
0.9V
0.9V
500mV/div
V
OUT
I
L
200mA/div
40μs/div
_______________________________________________________________________________________
9
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Bump Description
PIN
NAME
FUNCTION
Analog Supply Voltage Input. The input voltage range is 2.5V to 5.5V. Place an 11Ω resistor between
IN1 and the input supply. Bypass IN1 to analog ground with a 0.1µF ceramic capacitor as close as
possible to the IC. Connect IN1 and IN2 to the same power source.
A1
IN1
A2
A3
AGND
VID1
Analog Ground. Connect AGND to the PCB ground plane.
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
Power-Supply Voltage Input. The input voltage range is from 2.5V to 5.5V. IN2 powers the internal
p-channel and n-channel MOSFETs. Bypass IN2 to PGND with 10µF and 0.1µF ceramic capacitors
as close as possible to the IC. Connect IN1 and IN2 to the same power source.
A4
IN2
B1
B2
SNS+
EN
Output Voltage Remote Sense, Positive Input. Connect SNS+ directly to the output at the load.
Logic Enable Input. Drive EN high to enable the DC-DC step-down regulator, or low to place in
shutdown mode. In shutdown mode, this logic input has an internal pulldown resistor to AGND.
Inductor Connection. LX is connected to the drains of the internal p-channel and n-channel
MOSFETs. LX is high impedance during shutdown.
B3, B4
C1
LX
/MX8649A
SNS-
VID0
PGND
Output Voltage Sense, Negative Input. Connect to a quiet ground directly at the IC.
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
C2
C3, C4
Power Ground. Connect both PGND bumps to the PCB ground plane.
Logic Input Supply Voltage. Connect V
to the logic supply driving SDA, SCL, and SYNC. Bypass
2
DD
D1
V
V
to AGND with a 0.1µF ceramic capacitor. When V
drops below the UVLO threshold, the I C
DD
DD
DD
registers are reset, but the EN control is still active in this mode.
2
D2
D3
SDA
SCL
I C Data Input. Data is read on the rising edge of SCL and data is clocked out on the falling edge of SCL.
2
I C Clock Input
External Clock Synchronization Input. Connect SYNC to a 13MHz, 19.2MHz, or 26MHz system clock.
2
D4
SYNC
The DC-DC regulator can be forced to synchronize to this external clock depending on I C setting. See
Table 8. SYNC does not have an internal pulldown. Connect SYNC to AGND if not used.
10 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
SYNC
OSC
CLOCK GEN
IN2
LX
V
DD
2
SCL
SDA
I C INTERFACE
PWM LOGIC
IN1
EN
PGND
SNS+
V
VOLTAGE
CONTROL, V
BIAS, ETC.
DAC
VID0
VID1
,
REF
SNS-
MAX8649
MAX8649A
AGND
Figure 1. Block Diagram
For each of the different output modes, the following
parameters are programmable:
Detailed Description
The MAX8649/MAX8649A high-efficiency, 3.25MHz
step-down switching regulator delivers up to 1.8A of
output current. The device operates from a 2.5V to 5.5V
input voltage range, and the output voltage is I2C pro-
grammable from 0.75V to 1.38V in 10mV increments.
Remote sense ensures precise DC regulation at the
load. Total output error is less than 2% over load, line,
•
•
•
Output voltage from 0.75V to 1.38V in 10mV steps
Mode of operation: Forced PWM or power save
Enable/disable of synchronization of switching
frequency to external clock source
The relation between the VID0/VID1 and operation
mode is given by Table 1.
2
and temperature. The ICs feature different I C address-
es so that multiple devices may be used in a system
(see the Ordering Information section.)
The VID_ inputs have internal pulldown resistors. These
pulldown resistors can be disabled through the CONTROL
register after the ICs are enabled, achieving lowest
possible quiescent current. When EN is low, the CON-
TROL register is reset to default, enabling the pulldown
resistors (see Table 7).
Dynamic Voltage Scaling
The output voltage is dynamically adjusted by use of
the VID0 and VID1 logic inputs, allowing selection
between four predefined operation modes/voltage
configurations.
Table 1. VID0 and VID1 Configuration
DEFAULT
SWITHCING
MODE
DEFAULT
OUTPUT
VOLTAGE (V)
DEFAULT
SYNCHRONIZATION
2
VID1
VID0
MODE
I C REGISTER
0
0
1
1
0
1
0
1
MODE0
MODE1
MODE2
MODE3
Table 3
Table 4
Table 5
Table 6
FORCED PWM
POWER SAVE
FORCED PWM
FORCED PWM
OFF
OFF
OFF
OFF
1.27
1.05
1.23
1.05
______________________________________________________________________________________ 11
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
forced-PWM mode. This is done by writing to the
MODE_ registers (see Table 3 to Table 6). The mode of
operation can be changed at any time.
Enable
The DC-DC step-down regulators are enabled/disabled
using the EN logic input. The EN input is able to handle
input voltages up to V , ensuring that the EN logic
IN1
In power-save mode, the PWM switching frequency
depends on the load current. For medium to high load
condition, the ICs operate in fixed-frequency PWM
mode. For light load conditions, the ICs operate in hys-
teretic mode. The proprietary hysteretic PWM control
scheme ensures high efficiency, fast switching, and
fast transient response. This control scheme is simple:
when the output voltage is below the regulation thresh-
old, the error comparator begins a switching cycle by
turning on the high-side switch. This switch remains on
until the minimum on-time expires and the output volt-
age is above the regulation threshold plus hysteresis
or the inductor current is above the current-limit
threshold. Once off, the high-side switch remains off
until the minimum off-time expires and the output volt-
age falls again below the regulation threshold. During
the off period, the low-side synchronous rectifier turns
on and remains on until either the high-side switch
turns on again or the inductor current approaches
zero. The internal synchronous rectifier eliminates the
need for an external Schottky diode.
input can be controlled by a wide variety of
signals/supplies.
The EN input has an internal pulldown resistor that
ensures EN is discharged during off conditions. This
pulldown resistor can be disabled through the
CONTROL register (see Table 7) once the ICs are
enabled, achieving lowest possible quiescent current.
When EN is low, the CONTROL register is reset to
default, enabling the pulldown resistors on EN, VID0,
and VID1. See Figures 2 and 3 for detailed information
on power-up and power-down sequencing and opera-
tion mode changes.
DC-DC Regulator Operating Modes
The ICs operate in one of four modes determined by
the state of the VID_ inputs (see Table 1). At power-up,
the ICs are default set to operate in power-save opera-
tion for MODE1 and forced-PWM mode for MODE0,
MODE2, and MODE3. For each of the operation modes,
MODE0 to MODE3, the DC-DC step-down regulators
can be set to operate in either power-save mode or
/MX8649A
A
B
C
D
E
IN
1.27V
1.23V
1.05V
OUT
EN
VID1
VID0
V
DD
A: POWER CONNECTED TO IN1 AND IN2.
B: EN LOGIC INPUT PULLED HIGH, OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I C REGISTER FOR MODE0 (SEE TABLE 1).
C: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE I C REGISTER FOR MODE1.
2
2
2
D: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF I C REGISTER FOR MODE3.
2
E: V PULLED HIGH, ENABLING I C INTERFACE.
DD
Figure 2. Power-Up Sequence
12 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
A
B
IN
OUT
EN
V
DD
2
A: V PULLED LOW, I C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1) AND THE OUTPUT VOLTAGE CHANGES TO THE DEFAULT VALUE.
DD
B: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS SHUTDOWN MODE.
Figure 3a. Shutdown by Pulling V
Low Before EN
DD
A
B
IN
OUT
EN
V
DD
2
A: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS I C READY MODE, OUTPUT DISABLED.
2
B: V PULLED LOW, I C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).
DD
Figure 3b. Shutdown by Pulling EN Low Before V
DD
A
IN1
OUT
EN
V
DD
2
A: IN1 DROPS BELOW UVLO, IC ENTERS SHUTDOWN MODE, I C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).
Figure 3c. Shutdown Due to IN1 Undervoltage Lockout
______________________________________________________________________________________ 13
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
The transition between PWM and hysteretic operation is
based on the number of consecutive zero-crossing
cycles. When more than 16 consecutive zero-crossing
cycles are detected, the DC-DC step-down converter
enables the bias for hysteretic operation. Once correct-
ly biased and the number of consecutive zero-crossing
cycles exceeds 24, the DC-DC step-down converter
begins hysteretic operation.
DC-DC converter starting PWM, the converter supports
full current on the output during hysteretic operation.
See Figure 5 for a detailed state diagram.
Power-save operation offers improved efficiency at light
loads by changing to hysteretic mode, reducing the
switching frequency depending on the load condition.
With moderate to heavy loading, the regulator switches
at a fixed switching frequency as it does in forced-PWM
mode. In power-save mode, the transition from hys-
teretic mode to fixed-frequency switching occurs at the
load current specified in the following equation:
During hysteretic operation, there is a silent DC offset
due to the use of valley regulation. See Figure 4.
When operating in power-save mode and the load cur-
rent is increased so that the number of consecutive
zero-crossing cycles is less than 16, the PWM mode is
biased. Once fully biased and the number of zero-
crossing cycles drops below 8, the DC-DC converter
then begins PWM operation. Since there is a delay
between the increase in load current and the
V
− V
2×L
V
OUT
V × f
IN OSC
IN
OUT
I
=
×
OUT
In forced-PWM mode, the regulator operates with a
constant (3.25MHz or synchronized to external clock
source) switching frequency regardless of output load.
Forced-PWM mode is ideal for low-noise systems
because switching harmonics occur at multiples of the
constant switching frequency and are easily filtered.
However, light-load power consumption in forced-PWM
mode is higher than that of power-save mode.
/MX8649A
REGULATION
THRESHOLD
OUTPUT
RIPPLE
Figure 4. Output Regulation in Hysteretic Operation
MORE THAN 16 CONSECUTIVE
ZERO-CROSSING CYCLES
PWM MODE
WITH POWER-SAVE
MODE BIASED
PWM
MODE
POWER SAVE NOT READY
LESS THAN 8 CONSECUTIVE
ZERO-CROSSING CYCLES
LESS THAN 8 CONSECUTIVE
ZERO-CROSSING CYCLES
AND PWM MODE READY
MORE THAN 24 CONSECUTIVE
ZERO-CROSSING CYCLES
AND POWER-SAVE MODE READY
MORE THAN 24 CONSECUTIVE
ZERO-CROSSING CYCLES
POWER-SAVE
MODE WITH
PWM BIASED
POWER-SAVE
MODE
PWM NOT READY
LESS THAN 16 CONSECUTIVE
ZERO-CROSSING CYCLES
Figure 5. Mode Change for DC-DC Step-Down Converter
14 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
MAX8649
mode. When the regulator is set for power-save mode
and the RAMP_DOWN bit is cleared, the ramp-down is
not actively controlled, and the regulator output voltage
ramps down at the rate determined by the output
capacitance and the external load. Small loads result in
an output-voltage decay that is slower than that speci-
fied by RAMP; large loads result in an output-voltage
decay that is no faster than that specified by RAMP
When the RAMP_DOWN bit is set in power-save mode,
the zero-cross comparator is disabled during the ramp-
down condition. Active ramp-down functionality is
inherent in forced-PWM operation.
Soft-Start
The ICs include internal soft-start circuitry that eliminates
inrush current at startup, reducing transients on the
input source (see the Typical Operating Charac-
teristics). Soft-start is particularly useful for high-imped-
ance input sources, such as Li+ and alkaline cells.
When enabling the ICs into a prebiased output, the ICs
perform a complete soft-start cycle.
Synchronous Rectification
An internal n-channel synchronous rectifier eliminates
the need for an external Schottky diode and improves
efficiency. The synchronous rectifier turns on during the
second half of each switching cycle (off-time). During
this time, the voltage across the inductor is reversed,
and the inductor current ramps down. In PWM mode,
the synchronous rectifier turns off at the end of the
switching cycle. In power-save mode, the synchronous
rectifier turns off when the inductor current falls below
50mA (typ) or at the end of the switching cycle,
whichever occurs first.
Calculate the maximum and minimum values for the
ramp rate as follows:
V
1
OUT _LSB
t
=
×
RAMP _MIN
RAMP _ CODE
t
2
CLK _MAX
V
1
OUT _LSB
t
=
×
RAMP _MAX
RAMP _ CODE
t
2
CLK _MIN
where:
Ramp-Rate Control
The output voltage has an actively controlled variable
ramp rate, set with the I2C interface (see Figures 6, 7,
and 8). The value set in the RAMP register controls the
output voltage ramp rate. The RAMP_DOWN bit con-
trols the active ramp-down behavior in power-save
V
=10mV
OUT _LSB
1
t
t
=
CLK _MAX
f
SW _MIN
1
=
CLK _MIN
f
SW _MAX
OUTPUT
VOLTAGE
f
f
= 3.25MHz 10% for PWM operation
SW
DELTA V = 10mV
= 3.25MHz 25% for hysteretic operation
SW
V
'
OUT
f
SYNC
n
f
=
SW
f
= frequency of external clock
SYNC
10mV/RAMP RATE
TIME
V
OUT
n = 4 for 13MHz, 6 for 19.2MHz, and 8 for 26MHz
RAMP_CODE = value of the RAMP[2:0] register (see
Table 9)
Figure 6. Ramp-Up Function
FINAL
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
V
OUT
DELTA
V = 10mV
10mV/RAMP
RATE
V
'
OUT
MODE CHANGE
TO HIGHER VOUT
MODE CHANGE
TO LOWER VOUT
TIME
Figure 7. Ramp-Down Function
Figure 8. Mode Change Before Final Value is Reached
______________________________________________________________________________________ 15
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
SDA
SCL
DATA LINE STABLE DATA VALID
CHANGE OF DATA ALLOWED
2
Figure 9. I C Bit Transfer
/MX8649A
Each transmit sequence is framed by a START (S) con-
dition and a STOP (P) condition. Each data packet is 9
bits long; 8 bits of data followed by the acknowledge
bit. The ICs support data transfer rates with SCL fre-
quencies up to 400kHz.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the ICs. When internal thermal sensors detect a
die temperature in excess of +160°C (typ), the
DC-DC step-down regulator is shut down, allowing the
IC to cool. The DC-DC step-down regulator is turned on
again after the junction cools by 20°C (typ), resulting in
a pulsed output during continuous thermal-overload
conditions.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by
issuing a START (S) condition. A START condition is a
high-to-low transition on SDA with SCL high. A STOP
(P) condition is a low-to-high transition on SDA, while
SCL is high (Figure 10).
During thermal overload, the I2C interface remains
active and all register values are maintained.
2
I C Interface
An I2C-compatible, 2-wire serial interface controls the
step-down converter output voltage, ramp rate, operat-
ing mode, and synchronization. The serial bus consists
of a bidirectional serial-data line (SDA) and a serial-
clock input (SCL). The master initiates data transfer on
the bus and generates SCL to permit data transfer.
SDA
SCL
I2C is an open-drain bus. SDA and SCL require pullup
resistors (500Ω or greater). Optional (24Ω) in series
with SDA and SCL protect the device inputs from high-
voltage spikes on the bus lines. Series resistors also
minimize crosstalk and undershoot on bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse (see Figure 9).
Changes in SDA while SCL is high are control signals
(see the START and STOP Conditions section for more
information).
START
CONDITION
STOP
CONDITION
2
Figure 10. I C START and STOP Conditions
16 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
SDA
SCL
MASTER
TRANSMITTER/RECEIVER
SLAVE
TRANSMITTER/RECEIVER
SLAVE RECEIVER
2
Figure 11. I CMaster/Slave Configuration
A START condition from the master signals the begin-
ning of a transmission to the ICs. The master termi-
nates transmission by issuing a not acknowledge
followed by a STOP condition (see the Acknowledge
section for more information). The STOP condition frees
the bus. To issue a series of commands to the slave,
the master can issue REPEATED START (Sr) com-
mands instead of a STOP command to maintain control
of the bus. In general, a REPEATED START command
is functionally equivalent to a regular START command.
SDA OUTPUT
FROM TRANSMITTER
D0
D7
D6
NOT ACKNOWLEDGE
SDA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
8
SCL FROM
MASTER
1
2
9
When a STOP condition or incorrect address is detect-
ed, the MAX8649/MAX8649A internally disconnects
SCL from the serial interface until the next START con-
dition, minimizing digital noise and feedthrough.
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START CONDITION
System Configuration
A device on the I2C bus that generates a message is
called a transmitter and a device that receives the mes-
sage is a receiver. The device that controls the mes-
sage is the master and the devices that are controlled
by the master are called slaves. See Figure 11.
2
Figure 12. I C Acknowledge
The device that acknowledges must pull down the
DATA line during the acknowledge clock pulse, so that
the DATA line is stable low during the high period of the
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
data to the transmitter by not generating an acknowl-
edge on the last byte that has been clocked out of the
slave. In this case, the transmitter must leave SDA high
to enable the master to generate a STOP (P) condition.
Acknowledge
The number of data bytes between the START and
STOP conditions for the transmitter and receiver are
unlimited. Each 8-bit byte is followed by an acknowl-
edge bit. The acknowledge bit is a high-level signal put
on SDA by the transmitter during which time the master
generates an extra acknowledge-related clock pulse. A
slave receiver that is addressed must generate an
acknowledge after each byte it receives. Also, a master
receiver must generate an acknowledge after each
byte it receives that has been clocked out of the slave
transmitter. See Figure 12.
Register Reset
The I2C resisters reset back to their default values when
the voltage at either IN1 or V
corresponding UVLO threshold (see the Electrical
Characteristics table).
drops below the
DD
______________________________________________________________________________________ 17
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
A
B
C
D
E
OUT
S
SLAVE ID
ASr
REG PTR
ASr
DATA
A
P
SDA
VID0
VID1
V
2
2
2
DD
A: I C START COMMAND.
B: I C SLAVE ADDRESS OF SEND OUT.
C: I C REGISTER POINTER SEND OUT.
D: DATA SEND OUT.
2
E: ISSUE ACKNOWLEDGE AND CHANGES THE OUTPUT VOLTAGE ACCORDING TO NEW I C SETTINGS.
Figure 13. Update Output Operation
Update of Output Operation Mode
If updating the output voltage or Operation Mode regis-
ter for the mode that the ICs are currently operating in,
the output voltage/operation mode is updated at the
same time the ICs send the acknowledge for the I2C
data byte (see Figure 13).
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
/MX8649A
7) The slave acknowledges the data byte.
8) The slave updates with the new data.
9) The master sends a STOP (P) condition.
Slave Address
A bus master initiates communication with a slave
device (MAX8649/MAX8649A) by issuing a START (S)
condition followed by the slave address (the slave
address byte consists of 7 address bits (1100 000x for
MAX8649; 1100 010x for MAX8649A) and a read/write
bit (R/W)). After receiving the proper address, the ICs
issues an acknowledge by pulling SDA low during the
ninth clock cycle.
In addition to the write-byte protocol, the ICs can write to
multiple registers as shown in Figure 14b. This protocol
allows the I2C master device to address the slave only
once and then send data to a sequential block of regis-
ters starting at the specified register pointer.
Use the following procedure to write to a sequential
block of registers:
1) The master sends a start command.
2
The ICs provide different I C slave addresses, allowing
2) The master sends the 7-bit slave address followed
by a write bit.
up to two devices to be used in a system without caus-
ing bus collisions. Contact the factory for availability.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
Write Operations
The ICs recognize the write byte protocol as defined in
the SMBus specification and shown in Figures 14a and
14b. The write byte protocol allows the I2C master device
to send 1 byte of data to the slave device. The write byte
protocol requires a register pointer address for the sub-
sequent write. The ICs acknowledge any register pointer
even though only a subset of those registers actually
exists in the device. The write byte protocol is as follows:
4) The master sends the 8-bit register pointer of the
first register to write.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave acknowledges the data byte.
8) The slave updates with the new data.
1) The master sends a start command.
9) Steps 6 to 8 are repeated for as many registers in
the block, with the register pointer automatically
incremented each time.
2) The master sends the 7-bit slave address followed
by a write bit.
10) The master sends a STOP condition.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
18 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL
1
7
1
0
1
8
1
8
1
1
NUMBER OF BITS
S
SLAVE ADDRESS
A
REGISTER POINTER
A
DATA
A
P
R/W
b) WRITING TO MULTIPLE REGISTERS
NUMBER OF BITS
1
7
1
1
8
1
8
1
8
1
...
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
DATA X
A
DATA X+1
A
R/W
8
1
8
1
NUMBER OF BITS
...
DATA X+n-1
A
DATA X+n
A
P
Figures 14a and 14b. Writing to the ICs
Read Operations
1) The master sends a start command.
The method for reading a single register (byte) is
shown in Figure 15a. To read a single register:
2) The master sends the 7-bit slave address followed
by a write bit.
1) The master sends a start command.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
2) The master sends the 7-bit slave address followed
by a write bit.
4) The master sends an 8-bit register pointer of the
first register in the block.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
5) The slave acknowledges the register pointer.
6) The master sends a repeated START condition.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a repeated START (S) condition.
7) The master sends the 7-bit slave address followed
by a read bit.
7) The master sends the 7-bit slave address followed
by a read bit.
8) The slave asserts an acknowledge by pulling SDA low.
9) The slave sends the 8-bit data (contents of the reg-
ister).
8) The slave asserts an acknowledge by pulling SDA low.
9) The slave sends the 8-bit data (contents of the
register).
10) The master asserts an acknowledge by pulling SDA
low when there is more data to read, or a not
acknowledge by keeping SDA high when all data
has been read.
10) The master asserts a not acknowledge by keeping
SDA high.
11) Steps 9 and 10 are repeated for as many registers
in the block, with the register pointer automatically
incremented each time.
11) The master sends a STOP (P) condition.
In addition, the MAX8649/MAX8649A can read a block of
multiple sequential registers as shown in Figure 15b. Use
the following procedure to read a sequential block of reg-
isters:
12) The master sends a STOP condition.
______________________________________________________________________________________ 19
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) READING A SINGLE REGISTER
1
7
1
0
1
8
1
1
7
1
1
8
1
1
NUMBER OF BITS
S
SLAVE ADDRESS
A
REGISTER POINTER
A
Sr
SLAVE ADDRESS
1
A
DATA
A
P
R/W
R/W
b) READING MULTIPLE REGISTERS
NUMBER OF BITS
1
7
1
1
8
1
1
7
1
8
1
1
1
...
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
Sr
SLAVE ADDRESS
A
DATA X
A
R/W
...
R/W
1
8
1
8
8
1
1
NUMBER OF BITS
...
DATA X+1
A
DATA X+n-1
A
DATA X+n
A
P
/MX8649A
Figures 15a and 15b. Reading from the ICs
SDA
t
BUF
t
SU_STA
t
SU_DAT
t
HD_STA
t
LOW
t
SU_STO
t
HD_DAT
t
SCL
HIGH
t
HD_STA
t
R
t
F
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
2
Figure 16. I C Timing Diagram
20 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
2
Table 2. I C Register Map
POINTER
REGISTER
POR
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
OPER
MODE
SYNC
MODE
0x00
MODE0
0xB4
OUT MODE0[5:0]
OUT MODE1[5:0]
OUT MODE2[5:0]
OUT MODE3[5:0]
OPER
MODE
SYNC
MODE
0x01
0x02
0x03
MODE1
MODE2
MODE3
0x1E
0xB0
0x9E
OPER
MODE
SYNC
MODE
OPER
MODE
SYNC
MODE
0x04
0x05
0x06
0x08
0x09
CONTROL
SYNC
0xE0
0x00
0x01
0x20
0x0E
EN_PD
VID0_PD VID1_PD
—
—
—
—
—
—
—
SYNC[1:0]
RAMP[2:0]
—
—
—
—
—
—
RAMP
FORCE_HYS FORCE_OSC
RAMP_DOWN
CHIP_ID1
CHIP_ID2
DIE TYPE[7:4]
DASH[3:0]
DIE TYPE[3:0]
MASK REV[3:0]
2
Table 3. I C Register: MODE0
This register contains output voltage and operation mode control for MODE0, VID0 = GND, VID1 = GND.
REGISTER NAME
MODE0
0x00h
Address
Reset Value
Type
0xB4h
Read/write
Special Features
Reset upon V
or IN1 UVLO
DD
DEFAULT
VALUE
BIT
NAME
DESCRIPTION
DC-DC Step-Down Converter Operation Mode for MODE0
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
B7 (MSB)
OPERATION_MODE0
1
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
B6
SYNC_MODE0
0
1 = DC-DC converter synchronizes to external SYNC input when available.
Output Voltage Selection for MODE0
000000 = 0.75V
000001 = 0.76V
110011 = 1.26V
110100 = 1.27V
B5
B4
B3
OUT_ MODE0 [5:0]
110100
B2
110101 = 1.28V
111110 = 1.37V
B1
B0 (LSB)
111111 = 1.38V
______________________________________________________________________________________ 21
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
2
Table 4. I C Register: MODE1
This register contains output voltage and operation mode control for MODE1, VID1 = GND, VID0 = V
.
DD
REGISTER NAME
MODE1
0x01h
Address
Reset Value
Type
0x1Eh
Read/write
Special Features
Reset upon V
or IN1 UVLO
DD
DEFAULT
VALUE
BIT
NAME
DESCRIPTION
DC-DC Step-Down Converter Operation Mode for MODE1
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
B7 (MSB)
OPERATION_MODE1
0
0
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
/MX8649A
B6
SYNC_MODE1
1 = DC-DC converter synchronizes to external SYNC input when available.
Output Voltage Selection for MODE1
000000 = 0.75V
000001 = 0.76V
011101 = 1.04V
011110 = 1.05V
B5
B4
B3
OUT_MODE1[5:0]
011110
B2
011111 = 1.06V
111110 = 1.37V
B1
B0 (LSB)
111111 = 1.38V
22 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
2
Table 5. I C Register: MODE2
This register contains output voltage and operation mode control for MODE2, VID1 = V , VID0 = GND.
DD
REGISTER NAME
MODE2
0x02h
Address
Reset Value
Type
0xB0h
Read/write
Special Features
Reset upon V
or IN1 UVLO
DD
DEFAULT
VALUE
BIT
NAME
DESCRIPTION
DC-DC Step-Down Converter Operation Mode for MODE2
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
B7 (MSB)
OPERATION_MODE2
1
0
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
B6
SYNC_MODE2
1 = DC-DC converter synchronizes to external SYNC input when available.
Output Voltage Selection for MODE2
000000 = 0.75V
000001 = 0.76V
101110 = 1.21V
101111 = 1.22V
B5
B4
B3
OUT_MODE2[5:0]
110000
B2
110000 = 1.23V
111110 = 1.37V
B1
B0 (LSB)
111111 = 1.38V
______________________________________________________________________________________ 23
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
2
Table 6. I C Register: MODE3
This register contains output voltage and operation mode control for MODE3, VID1 = V , VID0 = V
.
DD
DD
REGISTER NAME
MODE3
0x03h
Address
Reset Value
Type
0x9Eh
Read/write
Special Features
Reset upon V
or IN1 UVLO
DD
DEFAULT
VALUE
BIT
NAME
DESCRIPTION
DC-DC Step-Down Converter Operation Mode for MODE3
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
B7 (MSB)
OPERATION_MODE3
1
0
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
/MX8649A
B6
SYNC_MODE3
1 = DC-DC converter synchronizes to external SYNC input when available.
Output Voltage Selection for MODE3
000000 = 0.75V
000001 = 0.76V
011101 = 1.04V
011110 = 1.05V
B5
B4
B3
OUT_MODE3[5:0]
011110
B2
011111 = 1.06V
111110 = 1.37V
B1
B0 (LSB)
111111 = 1.38V
24 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
2
Table 7. I C Register: CONTROL
This register enables or disables pulldown resistors.
REGISTER NAME
CONTROL
0x04h
Address
Reset Value
Type
0xE0h
Read/write
Special Features
Reset upon V , IN1 UVLO or EN pulled low
DD
DEFAULT
VALUE
BIT
B7 (MSB)
B6
NAME
EN_PD
DESCRIPTION
0 = Pulldown on EN input is disabled.
1
1 = Pulldown on EN input is enabled.
0 = Pulldown on VID0 input is disabled.
1 = Pulldown on VID0 input is enabled.
VID0_PD
VID1_PD
1
1
0 = Pulldown on VID1 input is disabled.
1 = Pulldown on VID1 input is enabled.
B5
B4
B3
—
—
—
—
—
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
0
0
0
0
0
B2
B1
B0 (LSB)
______________________________________________________________________________________ 25
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
2
Table 8. I C Register: SYNC
This register specifies the clock frequency of external clock source.
REGISTER NAME
SYNC
0x05h
0x00h
Read
Address
Reset Value
Type
Special Features
Reset upon V
or IN1 UVLO
DD
DEFAULT
VALUE
BIT
NAME
DESCRIPTION
Sets Clock Frequency of External Clock Present on SYNC Input
B7 (MSB)
00 = 26MHz
01 = 13MHz
10 = 19.2MHz
11 = 19.2MHz
SYNC[1:0]
00
B6
B5
B4
—
—
—
—
—
—
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
0
0
0
0
0
0
/MX8649A
B3
B2
B1
B0 (LSB)
26 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
2
Table 9. I C Register: RAMP
This register controls of ramp-up/down function.
REGISTER NAME
RAMP
0x06h
0x01h
Read
Address
Reset Value
Type
Special Features
Reset upon V
or IN1 UVLO
DD
DEFAULT
VALUE
BIT
NAME
DESCRIPTION
Control the RAMP Timing
000 = 32mV/µs
001 = 16mV/µs
010 = 8mV/µs
B7 (MSB)
B6
B5
RAMP[2:0]
011 = 4mV/µs
100 = 2mV/µs
101 = 1mV/µs
110 = 0.5mV/µs
111 = 0.25mV/µs
000
Only Valid When Converter is Operating in OPERATION_MODE 0
0 = Automatically change between power-save mode and PWM mode,
depending on load current.
1 = Converter always operates in power-save mode regardless of load
current as long as OPERATION_MODE = 0. If OPERATION_MODE =
1, this setting is ignored.
B4
FORCE_HYS
FORCE_OSC
0
0
Force Oscillator While Running in Hysteretic Mode
0 = Internal oscillator is disabled in power save when operating in
hysteretic mode.
B3
1 = Internal oscillator is enabled in power save even when operating in
hysteretic mode.
B2
B1
—
RAMP_DOWN
—
Reserved for future use.
0
0
1
Active Ramp-Down Control for Power-Save Mode
0 = Active ramp disabled for power-save mode.
1 = During ramp-down, the error crossing detector is disabled allowing
negative current to flow thought the nMOS device.
B0 (LSB)
Reserve for future use.
______________________________________________________________________________________ 27
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
2
Table 10. I C Register: CHIP_ID1
This register contains the die type number (20).
REGISTER NAME
CHIP_ID1
Address
0x08h
0x20h
Read
—
Reset Value
Type
Special Features
DEFAULT
VALUE
BIT
NAME
DESCRIPTION
B7 (MSB)
B6
DIE_TYPE[7:4]
BCD character (2)
BCD character (0)
0010
0000
B5
B4
B3
/MX8649A
B2
DIE_TYPE[3:0]
B1
B0 (LSB)
2
Table 11. I C Register: CHIP_ID2
This register contains the die type dash number and mask revision level.
REGISTER NAME
CHIP_ID2
0x09h
0x0Eh
Read
Address
Reset Value
Type
Special Features
—
DEFAULT
VALUE
BIT
NAME
DESCRIPTION
B7 (MSB)
B6
DASH
BCD character 0
BCD character E
0000
1110
B5
B4
B3
B2
MASK_REV
B1
B0 (LSB)
28 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
Given L
0.25 x I
OUT(MAX)
, the peak-to-peak inductor ripple current is
OUT(MAX)
. Make sure that the saturation current of the
IDEAL
Applications Information
. The peak inductor current is 1.125 x
Inductor Selection
I
Calculate the inductor value (L
) using the follow-
inductor exceeds the peak inductor current, and the
rated maximum DC inductor current exceeds the maxi-
mum output current I
er than L
IDEAL
ing formula:
. Inductance values small-
OUT(MAX)
4 × V × D × 1-D
(
)
IN
OUT MAX
can be used to reduce inductor size;
IDEAL
L
=
IDEAL
I
× f
OSC
however, if much smaller values are used, peak inductor
current rises and a larger output capacitance may be
required to suppress output ripple. Larger inductance
(
)
This sets the peak-to-peak inductor current ripple to 1/4
the maximum output current. The oscillator frequency,
values than L
can be used to obtain higher output
IDEAL
f
, is 3.25MHz, and the duty cycle, D, is:
OSC
current, but typically require a physically larger inductor
size. See Table 12 for recommended inductors.
V
OUT
D =
V
IN
Table 12. Recommended Inductors
INDUCTANCE
(µH)
DC RESISTANCE CURRENT RATING
DIMENSIONS
L x W x H (mm)
MANUFACTURER
SERIES
(Ω typ)
(mA)
1.0
1.5
2.2
0.075
0.075
0.115
1800
1800
1400
KSLI-2520AG
Multilayer
2.5 x 2.0 x 1.0
2.0 x 1.6 x 1.0
Hitachi Metals
0.75
1.0
1.5
0.09
0.09
0.13
1500
1500
1100
KLSI-2016AG
0.5
1.3
1.6
2.0
0.11
0.10
0.09
0.06
2000
2000
2000
2000
MIPSA2520D
Multilayer
FDK
2.5 x 2.0 x 0.5
3.2 x 1.6 x 0.9
1.0
1.5
2.2
0.11
0.13
0.14
1100
1000
900
CKP3216
Multilayer
Taiyo Yuden
1.0
1.5
0.03
0.04
2100
1800
NR3015
3.0 x 3.0 x 1.5
3.0 x 3.0 x 1.5
1.0
2.2
0.048
0.070
2000
1400
TDK
VLS3015T
0.56
1.2
1.5
2.0
0.032
0.044
0.050
0.067
2300
1800
1500
1400
TOKO
DE2812C
LPS3008
3.2 x 3.0 x 1.2
3.0 x 3.0 x 0.8
0.56
0.80
1.0
1.5
2.2
0.072
0.092
0.125
0.134
1800
1600
1400
1150
Coilcraft
0.68
1.0
1.5
1.8
2.2
0.070
0.080
0.085
0.120
0.150
2300
1800
1600
1300
1200
LPS3010
3.0 x 3.0 x 1.0
______________________________________________________________________________________ 29
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
Input Capacitor Selection
Power Dissipation
The input capacitor in a step-down DC-DC regulator
reduces current peaks drawn from the battery or other
input power source and reduces switching noise in the
controller. A 10µF ceramic capacitor in parallel with a
0.1µF ceramic capacitor is recommended for most appli-
cations. The impedance of the input capacitor at the
switching frequency should be less than that of the input
source so that high-frequency switching currents do not
pass through the input source. The input capacitor must
meet the input ripple-current requirement imposed by
the step-down regulator. Ceramic capacitors are pre-
ferred due to their resilience to power-up surge currents.
Choose the input capacitor so that the temperature rises
due to input ripple current do not exceed approximately
+10°C. For a step-down DC-DC regulator, the maximum
input ripple current is 1/2 of the output. This maximum
input ripple current occurs when the step-down regulator
The ICs have a thermal-shutdown feature that protects
the IC from damage when the die temperature exceeds
+160°C. See the Thermal-Overload Protection section
for more information. To prevent thermal overload and
allow the maximum load current on each regulator, it is
important to ensure that the heat generated by the ICs
can be dissipated into the PCB.
When properly mounted on a multilayer PCB, the junc-
tion-to-ambient thermal resistance (θ ) is typically
JA
76°C/W.
PCB Layout
Due to fast switching waveforms and high current paths,
careful PCB layout is required to achieve optimal perfor-
mance. Due to fast switching waveforms and high cur-
rent paths, careful PCB layout is required to achieve
optimal performance. Minimize trace lengths between
the ICs and the inductor, the input capacitor, and the
output capacitor; keep these traces short, direct, and
operates at 50% duty factor (V = 2 x V
). Refer to
OUT
IN
the MAX8649 Evaluation Kit data sheet for specific input
capacitor recommendations.
/MX8649A
wide. The ground connections of C and C
should
IN
OUT
be as close together as possible and connected to
PGND. Connect AGND and PGND directly to the ground
plane. The MAX8649 Evaluation Kit illustrates an exam-
ple PCB layout and routing scheme. Special care should
be taken when routing the remote sense signals. Use a
wide SNS+ trace to minimize parasitic inductance in the
SNS+ feedback trace. Do not use vias on the SNS+
trace because they introduce additional inductance.
Connect SNS- to the local AGND plane for the ICs.
Output Capacitor Selection
The step-down DC-DC regulator output capacitor
keeps output ripple small and ensures control-loop
stability. A 10µF ceramic capacitor in parallel with a
0.1µF ceramic capacitor is recommended for most
applications. The output capacitor must also have low
impedance at the switching frequency. Ceramic, poly-
mer, and tantalum capacitors are suitable, with ceramic
exhibiting the lowest ESR and lowest high-frequency
impedance.
Chip Information
Output ripple due to capacitance (neglecting ESR) is
approximately:
PROCESS: BiCMOS
I
L PEAK
(
)
Package Information
V
=
RIPPLE
2π × f
× C
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
OSC
OUT
Additional ripple due to capacitor ESR is:
ESR = I ×ESR
V
(
)
RIPPLE
L PEAK
(
)
PACKAGE PACKAGE OUTLINE
LAND
TYPE
CODE
NO.
PATTERN NO.
Refer to the MAX8649 Evaluation Kit data sheet for spe-
cific output capacitor recommendations.
16 WLP
0.5mm Pitch
Refer to Application
W162B2+1 21-0200
Note 1891
30 ______________________________________________________________________________________
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
/MX8649A
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
2
3
9/09
2/10
9/10
2/11
Initial release
—
11, 12
1–31
30
Corrected errors in Table 1 and Figure 2
Added MAX8649A to data sheet
Updated the PCB Layout section
Updated remote sense, Typical Operating Circuit, SNS+ and SNS- input impedance
entry, C1 bump description, Figure 1, and PCB Layout section
1, 5, 10,
11, 30
4
6/11
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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