MAX8707ETL-T [MAXIM]
Switching Controller, Current-mode, 660kHz Switching Freq-Max, BICMOS, 6 X 6 MM, 0.8 MM HEIGHT, MO-220WJJD, TQFN-40;
| 型号： | MAX8707ETL-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switching Controller, Current-mode, 660kHz Switching Freq-Max, BICMOS, 6 X 6 MM, 0.8 MM HEIGHT, MO-220WJJD, TQFN-40 信息通信管理 开关 |
| 文件： | 总37页 (文件大小：766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3360; Rev 0; 8/04
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
General Description
Features
The MAX8707 is a multiphase (3-/4-phase), interleaved,
fixed-frequency, step-down controller for AMD Hammer
CPU core supplies. Interleaved multiphase operation
reduces the input ripple current and output voltage ripple
while easing component selection and layout placement.
The MAX8707 includes active voltage positioning with
adjustable gain and offset, reducing power dissipation
and bulk output-capacitance requirements.
ꢀ 3-/4-Phase Interleaved Fixed-Frequency
Controller
ꢀ ±±0.75 ꢀ
Accuracy Over Line, Load, and
OUT
Temperature
ꢀ 7-Bit On-Board Digital-to-Analog Converter
(DAC)—±08±ꢀ to 1077ꢀ
ꢀ Adjustable Suspend ꢀoltage Input
The MAX8707 is intended for two different notebook
CPU core applications: stepping down the battery
directly or stepping down the +5V system supply to
create the core voltage. The single-stage conversion
method allows these devices to directly step down
high-voltage batteries for the highest possible efficien-
cy. Alternatively, 2-stage conversion (stepping down
the +5V system supply instead of the battery) at higher
switching frequency provides the minimum possible
physical size.
ꢀ Active ꢀoltage Positioning with Adjustable Gain
and Offset
ꢀ Accurate Lossless Current Balance
ꢀ Accurate Droop and Current Limit
ꢀ Remote Output and Ground Sense
ꢀ Output Slew-Rate Control
ꢀ Power-Good Window Comparator
The MAX8707 features dedicated differential current-
sense inputs for each phase and includes a fifth pair of
current-sense inputs to provide an accurate voltage-
positioning slope and average current-limit protection
using a single current-sense resistor. The MAX8707 also
has two dedicated inputs that provide differential remote
voltage sensing.
ꢀ Selectable 2±±kHz/3±±kHz/6±±kHz Switching
Frequency
ꢀ Output Overvoltage and Undervoltage Protection
ꢀ Thermal Fault Protection
ꢀ 2ꢀ ±±0.5 Reference Output
The MAX8707 provides an analog input for setting the
suspend voltage and a slew-rate controller for transi-
tions between VID codes or the suspend voltage. The
controllers reduce the transition slew rate during startup
and shutdown, providing soft-start with minimal input
surge current and damped soft-shutdown without nega-
tive output undershoot. The MAX8707 includes output
fault protection—undervoltage, nonlatched overvoltage,
and thermal overload—and an independent voltage-
regulator power-OK (VROK) output.
ꢀ Soft-Startup and Shutdown
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX8707ETL
-40°C to +85°C 40 Thin QFN 6mm x 6mm
Applications
The MAX8707 has a selectable switching frequency,
allowing 200kHz, 300kHz, or 600kHz per-phase opera-
tion. The MAX8707 is available in the low-profile, 40-pin,
6mm x 6mm thin QFN package. Refer to the MAX8702/
MAX8703 for compatible drivers.
AMD Hammer Desknote Computers
Multiphase CPU Core Supplies
Voltage-Positioned Step-Down Converters
Notebook/Desktop Computers
Servers
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
ABSOLUTE MAXIMUM RATINGS
CC
V
to GND..............................................................-0.3V to +6V
SHDN to GND (Note 1)...........................................-0.3V to +14V
D0–D4 to GND..........................................................-0.3V to +6V
SKIP, SUS, VROK, ILIM(AVE) to GND......................-0.3V to +6V
SUSV, OFS, OSC to GND.........................................-0.3V to +6V
CSP_, CSN_, CRSP, CRSN to GND .........................-0.3V to +6V
REF Short-Circuit Duration .........................................Continuous
Continuous Power Dissipation (T = +70°C)
A
40-Pin 6mm x 6mm Thin QFN
(derate 26.3mW/°C above +70°C)................................2.105W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
VPS, FBS, CCV, REF to GND .....................-0.3V to (V
ILIM(PK), TRC, TIME to GND .....................-0.3V to (V
PWM_, DRSKP to PGND ............................-0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
CC
CC
CC
PGND, GNDS to GND ...........................................-0.3V to +0.3V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: SHDN can be forced to 12V for debugging prototype boards using the no-fault test mode, which disables fault protection.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1. V
= V
= 5V, OSC = REF, V
= V
= V
= V
= V
= 1.20V, V
= 0.8V, OFS = SUS =
CC
SHDN
VPS
FBS
CRSN
CRSP
CSP_
SUSV
GNDS = PGND = SKIP = GND, D0–D4 set for 1.20V (D0–D4 = 01110). T = 0°C to +85°C, unless otherwise specified. Typical values
A
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Input Voltage Range
V
4.5
5.5
V
CC
DAC codes from
1.10V to 1.55V
-0.75
+0.75
Includes load-
regulation error
(VPS = FBS)
%
DC Output Voltage Accuracy
V
OUT
DAC codes from
0.80V to 1.075V
-2.0
+2.0
SUS = V
-20
0.4
-0.1
0
+20
2.0
mV
V
CC
SUSV Input Range
V
SUSV
SUSV Input-Bias Current
I
V
= 0.4V to 2V
+0.1
0.8
µA
SUSV
SUSV
Negative offsets
Positive offsets
OFS Input Range
OFS GAIN
V
V
OFS
1.2
2.0
∆V
/ ∆V
, ∆V
= V
= V
,
OFS
OUT
OFS
OFS
OFS
-0.131 -0.125 -0.118
-0.131 -0.125 -0.118
V
= 0 to 0.8V
OFS
A
V/V
OFS
∆V
/ ∆V
, ∆V
-V
,
OUT
OFS
OFS REF
V
= 1.2V to 2V
OFS
OFS Input-Bias Current
GNDS Input Range
I
V
= 0 to 2V
-0.1
+0.1
µA
OFS
OFS
V
-200
+200
mV
GNDS
GNDS
GNDS
∆V
/ ∆V
,
GNDS
OUT
GNDS Gain
A
0.95
1.00
1.05
V/V
-200mV ≤ V
≤ +200mV
GNDS
GNDS Input-Bias Current
FBS Input-Bias Current
I
-2
+2
µA
µA
I
CRSP = CRSN, CSP_ = CSN_
OSC = GND
-10
180
270
540
+10
220
330
660
FBS
200
300
600
Switching Frequency Accuracy
(Per Phase)
f
OSC = REF
kHz
SW
OSC = V
CC
2
_______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V
= V
= 5V, OSC = REF, V
= V
= V
= V
= V
= 1.20V, V
= 0.8V, OFS = SUS =
CC
SHDN
VPS
FBS
CRSN
CRSP
CSP_
SUSV
GNDS = PGND = SKIP = GND, D0–D4 set for 1.20V (D0–D4 = 01110). T = 0°C to +85°C, unless otherwise specified. Typical values
A
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
R
R
= 143kΩ (6.25mV/µs)
-10
+10
TIME
= 47kΩ (19mV/µs) to 392kΩ
TIME
-15
-20
+15
+20
(2.28mV/µs)
TIME Slew-Rate Accuracy
%
Startup and shutdown, R
(4.75mV/µs) to 392kΩ (0.57mV/µs)
= 47kΩ
TIME
BIAS AND REFERENCE
Measured at V , VPS and FBS forced
CC
above the regulation points
Quiescent Supply Current (V
)
CC
I
7
12
mA
CC
Shutdown Supply Current (V
Reference Voltage
)
CC
I
Measured at V , SHDN = GND
0.05
2.000
-0.2
10
µA
V
CC(SHDN)
CC
V
V
= 4.5V to 5.5V, I
= 0 to 500µA
= -100µA to 0
= 0
1.986
-2
2.014
REF
CC
REF
REF
REF
I
I
Reference Load Regulation
∆V
mV
REF
0.21
6.2
FAULT PROTECTION
PWM (SKIP = GND)
or SKIP mode when
Measured at VPS
with respect to
unloaded output
voltage, rising edge,
8mV hysteresis
150
200
250
mV
V
V
≤ V
TRIP
OUT
Output Overvoltage-Protection
Threshold
V
OVP
SKIP = V
and
CC
1.70
1.75
1.1
10
1.80
V
> V
TRIP
OUT
Minimum OVP level
Output Overvoltage Propagation
Delay
t
VPS forced 25mV above trip threshold
µs
mV
µs
OVP
Output Undervoltage-Protection
Threshold
Measured at VPS with respect to 70% of the
unloaded nominal output voltage
V
-30
+30
UVP
Output Undervoltage
Propagation Delay
t
VPS forced 25mV below trip threshold
10
20
UVP
Measured from the time when VPS reaches
VROK Transition Blanking Time
t
the target voltage, slew rate set by R
(Note 2)
µs
BLANK
TIME
Undervoltage measured at VPS with
respect to 87.5% unloaded output voltage,
falling edge, 15mV hysteresis
-30
-30
+30
+30
VROK Threshold
VROK Delay
mV
µs
Overvoltage measured at VPS with respect
to 112.5% of the unloaded output voltage,
rising edge, 15mV hysteresis
VPS forced 25mV outside the VROK trip
thresholds
t
10
VROK
VROK Output Low Voltage
VROK Leakage Current
I
= 3mA
0.4
1
V
SINK
High state, VROK forced to 5.5V
µA
_______________________________________________________________________________________
3
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V
= V
= 5V, OSC = REF, V
= V
= V
= V
= V
= 1.20V, V
= 0.8V, OFS = SUS =
CC
SHDN
VPS
FBS
CRSN
CRSP
CSP_
SUSV
GNDS = PGND = SKIP = GND, D0–D4 set for 1.20V (D0–D4 = 01110). T = 0°C to +85°C, unless otherwise specified. Typical values
A
are at T = +25°C.)
A
PARAMETER
Undervoltage-Lockout
SYMBOL
CONDITIONS
MIN
TYP
4.25
MAX
UNITS
V
V
Rising edge, hysteresis = 20mV, PWM_
disabled below this level
CC
V
4.10
4.45
UVLO(VCC)
Threshold
Thermal-Shutdown Threshold
T
Rising edge hysteresis = 15°C
+160
°C
SHDN
DROOP AND TRANSIENT RESPONSE
DC Droop Amplifier Offset
-1.5
194
+1.5
206
mV
µS
DC Droop Amplifier
Transconductance
(CRS Sense Enabled)
∆I
/ (N x ∆V
), V
= V
= 1.2V,
CRSN
VPS
CRS
VPS
V
- V
= -60mV to +60mV,
G
m(VPS)
G
m(VPS)
R
TRANS
200
200
5.0
CRSP
CRSN
N = number of phases enabled
DC Droop Amplifier
Transconductance
(CRS Sense Disabled)
∆I
VPS
/ (Σ∆V ), V
= V
,
CC
CS
CRSP
V
= V
_ = 1.2V,
CSN
194
4.75
-30
206
5.25
-20
µS
kΩ
mV
VPS
V
_ – V
_ = -60mV to +60mV
CSN
CSP
Current-sense gain (A = 10 typ) divided
CS
by the voltage preamplifier
transconductance (G
Transient-Droop Transresistance
= 2ms typ)
m(TRC)
Measured at VPS with respect to steady-
state VPS regulation voltage; falling edge,
5.5mV hysteresis (typ)
Transient Detection Threshold
-25
CURRENT LIMIT AND BALANCE
Current-Sense Input Preamplifier
Offsets
CSP_ - CSN_
-2.0
+2.0
mV
V
ILIM(AVE) Input Range
(Adjustable Mode)
V
V
REF
- 0.2
REF
V
ILIM(AVE)
AVELIMIT
- 1.0
ILIM(AVE) Average Current-Limit
Threshold Voltage
(Positive, Default)
V
CRSP - CRSN; ILIM(AVE) = V
22
25
28
mV
mV
CC
ILIM(AVE) Average Current-Limit
Threshold Voltage
(Positive, Adjustable)
V
V
= V
- 0.2V
- 1.0V
7
10
50
13
54
ILIM(AVE)
ILIM(AVE)
REF
REF
V
CRSP - CRSN
AVELIMIT
ILIM(AVE)
= V
46
ILIM(AVE) Average Current-Limit
Threshold Voltage (Negative)
CRSP - CRSN; ILIM(AVE) = V
-30
-0.1
3
-25
-20
mV
µA
V
CC
ILIM(AVE) Input Current
I
+0.1
ILIM(AVE) Current-Limit Default
Switchover Threshold
V
V
CC
- 0.4
CC
- 1.0
CSP_ - CSN_,
V
V
= 30mV
= 50mV
24
40
30
36
PKLIMIT
PKLIMIT
ILIM(PK) Peak Current-Limit
Threshold Voltage (Positive)
R
= R
x
TRC
V
mV
mV
ILIM(PK)
PKLIMIT
50
60
8V / V
LIM(PK)
ILIM(PK) Peak Current-Limit
Threshold Voltage (Negative)
CSP_ - CSN_, R
= R
= 50mV
x 8V /
TRC
ILIM(PK)
-60
-50
-40
V
, V
PKLIMIT PKLIMIT
4
_______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V
= V
= 5V, OSC = REF, V
= V
= V
= V
= V
= 1.20V, V
= 0.8V, OFS = SUS =
CC
SHDN
VPS
FBS
CRSN
CRSP
CSP_
SUSV
GNDS = PGND = SKIP = GND, D0–D4 set for 1.20V (D0–D4 = 01110). T = 0°C to +85°C, unless otherwise specified. Typical values
A
are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
CSP_ - CSN_, V ≥ 1.2V,
MIN
TYP
MAX
UNITS
SKIP
ILIM(PK) Idle Current-Limit
Threshold Voltage (Skip Mode)
R
= R
x 8V / V
,
V
2
5
8
mV
ILIM(PK)
TRC
PKLIMIT
IDLE
V
= 50mV
PKLIMIT
CSP_, CRSP
CSN_, CRSN
-0.2
-1.0
+0.2
+1.0
Current-Sense Input Current
µA
V
Current-Sense Common-Mode
Input Range
CRSP, CRSN, CSP_, CSN_
0
3
3
2
V
0.4
-
-
CC
Phase Disable Threshold
CSP4
CRSP
V
V
- 1
V
CC
CC
CRS Sense Input Disable
Threshold
V
CC
- 1
V
0.4
LOGIC AND I/O
Logic Input High Voltage
Logic Input Low Voltage
SHDN No-Fault Threshold
D0–D4 Logic Input High Voltage
D0–D4 Logic Input Low Voltage
V
SHDN, SUS
2.4
V
V
V
V
V
IH
V
SHDN, SUS
0.8
13
IL
To enable no-fault mode
11
0.8
0.4
V
0.4
-
CC
High (V
)
CC
OSC 3-Level Input Logic Levels
V
V
OSC
Medium (REF)
1.8
1.2
-1
2.2
0.4
Low (GND)
High
Low (GND)
SKIP Input Logic Levels
Logic Input Current
V
V
µA
V
SKIP
0.8
+1
SHDN, SKIP, SUS, OSC, D0–D4 = 0 to 5V
V
-
CC
Logic Output High Voltage
Logic Output Low Voltage
V
PWM_, DRSKP; I
= 3mA
SOURCE
OH
0.4
V
PWM_, DRSKP; I
= 3mA
SINK
0.4
V
OL
_______________________________________________________________________________________
5
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1. V
= V
= 5V, OSC = REF, V
= V
= V
= V
= V
= 1.20V, V
= 0.8V, OFS = SUS =
CC
SHDN
VPS
FBS
CRSN
CRSP
CSP_
SUSV
GNDS = PGND = SKIP = GND, D0–D4 set for 1.20V (D0–D4 = 01110). T = -40°C to +85°C, unless otherwise specified.) (Note 3)
A
PARAMETER
PWM CONTROLLER
Input Voltage Range
SYMBOL
CONDITIONS
MIN
MAX
UNITS
V
4.5
5.5
V
CC
DAC codes from
1.10V to 1.55V
-1.0
+1.0
Includes load-
regulation error
(VPS = FBS)
%
DC Output Voltage Accuracy
V
OUT
DAC codes from
0.80V to 1.075V
-3.0
+3.0
SUS = V
-25
0.4
0
+25
2.0
0.8
2.0
mV
V
CC
SUSV Input Range
OFS Input Range
V
SUSV
Negative offsets
Positive offsets
V
V
OFS
1.2
∆V
/ ∆V
= 0 to 0.8V
; ∆V
= V
= V
OUT
OFS
OFS
OFS
OFS,
OFS
-0.131
-0.118
V
OFS
OFS GAIN
A
V/V
OFS
∆V
/ ∆V
= 1.2V to 2V
; ∆V
- V
REF,
OUT
OFS
-0.131
-200
-0.118
+200
1.05
V
OFS
GNDS Input Range
GNDS Gain
V
A
mV
V/V
GNDS
∆V
/ ∆V
,
GNDS
OUT
0.95
GNDS
-200mV ≤ V
≤ +200mV
GNDS
OSC = GND
OSC = REF
180
270
540
-10
220
330
660
+10
Switching Frequency Accuracy
(Per Phase)
f
kHz
%
SW
OSC = V
CC
R
TIME
= 143kΩ (6.25mV/µs)
R
TIME
= 47kΩ (19mV/µs) to 392kΩ
-15
-20
+15
+20
(2.28mV/µs)
TIME Slew-Rate Accuracy
Startup and shutdown, R
(4.75mV/µs) to 392kΩ (0.57mV/µs)
= 47kΩ
TIME
BIAS AND REFERENCE
Measured at V , VPS and FBS forced
CC
above the regulation points
Quiescent Supply Current (V
)
CC
I
12
mA
CC
Shutdown Supply Current (V
Reference Voltage
)
CC
I
Measured at V , SHDN = GND
10
µA
V
CC(SHDN)
CC
V
V
= 4.5V to 5.5V, I
= 0 to 500µA
= -100µA to 0
= 0
1.98
-2
2.02
REF
CC
REF
REF
REF
I
I
mV
mV
Reference Load Regulation
∆V
REF
6.2
FAULT PROTECTION
PWM (SKIP = GND)
or SKIP mode when
Measured at VPS
with respect to
unloaded output
voltage, rising edge,
8mV hysteresis
150
250
mV
V
Output Overvoltage-Protection
Threshold
V
≤ V
TRIP
OUT
V
OVP
SKIP = V
and
CC
1.70
1.80
V
> V
TRIP
OUT
6
_______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V
= V
= 5V, OSC = REF, V
= V
= V
= V
= V
= 1.20V, V
= 0.8V, OFS = SUS =
CC
SHDN
VPS
FBS
CRSN
CRSP
CSP_
SUSV
GNDS = PGND = SKIP = GND, D0–D4 set for 1.20V (D0–D4 = 01110). T = -40°C to +85°C, unless otherwise specified.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Output Undervoltage-Protection
Threshold
Measured at VPS with respect to 70% of the
unloaded nominal output voltage
V
-40
+40
mV
UVP
Undervoltage, measured at VPS with
respect to 87.5% of the unloaded output
voltage, falling edge, 15mV hysteresis
-40
-40
+40
+40
VROK Threshold
mV
Overvoltage, measured at VPS with respect
to 112.5% of the unloaded output voltage,
rising edge, 15mV hysteresis
VROK Output Low Voltage
I
= 3mA
0.4
V
V
SINK
V
Undervoltage-Lockout
Rising edge, hysteresis = 20mV, PWM_
disabled below this level
CC
V
4.10
4.45
UVLO(VCC)
Threshold
DROOP AND TRANSIENT RESPONSE
DC Droop Amplifier Offset
-2
+2
mV
µS
DC Droop Amplifier
Transconductance
(CRS Sense Enabled)
∆I
/ (N x ∆V
); V
= V
= 1.2V,
CRSN
VPS
CRS
VPS
V
- V
= -60mV to +60mV,
G
m(VPS)
G
m(VPS)
R
TRANS
190
210
CRSP
CRSN
N = number of phases enabled
DC Droop Amplifier
Transconductance
(CRS Sense Disabled)
∆I
VPS
/ (Σ∆V ), V
= V
,
CC
CS
CRSP
V
V
= V
_ = 1.2V,
CSN
190
210
µS
VPS
CSP
_ - V
_ = -60mV to +60mV
CSN
Current-sense gain (A = 10 typ) divided
CS
by the voltage preamplifier
Transient-Droop Transresistance
4.50
5.25
kΩ
transconductance (G
= 2mS typ)
m(TRC)
CURRENT LIMIT AND BALANCE
Current-Sense Input Preamplifier
Offsets
CSP_ - CSN_
-2.5
+2.5
mV
V
ILIM(AVE) Input Range
(Adjustable Mode)
V
V
REF
- 0.2
REF
V
V
ILIM(AVE)
- 1.0
ILIM(AVE) Average Current-Limit
Threshold Voltage
(Positive, Default)
CRSP - CRSN; ILIM(AVE) = V
20
30
mV
mV
AVELIMIT
CC
ILIM(AVE) Average Current-Limit
Threshold Voltage
(Positive, Adjustable)
V
V
= V
- 0.2V
- 1.0V
5
15
56
ILIM(AVE)
ILIM(AVE)
REF
REF
V
CRSP - CRSN
AVELIMIT
= V
44
ILIM(AVE) Average Current-Limit
Threshold Voltage (Negative)
CRSP - CRSN; ILIM(AVE) = V
-31
3
-19
mV
V
CC
ILIM(AVE) Current-Limit Default
Switchover Threshold
V
CC
- 0.4
_______________________________________________________________________________________
7
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V
= V
= 5V, OSC = REF, V
= V
= V
= V
= V
= 1.20V, V
= 0.8V, OFS = SUS =
CC
SHDN
VPS
FBS
CRSN
CRSP
CSP_
SUSV
GNDS = PGND = SKIP = GND, D0–D4 set for 1.20V (D0–D4 = 01110). T = -40°C to +85°C, unless otherwise specified.) (Note 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
CSP_ - CSN_,
V
V
= 30mV
= 50mV
24
36
PKLIMIT
PKLIMT
ILIM(PK) Peak Current-Limit
Threshold Voltage (Positive)
V
R
= R x
TRC
mV
PKLIMIT
ILIM(PK)
40
60
8V / V
LIM(PK)
CSP_ - CSN_,
ILIM(PK) Peak Current-Limit
Threshold Voltage (Negative)
R
= R
x 8V / V
PKLIMIT
,
-60
-40
mV
mV
ILIM(PK)
PKLIMIT
TRC
V
= 50mV
CSP_ - CSN_, V
≥ 1.2V,
SKIP
ILIM(PK) Idle Current-Limit
Threshold Voltage (Skip Mode)
V
R
= R
x 8V / V
,
2
8
IDLE
ILIM(PK)
PKLIMIT
TRC
PKLIMIT
V
= 50mV
CSP_, CRSP
CSN_, CRSN
-0.2
-1.0
+0.2
+1.0
Current-Sense Input Current
µA
V
Current-Sense Common-Mode
Input Range
CRSP, CRSN, CSP_, CSN_
0
3
3
2
V
CC
Phase Disable Threshold
CSP4
CRSP
V
- 0.4
CRS Sense Input Disable
Threshold
V
CC
- 0.4
V
LOGIC AND I/O
Logic Input High Voltage
Logic Input Low Voltage
D0–D4 Logic Input High Voltage
D0–D4 Logic Input Low Voltage
V
SHDN, SUS
SHDN, SUS
2.4
0.8
V
V
V
V
IH
V
0.8
0.4
IL
V
- 0.4
CC
High (V
)
CC
OSC 3-Level Input Logic Levels
V
V
OSC
Medium (REF)
Low (GND)
High
1.8
2.2
0.4
1.2
SKIP Input Logic Levels
V
V
V
SKIP
Low (GND)
0.8
V
CC
Logic Output High Voltage
V
PWM_, DRSKP; I
= 3mA
OH
SOURCE
- 0.4
Note 2: VROK is blanked during the transitions, when the internal target is being slewed. See the Output-Voltage Transition Timing
section. VROK is reenabled in t (20µs) after the transition is completed.
BLANK
Note 3: Specifications to T = -40°C are guaranteed by design and are not production tested.
A
8
_______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Typical Operating Characteristics
(Circuit of Figure 1. V = 12V, V = 5V, SUS = SKIP = GND, SHDN = V , V
= 0.80V, T = +25°C, unless otherwise specified.)
IN
CC
CC SUSV
A
EFFICIENCY vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
(V
OUT
= 1.525V)
(V
OUT
= 1.300V)
(V
OUT
= 1.000V)
100
90
80
70
60
50
100
90
80
70
60
50
100
90
80
70
60
50
V
= 8V
V
= 8V
IN
IN
V
= 8V
IN
V
= 12V
V
= 12V
IN
IN
V
= 12V
IN
V
= 20V
V
= 20V
IN
IN
V
= 20V
IN
1
0
0
10
100
1
10
100
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
SINGLE-PHASE
EFFICIENCY vs. LOAD CURRENT
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
(4-PHASE FORCED-PWM MODE)
OUTPUT VOLTAGE DEVIATION
vs. LOAD CURRENT
(V
= 0.800V)
OUT
20
0
100
90
80
70
60
50
200
150
100
50
V
= 12V
IN
V
= 8V
I
IN
V = 12V
IN
BIAS
-20
-40
-60
-80
-100
-120
V
= 1.00V
OUT
I
IN
V
= 20V
IN
V
= 1.30V
OUT
20
SKIP = V
5
SKIP = SUS = V
10 100
CC
CC
0
40
LOAD CURRENT (A)
60
80
0.1
1
0
10
15
20
25
LOAD CURRENT (A)
INPUT VOLTAGE (V)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
(1-PHASE PULSE SKIPPING)
REFERENCE VOLTAGE
DISTRIBUTION
OUTPUT OFFSET VOLTAGE
vs. OFS VOLTAGE
50
40
30
20
10
0
150
100
50
10
8
SAMPLE SIZE = 100
SKIP = GND
I
BIAS
6
0
4
-50
-100
-150
2
I
= 15µA
IN
UNDEFINED
REGION
0
1.990
1.995
2.000
2.005
2.010
0
0.5
1.0
1.5
2.0
5
10
15
20
25
REFERENCE VOLTAGE (V)
OFS VOLTAGE (V)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Typical Operating Characteristics
(Circuit of Figure 1. V = 12V, V = 5V, SUS = SKIP = GND, SHDN = V , V
= 0.80V, T = +25°C, unless otherwise specified.)
IN
CC
CC SUSV
A
VPS TRANSCONDUCTANCE
DISTRIBUTION
OUTPUT OFFSET VOLTAGE
DISTRIBUTION
CURRENT-SENSE VOLTAGE DIFFERENCE
vs. LOAD CURRENT
70
60
50
40
30
20
10
0
50
40
30
20
10
0
0.6
SAMPLE SIZE = 100
SAMPLE SIZE = 100
0.800V
1.550V
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
205
195
197
199
201
203
-5
-3
-1
1
3
5
0
5
10
15
20
25
TRANSCONDUCTANCE (µS)
OUTPUT OFFSET VOLTAGE (mV)
LOAD CURRENT (A)
SHUTDOWN WAVEFORM
(NO LOAD)
STARTUP WAVEFORM
(NO LOAD)
STARTUP WAVEFORM
(20A LOAD)
MAX8707 toc15
MAX8707 toc14
MAX8707 toc13
3.3V
0
A
3.3V
3.3V
A
A
B
0
5V
0
0
5V
0
B
5V
0
1.3V
B
2V
2V
C
C
0
1V
0
1V
D
0
C
D
D
0
0
E
F
G
E
F
G
0
E
200µs/div
200µs/div
200µs/div
A. SHDN, 5V/div
B VROK, 10V/div
C. OUT, 1V/div
D. DL1, 10V/div
A. SHDN, 5V/div
B. DRSKP, 10V/div
C. REF, 2V/div
E. VROK, 10V/div
F. DL1, 10V/div
A. SHDN, 5V/div
E. VROK, 10V/div
F. DL1, 10V/div
E. INDUCTOR CURRENT
B. DRSKP, 10V/div
C. REF, 2V/div
(I ), 10A/div
L1
G. INDUCTOR CURRENT
G. INDUCTOR CURRENT
D. OUT, 1V/div
(I ), 10A/div
L1
D. OUT, 1V/div
(I ), 10A/div
L1
10 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V = 12V, V = 5V, SUS = SKIP = GND, SHDN = V , V
= 0.80V, T = +25°C, unless otherwise specified.)
IN
CC
CC SUSV
A
LOAD TRANSIENT
LOAD TRANSIENT
(V = 1.00V)
TRANSIENT PHASE REPEAT
(V
= 1.30V)
OUT
OUT
MAX8707 toc18
MAX8707 toc16
MAX8707 toc17
70A
65A
30A
0
A
A
A
0A
1.30V
10A
1.00V
1.30V
B
B
B
12V
12V
20V
C
C
C
0
0
0
10A
0
20A
10A
20A
D
D
D
10A
0
0
V
= 20V
IN
2µs/div
20µs/div
= 10A TO 65A,
20µs/div
A. I
= 0 TO 70A,
C. LX1, 10V/div
A. I
C. LX1, 10V/div
A. I
= 0 TO 30A,
C. LX1, 10V/div
OUT
100A/div
OUT
50A/div
OUT
50A/div
D. INDUCTOR CURRENT
D. INDUCTOR CURRENT
D. INDUCTOR CURRENT
B. V , 100mV/div
(I ), 10A/div
L1
B. V , 100mV/div
OUT
(I ), 10A/div
L1
B. V , 50mV/div
(I ), 10A/div
L1
OUT
OUT
SUSPEND TRANSITION
(SKIP = SUS)
DEEP-SLEEP TRANSITION
SUSPEND EXIT TRANSITION
MAX8707 toc19
MAX8707 toc20
MAX8707 toc21
3.3V
0
3.3V
0
A
3.3V
0
A
A
1.30V
1.30V
0.2V
B
B
B
0
0.80V
5V
0.80V
5V
C
1.300V
C
C
0
0
1.275V
5A
D
E
D
E
D
E
5A
I
= 20A
OUT
20µs/div
20µs/div
200µs/div
A. DPSLP, 5V/div
B. OFS, 200mV/div
D. INDUCTOR CURRENT
A. SUS, 5V/div
OUT
D. INDUCTOR CURRENT
A. SUS, 5V/div
OUT
D. INDUCTOR CURRENT
(I ), 10A/div
B. V , 500mV/div
(I ), 10A/div
B. V , 500mV/div
(I ), 10A/div
L1
L1
L1
C. V , 25mV/div
E. INDUCTOR CURRENT
(I ), 10A/div
L3
E. INDUCTOR CURRENT
(I ), 10A/div
L3
E. INDUCTOR CURRENT
(I ), 10A/div
L3
OUT
C. DRSKP, 5V/div
C. DRSKP, 5V/div
______________________________________________________________________________________ 11
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V = 12V, V = 5V, SUS = SKIP = GND, SHDN = V , V
= 0.80V, T = +25°C, unless otherwise specified.)
IN
CC
CC SUSV
A
SUSPEND TRANSITION
(SKIP = SUS)
SUSPEND TRANSITION
D1 (25mV) VID TRANSITION
MAX8707 toc24
(SKIP = GND)
MAX8707 toc22
MAX8707 toc23
3.3V
0
3.3V
0
A
A
3.3V
0
A
B
1.30V
1.30V
B
B
1.30V
0.80V
5V
0.80V
5V
1.275V
C
0
C
0
0
C
D
D
E
D
E
0
100µs/div
40µs/div
20µs/div
A. SUS, 5V/div
OUT
D. INDUCTOR CURRENT
A. SUS, 5V/div
OUT
D. INDUCTOR CURRENT
A. D1, 5V/div
B. V , 25mV/div
C. INDUCTOR CURRENT
B. V , 500mV/div
(I ), 10A/div
B. V , 500mV/div
(I ), 10A/div
(I ), 10A/div
L1
L1
OUT
L1
E. INDUCTOR CURRENT
(I ), 10A/div
L3
E. INDUCTOR CURRENT
(I ), 10A/div
L3
D. INDUCTOR CURRENT
(I ), 10A/div
L3
C. DRSKP, 5V/div
C. DRSKP, 5V/div
D3 (200mV) VID TRANSITION
MAX8707 toc25
3.3V
0
A
B
1.30V
1.10V
0
C
D
0
20µs/div
A. D3, 5V/div
B. V , 200mV/div
C. INDUCTOR CURRENT
(I ), 10A/div
OUT
L1
D. INDUCTOR CURRENT
(I ), 10A/div
L3
12 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Pin Description
PIN
NAME
FUNCTION
Low-Voltage VID DAC Code Input. The D0–D4 inputs do not have internal pullups. These 1.0V logic inputs
are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the output voltage
is set by the VID code indicated by the logic-level voltages on D0–D4. In suspend mode (SUS = high), the
output voltage tracks the voltage at SUSV.
1
D2
2
3
4
D3
D4
Low-Voltage VID DAC Code Input
Low-Voltage VID DAC Code Input (MSB)
No Connect. Leave open. Pin internally connected.
N.C.
Pulse-Skipping Indicator Input. When pulse skipping, the controller blanks the VROK upper threshold.
3.3V or V
(high) = 1-phase pulse-skipping operation (phases 2, 3, and 4 disabled)
CC
5
SKIP
GND = multiphase forced-PWM operation
The controller automatically enters forced-PWM mode during startup, shutdown, and the no-CPU VID
mode.
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V for normal
CC
operation. Connect to ground to put the IC into its 50nA (typ) shutdown state. During the startup and
shutdown transitions, the output voltage is ramped at 1/4th the output-voltage slew rate programmed by
6
SHDN
R . After completing soft-shutdown, the drivers are disabled—DRSKP and PWM_ are pulled low.
TIME
Forcing SHDN to 11V~13V disables both overvoltage-protection and undervoltage-protection circuits, and
clears the fault latch. Do not connect SHDN to >13V.
Suspend Control Input. When the controller detects a transition on SUS, the controller slews the output
voltage to the new voltage level determined by SUSV (SUS = high) or D0–D4 (SUS = low). The controller
blanks VROK during the transition and another 20µs after the new target voltage is reached. When SUS is
high, the offset (OFS) is automatically disabled.
7
8
SUS
Suspend-Mode Voltage Input. Connect to the output of a resistive voltage-divider from REF to GND to
provide an analog voltage between 0.4V to 2V. The output voltage is set by the voltage at SUSV when SUS
is high.
SUSV
Average Current-Limit Threshold Adjustment. The controller uses the accurate CRSP-to-CRSN current-
sense voltage to limit the average current per phase. When the average current-limit threshold is
exceeded, the controller internally reduces the peak inductor current-limit threshold (ILIM(PK)) at 2% of
I
per µs until the average current remains within the programmed limits. When the accurate current
PKLIMIT
sensing is disabled (CRSP = V ), the average current-limit circuit is disabled and I
should be
LIM(AVE)
CC
9
ILIM(AVE)
connected to V
.
CC
The average current-limit threshold defaults to 25mV if ILIM(AVE) is connected to V . In adjustable mode,
CC
the average current-limit threshold voltage is precisely 1/20th the voltage difference between ILIM(AVE)
and the reference: (V
- V
) / 20 for a range of 1.0V (V
- 1V) to 1.8V (V
- 0.2V). The logic
REF
REF
ILIM(AVE)
REF
threshold for switchover to the 25mV default value is approximately V
- 1V.
CC
Adjustable Offset Voltage Input. For 0 < V
< 0.8V, 1/8th the voltage at OFS is subtracted from the
OFS
output. For 1.2V < V
Voltages in the range of 0.8V < V
< 2.0V, 1/8th the difference between REF and OFS is added to the output.
OFS
10
OFS
< 1.2V are undefined. The controller disables the offset amplifier
OFS
during suspend mode (SUS = high).
______________________________________________________________________________________ 13
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Pin Description (continued)
PIN
NAME
FUNCTION
Oscillator Select Input. OSC is a 3-level logic input for selecting the per-phase switching frequency.
Connect to GND for 200kHz, connect to REF for 300kHz, or connect to V for 600kHz per phase.
11
OSC
CC
Ground Remote-Sense Input. Connect GNDS directly to the CPU ground-sense pin. GNDS internally
connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the regulator
ground to the load ground.
12
13
GNDS
TIME
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew rate. A 47kΩ to
392kΩ corresponds to slew rates of 19mV/µs to 2.28mV/µs, respectively, for all suspend voltage
transitions.
|V
dV
− V
|
NEW
OLD
/dt
t
=
TRAN(SUS)
TARGET
where dV
/ dt = 6.25mV/µs × 143kΩ / R is the slew rate. For soft-start and shutdown, the
TIME
TARGET
controller automatically reduces the slew rate by 1/4th. For all dynamic VID transitions, the rate at which
the VID inputs (D0–D4) are clocked sets the slew rate, as long as it is less than the dv/dt set by R
.
TIME
Peak Inductor Current-Limit Threshold Adjustment (Cycle-by-Cycle Current Limit). If the voltage across the
current-sense inputs (CSP to CSN) exceeds the peak current-limit threshold, the controller immediately
terminates the respective phase’s on-time. Connect a resistor R
from ILIM(PK) to GND to set the
ILIM(PK)
cycle-by-cycle peak current-limit threshold:
14
ILIM(PK)
8V × R
TRC
R
R
=
ILIM(PK)
I
PKLIMIT CS
where R is the resistance value of the current-sense element (inductors’ DCR or current-sense resistor),
CS
R
TRC
is the resistance between TRC and REF, and I
is the desired peak current limit (per phase).
PKLIMIT
Voltage Integrator Capacitor Connection. Connect a 470pF x (4 / η ) or greater capacitor from CCV to
analog ground (GND) to set the integration time constant.
PH
15
16
CCV
TRC
Transient-Voltage Preamplifier Output. Connect a resistor (R
) between TRC and REF to set the
TRC
transient droop based on the voltage-positioning requirements. TRC does not affect the DC steady-state
droop. Choose R based on the equation:
TRC
R
R
TRANS CS
R
R
= A
CS
TRC
η
PH DROOP(AC)
as defined in the Design Procedure (page 33). If voltage positioning is not required, R
is determined
TRC
by the stability requirements. TRC is high impedance in shutdown.
14 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Pin Description (continued)
PIN
NAME
FUNCTION
2.0V Reference Output. Bypass to GND with a 0.22µF to 1µF (max) ceramic capacitor. The reference can
source 500µA for external loads. Loading REF degrades output-voltage accuracy according to the REF
load-regulation error.
17
REF
Open-Drain Power-Good Output. After power-up, VROK remains high impedance as long as the output
voltage remains in regulation. The controller blanks VROK (high impedance) whenever the slew-rate
control is active (output-voltage transitions). VROK is forced low during startup and shutdown. In pulse-
skipping mode (SKIP = high), the upper VROK threshold is disabled.
18
VROK
19
20
GND
Analog Ground. Connect the MAX8707’s exposed pad to analog ground.
PGND
Power Ground. Ground connection for the driver control outputs (PWM_) and driver skip output (DRSKP).
Analog Supply-Voltage Input. Connect V
resistor. Bypass to analog GND with a 1µF or greater ceramic capacitor, as close to the IC as possible.
to the system supply voltage (4.5V to 5.5V) with a series 10Ω
CC
21
V
CC
22
23
24
25
PWM1
PWM2
PWM3
PWM4
PWM Driver Control Output for Phase 1. Logic low in shutdown.
PWM Driver Control Output for Phase 2. Logic low in shutdown.
PWM Driver Control Output for Phase 3. Logic low in shutdown.
PWM Driver Control Output for Phase 4. Logic low when disabled (CSP4 = V ) and in shutdown.
CC
Driver Skip Control Output. Push/pull logic output that controls the operating mode of the skip-mode driver ICs.
DRSKP swings from V to PGND. When DRSKP is high, the driver ICs operate in forced-PWM mode. When
26
DRSKP
CC
DRSKP is low, the driver ICs enable their zero-crossing comparators and operate in pulse-skipping mode.
Remote Feedback Sense Input. Connect FBS to the CPU output sense point. To minimize output-voltage
errors due to any resistance in series with the FBS input, the controller generates an FBS input bias
current equal in magnitude and opposite in polarity to the VPS output current. FBS is high impedance
in shutdown.
27
FBS
Voltage-Positioning Transconductance-Amplifier Output. Connect a resistor R
between VPS and FBS to
VPS
set the DC steady-state droop (load line) based on the required voltage-positioning slope (see the
Voltage-Positioning Amplifier section).
R
VPS
= R
/ (R
x G
)
DROOP
SENSE
M(VPS)
where R
is the desired DC voltage-positioning slope, R
is the current-sense resistor, and
DROOP
SENSE
28
29
VPS
G
= 200µS. R
is the accurate sense resistor used to generate current-sense voltage (CRSP,
SENSE
M(VPS)
CRSN). When CRSP is connected to V , the input to the transconductance amplifier is the sum of the
current-sense voltage (CSP_, CSN_) inputs. When the inductors’ DC resistances (R
current-sense elements (for lossless sensing), R
temperature dependence of the voltage-positioning slope. To disable voltage positioning, short VPS to
FBS. VPS is high impedance in shutdown.
CC
) are used as the
DCR
should include an NTC thermistor to minimize the
VPS
Negative Current-Sense Resistor Input. CRSN is the negative differential input used for accurate sensing
of the phase 1 inductor current. Connect a current-sense resistor between CRSP and CRSN for accurate
CRSN
voltage positioning and current limit. Float CRSN when not used (CRSP pulled up to V ).
CC
______________________________________________________________________________________ 15
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Pin Description (continued)
PIN
NAME
FUNCTION
Positive Current-Sense Resistor Input. CRSP is the positive differential input used for accurate sensing of
the phase 1 inductor current. Connect a current-sense resistor between CRSP and CRSN. If current-sense
resistors are used on all phases (CSP_, CSN_), this additional current-sense (CRSP, CRSN) feature can be
30
CRSP
disabled by connecting CRSP to V and floating CRSN.
CC
Positive Current-Sense Input for Phase 1. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented.
31
CSP1
32
33
CSN1
CSN2
Negative Current-Sense Input for Phase 1
Negative Current-Sense Input for Phase 2
Positive Current-Sense Input for Phase 2. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented.
34
35
CSP2
CSP3
Positive Current-Sense Input for Phase 3. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented.
36
37
CSN3
CSN4
Negative Current-Sense Input for Phase 3
Negative Current-Sense Input for Phase 4
Positive Current-Sense Input for Phase 4. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
38
CSP4
implemented. Connect CSP4 to V
for fixed 3-phase operation.
CC
Low-Voltage VID-DAC Code Inputs. The D0–D4 inputs do not have internal pullups. These 1.0V logic
inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = low), the output
voltage is set by the D0–D4 VID-DAC inputs. In suspend mode (SUS = high), the output voltage tracks the
voltage at SUSV.
39
40
D0
D1
Low-Voltage VID-DAC Code Inputs
The +5V bias supply must provide V
(PWM con-
CC
Detailed Description
troller) and V
(FET gate-drive power), so the maxi-
DRV
+5V Bias Supply (V
)
CC
mum current drawn is:
The MAX8707 requires an external +5V bias supply in
addition to the battery. Typically, this +5V bias supply is
the notebook’s 95%-efficient, +5V system supply.
Keeping the bias supply external to the controller
improves efficiency and eliminates the cost associated
with the +5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the +5V bias supply
can be generated with an external linear regulator.
I
= I
+ I
CC DRIVE
BIAS
where I
is provided in the Electrical Characteristics
CC
table and I
is the driver’s supply current dominat-
DRIVE
ed by f
x Q (per phase) as defined in the driver’s
SW
G
data sheet. If the +5V bias supply is powered up prior
to the battery supply, the enable signal (SHDN going
from low to high) must be delayed until the battery volt-
age is present to ensure startup.
16 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
oscillator edges. This effectively triggers a phase a full
cycle early, increasing the total inductor-current slew
rate and providing an immediate transient response.
Switching Frequency (OSC)
OSC is a 3-level logic input used to set the per-phase
switching frequency. Connect OSC directly to GND,
REF, or V
for 200kHz, 300kHz, and 600kHz opera-
CC
Feedback-Adjustment Amplifiers
tion, respectively. High-frequency (600kHz, OSC =
) operation optimizes the application for the small-
Voltage-Positioning Amplifier (Steady-State Droop)
The multiphase controllers include a transconductance
amplifier for adding gain to the voltage-positioning
sense path. The current-sense inputs differentially
sense the voltage across either a single current-sense
resistor (CRS sensing enabled) or the inductor’s DCR
(CRS sensing disabled). The VPS amplifier’s input is
generated by sensing either a single phase (CRS sens-
ing) and multiplying by the number of active phases, or
by summing the current-sense (CS_) inputs of all active
V
CC
est component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra-
portable devices where the load currents are lower.
Low-frequency (200kHz, OSC = GND) operation offers
the best overall efficiency at the expense of component
size and board space.
Interleaved Multiphase Operation
The MAX8707 interleaves all the active phases—result-
ing in out-of-phase operation that minimizes the input
and output filtering requirements, reduces electromag-
netic interference (EMI), and improves efficiency. The
multiphase controller shares the current between multiple
phases that operate 90° out-of-phase (4-phase opera-
tion) or 120° out-of-phase (3-phase operation). The high-
side MOSFETs do not turn on simultaneously during
normal operation. The instantaneous input current is
effectively reduced by the number of active phases,
resulting in reduced input voltage ripple, ESR power loss,
and RMS ripple current (see the Input-Capacitor
Selection section). Therefore, the controller achieves high
performance while minimizing the component count—
which reduces cost, saves board space, and lowers
component power requirements—making the MAX8707
ideal for high-power, cost-sensitive applications.
phases (CRSP = V ). The transconductance amplifi-
CC
er’s output connects to the regulator’s voltage-posi-
tioned feedback input (VPS), so the resistance between
VPS and the output voltage-sense point (FBS) deter-
mines the voltage-positioning gain:
V
= V
- R I
VPS VPS
OUT
TARGET
where the target voltage (V
) is defined in the
TARGET
Nominal Output-Voltage Selection section, and the
transconductance amplifier’s output current (I
) is
VPS
determined by the current-sense voltage and the num-
ber of active phases (η ):
PH
I
= η (V
- V
) G
VPS
PH CRSP
CRSN M(VPS)
when CRS sensing is enabled, or:
= ∑ (V - V
I
) G
M(VPS)
VPS
CSP_
CSN_
when CRS sensing is disabled (CRSP = V ).
CC
Transient Phase Repeat
When a transient occurs, the response time of the con-
troller depends on its ability to quickly respond to the
output-voltage deviation and slew the inductor current
to the new current level. Multiphase, fixed-frequency
controllers typically respond only to the clock edge,
resulting in a delayed response from the actual tran-
sient event. To eliminate this delay time, the MAX8707
includes transient phase repeat, which allows the con-
troller to immediately respond when heavy load tran-
sients are detected. If the controller detects that the
output voltage has dropped by 25mV, the transient
detection comparator immediately retriggers the phase
that completed its on-time last. The controller triggers
the subsequent phases as normal—on the appropriate
where G
is typically 200µS as defined in the
M(VPS)
Electrical Characteristics table. To avoid output-voltage
errors caused by the VPS current flowing through para-
sitic trace resistance or feedback fliter resistance, a
second transconductance amplifier generates an equal
and opposite current on the FBS input.
Disable voltage positioning by shorting VPS directly to FBS.
______________________________________________________________________________________ 17
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Figure 1. Standard MAX8707 AMD Hammer Application Circuit
18 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Transient-Droop Amplifier
Table 1. Component Selection for
Standard Multiphase Applications
The MAX8707 controller includes a transient-droop
transconductance amplifier to handle the instantaneous
load transients typical of CPU applications. The tran-
sient-droop amplifier sets the correct voltage-positioning
slope during a load transient, complimenting the slower
steady-state voltage-positioning amplifier. The current-
sense inputs differentially sense the voltage across the
CSP_ and CSN_ current-sense element (inductor’s DCR
or current-sense resistor). The transconductance amplifi-
er’s output connects to the regulator’s transient-response
input (TRC), so the resistance between TRC and the ref-
erence voltage (REF) determines the transient voltage-
positioning gain as defined in the Multiphase,
Fixed-Frequency Design Procedure section.
MAX8707
AMD HAMMER
COMPONENTS
DESIGNATION
Circuit of Figure 1
Input Voltage Range
7V to 24V
VID Output Voltage (D4–D0)
1.50V (D4–D0 = 00010)
SUSV Suspend Voltage
(SUS = High)
0.80V
Maximum Load Current
80A
4 phases
Number of Phases (η
)
TOTAL
(1) MAX8705 + (2) MAX8702
If voltage positioning is not required, R
is
DROOP
defined by the maximum output-voltage sag with the
) and is sub-
ject to stability requirements. TRC is high impedance in
shutdown.
0.56µH, 1.6mΩ
Panasonic ETQP4LR56WFC
Inductor (Per Phase)
worst-case transient load (∆V
/ ∆I
OUT
OUT
Switching Frequency
(Per Phase)
300kHz (OSC = REF)
Siliconix (1) Si7892DP
Siliconix (2) Si7356DP
Differential Remote Sense
The multiphase controllers include differential, remote-
sense inputs to eliminate the effects of voltage drops
down the PC board traces and through the processor’s
power pins.
High-Side MOSFET
(N , Per Phase)
H
Low-Side MOSFET
(N , Per Phase)
L
The MAX8707 GNDS amplifier adds an offset directly to
the target voltage, adjusting the output voltage to coun-
teract the voltage drop in the ground path. Connect the
feedback sense (FBS), voltage-positioning resistor
(8) 10µF, 25V
TDK C3225X7R1E106M
Taiyo Yuden
Total Input Capacitance (C
Total Output Capacitance
)
IN
TMK325BJ106MN
(R
), and ground-sense (GNDS) inputs directly to the
VPS
(6) 330µF, 2.5V, 9mΩ
Sanyo 2R5TPE330M9
processor’s core supply remote- sense outputs.
(C
)
OUT
Integrator Amplifier
Current-Sense Resistor
(R
1.0mΩ
An integrator amplifier forces the DC average of the
VPS voltage to equal the target voltage. This transcon-
ductance amplifier integrates the feedback voltage and
provides a fine adjustment to the regulation voltage
(Figure 2), allowing accurate DC output-voltage regula-
tion regardless of the output ripple voltage. The integra-
tor amplifier has the ability to shift the output voltage by
100mV (typ). The differential input voltage range is at
least 60mV total, including DC offset and AC ripple.
The integration time constant can be set easily with an
external compensation capacitor at the CCV pin. Use a
)
Panasonic ERJM1WTJ1M0U
SENSE
When voltage positioning is disabled (VPS = FBS), the
transient droop must be less than the 80mV minimum
adjustment range of the integrator amplifier to guaran-
tee proper DC output-voltage accuracy.
Offset Amplifier
The multiphase controllers include a fifth amplifier used
to add small offsets to the voltage-positioned load line.
The offset amplifier sums directly with the target volt-
age, making the offset gain independent of the DAC
code. This amplifier has the ability to offset the output
by 100mV. The offset is adjusted using resistive volt-
age-dividers at the OFS input. For inputs from 0 to 0.8V,
the offset amplifier adds a negative offset to the output
that is equal to 1/8th the voltage appearing at the OFS
470pF x (4 / η ) or greater ceramic capacitor.
PH
The MAX8707 disables the integrator by connecting the
amplifier inputs together at the beginning of all transi-
tions done in pulse-skipping mode (SKIP = high). The
integrator remains disabled until 20µs after the transition
is completed (the internal target settles) and the output
is in regulation (edge detected on the error comparator).
input (V
= -0.125 x V
). For inputs from 1.2V
OFS
OFFSET
______________________________________________________________________________________ 19
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
V
CC
REF
(2.0V)
REF
UVLO
MAX8707
RUN
GND
REFOK
D4
D3
D2
D1
D0
SUS
CHANGE
WINDOW
COMPARATOR
DAC
OFS
G
M
SUSV
GNDS
TARGET
SUS
G
M
SHDN
FAULT
C
SLEW
ERROR
AMP
R-TO-I
CONVERTER
REF
TIME
x 4
CSP_
x 4
FBS
TRC
A = 10
CSN_
SKIP
OSC
TARGET
REF
G
M(TRC)
PHASE ENABLE
DETECT
TRC
CLAMP
OSCILLATOR
SKIP
R-TO-I
CONVERTER
ILIM(PK)
EA[4:1]
4-PHASE
FIXED-FREQ
CURRENT-MODE
PWM LOGIC
ILIM(AVE)
CURRENT-
LIMIT
COMPARATOR
PWM_
DRSKP
SUS
RUN
25mV
CRSP
DROOP
M(VPS)
500kΩ
TRAN
PGND
CRSN
VPS
G
LOAD-TRANSIENT
DETECT COMPARATOR
VPS
160µS
TARGET
PGOOD AND
FAULT DETECT
CCV
VROK
CHANGE
INTEGRATOR
AMP
FAULT
(UVP + THERMAL)
Figure 2. MAX8707 Functional Diagram
20 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Table 2. Component Suppliers
MANUFACTURER
BI Technologies
WEBSITE
www.bitechnologies.com
www.centralsemi.com
www.coilcraft.com
www.coiltronics.com
www.fairchildsemi.com
www.irf.com
Central Semiconductor
Coilcraft
Coiltronics
Fairchild Semiconductor
International Rectifier
Kemet
www.kemet.com
Panasonic
www.panasonic.com
www.secc.co.jp
Sanyo
Siliconix (Vishay)
Sumida
www.vishay.com
www.sumida.com
www.t-yuden.com
www.component.tdk.com
www.tokoam.com
Taiyo Yuden
TDK
TOKO
Table 3. Operating-Mode Truth Table
OUTPUT
VOLTAGE
SHDN
SUS
SKIP
OFS
OPERATING MODE
Low-Power Shutdown Mode. PWM_ outputs are forced low,
and the controller is disabled. The supply current drops to
10µA (max).
GND
X
X
X
GND
D0–D4
(no offset)
Normal Operation. The no-load output voltage is determined
by the selected VID DAC code (D0–D4, Table 4).
V
V
GND
GND
GND or REF
CC
CC
Pulse-Skipping Operation. When SKIP is pulled high, the
MAX8707 immediately enters pulse-skipping operation
allowing automatic PWM/PFM switchover under light loads.
The VROK upper threshold is blanked.
D0–D4
(no offset)
GND
GND
V
GND or REF
CC
0 to 0.8V
or
1.2V to 2.0V
Deep-Sleep Mode. The no-load output voltage is determined
by the selected VID-DAC code (D0–D4, Table 4) plus the
offset voltage set by OFS.
D0–D4
(plus offset)
V
V
V
X
X
X
CC
CC
CC
Suspend Mode/One Phase Skip. The no-load output voltage
is determined by the suspend voltage present on SUSV,
overriding all other active modes of operation.
SUSV
(no offset)
V
X
X
CC
X
Fault Mode. The fault latch has been set by either UVP or
thermal shutdown. The controller remains in FAULT mode
GND
until V
power is cycled or SHDN toggled.
CC
X = Don’t Care
______________________________________________________________________________________ 21
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
to 2V, the offset amplifier adds a positive offset to the
output that is equal to 1/8th the difference between the
OUTPUT OFFSET VOLTAGE
vs. OFS INPUT VOLTAGE
reference voltage and the voltage appearing at the
OFS input (V
= 0.125 x (V
- V
)). With this
OFFSET
REF
OFS
200mV
100mV
0
scheme, the controller supports both positive and neg-
ative offsets with a single input. The piecewise linear-
transfer function is shown in Figure 3. The regions of
the transfer function below zero, above 2.0V, and
between 0.8V and 1.2V are undefined. OFS inputs are
disallowed in these regions, and the respective effects
on the output are not specified.
UNDEFINED
REGION
The controller disables the offset amplifier during sus-
pend mode (SUS = high).
-100mV
-200mV
Nominal Output-Voltage Selection
0.8V
1.2V
The nominal no-load output voltage (V ) is defined
TARGET
by the selected voltage reference (VID DAC or SUSV)
plus the offset voltage and remote ground-sense adjust-
0
0.5V
1.0V
1.5V
2.0V
OFS VOLTAGE (V
)
OFS
ment (V ) as defined in the following equation:
GNDS
V
= V
+ V
+ V
TARGET
DAC
OFFSET GNDS
Figure 3. Output Offset Voltage vs. OFS Input Voltage
when SUS = GND
where V is the selected VID voltage during normal
DAC
are compatible with the AMD Hammer (Table 4) specifi-
cations.
operation (SUS = low, Table 4), and V
is the offset
OFFSET
voltage defined by the OFS pin (Figure 3). In suspend
mode (SUS = high), the offset voltage amplifier is disabled
and the target voltage tracks the SUSV input voltage:
Suspend Mode
When the processor enters low-power suspend mode,
the processor sets the regulator to a lower output voltage
to reduce power consumption. The MAX8707 includes a
buffered suspend-voltage input (SUSV) and a digital
SUS control input. The suspend voltage is adjusted with
an external resistive voltage-divider from REF to SUSV to
analog ground. The suspend-voltage adjustment range
V
= V
+ V
TARGET
SUSV GNDS
when SUS = V
CC
The MAX8707 uses a multiplexer that selects from one of
three different inputs (Figure 2)—the output of the VID
DAC, the SUSV suspend voltage, or ground (controller
disabled). On startup, the MAX8707 slews the target volt-
age from ground to either the decoded D0–D4 (SUS =
low) voltage or the SUSV voltage (SUS = high).
is from 0.4V to 2.0V (V
).
REF
When the CPU suspends operation (SUS = high), the
controller disables the offset amplifier, overrides the 5-bit
VID-DAC code set by D0–D4, and slews the output volt-
age to the target voltage set by the SUSV voltage. During
the transition, the MAX8707 blanks both VROK thresh-
olds until 20µs after the slew-rate controller reaches the
suspend-mode voltage. Once the 20µs timer expires, the
MAX8707 (SKIP pulled low) automatically switches to the
1-phase, pulse-skipping control scheme, forces DRSKP
low, and blanks the upper VROK threshold.
DAC Inputs (D0–D4)
During normal forced-PWM operation (SUS = low), the
DAC programs the output voltage using the D0–D4
inputs. D0–D4 are low-voltage (1.0V) logic inputs,
designed to interface directly with the CPU. Do not leave
D0–D4 unconnected. D0–D4 can be changed while the
MAX8707 is active, initiating a transition to a new output-
voltage level. Change D0–D4 together, avoiding greater
than 50ns skew between bits. Otherwise, incorrect DAC
readings may cause a partial transition to the wrong volt-
age level followed by the intended transition to the cor-
rect voltage level, lengthening the overall transition time.
The available DAC codes and resulting output voltages
Output-Voltage Transition Timing
The MAX8707 performs mode transitions in a controlled
manner, automatically minimizing input surge currents.
This feature allows the circuit designer to achieve nearly
22 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Table 4. AMD Hammer Output-Voltage VID DAC Codes (SUS = GND)
OUTPUT VOLTAGE
(V)
OUTPUT VOLTAGE
(V)
D4
D3
D2
D1
D0
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
No CPU*
*No-CPU Mode: The controller enters the no-CPU mode by ramping down the output voltage to 0V with the shutdown slew rate.
When exiting the no-CPU mode, the controller ramps the output up to the new VID output voltage using the startup slew rate. In no-
CPU mode, the controller remains in standby so VID transitions may be detected.
ideal transitions, guaranteeing just-in-time arrival at the
new output-voltage level with the lowest possible peak
currents for a given output capacitance.
The MAX8707 automatically controls the current to the
minimum level required to complete the transition in the
calculated time. The slew-rate controller uses an inter-
nal capacitor and current source programmed by
At the beginning of an output-voltage transition, the
MAX8707 blanks both VROK thresholds, preventing the
VROK open-drain output from changing states during
the transition. The controller enables the lower VROK
threshold approximately 20µs after the slew-rate con-
troller reaches the target output voltage, but the upper
VROK threshold is enabled only if the controller remains
in forced-PWM operation. If the controller enters pulse-
skipping operation, the upper VROK threshold remains
R
to transition the output voltage. The total transi-
TIME
tion time depends on R
the accuracy of the slew-rate controller (C
, the voltage difference, and
TIME
accura-
SLEW
cy). The slew rate is not dependent on the total output
capacitance, as long as the surge current is less than
the current limit set by ILIM(AVE) and ILIM(PK). For
voltage transitions into and out of suspend mode, the
transition time (t
) is given by:
TRAN
blanked. The slew-rate (set by resistor R ) must be
TIME
|V
dV
- V
|
NEW
OLD
/dt
set fast enough to ensure that the transition can be
completed within the maximum allotted time.
t
=
TRAN(SUS)
TARGET
When transitions occur in pulse-skipping mode, the
MAX8707 sets OVP to 1.75V and disables the integrator
at the beginning of all transitions. OVP remains at 1.75V
and the integrator remains disabled until 20µs after the
transition is completed (internal target settles) and the
output is in regulation (an error-comparator edge is
detected).
where dV
/ dt = 6.25mV/µs × 143kΩ / R
is
TIME
TARGET
the slew rate, V
is the original output voltage, and
OLD
V
is the new target voltage. See TIME Slew-Rate
NEW
Accuracy in the Electrical Characteristics for t
lim-
SLEW
its. For soft-start and shutdown, the controller automati-
cally reduces the slew rate by 1/4th:
______________________________________________________________________________________ 23
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
When exiting deeper sleep (SUS pulled low), the
4V
TARGET
MAX8707 starts to slew the internal target up towards
the new target. The controller remains in skip mode
while the output voltage is higher than the internal tar-
get. As the internal target approaches the output volt-
age, the MAX8707 activates all enabled phases
(DRSKP driven high) so the output voltage may be
t
= t
=
TRAN(SHDN)
TRAN(START)
dV
/dt
TARGET
For all dynamic VID transitions, the rate at which the
VID inputs (D0–D4) are clocked sets the slew rate, with
a maximum slew-rate limit set by the R
value. The
TIME
practical range of R
is 47kΩ to 392kΩ correspond-
ramped up at the slew rate set by R
. The controller
TIME
TIME
ing to slew rates of 19mV/µs to 2.28mV/µs, respectively.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth.
blanks VROK (forced high impedance) until 20µs after
the transition is completed.
Forced-PWM Operation (Normal Mode)
During soft-start, soft-shutdown, and normal operation—
when the CPU is actively running (SKIP = low, Table 5)—
the MAX8707 operates with a low-noise, forced-PWM con-
trol scheme. Forced-PWM operation forces DRSKP high,
instructing the drivers to disable their zero-crossing com-
parators and force the low-side gate-drive waveforms to
constantly be the complement of the high-side gate-drive
waveforms. This keeps the switching frequency constant
and allows the inductor current to reverse under light
loads, providing fast, accurate negative output-voltage
transitions by quickly discharging the output capacitors.
The average inductor current per phase required to
make an output-voltage transition is:
C
η
OUT
I ≅
×(dV
/dt)
L
TARGET
PH
where dV
/ dt is the required slew rate, C
is
OUT
TARGET
the total output capacitance, and η
is the number of
PH
active phases.
Suspend Transition
(Forced-PWM Operation Selected)
When the MAX8707 enters suspend mode while config-
ured for forced-PWM operation (SKIP pulled low), the
controller ramps the output voltage down to the pro-
grammed SUSV voltage at the slew rate determined by
Forced-PWM operation comes at a cost: the no-load +5V
bias supply current remains between 10mA to 200mA
per phase, depending on the external MOSFETs and
switching frequency. To maintain high efficiency under
light-load conditions, the controller switches to a low-
power pulse-skipping control scheme after entering sus-
pend mode.
R
. The controller blanks VROK (forced high imped-
TIME
ance) until 20µs after the transition is completed—internal
target voltage equals the SUSV voltage. After this blank-
ing time expires, the controller automatically shuts down
phases 2, 3, and 4 (DRSKP pulled low), and enters sin-
gle-phase, pulse-skipping operation. VROK monitors only
the lower threshold in skip mode.
Light-Load Pulse-Skipping Operation
The MAX8707 includes a light-load operating-mode con-
trol input (SKIP) used to disable extra phases and
enable/disable the driver’s zero-crossing comparator.
When the driver’s zero-crossing comparators are enabled
(DRSKP pulled low), the controller forces PWM_ low for
the disabled phases so the driver pulls DL_ low when its
current-sense inputs detect zero inductor current. This
keeps the inductor from discharging the output capaci-
tors and forces the controller to skip pulses under light-
load conditions to avoid overcharging the output. When
the zero-crossing comparators are disabled, each con-
troller maintains PWM operation under light-load condi-
tions (forced PWM).
When exiting suspend mode (SUS pulled low), the
MAX8707 immediately activates all enabled phases
(DRSKP driven high) so the output voltage may be
ramped up at the slew rate set by R
. The controller
TIME
blanks VROK (forced high impedance) until 20µs after
the transition is completed—internal target voltage
equals the selected VID-DAC voltage.
Suspend Transition
(Pulse-Skipping Operation Selected)
If the MAX8707 is configured for pulse-skipping opera-
tion (SKIP = high) when SUS goes high, the MAX8707
immediately disables phases 2, 3, and 4 (DRSKP pulled
low) and enters pulse-skipping operation (Figure 5). The
output drops at a rate determined by the load and the
output capacitance. The internal target still ramps as
before, and VROK remains high impedance until the
new target is reached plus an extra 20µs. After this time
expires, VROK monitors only the lower threshold.
After the MAX8707 enters suspend mode while config-
ured for forced-PWM operation (SKIP pulled low), the
controller automatically switches to the pulse-skipping
control scheme 20µs after the target voltage reaches
the programmed SUSV voltage.
When pulse-skipping operation is enabled, the con-
troller terminates the on-time when the output voltage
exceeds the feedback threshold and when the current-
24 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
VID
CPU CORE
VOLTAGE
SUSV
SUS
INTERNAL
PWM CONTROL
AUTO 1-PHASE SKIP
FORCED-PWM
FORCED-PWM
PWM1
PWM2
PWM3
PWM4
DRSKP
VROK
LOW THRESHOLD ONLY
HIGH-Z
HIGH-Z
t
t
BLANK
BLANK
20µs typ
20µs typ
NOTE: OVP CONSTANTLY TRACKS THE INTERNAL TARGET, AND THE INTEGRATOR (CCV) IS CONSTANTLY ENABLED.
Figure 4. Suspend Transition in Forced-PWM Mode (SKIP = low)
VID
ACTUAL V
TARGET
OUT
CPU CORE
VOLTAGE
SUSV
SKIP = SUS
INTERNAL
PWM CONTROL
1-PHASE SKIP
FORCED PWM
PWM1
PWM2
PWM3
PWM4
DRSKP
VROK
HIGH-Z
HIGH-Z
LOW VROK THRESHOLD ONLY
OVP TRACKS INTERNAL TARGET
INTEGRATOR ENABLED
OVP/CCV
OVP = 1.8V INTEGRATOR DISABLED
t
t
BLANK
20µs
BLANK
20µs
Figure 5. Suspend Transition in Pulse-Skipping Operation (SKIP = SUS)
______________________________________________________________________________________ 25
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Table 5. SKIP Settings
SKIP
(INPUT)
SUS
(INPUT)
DRSKP
(OUTPUT)
MODE
OPERATION
The controller operates with a constant switching
frequency, providing low-noise forced-PWM operation. The
controller disables the zero-crossing comparators, forcing
the low-side gate-drive waveform to constantly be the
complement of the high-side gate-drive waveform.
Low
(GND)
Multiphase
Forced-PWM
High
(V
DD
)
Low
The controller automatically switches to pulse-skipping
operation 20µs after the target voltage reaches the SUSV
voltage. Pulse-skipping operation forces the controller into
PFM operation under light loads. Phase 1 remains active
while the other three phases are disabled—PWM2, PWM3,
and PWM4 pulled low.
(GND)
High
(3.3V or V
1-Phase Pulse
Skipping
Low
(PGND)
)
CC
Pulse-skipping operation forces the controller into PFM
operation under light loads. Phase 1 remains active while
the other three phases are disabled—PWM2, PWM3, and
PWM4 pulled low.
High
(>1.2V)
1-Phase Pulse
Skipping
Low
(PGND)
Don’t Care
sense voltage exceeds the Idle Mode current-sense
threshold (V = 0.1 x V ). Under heavy-load
troller does not initiate another on-time. This forces the
controller to actually regulate the valley of the output
voltage ripple under light-load conditions.
IDLE
PKLIMIT
conditions, the continuous inductor current remains
above the Idle-Mode current-sense threshold, so the
on-time depends only on the feedback-voltage thresh-
old. Under light-load conditions, the controller remains
above the feedback-voltage threshold, so the on-time
duration depends solely on the Idle-Mode current-
sense threshold, which is approximately 10% of the full-
load current-limit threshold set by ILIM(PK).
Automatic Pulse-Skipping Crossover
In skip mode, the MAX8707 disables three phases and
forces DRSKP low to instruct the skip-mode drivers to
activate their zero-crossing comparators. Therefore, an
inherent automatic switchover to PFM takes place at light
loads (Figure 6), resulting in a highly efficient operating
mode. This switchover is affected by a comparator that
truncates the low-side switch on-time at the inductor cur-
rent’s zero crossing. The driver’s zero-crossing compara-
tor senses the inductor current across the low-side
MOSFET (refer to the skip-mode driver data sheet).
When the controller enters suspend mode while SKIP is
pulled high, the multiphase controller immediately dis-
ables three phases, and only the main phase (PWM1)
remains active. When pulse skipping, the controller
blanks the upper VROK threshold and the OVP threshold
tracks the selected VID DAC code. The MAX8707 auto-
matically uses forced-PWM operation during soft-start
and soft-shutdown, regardless of the SKIP configuration.
Once V
- V
drops below the zero-crossing
PGND
LX
threshold, the driver forces DL low. This mechanism
causes the threshold between pulse-skipping PFM and
nonskipping PWM operation to coincide with the bound-
ary between continuous and discontinuous inductor-cur-
rent operation (also known as the critical conduction
point). The load-current level at which the PFM/PWM
Idle-Mode Current Sense Threshold
The Idle-Mode current-sense threshold forces a lightly
loaded regulator to source a minimum amount of ener-
gy with each on-time since the controller cannot termi-
nate the on-time until the current-sense voltage
crossover occurs, I , is given by:
LOAD(SKIP)
V
V
− V
OUT
(
)
exceeds the Idle-Mode current-sense threshold (V
OUT IN
IDLE
I
=
LOAD(SKIP)
= 0.1 x V
). Since the zero-crossing comparator
PKLIMIT
2V f
L
IN SW
prevents the switching regulator from sinking current,
the controller must skip pulses to avoid overcharging
the output. When the clock edge occurs, if the output
voltage still exceeds the feedback threshold, the con-
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
Idle Mode is a trademark of Maxim Integrated Products, Inc.
26 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
V
OUT
f
t
=
ON(SKIP)
V
IN SW
I
IDLE
I
≈ I
LOAD
LOAD(SKIP)
2
Current Sense
The output current of each phase is sensed differential-
ly. Each phase of the MAX8707 has an independent
return path for fully differential current-sense. A low off-
set voltage and high-gain (10V/V) differential current
amplifier at each phase allow low-resistance current-
sense resistors to be used to minimize power dissipa-
tion. Sensing the current at the output of each phase
offers advantages, including less noise sensitivity, more
accurate current sharing between phases, and the flexi-
bility of using either a current-sense resistor or the DC
resistance of the output inductor.
0
ON-TIME
TIME
Figure 6. Pulse-Skipping/Discontinuous Crossover Point
L
ESL
=R
C
EQ SENSE
R
SENSE
Using the DC resistance (R
) of the output inductor
DCR
where L
is the equivalent series inductance of the
ESL
allows higher efficiency. In this configuration, the initial
tolerance and temperature coefficient of the inductor’s
DCR must be accounted for in the output-voltage
droop-error budget. This current-sense method uses an
RC filtering network to extract the current information
from the output inductor (Figure 7). The time constant
of the RC network should match the inductor’s time
current-sense resistor, R
is the current-sense
SENSE
resistance value, C
tor, and R is the equivalent compensation resistance.
is the compensation capaci-
SENSE
EQ
Current Balance
The fixed-frequency, multiphase, current-mode archi-
tecture automatically forces the individual phases to
remain current balanced. After the oscillator triggers an
on-time, the controller does not terminate the on-time
until the amplified differential current-sense voltage
constant (L/R
):
DCR
L
=R
C
EQ SENSE
reaches the integrated threshold voltage (V
- V
).
REF
TRC
R
DCR
This control scheme regulates the peak inductor cur-
rent of each phase, forcing them to remain properly
balanced. Therefore, the average inductor-current vari-
ation depends mainly on the variation in the current-
sense element and inductance value.
where C
is the sense capacitor and R
is the
EQ
SENSE
equivalent sense resistance. To minimize the current-
sense error due to the current-sense inputs’ bias cur-
rent (I
_ and I
_), choose R
less than 2kΩ and
EQ
CSP
CSN
use the above equation to determine the sense capaci-
tance (C ). Choose capacitors with 5% tolerance
Peak/Average Current Limit
The MAX8707 current-limit circuit employs a fast peak
inductor current-sensing algorithm. Once the current-
sense signal (CSP to CSN) of the active phase exceeds
the peak current-limit threshold, the PWM controller ter-
minates the on-time. The MAX8707 also includes a
slower average current sense that uses a current-sense
resistor between CRSP and CRSN to accurately limit
the inductor current. When this average current-sense
threshold is exceeded, the current-limit circuit lowers
the peak current-limit threshold, effectively lowering the
average inductor current. See the Current Limit section
in the Design Procedure section.
SENSE
and resistors with 1% tolerance specifications.
Temperature compensation is recommended for this
current-sense method.
When using a current-sense resistor for accurate out-
put-voltage positioning (CRSP to CRSN for the
MAX8707), differential RC-filter circuits should be used
to cancel the equivalent series inductance of the cur-
rent-sense resistor (Figure 7). Similar to inductor DCR-
sensing methods, the RC filter’s time constant should
match the L/R time constant formed by the current-
sense resistor’s parasitic inductance:
______________________________________________________________________________________ 27
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
INPUT (V
)
IN
INPUT (V
)
IN
C
C
IN
IN
DRIVER
DRIVER
N
N
H
INDUCTOR
H
DH
LX
DH
LX
L
R
L
R
DCR
SENSE
C
C
OUT
OUT
N
N
L
L
DL
DL
D
D
L
L
R
C
SENSE
EQ
PWM
PGND
PWM
PGND
PWM_
PWM_
CSP_
CSN_
CSP_
CSN_
CONTROLLER
CONTROLLER
A) OUTPUT SERIES RESISTOR SENSING
B) LOSSLESS INDUCTOR SENSING
Figure 7. Current-Sense Methods
Power-Up Sequence (POR, UVLO)
Power-on reset (POR) occurs when V rises above
down until the fault latch is cleared by toggling SHDN
or cycling the V power supply below 1V.
CC
CC
approximately 2V, resetting the fault latch and prepar-
ing the controller for operation. The V undervoltage-
lockout (UVLO) circuitry inhibits switching—forces
DRSKP high and pulls the PWM_ outputs low—until
If the V
voltage drops below 4.25V, the controller
CC
CC
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from over-
voltage faults, the controller shuts down immediately—
forces DRSKP high and pulls the PWM_ outputs low.
V
rises above 4.25V. The controller powers up the
CC
reference once the system enables the controller—V
CC
above 4.25V and SHDN pulled high. With the reference
in regulation, the controller begins to slew the output
voltage to the target voltage—either the output of the
VID DAC (SUS = low) or the SUSV suspend voltage
Shutdown
When SHDN goes low, the MAX8707 enters low-power
shutdown mode. VROK is pulled low immediately, and
the output voltage ramps down at 1/4th the slew rate
(SUS = high)—at 1/4th the slew rate set by R
:
set by R
:
TIME
TIME
4V
4V
TARGET
OUT
t
=
t
=
TRAN(START)
TRAN(SHDN)
dV
/dt
dV
/dt
TARGET
TARGET
where dV
/ dt = 6.25mV/µs × 143kΩ / R
is the
where dV
/ dt = 6.25mV/µs × 143kΩ / R
is
TIME
TARGET
TIME
TARGET
slew rate. The soft-start circuitry does not use a variable
current limit, so full output current is available immediate-
ly. VROK becomes high impedance approximately 20µs
after the MAX8707 reaches the target voltage.
the slew rate. Slowly discharging the output capacitors
by slewing the output over a long period of time keeps
the average negative inductor current low (damped
response), thereby eliminating the negative output volt-
age excursion that occurs when the controller dis-
charges the output quickly by permanently turning on
the low-side MOSFET (underdamped response). This
eliminates the need for the Schottky diode normally
connected between the output and ground to clamp
For automatic startup, the battery voltage should be
present before V . If the controller attempts to bring
CC
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
28 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
V
CC
SHDN
INVALID
CODE
INVALID
CODE
VID (D0-D4)
SOFT-START
SOFT-SHUTDOWN
TH
TH
1/4 SLEW RATE SET BY R
1/4 SLEW RATE SET BY R
TIME
TIME
V
CORE
INTERNAL
PWM CONTROL
FORCED-PWM
FORCED-PWM
DRSKP
VROK
t
t
BLANK
20s typ
BLANK
20s typ
Figure 8. Power-Up and Shutdown Sequence Timing Diagram
the negative output-voltage excursion. When the con-
troller reaches the 0V target, the drivers are disabled
(DRSKP driven low and PWM_ outputs pulled low), the
reference turns off, and the supply current drops to
about 10µA (max). When a fault condition—output
UVLO or thermal shutdown—activates the shutdown
sequence, the protection circuitry sets the fault latch to
prevent the controller from restarting. To clear the fault
latch and reactivate the controller, toggle SHDN or
vers high (DL = V ) and pull the high-side gate dri-
DD
vers low (DH = LX). The controller does not initiate an
on-time pulse until the output voltage drops below the
OVP threshold. This action turns on the synchronous-
rectifier MOSFET with 100% duty and, in turn, rapidly
discharges the output filter capacitor and forces the
output low. If the condition that caused the overvoltage
(such as a shorted high-side MOSFET) persists, the
battery fuse blows.
cycle V
power below 1V.
CC
Overvoltage protection can be disabled through the no-
fault test mode (see the No-Fault Test Mode section).
Fault Protection
Output Overvoltage Protection (Unlatched)
Output Undervoltage Protection (Latched)
The output undervoltage-protection (UVP) function is
similar to foldback current limiting, but employs a timer
rather than a variable current limit. If the MAX8707 out-
put voltage is under 70% of the nominal value, the con-
troller activates the shutdown sequence and sets the
fault latch. Once the controller ramps down to the 0V
setting, it forces the PWM_ driver outputs low. Toggle
The overvoltage-protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The MAX8707 continuously monitors the output for an
overvoltage fault. The controller detects an OVP fault if
the output voltage exceeds the set target voltage by
more than 200mV. After entering pulse-skipping opera-
tion (SKIP rising edge), the OVP threshold is set to
1.75V until the output voltage drops below the target
voltage for the first time. Once the MAX8707 detects
SHDN or cycle the V
power supply below 1V to clear
CC
the fault latch and reactivate the controller.
UVP can be disabled through the no-fault test mode
(see the No-Fault Test Mode section).
the output is being regulated (V
≈ V
), the
TARGET
OUT
OVP threshold begins tracking the target voltage again.
When the OVP circuit detects an overvoltage fault, it
immediately enters forced-PWM operation—pulling
DRSKP high so the drivers force the low-side gate dri-
Thermal Fault Protection (Latched)
The MAX8707 features a thermal fault-protection circuit.
When the junction temperature rises above +160°C, a
______________________________________________________________________________________ 29
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
thermal sensor sets the fault latch and activates the
soft-shutdown sequence. Once the controller ramps
down to the 0V setting, it forces the PWM_ driver out-
where η is the total number of active phases.
PH
Switching Frequency: This choice determines the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are pro-
puts low. Toggle SHDN or cycle the V
power supply
CC
below 1V to clear the fault latch and reactivate the con-
troller after the junction temperature cools by 15°C.
Thermal shutdown can be disabled through the no-fault
test mode (see the No-Fault Test Mode section).
portional to frequency and V 2. The optimum frequen-
IN
cy is also a moving target, due to rapid improvements
in MOSFET technology that are making higher frequen-
cies more practical.
No-Fault Test Mode
The latched fault protection features can complicate
the process of debugging prototype breadboards
since there are (at most) a few milliseconds in which to
determine what went wrong. Therefore, a no-fault test
mode is provided to disable the fault protection—over-
voltage protection, undervoltage protection, and ther-
mal shutdown. Additionally, the test mode clears the
fault latch if it has been set. The no-fault test mode is
entered by forcing 11V to 13V on SHDN.
Inductor Operating Point: This choice provides trade-
offs between size vs. efficiency and transient response
vs. output noise. Low inductor values provide better
transient response and smaller physical size, but also
result in lower efficiency and higher output noise due to
increased ripple current. The minimum practical induc-
tor value is one that causes the circuit to operate at the
edge of critical conduction (where the inductor current
just touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit. The optimum operating point is usu-
ally found between 20% and 50% ripple current.
Multiphase, Fixed-Frequency
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
V
− V
V
OUT
IN
OUT
L = η
PH
f
I
LIR
V
SW LOAD(MAX)
IN
Input Voltage Range: The maximum value (V
)
IN(MAX)
where η is the total number of phases, and f
is the
SW
must accommodate the worst-case high AC-adapter
voltage. The minimum value (V ) must account for
PH
switching frequency per phase.
IN(MIN)
the lowest input voltage after drops due to connectors,
fuses, and battery selector switches. If there is a choice
at all, lower input voltages result in better efficiency.
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. If using a
swinging inductor (where the no-load inductance
decreases linearly with increasing current), evaluate
the LIR with properly scaled inductance values. For the
selected inductance value, the actual peak-to-peak
Maximum Load Current: There are two values to con-
sider. The peak load current (I
) determines
LOAD(MAX)
the instantaneous component stresses and filtering
requirements, and thus drives output capacitor selec-
tion, inductor saturation rating, and the design of the
inductor ripple current (∆I
) is defined by:
INDUCTOR
V
(V − V
)
current-limit circuit. The continuous load current (I
)
LOAD
OUT IN
OUT
∆I
=
INDUCTOR
determines the thermal stresses and thus drives the
selection of input capacitors, MOSFETs, and other criti-
cal heat-contributing components. Modern notebook
V
f
L
IN SW
Ferrite cores are often the best choice, although pow-
dered iron is inexpensive and can work well at 200kHz.
The core must be large enough not to saturate at the
CPUs generally exhibit I
= I
x 80%.
LOAD
LOAD(MAX)
For multiphase systems, each phase supports a frac-
tion of the load, depending on the current balancing.
When properly balanced, the load current is evenly dis-
tributed among each phase:
peak inductor current (I
):
PEAK
I
∆I
LOAD(MAX)
INDUCTOR
I
=
+
PEAK
η
2
PH
I
LOAD
I
=
LOAD(PHASE)
η
PH
30 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
1/20th the voltage difference between ILIM(AVE) and
the reference:
Current Limit
Peak Inductor Current Limit (ILIM(PK))
The MAX8707 overcurrent protection employs a peak
current-sensing algorithm that uses either current-
sense resistors or the inductor’s DCR as the current-
sense element (see the Current Sense section). Since
the controller limits the peak inductor current, the maxi-
mum average load current is less than the peak cur-
rent-limit threshold by an amount equal to half the
inductor ripple current. Therefore, the maximum load
capability is a function of the current-sense resistance,
inductor value, switching frequency, and input voltage.
When combined with the undervoltage-protection cir-
cuit, this current-limit method is highly effective.
V
− V
ILIM(AVE)
REF
V
=
LAVE
20
The logic threshold for switchover to the 25mV default
value is approximately V - 1V. The average current-
CC
limit circuit also prevents against excessive reverse
inductor current when V is sinking current. The neg-
OUT
ative current-limit threshold is equivalent to the positive
current limit, and tracks the positive current limit when
V
is adjusted.
LAVE
Output-Capacitor Selection
The peak current-limit threshold is set with a single exter-
nal resistor between ILIM(PK) and analog ground, where
the resistor is determined by the following equation:
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements. In CPU V
converters
CORE
and other applications where the output is subject to
large load transients, the output capacitor’s size typi-
cally depends on how much ESR is needed to prevent
the output from dipping too low under a load transient.
Ignoring the sag due to finite capacitance:
8V × R
TRC
R
=
ILIM(PK)
I
R
PKLIMIT SENSE
where R
is the resistance value of the current-
sense element (inductors’ DCR or current-sense resis-
tor), R is the resistance between TRC and REF, and
is the desired peak current limit (per phase).
The peak current-limit-threshold voltage adjustment
range is from 20mV to 80mV.
SENSE
V
TRC
PKLIMIT
STEP
(R
+R
) ≤
ESR
PCB
I
∆I
LOAD(MAX)
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capaci-
tor’s ESR. When operating multiphase systems out-of-
phase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage
The peak current-limit circuit also prevents excessive
reverse inductor currents when V
is sinking current.
OUT
The negative current-limit threshold is equivalent to the
positive current limit, and tracks the positive current limit
when R
or R
are adjusted. When a phase
TRC
ILIM(PK)
drops below the negative current limit, the controller acti-
vates an on-time pulse at the next clock edge, regard-
less of the error-amplifier state, until the inductor current
rises above the negative current-limit threshold.
(V
) by reducing the total inductor ripple current.
RIPPLE
For nonoverlapping, multiphase operation (V ≥ η
IN
PH
V
), the maximum ESR to meet the output-ripple-
x
OUT
Average Inductor Current-Limit
(ILIM(AVE))
voltage requirement is:
The MAX8707 also uses the accurate CRSP to CRSN cur-
rent-sense voltage to limit the average current per phase.
When the average current-limit threshold is exceeded,
the controller internally reduces the peak inductor cur-
rent-limit threshold (ILIM(PK)) until the average current
remains within the programmed limits. When the accurate
V
f
L
IN SW
R
≤
V
RIPPLE
ESR
(V − η
V
)V
IN
PH OUT OUT
where η is the total number of active phases, and f
PH
SW
is the switching frequency per phase. The actual capac-
itance value required relates to the physical size need-
ed to achieve low ESR, as well as to the chemistry of the
capacitor technology. Thus, the capacitor selection is
usually limited by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
current sensing is disabled (CRSP = V ), the average
CC
current-limit circuit is disabled.
The average current-limit threshold defaults to 25mV if
ILIM(AVE) is connected to V . In adjustable mode, the
CC
average current-limit threshold voltage is precisely
______________________________________________________________________________________ 31
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
The capacitance value required is determined primarily
by the output transient-response requirements. Low
inductor values allow the inductor current to slew faster,
replenishing the charge removed from or added to the
output filter capacitors by a sudden load step.
Therefore, the amount of output soar when the load is
removed is a function of the output voltage and induc-
tor value. The minimum output capacitance required to
Setting Voltage Positioning
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor’s power-dissipation
requirements. The controller uses two transconduc-
tance amplifiers to set the transient and DC output volt-
age droop (Figure 2). The transient-compensation
(TRC) amplifier determines how quickly the MAX8707
responds to the load transient. The slower voltage-posi-
tioning (VPS) amplifier adjusts the steady-state regula-
tion voltage as a function of the load. This adjustability
allows flexibility in the selected current-sense resistor
value or inductor DCR, and allows smaller current-
sense resistance to be used, reducing the overall
power dissipated.
prevent overshoot (V
) due to stored inductor ener-
SOAR
gy can be calculated as:
2
(∆I
) L
LOAD(MAX)
C
≥
OUT
2η
V
V
PH OUT SOAR
where η
is the total number of active phases. When
PH
using low-capacity ceramic filter capacitors, capacitor
size is usually determined by the capacity needed to
Steady-State Voltage Positioning
VPS
Connect a resistor (R
) between VPS and FBS to set
prevent V
from causing problems during load
SOAR
the DC steady-state droop (load line) based on the
required DC voltage-positioning slope (R ):
transients. Generally, once enough capacitance is
added to meet the overshoot requirement, undershoot
at the rising load edge is no longer a problem.
DROOP
R
DROOP
R
=
VPS
Input Capacitor Selection
R
G
SENSE M(VPS)
The input capacitor must meet the ripple-current
requirement (I ) imposed by the switching currents.
RMS
where the current-sense resistance (R
) depends
SENSE
The multiphase controllers operate out-of-phase, which
reduces the RMS input current by dividing the input cur-
rent between several staggered stages. For duty cycles
on the current-sense method, and the voltage-position-
ing amplifier’s transconductance (G ) is typically
M(VPS)
200µS as defined in the Electrical Characteristics table.
When the MAX8707 CRS sensing is enabled, R is
less than 100%/η
per phase, the I
requirements
PH
RMS
SENSE
can be determined by the following equation:
defined as the accurate CRS current-sense resistance:
R
= R
SENSE
CRS
I
η
LOAD
I
=
η
V
(V − η
V
)
RMS
PH OUT IN
PH OUT
when CRS sensing is enabled.
V
PH IN
When the MAX8707 CRS sensing is disabled, the con-
troller sums together the input signals of the current-
sense inputs (CSP_, CSN_). These inputs typically use
where η is the total number of out-of-phase switching
regulators. The worst-case RMS current requirement
occurs when operating with V = 2η
point, the above equation simplifies to I
PH
the inductors’ DC resistance (R
) to sense the cur-
DCR
V
RMS
. At this
= 0.5 x
IN
PH OUT
rent, so R
is defined as the average of the effec-
SENSE
tive CS current-sense resistances (see the Current
Sense section):
I
/ η
.
LOAD
PH
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to inrush surge currents, typical of systems
with a mechanical switch or connector in series with the
input. If the MAX8707 is operated as the second stage
of a two-stage power-conversion system, tantalum
input capacitors are acceptable. In either configuration,
choose an input capacitor that exhibits less than 10°C
temperature rise at the RMS input current for optimal
circuit longevity.
R
= R
DCR
SENSE
when CRS sensing is disabled.
When the inductors’ DCR (R
rent-sense elements (for lossless sensing), R
include an NTC thermistor to minimize the temperature
dependence of the voltage-positioning slope.
) is used as the cur-
DCR
should
VPS
To avoid output-voltage errors caused by the voltage-
positioning current, a second transconductance ampli-
fier generates an equivalent current on the FBS input.
Accurate MAX8707 CRS sensing is disabled by con-
necting CRSP to V
.
CC
32 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Disable voltage positioning by shorting VPS directly to FBS.
the controller to effectively operate with a lower switch-
ing frequency. This results in an input threshold voltage
Transient Droop
at which the controller begins to skip pulses (V
):
IN(SKIP)
Connect a resistor (R
) between TRC and REF to set
DROOP(AC)
TRC
the transient droop (R
) based on the voltage-
1
V
= V
OUT
positioning requirements. TRC allows the controller to
quickly respond to load transients, but it does not affect
IN(SKIP)
f
t
SW ON(MIN)
the DC steady-state droop. Choose R
equation:
based on the
TRC
where f
is the switching frequency per phase select-
SW
ed by OSC, and t
is 110ns plus the driver’s
ON(MIN)
turn-off delay (PWM low to LX low) minus the driver’s
turn-on delay (PWM high to LX high). For the best high-
voltage performance, use the slowest switching-fre-
quency setting (200kHz per phase, OSC = GND).
R
R
TRANS CS
R
R
=
TRC
η
PH DROOP(AC)
where R is the current-sense element connected from
CS
CSP_ to CSN_ (which is typically the inductor’s effective
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 9). If possible, mount all of the power compo-
nents on the top side of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
DCR: R
= L / R
C
), R
is the current-
TRANS
CS
EQ SENSE
sense amplifier gain divided by the transient amplifier’s
transconductance as defined in the Electrical Character-
istics table, and R
is typically 80% of the DC
DROOP(AC)
voltage-positioning slope to minimize the transient
sag voltage.
The TRC resistance also sets the small-signal loop gain,
so a maximum R
value is required for stability, even
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
TRC
if voltage positioning is not used (VPS = FBS).
V
R
< (R ∆I ) / 3
R
RIPPLE TRC
TRANS SENSE
L
2) Connect all analog grounds to a separate solid cop-
per plane, which connects to the GND pin of the
TRC is high impedance in shutdown.
controller. This includes the V
bypass capacitor,
Applications Information
CC
REF and GNDS bypass capacitors, compensation
(CCV, TRC) components, and the resistive dividers
Duty-Cycle Limits
connected to I
, SUSV, and OFS.
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by stability requirements, not the minimum
). The MAX8707 does not include
slope compensation, so the controller becomes unsta-
ble with duty cycles greater than 50% per phase:
LIM(AVE)
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance caus-
es a measurable efficiency penalty.
off-time (t
OFF(MIN)
V
≥ 2V
OUT(MAX)
IN(MIN)
However, the controller may briefly operate with duty
cycles over 50% during heavy load transients.
4) Connections for current limiting (CSP_, CSN_) and
voltage positioning (CRSP, CRSN) must be made
using Kelvin-sense connections to guarantee the
current-sense accuracy.
Maximum Input Voltage
The MAX8707 controller and driver has a minimum on-
time, which determines the maximum input operating
voltage that maintains the selected switching frequen-
cy. With higher input voltages, each pulse delivers
more energy than the output is sourcing to the load. At
the beginning of each cycle, if the output voltage is still
above the feedback threshold voltage, the controller
does not trigger an on-time pulse resulting in pulse-
skipping operation regardless of the operating mode
selected by SKIP. This allows the controller to maintain
regulation above the maximum input voltage, but forces
5) Route high-speed switching nodes and driver traces
away from sensitive analog areas (REF, CCV, TRC,
VPS, etc.). Make all pin-strap control input connec-
tions (SHDN, SKIP, SUS, OSC) to analog ground or
V
CC
rather than power ground or V
.
DD
6) Keep the drivers close to the MOSFET, with the
gate-drive traces (DL, DH, LX, and BST) short and
wide to minimize trace resistance and inductance.
______________________________________________________________________________________ 33
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
KELVIN SENSE VIAS UNDER
THE SENSE RESISTOR
(REFER TO THE EVALUATION KIT)
CPU
R
SENSE
OUTPUT
INDUCTOR
INDUCTOR
INDUCTOR
INDUCTOR
INPUT
PLACE CONTROLLER ON
BACKSIDE WHEN POSSIBLE,
USING THE GROUND PLANE
TO SHIELD THE IC FROM EMI
ANALOG GROUND
(INNER LAYER)
CONNECT THE
EXPOSED PAD TO
ANALOG GND
POWER GROUND
(INNER LAYER)
CONNECT GND AND PGND TO THE
CONTROLLER AT ONE POINT
ONLY AS SHOWN
Figure 9. PC Board Layout Example
34 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
This is essential for high-power MOSFETs that
require low-impedance gate drivers to avoid shoot-
through currents.
ground planes: input/output ground, where all the
high-power components go; the power ground
plane, where the PGND pin, V
bypass capacitor,
DD
and driver IC ground connection go; and the con-
7) When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
troller’s analog ground plane, where sensitive ana-
log components, the master’s GND pin, and the V
CC
bypass capacitor go. The controller’s analog ground
plane (GND) must meet the power ground plane
(PGND) only at a single point directly beneath the
IC. The power ground plane should connect to the
high-power output ground with a short, thick metal
trace from PGND to the source of the low-side
MOSFETs (the middle of the star ground).
Layout Procedure
1) Place the power components first, with ground termi-
5) Connect the output power planes (V
and sys-
CORE
nals adjacent (low-side MOSFET source, C , C
,
IN
OUT
tem ground planes) directly to the output-filter-
capacitor positive and negative terminals with
multiple vias. Place the entire DC-DC converter cir-
cuit as close to the CPU as is practical.
and D1 anode). If possible, make all these connec-
tions on the top layer with wide, copper-filled areas.
2) Mount the driver IC adjacent to the low-side
MOSFETs. The DL gate traces must be short and
wide (50mils to 100mils wide if the MOSFET is 1in
from the driver IC).
3) Group the gate-drive components (BST diodes and
capacitors, V
driver IC.
bypass capacitor) together near the
DD
4) Make the DC-DC controller ground connections as
shown in the Standard Application Circuits. This dia-
gram can be viewed as having three separate
______________________________________________________________________________________ 35
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Chip Information
Pin Configuration
TRANSISTOR COUNT: 9011
PROCESS: BiCMOS
TOP VIEW
40 39 38 37 36 35 34 33 32 31
D2
D3
1
2
CRSP
CRSN
VPS
30
29
28
27
26
25
24
D4
3
N.C.
4
FBS
SKIP
5
DRSKP
PWM4
PWM3
MAX8707
SHDN
SUS
6
7
8
SUSV
ILIM(AVE)
OFS
23 PWM2
22 PWM1
9
10
21
V
CC
11 12 13 14 15 16 17 18 19 20
THIN QFN
6mm x 6mm
36 ______________________________________________________________________________________
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
1
E
21-0141
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
2
E
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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