SY100E142JC [MICREL]

9-BIT SHIFT REGISTER; 9位移位寄存器


型号：	SY100E142JC
厂家：	MICREL SEMICONDUCTOR
描述：	9-BIT SHIFT REGISTER 9位移位寄存器移位寄存器
文件：	总4页 (文件大小：75K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

9-BIT SHIFT

SY10E142

SY100E142

FEATURES

DESCRIPTION

■ 700MHz min. shift frequency

■ Extended 100E VEE range of –4.2V to –5.5V

■ 9 bits wide for byte-parity applications

■ Asynchronous Master Reset

■ Dual clocks

The SY10/100E142 are high-speed 9-bit shift registers

designed for use in new, high-performance ECL systems.

The E142 can accept serial or parallel data to be shifted out

in one direction as both serial and parallel outputs. The

nine inputs, D0-D8, accept parallel input data, while S-IN

accepts serial input data.

The SEL (Select) control pin serves to determine the

modeofoperation, eitherSHIFTorLOAD. Theshiftdirection

is from bit 0 to bit 8. The input data has to meet the set-up

time before being clocked into the nine input registers on

the rising edge of CLK1 or CLK2. Shifting is also performed

on the rising edge of either CLK1 or CLK2. The MR (Master

Reset) control signal asynchronously resets all nine

registers to a logic LOW when a logic HIGH is applied to

MR.

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E142

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

The E142 is designed for applications such as diagnostic

scan registers, parallel-to-serial conversions and is also

suitable for byte-wide parity.

S-IN

D Q

PIN CONFIGURATION

25 24 23 22 21 20 19

CLK

VCC

PLCC

TOP VIEW

J28-1

VEE

S-IN

VCCO

10 11

PIN NAMES

D Q

D0-D8

S-IN

Function

Parallel Data Inputs

Serial Data Input

Mode Select Input

Clock Inputs

SEL

CLK1, CLK2

SEL

Master Reset

CLK1

CLK2

Q0-Q8

VCCO

Data Outputs

VCC to Output

Rev.: C

Amendment: /1

Issue Date: February, 1998

SY10E142

SY100E142

Micrel

TRUTH TABLE

SEL

MODE

LOAD

SHIFT

DC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

IIH

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

Input HIGH Current

—

150

—

150

—

150

µA

—

IEE

Power Supply Current

10E

100E

—

120 145

—

120

145

—

120

138

145

165

AC ELECTRICAL CHARACTERISTICS

VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND

TA = 0°C

TA = +25°C

TA = +85°C

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Condition

fSHIFT

Max. Shift Frequency

700 900

—

700 900

—

700 900

—

MHz

—

tPLH

tPHL

Propagation Delay to Output

CLK

600 800 1000 600 800 1000 600 800 1000

Set-up Time

SEL

—

50 –100

300 150

—

50 –100

300 150

—

50 –100

300 150

—

Hold Time

SEL

300 100

75 –150

—

300 100

75 –150

—

300 100

75 –150

—

tRR

tPW

Reset Recovery Time

900 700

—

900 700

—

900 700

—

Minimum Pulse Width

CLK, MR

400

—

400

—

400

—

tskew

Within-Device Skew

—

Rise/Fall Time

20% to 80%

300 525 800 300 525

800 300 525

800

—

NOTE:

1. Within-device skew is defined as identical transitions on similar paths through a device.

PRODUCT ORDERING CODE

Ordering

Code

Package

Type

Operating

Range

SY10E142JC

J28-1

Commercial

SY10E142JCTR

SY100E142JC

SY100E142JCTR

SY10E142

SY100E142

Micrel

28 LEAD PLCC (J28-1)

Rev. 03

SY10E142

SY100E142

Micrel

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.

SY100E142JC [MICREL]

相关型号：

SY100E142JCTR

SY100E142JZ

SY100E142JZ

SY100E142JZTR

SY100E143

SY100E143JC

SY100E143JCTR

SY100E143JZ

SY100E143JZTR

SY100E150

SY100E150JC

SY100E150JCTR