SY100S331FC [MICREL]
TRIPLE D FLIP-FLOP; 三重D触发器
| 型号： | SY100S331FC |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | TRIPLE D FLIP-FLOP |
| 文件： | 总7页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRIPLE D
FLIP-FLOP
SY100S331
FEATURES
DESCRIPTION
The SY100S331 offers three D-type, edge-triggered
master/slave flip-flops with true and complement outputs,
designed for use in high-performance ECL systems. Each
flip-flop is controlled by a common clock (CPc), as well as
its own clock pulse (CPn). The resultant clock signal
controlling the flip-flop is the logical OR operation of these
two clock signals. Data enters the master when both CPc
and CPn are LOW and enters the slave on the rising edge
of either CPc or CPn (or both).
■ Max. toggle frequency of 800MHz
■ Differential outputs
■ IEE min. of –80mA
■ Industry standard 100K ECL levels
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved
noise immunity
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SDn) and Direct Clear (CDn) signals. The MR,
MS, SDn and DCn signals override the clock signals. The
inputs on this device have 75KΩ pull-down resistors.
■ Internal 75KΩ input pull-down resistors
■ 150% faster than Fairchild
■ 40% lower power than Fairchild
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
PIN CONFIGURATIONS
BLOCK DIAGRAM
11 10 9
8 7 6 5
MS
12
13
14
15
16
17
18
4
3
Q
Q
1
1
CPC
CD
CP
2
VEE
2
V
V
V
CCA
CD
SD
CD
SD
CD
SD
Top View
PLCC
J28-1
C
VEES
1
CC
Q
Q
2
2
CP
D
CP
2
2
2
1
MR
28
27
26
CC
SD
1
1
Q
Q
2
2
D
D
SD
CD
19 20 21 22 23 24 25
Q
Q
1
1
CP
D
CP
1
1
1
0
D
24 23 22 21 20 19
18
CP
1
1
1
2
3
4
5
6
SD
CD
CP
0
SD
CD
CD
17
16
15
14
13
0
Top View
Flatpack
F24-1
SD
2
2
0
Q
Q
0
0
CP
D
CD
D
0
CP
0
0
0
CP2
Q
Q
0
0
D
D
2
SD
7
8
9 10 11 12
MS MR
Rev.: G
Amendment:/0
Issue Date: July, 1999
1
SY100S331
Micrel
PIN NAMES
Pin
CP0 – CP2
CPc
Function
Individual Clock Inputs
Common Clock Input
Data Inputs
D0 – D2
CD0 – CD2
SDn
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
MR
MS
Q0 – Q2
Q0 – Q2
VEES
Data Outputs
Complementary Data Outputs
VEE Substrate
VCCA
VCCO for ECL Outputs
TRUTH TABLES
Synchronous Operation(1)
Asynchronous Operation(1)
Inputs
Outputs
Inputs
Outputs
MS
MR
MS
MR
Dn
CPn
u
CPc
L
SDn
L
DCn
Qn
L
Dn
X
CPn
X
CPc
X
SDn
DCn
Qn (t+1)
H
L
L
H
H
H
L
L
L
L
L
L
L
L
L
X
X
X
H
u
L
L
H
L
L
u
L
L
X
X
X
H
U
H
L
u
L
H
NOTE:
1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U =
Undefined, t = Time before CP Positive Transition, t+1 = Time after CP
Positive Transition, u = Low-to-High Transition
X
X
L
L
L
Qn (t)
Qn (t)
Qn (t)
H
X
X
L
X
H
L
NOTE:
1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U =
Undefined, t = Time before CP Positive Transition, t+1 = Time after CP
Positive Transition, u = Low-to-High Transition
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol
IIH
Parameter
Min.
—
Typ.
—
Max.
200
Unit
µA
Condition
Input HIGH Current, All Inputs
Power Supply Current
VIN = VIH (Max.)
Inputs Open
IEE
–80
–65
–35
mA
2
SY100S331
Micrel
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Toggle Frequency
Min.
Max.
—
Min.
800
300
Max.
—
Min.
800
300
Max.
—
Unit
MHz
ps
Condition
fmax
800
300
tPLH
tPHL
Propagation Delay
CPc to Output
800
800
800
tPLH
tPHL
Propagation Delay
CPn to Output
300
300
300
300
800
900
300
300
300
300
800
900
300
300
300
300
800
900
ps
ps
ps
ps
ps
tPLH
tPHL
Propagation Delay
CDn, SDn to Output
tPLH
tPHL
Propagation Delay
MS, MR to Output
1000
900
1000
900
1000
900
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
tS
Set-up Time
Dn
400
500
800
—
—
—
400
500
800
—
—
—
400
500
800
—
—
—
CDn, SDn (Release Time)
MS, MR (Release Time)
tH
Hold Time Dn
300
800
—
—
300
800
—
—
300
800
—
—
ps
ps
tpw (H)
Pulse Width HIGH
CPn, CPc, DCn
SDn, MR, MS
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°C TA = +25°C
TA = +85°C
Symbol
Parameter
Toggle Frequency
Min.
Max.
—
Min.
800
300
Max.
—
Min.
800
300
Max.
—
Unit
MHz
ps
Condition
fmax
800
300
tPLH
tPHL
Propagation Delay
CPc to Output
700
700
700
tPLH
tPHL
Propagation Delay
CPn to Output
300
300
300
300
700
800
900
900
300
300
300
300
700
800
900
900
300
300
300
300
700
800
900
900
ps
ps
ps
ps
ps
tPLH
tPHL
Propagation Delay
CDn, SDn to Output
tPLH
tPHL
Propagation Delay
MS, MR to Output
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
tS
Set-up Time
Dn
400
500
800
—
—
—
400
500
800
—
—
—
400
500
800
—
—
—
CDn, SDn (Release Time)
MS, MR (Release Time)
tH
Hold Time Dn
300
800
—
—
300
800
—
—
300
800
—
—
ps
ps
tpw (H)
Pulse Width HIGH
CPn, CPc, DCn
SDn, MR, MS
3
SY100S331
Micrel
TIMING DIAGRAMS
DATA
0.7 ± 0.1 ns
0.7 ± 0.1 ns
–0.95V
80%
50%
20%
CLOCK
–1.69V
tpw (H)
1/fmax
t
t
PHL
PLH
tPLH
OUTPUT
OUTPUT
50%
t
PHL
t
THL
t
TLH
Propagation Delay (Clock) and Transition Times
NOTE:
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
0.7 ± 0.1 ns
, CD
0.7 ± 0.1 ns
+1.05V
80%
50%
20%
SD
n
n
MS, MR
+0.31V
t
S
(RELEASE TIME)
t
pw (H)
CLOCK
50%
t
t
PHL
PLH
tPLH
OUTPUT
OUTPUT
50%
t
PHL
80%
50%
20%
Propagation Delay (Sets and Resets)
4
SY100S331
Micrel
TIMING DIAGRAMS
+1.05V
DATA
50%
+0.31V
+1.05V
t
h
t
S
CLOCK
50%
+0.31V
Data Setup and Hold Time
NOTES:
ts is the minimum time before the transition of the clock that information must be present at the data input.
th is the minimum time after the transition of the clock that information must remain unchanged at the data input.
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY100S331FC
SY100S331JC
SY100S331JCTR
F24-1
J28-1
J28-1
Commercial
Commercial
Commercial
5
SY100S331
Micrel
24 LEAD CERPACK (F24-1)
Rev. 03
6
SY100S331
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
7
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