HV7350K6-G [MICROCHIP]
8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser;
| 型号： | HV7350K6-G |
| 厂家： | 
MICROCHIP |
| 描述： | 8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser |
| 文件： | 总16页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV7350
8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser
Features
General Description
• HVCMOS® Technology for High Performance
• High-density Integrated Ultrasound Transmitter
• 0V to ±60V Output Voltage
The HV7350 is an 8-channel monolithic high-voltage
high-speed pulse generator with built-in fast return to
zero-damping FETs. This high-voltage and high-speed
integrated circuit is designed for portable medical
ultrasound imaging system.
• ±1A Source and Sink Current in Pulse Mode
• ±1A Source and Sink Current in Return-to-Zero
(RTZ) Mode
The HV7350 consists of a controller logic interface
circuit, level translators, MOSFET gate drives, and
high-current power P-channel and N-channel
MOSFETs as the output stage for each channel.
• Up to 20 MHz Operating Frequency
• Matched Delay Times
• Optional Clock Realignment
The output peak currents of each channel are
guaranteed to be over ±1A with up to ±60V pulse
swings as well as Return-to-Zero mode. The gate
drivers for the output MOSFETs are powered by built-in
linear 5V regulators referenced to VPP and VNN. This
direct coupling topology of the gate drivers not only
saves four floating voltage supplies or AC coupling
capacitors per channel but also makes the PCB layout
smaller and easier.
• 3.3V CMOS Logic Interface and Reference
• +3.3V Low-voltage Supply for VDD
• Built-in Linear Regulators for Floating Gate
Drivers
• Built-in Output Drain Diodes and Bleed Resistors
Applications
• Portable Medical Ultrasound Imaging
• Piezoelectric Transducer Drivers
• Pulse Waveform Generator
An input clock pin is available to realign all the logic
input control lines to a master clock. Precise logic
timing is always essential in any ultrasound systems.
Package Type
56-lead (8 X 8) QFN
(Top view)
56
1
See Table 2-1 for pin information.
2016 Microchip Technology Inc.
DS20005627A-page 1
HV7350
Typical Application Circuit
+3.3V
0.1µF
+3.3V
+10 to +60V
1.0µF
1.0µF
1.0µF
1.0µF
VLL
VDD
CPOS
LRP
CPF VPP
LRP
1 of 8 Channels
REN
OEN
PIN1
GND
GND
VPF
RGND
+5.0V
P-Driver
+5.0V
DMP
-5.0V
3.3V Logic
NIN1
VPF
VNF
TX1
HVOUT
1
Logic
&
Level
Translator
PIN8
NIN8
CLK
X1
Rb
N-Driver
RGND
-5.0V
VNF
GND
GND
RGND
1.0µF
LRN
LRN
GND
CNEG
SUB
DAP
GND
CNF
VNN
1.0µF
1.0µF
-10 to -60V
DS20005627A-page 2
2016 Microchip Technology Inc.
HV7350
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
GND and Substrate Voltage, VSUB ........................................................................................................................... 0V
Positive Logic Supply, VLL .......................................................................................................................–0.5V to +5.5V
Positive Logic and Level Translator Supply, VDD ....................................................................................–0.5V to +5.5V
Positive Level Translator Decoupling Pin, CPOS to GND ........................................................................–0.5V to +5.5V
Negative Level Translator Decoupling Pin, CNEG to GND ......................................................................+0.5V to –5.5V
Positive Floating Gate Driver Decoupling Pin, VPP–CPF..........................................................................–0.5V to +5.5V
Floating Gate Driver Decoupling Pin, CNF–VNN.......................................................................................–0.5V to +5.5V
Differential High-voltage Supply, VPP–VNN ........................................................................................................... +130V
High-voltage Positive Supply, VPP ............................................................................................................–0.5V to +65V
High-voltage Negative Supply, VNN .........................................................................................................+0.5V to –65V
All Logic Input CLK, PINX, NINX, OEN and REN Voltages ......................................................................–0.5V to +5.5V
Operating Junction Temperature, TJ .....................................................................................................–40°C to +125°C
Storage Temperature, TS ......................................................................................................................–65°C to +150°C
ESD Rating (Note 1).................................................................................................................................ESD Sensitive
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: Devices are ESD sensitive. Handling precautions are recommended.
OPERATING SUPPLY VOLTAGES AND CURRENT
(EIGHT ACTIVE CHANNELS)
Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V, VNN = –60V, VCLK = +3.3V, TA = 25°C unless
otherwise indicated.
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
VDD Voltage Supply
VDD
UVLODD
VLL
2.97
2.3
2.5
1.3
+10
–60
—
3.3
2.6
3.3
1.55
—
5.2
2.8
5
V
V
V
V
V
V
V
DD UVLO
Logic Voltage Reference
VLL UVLO
UVLOLL
VPP
1.7
+60
–10
—
Positive High-voltage Supply
Negative High-voltage Supply
VLL Current
VNN
—
ILLQ
8
V
DD Current
PP Current
IDDQ
—
1
—
μA
μA
OEN = REN = 0
V
IPPQ
—
5
10
VNN Current
LL Current
INNQ
—
5
10
V
ILLEN
IDDEN
IPPEN
INNEN
IDDCW
IPPCW
INNCW
ILL,CLK
—
13
480
220
300
2.3
80
80
33
20
VDD Current
VPP Current
—
700
350
400
—
OEN = REN = 1
5 ms after f = 0 MHz
—
V
NN Current
DD Current
—
V
—
f = 5 MHz, continuous, no loads, for
calculation reference only
VPP Current
NN Current
—
—
mA
V
—
—
VLL Current
—
—
μA
fCLK = 10 MHz, PIN = NIN = 0
2016 Microchip Technology Inc.
DS20005627A-page 3
HV7350
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V,VNN = –60V, VCLK = +3.3V, TA = 25°C unless
otherwise indicated.
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
PULSER P-CHANNEL MOSFET
Output Saturation Current
Channel Resistance
IOUT
RON
1
1.5
—
—
A
—
13.2
Ω
ISD = 100 mA
PULSER P-CHANNEL MOSFET
Output Saturation Current
Channel Resistance
IOUT
RON
1
1.5
8
—
—
A
—
Ω
ISD = 100 mA
ISD = 100 mA
ISD = 100 mA
DAMPING P-CHANNEL MOSFET
Output Saturation Current
Channel Resistance
IOUT
RON
1
1.5
13
—
—
A
—
Ω
DAMPING N-CHANNEL MOSFET
Output Saturation Current
Channel Resistance
IOUT
RON
1
1.5
9
—
—
A
—
Ω
LOGIC INPUT
0.7 • VLL
0.8 • VLL
—
—
—
—
—
—
—
VLL = 2.5V to 3.3V
VLL = 5V
Input Logic High Voltage
Input Logic Low Voltage
VIH
VIL
VLL
V
V
0.3 • VLL
VLL = 2.5V to 3.3V
0
0.2 • VLL
VLL = 5V
Input Logic High Current
IIH
IIL
—
–10
—
10
—
5
μA
μA
pF
Input Logic Low Current
Input Logic Capacitance
CIN
MOSFET DRAIN BLEED RESISTOR
Output Bleed Resistance
RB1~8
12
—
17
—
25
50
kΩ
Bleed Resistors Power Limit
PRB1~8
mW
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V, VNN = –60V, VCLK = +3.3V, TA = 25°C unless
otherwise indicated.
Parameter
Output Rise Time
Sym.
Min. Typ. Max.
Unit Conditions
tr
tf
—
—
—
—
—
—
—
—
—
—
30
30
300
2.8
12
12
12
12
9
—
—
ns
ns
μs
μs
330 pF//2.5 kΩ load
10%–90%
Output Fall Time
Enable Time
tEN
tDIS
td1
500
10
—
Cap value (See Typical Application
Circuit.), OEN = REN
Disable Time
Delay Time on PINX Rise
Delay Time on NINX Rise
Delay Time on Damping Rise
Delay Time on Damping Fall
Delay Time on CLK Rise
Delay Time Matching
td2
—
1 Ω resistor load, D% < 1%
(See Timing Waveforms.)
50% inputs to 50% TX current
td3
—
ns
td4
—
tdc
—
∆tDELAY
±3
—
ns
ps
ns
P to N, channel to channel
VPP/VNN = +/–25V, input tr 50% to
HVOUT tr or tf 50%, with 330 pF//2.5 kΩ
load
Delay Jitter on Rise or Fall
RTZ FETs Drain Diode trr
tJ
—
—
30
25
—
—
trr
IF = 1A, IR = 1A, RL = 10Ω
DS20005627A-page 4
2016 Microchip Technology Inc.
HV7350
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V, VNN = –60V, VCLK = +3.3V, TA = 25°C unless
otherwise indicated.
Parameter
Sym.
Min. Typ. Max.
Unit Conditions
Retiming Clock Frequency
fCLK
10
—
220
0.5
—
5
MHz
Retiming Clock Rise and Fall
Times
trc, tfc
ns
Set-up Time, PIN/NIN to CLK
Hold time, CLK to PIN/NIN
Clock Time Low
tSU
tH
2
1
—
—
—
—
ns
ns
ns
tCLK_LO
tCLK_HI
tCLK_REC
tCLK_RLS
fOUT
2
—
100
100
—
CLK input must have at least one pulse
Clock Time High
2
—
ns
ns
before PIN and NIN inputs are not zero.
Be sure to return inputs to zero before
stopping clock.
Clock Recognition Time
Clock Release Time
—
150
—
—
—
2
300
—
800
20
ns
Output Frequency Range
Second Harmonic Distortion
Output Capacitance
MHz
dB
100Ω resistor load
HD2
–40
50
—
COSS
—
pF
VDS = 25V, f = 1 MHz of TX pin total
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
TEMPERATURE RANGE
Operating Junction Temperature
Storage Temperature
TJ
–40
–65
—
—
+125
+150
°C
°C
TS
PACKAGE THERMAL RESISTANCE
56-lead (8 X 8) QFN
JA
—
21
—
°C/W
LOGIC CONTROL TABLE
LOGIC INPUTS
TXN, OUTPUT
MODE
OEN
CLK
PINX
NINX
VPP
VNN
RGND
1
VLL
VLL
VLL
VLL
0
1
0
1
0
1
0
0
0
1
1
0
0
1
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
Asynchronous Mode
Output Change on
PIN/NIN
1
1
OFF
OFF
OFF
ON
1
OFF
OFF
OFF
ON
Synchronous Mode
Output Change at Retim-
ing Clock (CLK) Rising
Edge, registered by
PIN/NIN
1
1
1
OFF
OFF
OFF
1
0
1
1
OFF
OFF
OFF
OFF
OFF
OFF
Disabled
X
X
X
2016 Microchip Technology Inc.
DS20005627A-page 5
HV7350
Timing Waveforms
CLK
CLK
PINn
(NINn = 0)
NINn
(PINn = 0)
50%
50%
td1
td4
td3
IOUT
td2
50%
ITXn
0
0
ITXn
50%
Asynchronous Mode
IOUT
CLK
CLK
PINn
(NINn = 0)
NINn
(PINn = 0)
tdc
tdc
tdc
tdc
IOUT
50%
ITXn
0
ITXn
0
50%
Synchronous Mode
IOUT
DS20005627A-page 6
2016 Microchip Technology Inc.
HV7350
2.0
PAD DESCRIPTION
Table 2-1 details the description of pads in HV7350.
Refer to Package Type for the location of pins.
TABLE 2-1:
Pin
PAD FUNCTION TABLE
Pin
Description
Number Name
Input logic control of high-voltage output P-FET for Channel 2; High = on; Low = off
(See Logic Control Table.)
1
2
3
4
5
PIN2
NIN2
PIN3
NIN3
PIN4
Input logic control of high-voltage output N-FET for Channel 2; High = on; Low = off
(See Logic Control Table.)
Input logic control of high-voltage output P-FET for Channel 3; High = on; Low = off
(See Logic Control Table.)
Input logic control of high-voltage output N-FET for Channel 3; High = on; Low = off
(See Logic Control Table.)
Input logic control of high-voltage output P-FET for Channel 4; High = on; Low = off
(See Logic Control Table.)
Input logic control of high-voltage output N-FET for Channel 4; High = on; Low = off
(See Logic Control Table.)
6
7
NIN4
OEN
Output enable; High = on; Low = off (See Logic Control Table.)
Built-in positive and negative 5V voltage regulators enable; High = on; Low = off
If REN = 0, four isolated 5V power supplies may provide, as external supplies, for the VPP to CPF, CNF to
VNN, CPOS to GND and GND to CNEG pins. Note that between VPP to CPF and CNF to VNN, two must be
floating supplies. (See Logic Control Table.)
8
REN
Input logic control of high-voltage output P-FET for Channel 5; High = on; Low = off
(See Logic Control Table.)
9
PIN5
NIN5
PIN6
NIN6
PIN7
NIN7
PIN8
NIN8
Input logic control of high-voltage output N-FET for Channel 5; High = on; Low = off
(See Logic Control Table.)
10
11
12
13
14
15
16
Input logic control of high-voltage output P-FET for Channel 6; High = on; Low = off
(See Logic Control Table.)
Input logic control of high-voltage output N-FET for Channel 6; High = on; Low = off
(See Logic Control Table.)
Input logic control of high-voltage output P-FET for Channel 7; High = on; Low = off
(See Logic Control Table.)
Input logic control of high-voltage output N-FET for Channel 7; High = on; Low = off
(See Logic Control Table.)
Input logic control of high-voltage output P-FET for Channel 8; High = on; Low = off
(See Logic Control Table.)
Input logic control of high-voltage output N-FET for Channel 8; High = on; Low = off
(See Logic Control Table.)
17
18
19
20
21
22
23
VLL
GND
VDD
VPP
VPP
VPP
CPF
Logic supply voltage and reference input (+3.3V)
Logic and circuit return ground (0V)
Positive voltage power supply (+3.3V)
Positive high-voltage power supply (+10V to +60V)
Built-in linear voltage VPF regulator output decoupling capacitor pin, 1 uF from VPP to CPF for every CPF pin
Built-in linear voltage VNF regulator output decoupling capacitor pin, 1 uF from CNF to VNN for every CNF
pin
24
CNF
25
26
27
28
29
VNN
VNN
VNN
TX8
Negative high-voltage power supply (–10V to –60V)
TX pulser Channel 8 output
RGND Damping ground and bleed resistors common return ground
2016 Microchip Technology Inc.
DS20005627A-page 7
HV7350
TABLE 2-1:
Pin
PAD FUNCTION TABLE (CONTINUED)
Pin
Description
Number Name
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
TX7
RGND Damping ground and bleed resistors common return ground
TX6 TX pulser Channel 6 output
RGND Damping ground and bleed resistors common return ground
TX5 TX pulser Channel 5 output
TX pulser Channel 7 output
CNEG Built-in linear voltage –5V regulator output decoupling capacitor pin, 1 uF from CNEG to GND
CPOS Built-in linear voltage +5V regulator output decoupling capacitor pin, 1 uF from CPOS to GND
TX4
RGND Damping ground and bleed resistors common return ground
TX3 TX pulser Channel 3 output
RGND Damping ground and bleed resistors common return ground
TX2 TX pulser Channel 2 output
RGND Damping ground and bleed resistors common return ground
TX pulser Channel 4 output
TX1
VNN
VNN
VNN
TX pulser Channel 1 output
Negative high-voltage power supply (–10V to –60V)
Built-in linear voltage VNF regulator output decoupling capacitor pin, 1 uF from CNF to VNN for every CNF
pin
47
CNF
48
49
50
51
52
53
54
CPF
VPP
VPP
VPP
VDD
GND
CLK
Built-in linear voltage VPF regulator output decoupling capacitor pin, 1 uF from VPP to CPF for every CPF pin
Positive high-voltage power supply (+10V to +60V)
Positive voltage power supply (+3.3V)
Logic and circuit return ground (0V)
Retiming register clock input. Connect to VLL to disable the retiming function.
Input logic control of high-voltage output P-FET for Channel 1; High = on; Low = off
(See Logic Control Table.)
55
56
PIN1
NIN1
Input logic control of high-voltage output N-FET for Channel 1; High = on; Low = off
(See Logic Control Table.)
VSUB
(Thermal Pad)
Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be con-
nected to GND (0V) externally.
DS20005627A-page 8
2016 Microchip Technology Inc.
HV7350
3.0
FUNCTIONAL DESCRIPTION
Follow the steps below to power up and power down
the HV7350:
POWER-UP AND POWER-DOWN SEQUENCE (Note 1)
Power-Up
Power-Down
Description
Step
Description
VLL with logic signal low
Step
1
2
3
4
5
1
2
3
4
5
All logic signals go to low
VDD
VPP and VNN
REN = 1 (external supplies on)
VPP and VNN
REN = 0 (external supplies off)
VDD
VLL
Logic control signals active
Note 1: Powering up or down in any arbitrary sequence will not damage the device. The power-up sequence and
power-down sequence are only recommended to minimize possible inrush current.
OUTPUT CURRENT AND R (Note 1, Note 4)
ON
2
3
ISC
RonP
RonN
IDMP
1.5A
RonDP
RonDN
1.5A
13Ω
6.5Ω
13Ω
8Ω
Note 1:
VPP/VNN = +/-60V; VDD = +3.3V; REN = 1
2: ISC is current into 1Ω to GND.
3: IDMP is current from +/–30V connected to TX pin.
4: Maximum pulse width for current measurement on TX pin is 20 ns.
2016 Microchip Technology Inc.
DS20005627A-page 9
HV7350
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
56-lead QFN
Example
e3
e3
XXXXXX
HVV77335500KK66
YYWWNNN
1662211998877
Legend: XX...X Product Code or Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator ( )
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
DS20005627A-page 10
2016 Microchip Technology Inc.
HV7350
56-Lead QFN Package Outline (K6)
8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch
Note 1
D2
D
(Index Area
56
56
D/2 x E/2)
1
1
Note 1
(Index Area
D/2 x E/2)
e
b
E
E2
View B
Bottom View
Top View
Note 3
θ
A3
A
Seating
Plane
L
L1
Note 2
A1
Side View
View B
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Notes:
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a printed indicator.
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Symbol
A
A1
A3
b
D
7.85*
8.00
D2
2.75
5.70
E
7.85*
8.00
E2
2.75
5.70
e
L
L1
0.00
-
ș
0O
-
MIN
NOM
MAX
0.80
0.90
1.00
0.00
0.02
0.05
0.18
0.25
0.30
0.30
0.40
0.50
Dimension
(mm)
0.20
REF
0.50
BSC
8.15* 6.70† 8.15* 6.70†
0.15
14O
JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006.
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Drawings are not to scale.
2016 Microchip Technology Inc.
DS20005627A-page 11
HV7350
NOTES:
DS20005627A-page 12
2016 Microchip Technology Inc.
HV7350
APPENDIX A: REVISION HISTORY
Revision A (October 2016)
• Converted Supertex Doc# DSFP-HV7350 to
Microchip DS20005627A
• Changed the packaging quantity of 56-lead QFN
M937 from 2000/Reel to 3000/Reel
• Made minor text changes throughout the docu-
ment
2016 Microchip Technology Inc.
DS20005627A-page 13
HV7350
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
XX
PART NO.
Device
-
X
-
X
a) HV7350K6-G:
8-Channel High-Speed ±60V ±1A
Ultrasound RTZ Pulser,
56-lead VQFN, 250/Tray
Package
Options
Environmental
Media Type
b) HV7350K6-G-M937: 8-Channel High-Speed ±60V ±1A
Ultrasound RTZ Pulser,
56-lead VQFN, 3000/Reel
Device:
HV7350
=
8-Channel High-Speed ±60V ±1A
Ultrasound RTZ Pulser
Package:
K6
G
=
=
56-lead VQFN
Environmental:
Media Type:
Lead (Pb)-free/RoHS-compliant Package
(blank)
M937
=
=
250/Tray for a K6 Package
3000/Reel for a K6 Package
DS20005627A-page 14
2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
CERTIFIEDꢀBYꢀDNVꢀ
© 2016, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0997-7
== ISO/TSꢀ16949ꢀ==ꢀ
2016 Microchip Technology Inc.
DS20005627A-page 15
Worldwide Sales and Service
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Taiwan - Kaohsiung
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Taiwan - Taipei
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06/23/16
DS20005627A-page 16
2016 Microchip Technology Inc.
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