MCP39F511-E/MQ_技术文档

MCP39F511

Power-Monitoring IC with Calculation and Energy Accumulation

Features

Description

• Power Monitoring Accuracy Capable of 0.1%

Error Across 4000:1 Dynamic Range

The MCP39F511 is a highly integrated, complete

single-phase power-monitoring IC designed for

real-time measurement of input power for

AC/DC power supplies, power distribution units,

consumer and industrial applications. It includes

dual-channel Delta-Sigma ADCs, a 16-bit calculation

engine, EEPROM and a flexible 2-wire interface. An

integrated low-drift voltage reference with 10 ppm/°C in

addition to 94.5 dB of SINAD performance on each

measurement channel allows for better than 0.1%

accurate designs across a 4000:1 dynamic range.

• Built-In Calculations on Fast 16-Bit Processing

Core

- Active, Reactive, Apparent Power

- True RMS Current, RMS Voltage

- Line Frequency, Power Factor

• 64-bit Wide Import and Export Active Energy

Accumulation Registers

• 64-bit Four Quadrant Reactive Energy

Accumulation Registers

Package Types

• Signed Active and Reactive Power Outputs

MCP39F511

5x5 QFN*

• Dedicated Zero Crossing Detection (ZCD) Pin

Output with Less than 200 µs Latency

• Dedicated PWM Output Pin with Programmable

Frequency and Duty Cycle

• Automatic Event Pin Control through Fast Voltage

Surge Detection Less than 5 ms Delay

• Two Wire Serial Protocol with Selectable Baud

Rate Up to 115.2 kbps using Universal

Asynchronous Receiver/Transmitter (UART)

28 27 26 25 24 23 22

1

2

3

4

A_GND

EVENT1

21

NC

20 AN_IN

• Four Independent Registers for Minimum and

Maximum Output Quantity Tracking

19

18

V1+

V1-

EP

29

UART_RX

COMMON_A

• Fast Calibration Routines and Simplified

Command Protocol

5

6

7

17 I1-

I1+

16

15

OSCI

• 512 Bytes User-Accessible EEPROM through

Page Read/Write Commands

EVENT2

OSCO

• Low-Drift Internal Voltage Reference, 10 ppm/°C

Typical

8

9

10 11 12

13 14

• 28-lead 5x5 QFN Package

• Extended Temperature Range -40°C to +125°C

Applications

• Power Monitoring for Home Automation

• Industrial Lighting Power Monitoring

*Includes Exposed Thermal Pad (EP);

see Table 3-1.

• Real-Time Measurement of Input Power for

AC/DC Supplies

• Intelligent Power Distribution Units

 2015 Microchip Technology Inc.

DS20005393B-page 1

MCP39F511

Functional Block Diagram

A

AV

D

DV

DD

GND

DD

GND

Timing

OSCI

Generation

OSCO

Internal

Oscillator

UART_TX

UART_RX

UART

Serial

Interface

24-bit Delta-Sigma

Multi-level

Modulator ADC

I1+

I1-

+

-

PGA

16-BIT

PWM

CORE

FLASH

24-bit Delta-Sigma

Multi-level

Modulator ADC

V1+

V1-

EVENT1

EVENT2

+

-

PGA

Calculation

Engine

(CE)

Digital Outputs

ZCD

10-bit SAR

ADC

AN_IN

DS20005393B-page 2

 2015 Microchip Technology Inc.

MCP39F511

MCP39F511 Typical Application – Single Phase, Two-Wire Application Schematic

+3.3V

10 

0.1 µF

1 µF

LOAD

0.1 µF

AV

DV

RESET

DD

1 k

REFIN/OUT+

I1+

0.1 µF

+

-

33 nF

2 m

UART_TX

1 k

33 nF

1 k

to MCU UART

I1-

UART_RX

V1-

33 nF

MCP39F511

499 k

(OPTIONAL)

499 k

V1+

1 k

33 nF

NC

EVENT1

N.C.

Leave Floating

NC

EVENT2

DR

Connect on PCB

COMMON

A,B

ZCD

+3.3V

MCP9700A

AN_IN

PWM

OSCO

D

4 MHz

A

GND

OSCI

GND

22 pF

(OPTIONAL)

+3.3V

0.47µF

470

MCP1754

0.01 µF

470 µF

N

L

A

GND

D

GND

Note 1: The MCP39F511 demonstration board uses a switching power supply, however a low-cost

capacitive-based supply, as shown here, is sufficient for many applications.

2: The external sensing components shown here, a 2 mΩ shunt, two 499 kΩ and 1 kΩ resistors for the

1000:1 voltage divider, are specifically chosen to match the default values for the calibration registers

defined in Section 6.0 “Register Descriptions”. By choosing low-tolerance components of these

values (e.g. 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero

calibration. See Section 9.0 “MCP39F511 Calibration” for more information.

 2015 Microchip Technology Inc.

DS20005393B-page 3

MCP39F511

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operation listings of this specification is

not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

DV .................................................................. -0.3 to +4.5V

DD

AV .................................................................. -0.3 to +4.0V

DD

Digital inputs and outputs w.r.t. A

...............-0.3V to +4.0V

GND

Analog Inputs (I+,I-,V+,V-) w.r.t. A

...................-2V to +2V

GND

V

input w.r.t. A

........................ ....-0.6V to AV +0.6V

REF

GND DD

Maximum Current out of D

pin..............................300 mA

GND

Maximum Current into DV pin.................................250 mA

DD

Maximum Output Current Sunk by Digital IO................25 mA

Maximum Current Sourced by Digital IO.......................25 mA

Storage temperature .....................................-65°C to +150°C

Ambient temperature with power applied......-40°C to +125°C

Soldering temperature of leads (10 seconds) .............+300°C

ESD on the analog inputs (HBM,MM).................4.0 kV, 200V

ESD on all other pins (HBM,MM)........................4.0 kV, 200V

1.1

Specifications

ELECTRICAL CHARACTERISTICS

TABLE 1-1:

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

DV = +2.7 to +3.6V, T = -40°C to +125°C,

DD,

DD

A

MCLK = 4 MHz, PGA GAIN = 1.

Characteristic

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Power Measurement

Active Power (Note 1)

P

—

±0.1

—

%

4000:1 Dynamic Range

on Current Channel

(Note 2)

Reactive Power (Note 1)

Apparent Power (Note 1)

Current RMS (Note 1)

Voltage RMS (Note 1)

Q

S

—

±0.1

—

%

4000:1 Dynamic Range

on Current Channel

(Note 2)

4000:1 Dynamic Range

on Current Channel

(Note 2)

I_RMS

4000:1 Dynamic Range

on Current Channel

(Note 2)

V_RMS

4000:1 Dynamic Range

on Voltage Channel

(Note 2)

Power Factor (Note 1)

Line Frequency (Note 1)



—

±0.1

—

%

LF

Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4

line cycles.

2: Specification by design and characterization; not production tested.

3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or T

= 80 ms for

CAL

50 Hz line.

4: Applies to Voltage Sag and Voltage Surge events only.

5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance

Curves” for typical performance.

6:

V

= 1V = 353 mV

@ 50/60 Hz.

RMS

IN

PP

7: Variation applies to internal clock and UART only. All calculated output quantities are temperature compensated to the

performance listed in the respective specification.

8: Lower baud rates selectable only on system versions 0xFA14 and later.

DS20005393B-page 4

 2015 Microchip Technology Inc.

MCP39F511

TABLE 1-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

DV = +2.7 to +3.6V, T = -40°C to +125°C,

DD,

DD

A

MCLK = 4 MHz, PGA GAIN = 1.

Characteristic

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Calibration, Calculation and Event Detection Times

2^Nx (1/f_LINE

see

)

Auto-Calibration Time

t_CAL

—

ms

Note 3

Note 4

Minimum Time

for Voltage Surge/Sag

Detection

t_{AC_SASU}

Section 7.0

24-Bit Delta-Sigma ADC Performance

Analog Input

Absolute Voltage

V_IN

-1

—

1

+1

—

V

Analog Input

Leakage Current

A_IN

—

nA

mV

Differential Input

Voltage Range

(I1+ – I1-), -600/GAIN

(V1+ – V1-)

—

+600/GAIN

V_REF= 1.2V,

proportional to V_REF

Offset Error

V_OS

GE

Z_IN

-1

—

0.5

—

+1

—

+4

—

mV

µV/°C

%

Offset Error Drift

Gain Error

-4

Note 5

Gain Error Drift

—

1

ppm/°C

k

Differential Input

Impedance

232

142

72

38

36

33

92

—

G = 1

G = 2

G = 4

G = 8

G = 16

G = 32

Note 6

—

k

—

k

—

k

—

k

—

k

Signal-to-Noise

SINAD

94.5

dB

and Distortion Ratio

Total Harmonic Distortion

Signal-to-Noise Ratio

THD

SNR

—

92

—

-106.5

95

-103

—

dBc

dB

Note 6

Spurious Free

SFDR

111

—

dB

Dynamic Range

Crosstalk

CTALK

—

-122

-73

—

dB

AC Power

AC PSRR

AV_DDand

Supply Rejection Ratio

DV_DD= 3.3V + 0.6V_PP

,

100 Hz, 120 Hz, 1 kHz

DC Power

Supply Rejection Ratio

DC PSRR

—

-73

—

dB

AV_DDand DV_DD= 3.0 to

3.6V

Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4

line cycles.

2: Specification by design and characterization; not production tested.

3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or T

= 80 ms for

CAL

50 Hz line.

4: Applies to Voltage Sag and Voltage Surge events only.

5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance

Curves” for typical performance.

6:

V

= 1V = 353 mV

@ 50/60 Hz.

RMS

IN

PP

7: Variation applies to internal clock and UART only. All calculated output quantities are temperature compensated to the

performance listed in the respective specification.

8: Lower baud rates selectable only on system versions 0xFA14 and later.

 2015 Microchip Technology Inc.

DS20005393B-page 5

MCP39F511

TABLE 1-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

DV = +2.7 to +3.6V, T = -40°C to +125°C,

DD,

DD

A

MCLK = 4 MHz, PGA GAIN = 1.

Characteristic

DC Common

Mode Rejection Ratio

10-Bit SAR ADC Performance for Temperature Measurement

Sym.

Min.

Typ.

Max.

Units

Test Conditions

DC CMRR

—

-105

—

dB

V_CMvaries

from -1V to +1V

Resolution

N_R

V_IN

R_IN

—

D_GND- 0.3

—

10

—

bits

V

Absolute Input Voltage

D_VDD+ 0.3

2.5

Recommended

k

Impedance of

Analog Voltage Source

Integral Nonlinearity

Differential Nonlinearity

Gain Error

I_NL

—

±1

±2

±1.5

±3

LSb

sps

D_NL

G_ERR

E_OFF

±1

Offset Error

±1

f_LINE/2^N

±2

Temperature

—

Note 7

Measurement Rate

Clock and Timings

UART Baud Rate

UDB

f_MCLK

1.2 ⁽⁸⁾

-2%

—

4

115.2

+2%

15

kbps See Section 3.2 for

protocol details

Master Clock

and Crystal Frequency

MHz

Capacitive Loading

on OSCO pin

COSC2

f_{INT_OSC}

—

2

pF

%

When an external clock is

used to drive the device

Internal Oscillator

Tolerance

—

-40 to +85°C only

(Note 7)

Internal Voltage Reference

Internal Voltage

Reference Tolerance

V_REF

-2%

—

1.2

10

+2%

—

V

Temperature Coefficient

TCV_REF

ppm/°C T_A= -40°C to +85°C,

V_REFEXT= 0

Output Impedance

Current, V_REF

ZOUTV_REF

AI_DDV_REF

—

2

—

k

40

µA

Voltage Reference Input

Input Capacitance

—

10

pF

V

A

+ 1.1V

A

+ 1.3V

GND

Absolute Voltage on

V_REF+Pin

V_REF+

GND

Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4

line cycles.

2: Specification by design and characterization; not production tested.

3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or T

= 80 ms for

CAL

50 Hz line.

4: Applies to Voltage Sag and Voltage Surge events only.

5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance

Curves” for typical performance.

6:

V

= 1V = 353 mV

@ 50/60 Hz.

RMS

IN

PP

7: Variation applies to internal clock and UART only. All calculated output quantities are temperature compensated to the

performance listed in the respective specification.

8: Lower baud rates selectable only on system versions 0xFA14 and later.

DS20005393B-page 6

 2015 Microchip Technology Inc.

MCP39F511

TABLE 1-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV

DV = +2.7 to +3.6V, T = -40°C to +125°C,

DD,

DD

A

MCLK = 4 MHz, PGA GAIN = 1.

Characteristic

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Power Specifications

Operating Voltage

AV_DD, DV_DD

V_POR

2.7

—

3.6

0.7

V

DV_DDStart Voltage

to Ensure Internal

D_GND

Power-On Reset Signal

DV_DDRise Rate to

Ensure Internal

Power-On Reset Signal

SDV_DD

V_POR

SAV_DD

I_DD

0.05

A_GND

0.042

—

13

—

2.1

—

V/ms 0 – 3.3V in 0.1s, 0 – 2.5V

in 60 ms

AV_DDStart Voltage to

Ensure Internal

Power-On Reset Signal

V

AV_DDRise Rate to

Ensure Internal Power On

Reset Signal

V/ms 0 – 2.4V in 50 ms

Operating Current

Data EEPROM Memory

Cell Endurance

—

mA

EPS

T_IWD

100,000

—

4

—

E/W

ms

Self-Timed

Write Cycle Time

10,000,000

Number of Total

Write/Erase Cycles

Before Refresh

R_REF

—

E/W

Characteristic Retention

T_RETDD

I_DDPD

40

—

7

—

years Provided no other

specifications are violated

Supply Current during

Programming

mA

Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4

line cycles.

2: Specification by design and characterization; not production tested.

3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or T

= 80 ms for

CAL

50 Hz line.

4: Applies to Voltage Sag and Voltage Surge events only.

5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance

Curves” for typical performance.

6:

V

= 1V = 353 mV

@ 50/60 Hz.

RMS

IN

PP

7: Variation applies to internal clock and UART only. All calculated output quantities are temperature compensated to the

performance listed in the respective specification.

8: Lower baud rates selectable only on system versions 0xFA14 and later.

 2015 Microchip Technology Inc.

DS20005393B-page 7

MCP39F511

TABLE 1-2:

SERIAL DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV_DD,DV_DD= +2.7 to+ 3.6V,

T_A= -40°C to +125°C, MCLK = 4 MHz

Characteristic

Sym.

Min.

Typ.

Max.

Units

Test Conditions

High-Level Input Voltage

Low-Level Input Voltage

High-Level Output Voltage

Low-Level Output Voltage

Input Leakage Current

V_IH

V_IL

0.8 DV_DD

—

DV_DD

0.2 DV_DD

—

V

0

3

V_OH

V_OL

I_LI

—

V

I_OH= -3.0 mA, V_DD= 3.6V

I_OL= 4.0 mA, V_DD= 3.6V

—

0.4

V

—

1

µA

0.050

0.100

Digital Output pins only

(ZCD, PWM, EVENT1,

EVENT2)

TABLE 1-3:

TEMPERATURE SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV_DD,DV_DD= +2.7 to +3.6V.

Parameters

Temperature Ranges

Sym.

Min.

Typ.

Max.

Units

Conditions

Operating Temperature Range

Storage Temperature Range

T_A

-40

-65

—

+125

+150

°C

Thermal Package Resistances

Thermal Resistance, 28LD 5x5 QFN

_JA

—

36.9

—

°C/W

DS20005393B-page 8

 2015 Microchip Technology Inc.

MCP39F511

2.0

TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, AV_DD= +3.3V, DV_DD= +3.3V, T_A= +25°C, GAIN = 1, V_IN= -0.5 dBFS at 60 Hz.

0.50%

0.40%

0.30%

0.20%

0.10%

0.00%

-0.10%

-0.20%

-0.30%

-0.40%

-0.50%

0

-20

-40

f_IN= -60 dBFS @ 60 Hz

f

_D= 3.9 ksps

16384 pt FFT

OSR = 256

-60

-80

-100

-120

-140

-160

-180

-200

0.01

0.1

1

10

100

1000

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Frequency (Hz)

Current Channel Input Amplitude (mV_PEAK

)

FIGURE 2-1:

Active Power, Gain = 1.

FIGURE 2-4:

Spectral Response.

0.100%

0.050%

0.000%

-0.050%

-0.100%

0.1

1

10

100

1000

Input Voltage RMS (mV_PP

)

Total Harmonic Distortion (-dBc)

FIGURE 2-2:

RMS Current, Gain = 1.

FIGURE 2-5:

THD Histogram.

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

0

-10

G = 1

G = 8

G = 2

G = 4

G = 16

G = 32

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-1

1

-50

-25

0

25

50

75

100 125 150

10

100

1000

10000 100000

Temperature (°C)

Energy Accumulation (Watt-Hours)

FIGURE 2-3:

Energy, Gain = 8.

FIGURE 2-6:

THD vs. Temperature.

 2015 Microchip Technology Inc.

DS20005393B-page 9

MCP39F511

Note: Unless otherwise indicated, AV_DD= 3.3V, DV_DD= 3.3V, T_A= +25°C, GAIN = 1, V_IN= -0.5 dBFS at 60 Hz.

1.2008

1.2007

1.2006

1.2005

1.2004

1.2003

1.2002

1.2001

1.2000

1.1999

94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5

Signal-to-Noise and Distortion Ratio (dB)

-50

0

50

100

150

Temperature (C)

FIGURE 2-7:

SNR Histogram.

FIGURE 2-10:

Internal Voltage Reference

vs. Temperature.

100

90

80

70

60

50

40

30

20

10

0

G = 1

G = 8

G = 2

G = 4

G = 16

G = 32

-50 -25

0

25

50

75 100 125 150

Temperature (°C)

FIGURE 2-8:

SINAD vs. Temperature.

5

4

3

2

1

0

-1

-2

-3

-4

G = 1

G = 2

G = 4

G = 8

G = 16

G = 32

-5

-50 -25

0

25

50

75

100 125 150

Temperature (°C)

FIGURE 2-9:

Gain Error vs. Temperature.

DS20005393B-page 10

 2015 Microchip Technology Inc.

MCP39F511

3.0

PIN DESCRIPTION

The description of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Symbol

MCP39F511

5x5 QFN

Function

1

EVENT1

NC

Event 1 Output pin

2, 3, 8, 9

No Connect (must be left floating)

UART Communication RX pin

4

5

6

7

UART_RX

COMMON_A

OSCI

Common pin A, to be connected to pin 13 (COMMON_B)

Oscillator Crystal Connection pin or External Clock Input pin

Oscillator Crystal Connection pin

OSCO

10

11

RESET

AV_DD

Reset pin for Delta-Sigma ADCs

Analog Power Supply pin

12

UART_TX

COMMON_B

PWM

UART Communication TX pin

13

Common pin B, to be connected to pin 5 (COMMON_A)

Pulse-Width Modulation (PWM) Output pin

Event 2 Output pin

14

15

EVENT2

I1+

16

Noninverting Current Channel Input for 24-bit  ADC

Inverting Current Channel Input for 24-bit  ADC

Inverting Voltage Channel Input for 24-bit  ADC

Noninverting Voltage Channel Input for 24-bit  ADC

Analog Input for SAR ADC

17

I1-

18

V1-

19

V1+

20

AN_IN

A_GND

21

Analog Ground Pin, return path for internal analog circuitry

Zero Crossing Detection Output

22

ZCD

23

REFIN+/OUT

Noninverting Voltage Reference Input and Internal Reference Output Pin

24, 27

D_GND

DV_DD

Digital Ground pin, return path for internal digital circuitry

Digital Power Supply pin

25

26

Master Clear for device

MCLR

28

29

DR

EP

Data Ready (must be left floating)

Exposed Thermal Pad (to be connected to pins 24 and 27 (D_GND))

 2015 Microchip Technology Inc.

DS20005393B-page 11

MCP39F511

3.1

Event Output Pins (EVENTn)

3.8

24-Bit Delta-Sigma ADC

Differential Current Channel

Input Pins (I1+/I1-)

These digital output pins can be configured to act as

output flags based on various internal raise conditions.

Control is modified through the Event Configuration

register.

I1- and I1+ are the two fully-differential current-channel

inputs for the Delta-Sigma ADCs.

The linear and specified region of the channels are

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±600 mV_PEAK/GAIN

with V_REF= 1.2V.

3.2

UART Communication Pins

(UART_RX, UART_TX)

The MCP39F511 device contains an asynchronous

full-duplex UART. The UART communication is eight

bits with Start and Stop bit. See Section 4.3 “UART

Settings” for more information.

The maximum absolute voltage, with respect to A_GND

,

for each In+/- input pin is ±1V with no distortion

and ±6V with no breaking after continuous voltage.

3.3

Common Pins (COMMON and )

A B

3.9

24-Bit Delta-Sigma ADC

Differential Voltage Channel

Inputs (V1-/V1+)

COMMON_Aand COMMON_Bpins are internal

connections for the MCP39F511. These two pins

should be connected together in the application.

V1- and V1+ are the two fully-differential

voltage-channel inputs for the Delta-Sigma ADCs.

3.4

Oscillator Pins (OSCI/OSCO)

The linear and specified region of the channels are

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±600 mV_PEAK/GAIN

with V_REF= 1.2V.

OSCI and OSCO provide the master clock for the

device. Appropriate load capacitance should be

connected to these pins for proper operation. An

optional 4 MHz crystal can be connected to these pins.

If a crystal of external clock source is not detected, the

device will clock from the internal 4 MHz oscillator.

The maximum absolute voltage, with respect to A_GND

for each V_N+/- input pin is ±1V with no distortion

and ±2V with no breaking after continuous voltage.

,

3.5

Reset Pin (RESET)

3.10 Analog Input (AN_IN)

This pin is active-low and places the Delta-Sigma

ADCs, PGA, internal V_REFand other blocks associated

with the analog front-end in a Reset state when pulled

low. This input is Schmitt-triggered.

This is the input to the analog-to-digital converter that

can be used for temperature measurement and

compensation. If temperature compensation is

required in the application, it is advised to connect the

low-power active thermistor IC MCP9700A to this pin.

If temperature compensation is not required, this can

be used as a general purpose analog-to-digital

converter input.

3.6

Analog Power Supply Pin (AV

)

DD

AV_DDis the power supply pin for the analog circuitry

within the MCP39F511.

This pin requires appropriate bypass capacitors and

should be maintained to +2.7V and +3.6V for specified

operation. It is recommended to use 0.1 µF ceramic

capacitors.

3.11 Analog Ground Pin (A

)

GND

A_GNDis the ground connection to internal analog

circuitry (ADCs, PGA, voltage reference, POR). If an

analog ground pin is available on the PCB, it is

recommended that this pin be tied to that plane.

3.7

Pulse Width Modulator (PWM)

This digital output is a dedicated PWM output that can

be controlled through the PWM Frequency and PWM

Duty Cycle registers. See Section 8.0 “Pulse Width

modulation (PWM)” for more information.

3.12 Zero Crossing Detection (ZCD)

This digital output pin is the output of the zero crossing

detection circuit of the IC. The output here will be a

logic output with edges that transition at each zero

crossing of the voltage channel input. For more

information see Section 5.13 “Zero Crossing

Detection (ZCD)”.

DS20005393B-page 12

 2015 Microchip Technology Inc.

MCP39F511

3.13 Noninverting Reference

Input/Internal Reference Output

Pin (REFIN+/OUT)

This pin is the noninverting side of the differential

voltage reference input for the Delta-Sigma ADCs or

the internal voltage reference output.

For optimal performance, bypass capacitances should

be connected between this pin and A_GNDat all times,

even when the internal voltage reference is used.

However, these capacitors are not mandatory to

ensure proper operation.

3.14 Digital Ground Connection Pins

(D

)

GND

D_GNDis the ground connection to internal digital

circuitry (SINC filters, oscillator, serial interface). If a

digital ground plane is available, it is recommended to

tie this pin to the digital plane of the PCB. This plane

should also reference all other digital circuitry in the

system.

3.15 Digital Power Supply Pin (DV

)

DD

DV_DDis the power supply pin for the digital circuitry

within the MCP39F511. This pin requires appropriate

bypass capacitors and should be maintained between

+2.7V and +3.6V for specified operation. It is

recommended to use 0.1 µF ceramic capacitors.

3.16 Data-Ready Pin (DR)

The data-ready pin indicates if a new Delta-Sigma A/D

conversion result is ready to be processed. This pin is

for indication only and should be left floating. After each

conversion is finished, a low pulse will take place on the

data-ready pin to indicate the conversion result is ready

and an interrupt is generated in the calculation engine

(CE). This pulse is synchronous with the line frequency

to ensure an integer number of samples for each line

cycle.

Note:

This pin is internally connected to the IRQ

of the calculation engine and should be

left floating.

3.17 Exposed Thermal Pad (EP)

This pin is the exposed thermal pad. It must be

connected to pin 24 (D_GND).

 2015 Microchip Technology Inc.

DS20005393B-page 13

MCP39F511

NOTES:

DS20005393B-page 14

 2015 Microchip Technology Inc.

MCP39F511

4.1

Device Responses

4.0

COMMUNICATION PROTOCOL

After the reception of a communication frame, the

MCP39F511 has three possible responses, which will

be returned with or without data, depending on the

frame received. These responses are either:

The communication protocol for the MCP39F511

device is based on the Simple Sensor Interface (SSI)

protocol. This protocol is used for point-to-point

communication from

a

single-host MCU to

a

single-slave MCP39F511.

• Acknowledge (ACK, 0x06): Frame received with

success, commands understood and commands

executed with success.

All communication to the device occurs in frames. Each

frame consists of a header byte, the number of bytes in

the frame, command packet (or command packets)

and a checksum. It is important to note that the

maximum number of bytes in either a receive or

transmit frame is 35.

• Negative Acknowledge (NAK, 0x15): Frame

received with success, however commands not

executed with success, commands not

understood or some other error in the command

bytes.

Note:

If a custom communication protocol is

desired, please contact a Microchip sales

office.

• Checksum Fail (CSFAIL, 0x51): Frame received

with success, however the checksum of the frame

did not match the bytes in the frame.

Note:

There is one unique device ID response

which is used to determine which

This approach allows for single, secure transmission

from the host processor to the MCP39F511 with either

a single command or multiple commands. No com-

mand in a frame is processed until the entire frame is

complete and the checksum and number of bytes are

validated.

MCP39FXXX

device

is

present:

[NAK(0x15) + ID_BYTE]. If the device is

interrogated with 0x5A, i.e. it receives 0x5A

as the first byte instead of the standard

0xA5 first header byte, a special NAK is

returned followed by an ID_BYTE. For the

MCP39F511 the ID_BYTE is 0x01. This

functionality is only present on system ver-

sions 0xFA14 and later.

The number of bytes in an individual command packet

depend on the specific command. For example, to set

the instruction pointer, three bytes are needed in the

packet: the command byte and two bytes for the

address you want to set to the pointer. The first byte in

a command packet is always the command byte.

This protocol can also be used to set up transmission

from the MCP39F511 on specific registers.

A

predetermined single-wire transmission frame is

defined for one-wire interfaces. The Auto-transmit

mode can be initiated by setting the SINGLE_WIRE bit

in the System Configuration register, allowing for

single-wire communication within the application. See

Section 4.8 “Single-Wire Transmission Mode” for

more information on this communication.

Frame

Header Byte (0xA5) Number of Bytes Command Packet1 Command Packet2 Command Packet n

Checksum

...

Command

BYTE0

BYTE N

BYTE1 BYTE2

FIGURE 4-1:

Communication Frame.MCP39F511

 2015 Microchip Technology Inc.

DS20005393B-page 15

MCP39F511

4.2

Checksum

The checksum is generated using simple byte addition

and taking the modulus to find the remainder after

dividing the sum of the entire frame by 256. This oper-

ation is done to obtain an 8-bit checksum. All the bytes

of the frame are included in the checksum, including

the header byte and the number of bytes. If a frame

includes multiple command packets, none of the com-

mands will be issued if the frame checksum fails. In this

instance, the MCP39F511 will respond with a CSFAIL

response of 0x51.

On commands that are requesting data back from the

MCP39F511, the frame and checksum are created in

the same way, with the header byte becoming an

Acknowledge (0x06). Communication examples are

given in Section 4.5 “Example Communication

Frames and MCP39F511 Responses”.

4.3

UART Settings

The default baud rate is 115. 2 kbps and can be

changed using the UART bits in the System

Configuration Register. This is only available on

system versions 0xFA14 and later. For previous

versions the baud rate is fixed at 115.2k. Note that the

baud rate is changed at system power-up, so when

changing the baud rate, a Save To Flashcommand

followed by a power-on cycle is required. The UART

operates in 8-bit mode, plus one start bit and one stop

bit, for a total of 10 bits per byte, as shown in

Figure 4-2.

START

IDLE

D0 D1 D2 D3 D4 D5 D6 D7 STOP IDLE

FIGURE 4-2:

UART Transmission, N-8-1.

DS20005393B-page 16

 2015 Microchip Technology Inc.

MCP39F511

4.4

Command List

The following table is a list of all accepted command

bytes for the MCP39F511. There are 10 possible

accepted commands for the MCP39F511.

TABLE 4-1:

MCP39F511 INSTRUCTION SET

Successful

Number

Command

#

Command

Instruction

Parameter

Command

Response

ID

ofbytes

UART_TX

1

Register Read, N bytes

0x4E

Number of bytes

2

ACK, Data,

Checksum

2

3

4

5

Register Write, N bytes

Set Address Pointer

Save Registers To Flash

Page Read EEPROM

0x4D

0x41

0x53

0x42

Number of bytes

ADDRESS

None

1+N

3

ACK

1

PAGE

2

ACK, Data,

Checksum

6

7

Page Write EEPROM

0x50

0x4F

0x5A

0x7A

0x76

PAGE

None

18

1

ACK

Bulk Erase EEPROM

8

Auto-Calibrate Gain

Note 1

9

Auto-Calibrate Reactive Gain

Auto-Calibrate Frequency

Note 1

10

Note 1: See Section 9.0, MCP39F511 Calibration for more information on calibration.

4.5

Example Communication Frames

and MCP39F511 Responses

Tables 4-2 to 4-11 show exact hexadecimal

communication frames as recommended to be sent to

the MCP39F511 from the system MCU. The values

here can be used as direct examples for writing the

code to communicate to the MCP39F511.

TABLE 4-2:

REGISTER READ, N BYTES COMMAND (Note 1)

Byte # Value

Description

Response from MCP39F511

1

2

3

4

5

6

7

8

0xA5 Header Byte

0x08 Number of Bytes in Frame

0x41 Command (Set Address Pointer)

0x00 Address High

0x02 Address Low

0x4E Command (Register Read, N Bytes)

0x20 Number of Bytes to Read (32)

0x5E Checksum

ACK + Number of Bytes (35) + 32 bytes + Checksum

Note 1: This example Register Read, N bytesframe, as it is written here, can be used to poll a subset of the

output data, starting at the top, address 0x02, and reading 32 data bytes back or 35 bytes total in the frame.

 2015 Microchip Technology Inc.

DS20005393B-page 17

MCP39F511

TABLE 4-3:

Byte #

REGISTER WRITE, N BYTES COMMAND (Note 1)

Value

Description

Response from MCP39F511

1

2

0xA5

0x25

Header Byte

Number of Bytes in Frame

Command (Set Address Pointer)

Address High

3

0x41

4

0x00

5

0x82

Address Low

6

0x4D

Command (Register Write, N Bytes)

Number of Bytes to Write (20)

Data Bytes (20 total data bytes)

Checksum

7

0x14

8-36

37

*Data*

Checksum

ACK

Note 1: This Register Write, N Bytesframe, as it is written here, can be used to write the entire set of

calibration target data, starting at the top, address 0x82, and continuing to write until the end of this set of

registers, 20 bytes later. Note these are not the calibration registers, but the calibration targets which need

to be written prior to issuing the auto-calibration target commands. See Section 9.0 “MCP39F511

Calibration” for more information.

TABLE 4-4:

Byte #

SET ADDRESS POINTER COMMAND (Note 1)

Value

Description

Response from MCP39F511

1

2

3

4

5

6

0xA5

0x06

0x41

0x00

0x02

0xF8

Header Byte

Number of Bytes in Frame

Command (Set Address Pointer)

Address High

Address Low

Checksum

ACK

Note 1: The Set Address Pointercommand is typically included inside of a frame that includes a read or write

command, as shown in Tables 4-2 and 4-3. There is typically no reason for this command to have its own

frame, but is shown here as an example.

TABLE 4-5:

Byte #

SAVE TO FLASH COMMAND

Value

Description

Response from MCP39F511

1

2

3

4

0xA5

0x04

0x53

0xFC

Header Byte

Number of Bytes in Frame

Command (Save To Flash)

Checksum

ACK

TABLE 4-6:

Byte #

PAGE READ EEPROM COMMAND

Value

Description

Header Byte

Response from MCP39F511

1

2

3

4

5

0xA5

0x05

0x42

0x01

0xF8

Number of Bytes in Frame

Command (Page Read EEPROM)

Page Number (e.g. 1)

Checksum

ACK + EEPROM Page Data + Checksum

DS20005393B-page 18

 2015 Microchip Technology Inc.

MCP39F511

TABLE 4-7:

Byte #

PAGE WRITE EEPROM COMMAND

Value

Description

Response from MCP39F511

1

2

0xA5

0x15

Header Byte

Number of Bytes in Frame

Command (Page Write EEPROM)

Page Number (e.g. 1)

EEPROM Data (16 bytes/Page)

Checksum

3

0x50

4

0x01

5-20

21

*Data*

Checksum

ACK

TABLE 4-8:

Byte #

BULK ERASE EEPROM COMMAND

Value

Description

Response from MCP39F511

1

2

3

4

0xA5

0x04

0x4F

0xF8

Header Byte

Number of Bytes in Frame

Command (Bulk Erase EEPROM)

Checksum

ACK

TABLE 4-9:

Byte #

AUTO-CALIBRATE GAIN COMMAND

Value

Description

Response from MCP39F511

1

2

3

4

0xA5

0x04

0x5A

0x03

Header Byte

Number of Bytes in Frame

Command (Auto-Calibrate Gain)

Checksum

ACK (or NAK if unable to

calibrate)¹

Note 1: See Section 9.0 “MCP39F511 Calibration” for more information.

TABLE 4-10: AUTO-CALIBRATE REACTIVE GAIN COMMAND

Byte #

Value

Description

Response from MCP39F511

1

2

3

4

0xA5

0x04

0x7A

0x23

Header Byte

Number of Bytes in Frame

Command (Auto-Calibrate Reactive Gain)

Checksum

ACK (or NAK if unable to

calibrate)¹

Note 1: See Section 9.0 “MCP39F511 Calibration” for more information.

TABLE 4-11: AUTO-CALIBRATE FREQUENCY COMMAND

Byte #

Value

Description

Response from MCP39F511

1

2

3

4

0xA5

0x04

0x76

0x1F

Header Byte

Number of Bytes in Frame

Command (Auto-Calibrate Frequency)

Checksum

ACK (or NAK if unable to

calibrate)¹

Note 1: See Section 9.0 “MCP39F511 Calibration” for more information.

 2015 Microchip Technology Inc.

DS20005393B-page 19

MCP39F511

4.6.6

PAGE WRITE EEPROM (0x50)

4.6

Command Descriptions

The Page Write EEPROM command is expecting

17 additional bytes in the command parameters, which

are EEPROM page plus 16 bytes of data. A more

complete description of the memory organization of the

EEPROM can be found in Section 10.0 “EEPROM”

The response to this command is an Acknowledge.

4.6.1

REGISTER READ, N BYTES (0x4E)

The Register Read, N bytes command returns

the N bytes that follow whatever the current address

pointer is set to. It should typically follow

a

Set Address Pointercommand and can be used

in conjunction with other read commands. An

Acknowledge, Data and Checksum is the response for

this command. The maximum number of bytes that can

be read with this command is 32. If there are other

read commands within a frame, the maximum number

of bytes that can be read is 32 minus the number of

bytes being read in the frame. With this command, the

data is returned LSB first.

4.6.7

BULK ERASE EEPROM (0x4F)

The Bulk Erase EEPROM command will erase the

entire EEPROM array and return it to a state of 0xFFFF

for each memory location of EEPROM. A more

complete description of the memory organization of the

EEPROM can be found in Section 10.0 “EEPROM”.

The response to this command is Acknowledge.

4.6.2

REGISTER WRITE, N BYTES (0x4D)

bytes command is

4.6.8

AUTO-CALIBRATE GAIN (0x5A)

The Register Write,

N

The Auto-Calibrate Gain command initiates the

single-point calibration that is all that is typically

required for the system. This command calibrates the

RMS current, RMS voltage and Active power based on

the target values written in the corresponding registers.

See Section 9.0 “MCP39F511 Calibration” for more

information on device calibration. The response to this

command is Acknowledge.

followed by N bytes that will be written to whatever the

current address pointer is set to. It should typically

follow a Set Address Pointercommand and can

be used in conjunction with other write commands. An

Acknowledge is the response for this command. The

maximum number of bytes that can be written with this

command is 32. If there are other write commands

within a frame, the maximum number of bytes that can

be written is 32 minus the number of bytes being

written in the frame. With this command, the data is

written LSB first.

4.6.9

AUTO-CALIBRATE REACTIVE

POWER GAIN (0X7A)

The Auto-Calibrate Reactive Gaincommand

initiates single-point calibration to match the

measured Reactive power to the target Reactive

power. This is typically done at PF = 0.5. See section

Section 9.0 “MCP39F511 Calibration” for more

information on device calibration.

a

4.6.3

SET ADDRESS POINTER (0x41)

This command is used to set the address pointer for all

read and write commands. This command is expecting

the address pointer as the command parameter in the

following two bytes, Address High Byte followed by

Address Low Byte. The address pointer is two bytes in

length. If the address pointer is within the acceptable

addresses of the device, an Acknowledge will be

returned.

4.6.10

AUTO-CALIBRATE FREQUENCY

(0x76)

For applications not using an external crystal and

running the MCP39F511 off the internal oscillator, a

gain calibration to the line frequency indication is

required. The Gain Line Frequency register is set such

that the frequency indication matches what is set in the

Line Frequency Reference register. See Section 9.0

“MCP39F511 Calibration” for more information on

device calibration.

4.6.4

SAVE REGISTERS TO FLASH (0x53)

The Save Registers To Flashcommand makes

a copy of all the calibration and configuration registers

to flash. This includes all R/W registers in the register

set. The response to this command is an Acknowledge.

4.6.5

PAGE READ EEPROM (0x42)

The Page Read EEPROMcommand returns 16 bytes

of data that are stored in an individual page on the

MCP39F511. A more complete description of the mem-

ory organization of the EEPROM can be found in

Section 10.0 “EEPROM”. This command is expecting

the EEPROM page as the command parameter or the

following byte. The response to this command is an

Acknowledge, 16-bytes of data and CRC Checksum.

DS20005393B-page 20

 2015 Microchip Technology Inc.

MCP39F511

4.7

Notation for Register Types

4.8

Single-Wire Transmission Mode

The following notation has been adopted for describing

the various registers used in the MCP39F511:

In Single-Wire Transmission mode, at the end of each

computation cycle, the device automatically transmits a

frame of power data. This allows for single-wire com-

munication after the device has been configured.

TABLE 4-12: SHORT-HAND NOTATION

FOR REGISTER TYPES

The single-wire transmission frame consists of

20 bytes: three Header Bytes, one Checksum and

16 bytes of power data (including RMS current, RMS

voltage, Active Power, Reactive Power and Line

Frequency).

Notation

Description

u64

u32

s32

u16

s16

b32

Unsigned, 64-bit register

Unsigned, 32-bit register

Signed, 32-bit register

Unsigned, 16-bit register

Signed, 16-bit register

TABLE 4-13: SINGLE-WIRE

TRANSMISSION FRAME

(Note 2)

32-bit register containing discrete

Boolean bit settings

#

Byte

HEADERBYTE (0xAB)

1

2

3

4

5

6

7

8

9

HEADERBYTE2 (0xCD)

HEADERBYTE3 (0xEF)

CURRENT RMS – Byte 0

CURRENT RMS – Byte 1

CURRENT RMS – Byte 2

CURRENT RMS – Byte 3

VOLTAGE RMS – Byte 0

VOLTAGE RMS – Byte 1

10 ACTIVE POWER – Byte 0

11 ACTIVE POWER – Byte 1

12 ACTIVE POWER – Byte 2

13 ACTIVE POWER – Byte 3

14 REACTIVE POWER – Byte 0

15 REACTIVE POWER – Byte 1

16 REACTIVE POWER – Byte 2

17 REACTIVE POWER – Byte 3

18 LINE FREQUENCY – Byte 0

19 LINE FREQUENCY – Byte 1

20 CHECKSUM

2: For custom single-wire transmission

packets, contact a Microchip sales office.

 2015 Microchip Technology Inc.

DS20005393B-page 21

MCP39F511

NOTES:

DS20005393B-page 22

 2015 Microchip Technology Inc.

MCP39F511

For DC applications, offset can be removed by using

the DC Offset Current register. To compensate for any

external phase error between the current and voltage

channels, the Phase Compensation register can be

used.

5.0

5.1

CALCULATION ENGINE (CE)

DESCRIPTION

Computation Cycle Overview

The MCP39F511 uses a coherent sampling algorithm

to phase lock the sampling rate to the line frequency

with an integer number of samples per line cycle, and

reports all power output quantities at a 2^Nnumber of

line cycles. This is defined as a computation cycle and

is dependent on the line frequency, so any change in

the line frequency will change the update rate of the

power outputs.

See Section 9.0 “MCP39F511 Calibration” for more

information on device calibration.

5.4

RMS Current and RMS Voltage

The MCP39F511 device provides true RMS

measurements. The MCP39F511 device has two

simultaneous sampling 24-bit A/D converters for the

current and voltage measurements. The root mean

square calculations are performed on 2^Ncurrent and

voltage samples, where N is defined by the register

Accumulation Interval Parameter.

5.2

Accumulation Interval Parameter

The accumulation interval is defined as an 2^Nnumber

of line cycles, where N is the value in the Accumulation

Interval Parameter register.

EQUATION 5-1:

RMS CURRENT AND

VOLTAGE

5.3

Raw Voltage and Currents Signal

Conditioning

N

2

– 1

2

– 1

2

The first set of signal conditioning that occurs inside the

MCP39F511 is shown in Figure 5-1. All conditions set

in this diagram effect all of the output registers (RMS

current, RMS voltage, Active power, Reactive power,

Apparent power, etc.). The gain of the PGA, the

Shutdown and Reset status of the 24-bit ADCs are all

controlled through the System Configuration Register.

i 

v 



n

n = 0

I

=

-----------------------------

V

=

------------------------------

RMS

N

2

24-bit  ADC

Multi-Level

Modulator

I1+

I1-

+

PGA

i

HPF ¹



-

+

CHANNEL I1

DCOffsetCurrent:s16

SystemConfiguration:b32

PhaseCompensation:s16

24-bit  ADC

Multi-Level

Modulator

V1+

V1-

+

-

PGA

v

HPF ¹



CHANNEL V1

Note 1: High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel.

FIGURE 5-1:

Channel I1 and V1 Signal Flow.

 2015 Microchip Technology Inc.

DS20005393B-page 23

MCP39F511

Range:b32

2^N-1

N

÷ 2

÷2^RANGE



CurrentRMS:u32

i

0

X



+

ACCU

+

GainCurrentRMS:u16

OffsetCurrentRMS:s32

ApparentPower:u32

GainVoltageRMS:u16

X

2

^N-1

N

÷ 2

÷2^RANGE



v

VoltageRMS:u16

0

X

ACCU

Range:b32

FIGURE 5-2:

RMS Current and Voltage Calculation Signal Flow.

is considered positive (power or energy being

consumed by the load), and export power or energy is

considered negative (power or energy being delivered

by the load). The following figure represents the

measurements obtained by the MCP39F511.

5.5

Power and Energy

The MCP39F511 offers signed power numbers for

Active and Reactive power, import and export registers

for active energy, and four-quadrant Reactive power

measurement. For this device, import power or energy

Import Reactive Power

Consume, Inductive

Generate, Inductive

Quadrant I

+P, +Q

Quadrant II

-P, +Q

S

Q



P

Import Active Power

Export Active Power

Quadrant III

Quadrant IV

Consume, Capacitive

+P, -Q

Generate, Capacitive

-P, -Q

Export Reactive Power

FIGURE 5-3:

The Power Circle and Triangle (S = Apparent, P = Active, Q = Reactive).

DS20005393B-page 24

 2015 Microchip Technology Inc.

MCP39F511

For scaling of the Apparent power indication, the calcu-

lation engine uses the register Apparent Power Divisor.

This is described in the following register operations,

per Equation 5-3.

5.6

Energy Accumulation

Energy accumulation for all four energy registers

(import/export, active/reactive) occurs at the end of

each computation cycle, if the energy accumulation

has been turned on. See Section 6.3 “System Status

Register” on the energy control register. A no-load

threshold test is done to make sure the measured

energy is not below the no-load threshold, if it is above,

EQUATION 5-3:

APPARENT POWER (S)

CurrentRMS  VoltageRMS

S = --------------------------------------------------------------------

ApparentPowerDivisor

10

the accumulation occurs with

a default energy

resolution of 1mWh for all of the energy registers.

5.8

Active Power (P)

5.6.1

NO-LOAD THRESHOLD

The MCP39F511 has two simultaneous sampling A/D

converters. For the Active power calculation, the

instantaneous current and instantaneous voltages are

multiplied together to create instantaneous power.

This instantaneous power is then converted to Active

power by averaging or calculating the DC component.

The no-load threshold is set by modifying the value in

the No-Load Threshold register. The unit for this

register is power with a default resolution of 0.01W. The

default value is 100 or 1.00W. Any power that is below

1W will not be accumulated into any of the energy

registers.

Equation 5-4 controls the number of samples used in

this accumulation prior to updating the Active Power

output register.

5.7

Apparent Power (S)

This 32-bit register is the output register for the final

Apparent power indication. It is the product of RMS

current and RMS voltage as shown in Equation 5-2.

Please note that although this register is unsigned, the

direction of the Active power (import or export) can be

determined by the Active Power Sign bit located in the

System Status Register.

EQUATION 5-2:

S = I

APPARENT POWER (S)

EQUATION 5-4:

ACTIVE POWER

 V

RMS

N

k = 2 – 1

1

N

2

P = ------

V  I



k

k = 0

GainActivePower:u16

i

Range:b32

N

2

-1

÷ 2^N

÷2^RANGE

ActivePower:u32



X

0



+

ACCU

+

OffsetActivePower:s32

v

FIGURE 5-4:

Active Power Calculation Signal Flow.

 2015 Microchip Technology Inc.

DS20005393B-page 25

MCP39F511

Please note that although this register is unsigned, the

direction of the power can be determined by the

reactive power sign bit in the system status register.

5.9

Power Factor (PF)

Power factor is calculated by the ratio of P to S or

Active power divided by Apparent power.

EQUATION 5-5:

POWER FACTOR

P

PF = ---

S

The Power Factor Reading is stored in a signed 16-bit

register (Power Factor). This register is a signed, 2's

complement register with the MSB representing the

polarity of the power factor. A positive power factor

means Active power is being imported, negative power

factor represents export Active power. The sign of the

reactive power component is used to tell if the current

is lagging the voltage, with a positive sign meaning an

inductive load, and a negative sign meaning capacitive.

Each LSB is then equivalent to a weight of 2^-15. A

maximum register value of 0x7FFF corresponds to a

power factor of 1. The minimum register value of

0x8000 corresponds to a power factor of -1.

5.10 Reactive Power (Q)

In the MCP39F511, Reactive Power is calculated using

a 90 degree phase shift in the voltage channel. The

same accumulation principles apply as with active

power where ACCU acts as the accumulator. Any light

load or residual power can be removed by using the

Offset Reactive Power register. Gain is corrected by

the Gain Reactive Power register. The final output is an

unsigned 32-bit value located in the Reactive Power

register.

GainReactivePower:u16

Range1,2:b32

i

HPF

N

2 -1

÷ 2^N

÷2^RANGE



X



0

+

ACCU1

-

ReactivePower:u32

OffsetReactivePower:s32

v

HPF (+90deg.)

FIGURE 5-5:

Reactive Power Calculation Signal Flow.

DS20005393B-page 26

 2015 Microchip Technology Inc.

MCP39F511

5.11 10-Bit Analog Input

5.13 Zero Crossing Detection (ZCD)

The least 10 significant bits of the 16-bit Analog Input

register contain the output of the 10-bit ADC. The

conversion rate of the analog input occurs once every

computation cycle.

The zero crossing detection block generates a

logic pulse output on the ZCD pin that is coherent with

the zero crossing of the input AC signal present on

voltage input pins (V1+, V1-). The ZCD pin can be

enabled and disabled by the corresponding bit in the

System Configuration Register register. When

enabled, this produces a square wave with a frequency

that is equivalent to that of the AC signal present on the

voltage input. Figure 5-7 represents the signal on the

ZCD pin superimposed with the AC signal present on

the voltage input in this mode.

The Thermistor Voltage can be used for temperature

compensation of the calculation engine. See

Section 9.7 “Temperature Compensation” for more

information.

AnalogInput:u16

10-bit

ADC

MCP9700

<200 µs

FIGURE 5-6:

Using an Analog

Out-Temperature Sensor for Automatic

Temperature Compensation.

5.12 Minimum and Maximum

Recordings

FIGURE 5-7:

Operation (Noninverted, Nonpulse).

Zero Crossing Detection

The MCP39F511 has the ability to record minimum and

maximum outputs and keep them in a total of four

registers (two minimum and two maximum) based on

the value of address pointers located in the four

registers listed in this section.

A second mode is available that produces a 100 µs

pulse at each zero crossing, at a frequency that is twice

that of the AC signal present on the voltage input,

shown in Figure 5-8.

A minimum and maximum test is done after each

calculation interval. If the current measurement value

of the value directed to by the pointer is smaller or

larger than the value in the Minimum or Maximum

register, the record is updated appropriately.

<200 µs

The registers are:

• MinMaxPointer1 → MinimumRecord1,

Maximum-Record1

• MinMaxPointer2 → MinimumRecord2,

FIGURE 5-8:

Operation (Noninverted, Pulsed).

Zero Crossing Detection

Maximum-Record2

Only the Output Quantity register addresses can be

tracked by the Min/Max pointers. Output Quantity

registers are defined as those from Voltage RMS to

Apparent Power (addresses 0x0006 to 0x001A). All

other addresses will be ignored by the calculation

engine.

Switching modes is done by setting the corresponding

bit in the System Configuration Register. In addition,

either the toggling of this pin, or the pulse, can be

inverted. The ZCD Inversion bit is also in the System

Configuration register.

Please note that the 64-bit energy registers can not be

tracked through the Minimum and Maximum Recording

registers.

There are two bits in the System Configuration register

that can be used to modify the zero crossing. The zero

crossing output can be inverted by setting the Inversion

bit, or the zero crossing can be a 100 µs pulse at each

zero crossing, by setting the Pulse bit.

Note that a low-pass filter is included in the signal path

that allows the zero crossing detection circuit to

filter out the fundamental frequency. An internal

compensation circuit is then used to gain back the

phase delay introduced by the low-pass filter resulting

in a latency of less than 200 µs.

 2015 Microchip Technology Inc.

DS20005393B-page 27

MCP39F511

NOTES:

DS20005393B-page 28

 2015 Microchip Technology Inc.

MCP39F511

6.0

6.1

REGISTER DESCRIPTIONS

Complete Register Map

The following table describes the registers for the MCP39F511 device.

TABLE 6-1:

Address

MCP39F511 REGISTER MAP

Section Read/ Data

Number Write Type

Register Name

Description

Output Registers

0x0000 Instruction Pointer

0x0002 System Status

0x0004 System Version

6.2

6.3

R

u16 Address pointer for read or write commands

b16 System Status Register

u16 System version date code information for

MCP39F511, set at the Microchip factory;

format YMDD

0x0006 Voltage RMS

5.4

9.6

R

u16 RMS Voltage output

0x0008 Line Frequency

0x000A Analog Input Voltage

0x000C Power Factor

u16 Line Frequency output

u16 Output of the 10-bit SAR ADC

s16 Power Factor output

5.11

5.9

0x000E Current RMS

5.4

u32 RMS Current output

0x0012 Active Power (Note 1)

0x0016 Reactive Power (Note 1)

0x001A Apparent Power

5.8

u32 Active Power output

5.10

5.7

u32 Reactive Power output

u32 Apparent Power output

u64 Accumulator for Active Energy, Import

0x001E Import Active Energy

Counter

5.6

0x0026 Export Active Energy

Counter

5.6

R

u64 Accumulator for Active Energy, Export

u64 Accumulator for Reactive Energy, Import

u64 Accumulator for Reactive Energy, Export

0x002E Import Reactive Energy

Counter

0x0036 Export Reactive Energy

Counter

5.6

0x003E Minimum Record 1

5.12

u32 Minimum Value of the Output Quantity

Address in Min/Max Pointer 1 Register

0x0042 Minimum Record 2

u32 Minimum Value of the Output Quantity

Address in Min/Max Pointer 2 Register

0x0046 Reserved

—

R

u32 Reserved

0x004A Reserved

0x004E Maximum Record 1

5.12

u32 Maximum Value of the Output Quantity

Address in Min/Max Pointer 1 Register

0x0052 Maximum Record 2

5.12

R

u32 Maximum Value of the Output Quantity

Address in Min/Max Pointer 2 Register

0x0056 Reserved

0x005A Reserved

—

R

u32 Reserved

Note 1: The registers are unsigned, however their sign is kept as a separate bit in the System Status Register.

2: These registers are reserved for EMI filter compensation when necessary for power supply monitoring.

They may require specific adjustment depending on PSU parameters, please contact the local Microchip

office for further support.

3: The Overtemperature event is only available on system versions 0xFA14 and later.

 2015 Microchip Technology Inc.

DS20005393B-page 29

MCP39F511

TABLE 6-1:

Address

MCP39F511 REGISTER MAP (CONTINUED)

Section Read/ Data

Number Write Type

Register Name

Description

Calibration Registers

0x005E Calibration Register

Delimiter

9.8

R/W

u16 May be used to initiate loading of the default

calibration coefficients at start-up

0x0060 Gain Current RMS

0x0062 Gain Voltage RMS

0x0064 Gain Active Power

0x0066 Gain Reactive Power

0x0068 Offset Current RMS

0x006C Offset Active Power

0x0070 Offset Reactive Power

0x0074 DC Offset Current

0x0076 Phase Compensation

0x0078 Apparent Power Divisor

9.3.1

9.3

R/W

u16 Gain Calibration Factor for RMS Current

u16 Gain Calibration Factor for RMS Voltage

u16 Gain Calibration Factor for Active Power

u16 Gain Calibration Factor for Reactive Power

s32 Offset Calibration Factor for RMS Current

s32 Offset Calibration Factor for Active Power

s32 Offset Calibration Factor for Reactive Power

s16 Offset Calibration Factor for DC Current

s16 Phase Compensation

9.5.1

9.5.2

9.4

5.7

u16 Number of Digits for apparent power divisor to

match I_RMSand V_RMSresolution

Design Configuration Registers

0x007A System Configuration

6.5

7.0

R/W

b32 Control for device configuration, including

ADC configuration

0x007E Event Configuration

b16 Settings for the Event pins including Relay

Control

0x0082 Range

6.6

R/W

b32 Scaling factor for Outputs

0x0086 Calibration Current

9.3.1

u32 Target Current to be used during single-point

calibration

0x008A Calibration Voltage

9.3.1

9.6.1

R/W

u16 Target Voltage to be used during single-point

calibration

0x008C Calibration Power Active

0x0090 Calibration Power Reactive

0x0094 Line Frequency Reference

u32 Target Active Power to be used during

single-point calibration

u32 Target Active Power to be used during

single-point calibration

u16 Reference Value for the nominal line

frequency

0x0096 Reserved

0x009A Reserved

—

u32 Reserved

0x009E Accumulation Interval

Parameter

5.10

R/W

u16 N for 2^Nnumber of line cycles to be used

during a single computation cycle

0x00A0 Voltage Sag Limit

0x00A2 Voltage Surge Limit

0x00A4 Overcurrent Limit

0x00A8 Overpower Limit

7.2.2

7.2

R/W

u16 RMS Voltage threshold at which an event flag

is recorded

u16 RMS Voltage threshold at which an event flag

is recorded

u32 RMS Current threshold at which an event flag

is recorded

7.2

u32 Active Power Limit at which an event flag is

recorded

Note 1: The registers are unsigned, however their sign is kept as a separate bit in the System Status Register.

2: These registers are reserved for EMI filter compensation when necessary for power supply monitoring.

They may require specific adjustment depending on PSU parameters, please contact the local Microchip

office for further support.

3: The Overtemperature event is only available on system versions 0xFA14 and later.

DS20005393B-page 30

 2015 Microchip Technology Inc.

MCP39F511

TABLE 6-1:

Address

MCP39F511 REGISTER MAP (CONTINUED)

Section Read/ Data

Register Name

Description

Number Write

Type

EMI Filter Compensation Registers (Note 2)

0x00AC Reserved

0x00AE Reserved

0x00B0 Reserved

0x00B2 Reserved

0x00B4 Reserved

0x00B6 Reserved

0x00B8 Reserved

0x00BA Reserved

0x00BC Reserved

0x00BE Reserved

0x00C0 Reserved

0x00C2 Reserved

0x00C4 Reserved

—

R

u16 Reserved

—

Temperature Compensation and Peripheral Control Registers

0x00C6 Temperature Compensation

for Frequency

9.7

R/W

u16 Correction factor for compensating the line

frequency indication overtemperature

0x00C8 Temperature Compensation

for Current

u16 Correction factor for compensating the Current

RMS indication overtemperature

0x00CA Temperature Compensation

for Power

u16 Correction factor for compensating the active

power indication overtemperature

0x00CC Ambient Temperature

Reference Voltage

u16 Register for storing the reference temperature

during calibration

0x00CE PWM Period

0x00D0 PWM Duty Cycle

0x00D2 Reserved

8.2

8.3

R/W

—

u16 Input register controlling PWM Period

u16 Input register controlling PWM Duty Cycle

u16 Reserved

—

0x00D4 MinMaxPointer1

0x00D6 MinMaxPointer2

5.12

7.2.1

R/W

u16 Address Pointer for Min/Max 1 Outputs

u16 Address Pointer for Min/Max 2 Outputs

0x00D8 Overtemperature Limit

u16 Limit at which an Overtemperature event flag

(Note 3)

is recorded

0x00DA Reserved

—

R

u16 Reserved

0x00DC Energy Control

5.6

R/W

u16 Input register for reset/start of Energy

Accumulation

0x00DE PWM Control

8.1

R/W

u16 Input register for PWM On/Off and other PWM

Controls

0x00E0 No Load Threshold

5.6.1

u16 No Load Threshold for Energy Counting

Note 1: The registers are unsigned, however their sign is kept as a separate bit in the System Status Register.

2: These registers are reserved for EMI filter compensation when necessary for power supply monitoring.

They may require specific adjustment depending on PSU parameters, please contact the local Microchip

office for further support.

3: The Overtemperature event is only available on system versions 0xFA14 and later.

 2015 Microchip Technology Inc.

DS20005393B-page 31

MCP39F511

6.2

Address Pointer Register

This unsigned 16-bit register contains the address to

which all read and write instructions occur. This register

is only written through the Set Address Pointer

command and is otherwise outside the writable range

of register addresses.

6.3

System Status Register

The System Status register is a read-only register and

can be used to detect the various states of pin levels as

defined in Register 6-1.

REGISTER 6-1:

SYSTEM STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R-x

U-0

—

U-0

—

EVENT2

EVENT1

bit 15

bit 8

U-0

R-x

—

OVERTEMP

SIGN_PR

SIGN_PA OVERPOW

OVERCUR

VSURGE

VSAG

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11

Unimplemented: Read as ‘0’

EVENT2: State of Event2 Detection algorithm. This bit is latched and must be cleared.

1= Event 2 has occurred

0= Event 2 has not occurred

bit 10

EVENT1: State of Event1 Detection algorithm. This bit is latched and must be cleared.

1= Event 1 has occurred

0= Event 1 has not occurred

bit 9-7

bit 6

Unimplemented: Read as ‘0’

OVERTEMP: State of the Overtemperature Detection Algorithm

1= Overtemperature Threshold has been broken

0= Overtemperature Threshold has not been broken

bit 5

bit 4

bit 3

bit 2

SIGN_PR: Sign of Reactive Power

1= Reactive Power is positive, inductive and is in quadrants 1,2

0= Reactive Power is negative, is capacitive and is in quadrants 3,4

SIGN_PA: Sign of Active Power (import/export sign of active power)

1= Active Power is positive (import) and is in quadrants 1,4

0= Active Power is negative (export) and is in quadrants 2,3

OVERPOW: State of Overpower detection algorithm. An Overpower event has occurred in the system.

1= Overpower threshold has been broken

0= Overpower threshold has not been broken

OVERCUR: State of the Overcurrent detection algorithm. An Overcurrent event has occurred in the

system.

1= Overcurrent threshold has been broken

0= Overcurrent threshold has not been broken

bit 1

VSURGE: State of Voltage Surge Detection algorithm. This bit is latched and must be cleared.

1= Surge threshold has been broken

0= Surge threshold has not been broken

DS20005393B-page 32

 2015 Microchip Technology Inc.

MCP39F511

REGISTER 6-1:

SYSTEM STATUS REGISTER

bit 0

VSAG: State of Voltage Sag Detection algorithm. This bit is latched and must be cleared.

1= Sag threshold has been broken

0= Sag threshold has not been broken

6.4

System Version Register

TABLE 6-2:

Gain

PGA CONFIGURATION

SETTING (Note 1)

The System Version register is hard-coded by

Microchip Technology Incorporated and contains

calculation engine date code information. The

System Version register is a date code in the YMDD

format, with year and month in hex, day in decimal (e.g.

0xFA14 = 2015, October 14th).

Gain

(dB)

V_INRange

(V)

PGA_CHn<2:0> (V/V)

0

1

0

1

0

1

0

1

0

1

2

0

±0.6

6

±0.3

4

12

18

24

30

±0.15

6.5

System Configuration Register

8

±0.075

±0.0375

±0.01875

The System Configuration register contains bits for the

following control:

16

32

• PGA setting

Note 1: This table is defined with V_REF= 1.2V.

The two undefined settings, 110and 111

are G=1.

• ADC Reset State

• ADC Shutdown State

• Voltage Reference Trim

• Single Wire Auto-Transmission

These options are described in the following sections.

6.5.1

PROGRAMMABLE GAIN

AMPLIFIERS (PGA)

The two Programmable Gain Amplifiers (PGAs) reside

at the front-end of each 24-bit Delta-Sigma ADC. They

have two functions:

• translate the common mode of the input from

A_GNDto an internal level between A_GNDand A_VDD

• amplify the input differential signal

The translation of the common mode does not change

the differential signal but enters the common mode so

that the input signal can be properly amplified.

The PGA block can be used to amplify very low signals,

but the differential input range of the Delta-Sigma

modulator must not be exceeded. The PGA is

controlled by the PGA_CHn<2:0> bits in Register 6-2

the System Configuration register. Table 6-2

represents the gain settings for the PGAs.

 2015 Microchip Technology Inc.

DS20005393B-page 33

MCP39F511

6.5.2

24-BIT ADC RESET MODE

(SOFT RESET MODE)

24-bit ADC Reset mode (also called Soft Reset) can

only be entered through setting high the

RESET<1:0> bits in the System Configuration Register

register. This mode is defined as the condition where

the converters are active but their output is forced to ‘0’.

6.5.3

ADC SHUTDOWN MODE

ADC Shutdown mode is defined as a state where the

converters and their biases are OFF, consuming only

leakage current. When the Shutdown bit is reset to ‘0’,

the analog biases will be enabled, as well as the clock

and the digital circuitry.

Each converter can be placed in Shutdown mode

independently. This mode is only available through

programming of the SHUTDOWN<1:0> bits in the

System Configuration Register register.

6.5.4

V_REFTEMPERATURE

COMPENSATION

If desired, the user can calibrate out the temperature

drift for ultra-low V_REFdrift.

The internal voltage reference comprises a proprietary

circuit and algorithm to compensate first-order and

second-order

temperature

coefficients.

The

compensation allows very low temperature coefficients

(typically 10 ppm/°C) on the entire range of

temperatures from -40°C to +125°C. This temperature

coefficient varies from part to part.

The temperature coefficient can be adjusted on each

part through the System Configuration Register

register. The default value of this register is set to 0x42.

The typical variation of the temperature coefficient of

the internal voltage reference, with respect to

VREFCAL register code, is shown in Figure 6-1.

60

50

40

30

20

10

0

64

128

192

256

VREFCAL Register Trim Code (decimal)

FIGURE 6-1:

V_REFTempco vs. VREFCAL

Trimcode Chart.

DS20005393B-page 34

 2015 Microchip Technology Inc.

MCP39F511

REGISTER 6-2:

SYSTEM CONFIGURATION REGISTER

U-0

—

U-0

—

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

PGA_CH1<2:0>

PGA_CH0<2:0>

bit 31

bit 24

R/W-0

R/W-1

R/W-0

R/W-1

U-0

R/W-0

VREFCAL<7:0>

R/W-0

bit 23

bit 16

R/W-1

R/W-0

SINGLE_WIRE

bit 8

1

ZCD_INV

ZCD_PULS ZCD_OUTPUT_DIS

—

UART<2:0>

bit 15

R/W-0

TEMPCOMP

bit 7

R/W-0

U-0

—

U-0

—

RESET<1:0>

SHUTDOWN<1:0>

VREFEXT

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-30

bit 29-27

Unimplemented: Read as ‘0’

PGA_CH1 <2:0>: PGA Setting for the current channel.

111= Reserved (Gain = 1)

110= Reserved (Gain = 1)

101= Gain is 32

100= Gain is 16

011= Gain is 8 (Default)

010= Gain is 4

001= Gain is 2

000= Gain is 1

bit 26-24

PGA_CH0 <2:0>: PGA Setting for the voltage channel.

111= Reserved (Gain = 1)

110= Reserved (Gain = 1)

101= Gain is 32

100= Gain is 16

011= Gain is 8 (Default)

010= Gain is 4

001= Gain is 2

000= Gain is 1

bit 23-16

bit 15-13

VREFCAL<n>: Internal voltage reference temperature coefficient register value (See Section 6.5.4

“V_REFTemperature Compensation” for complete description)

UART<2:0>: UART Baud Rate bits (Note 1)

111= 1200

110= 2400

101= 4800

100= 9600

011= 19200

010= 38400

001= 57600

000= 115200 (Default)

 2015 Microchip Technology Inc.

DS20005393B-page 35

MCP39F511

REGISTER 6-2:

SYSTEM CONFIGURATION REGISTER (CONTINUED)

bit 12

bit 11

bit 10

ZCD_INV: Zero Crossing Detection Output Inverse

1= ZCD is inverted

0= ZCD is not inverted (Default)

ZCD_PULS: Zero Crossing Detection Pulse mode

1= ZCD output is 100 µs pulses on zero crossings

0= ZCD Output changes logic state on zero crossings (Default)

ZCD_OUTPUT_DIS: Disable the Zero Crossing output pin

1= ZCD output is disabled

0= ZCD output is enabled (Default)

bit 9

bit 8

Unimplemented: Read as ‘0’

SINGLE_WIRE: Single-Wire Enable bit

1= Single-wire transmission is enabled

0= Single-wire transmission is disabled (Default)

bit 7

TEMPCOMP: Temperature-Compensation Enable bit

1= Temperature compensation is enabled

0= Temperature compensation is disabled (Default)

bit 6-5

RESET <1:0>: Reset mode setting for ADCs

11= Both I1 and V1 are in Reset mode

10= V1 ADC is in Reset mode

01= I1 ADC is in Reset mode

00= Neither ADC is in Reset mode (Default)

bit 4-3

SHUTDOWN <1:0>: Shutdown mode setting for ADCs

11= Both I1 and V1 are in Shutdown

10= V1 ADC is in Shutdown

01= I1 ADC is in Shutdown

00= Neither ADC is in Shutdown (Default)

bit 2

VREFEXT: Internal Voltage Reference Shutdown Control

1= Internal Voltage Reference Disabled

0= Internal Voltage Reference Enabled (Default)

bit 1-0

Unimplemented: Read as ‘0’

Note 1: The UART Baud Rate bits are only available on system version 0xFA14 and later. Previous versions have

the baud rate fixed at 115200. The baud rate is only changed at system power-up, so a Save To Flash

command is required after changing the baud rate.

REGISTER 6-3:

ENERGY ACCUMULATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

ENRG_CNTRL

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bits 15-1

bit 0

Unimplemented: Read as ‘0‘

ENRG_CNTRL: Energy Accumulation Control bit

1= Energy is ON and all registers are accumulating

0= Energy accumulation is turned off and all energy accumulation registers are reset to 0 (Default)

DS20005393B-page 36

 2015 Microchip Technology Inc.

MCP39F511

The purpose of this register is two-fold: the number of

right-bit shifting (division by 2^RANGE) must be:

6.6

Range Register

The Range register is a 32-bit register that contains the

number of right-bit shifts for the following outputs,

divided into separate bytes defined below:

• high enough to prevent overflow in the output reg-

ister,

• low enough to allow for the desired output resolu-

tion.

• RMS Current

• RMS Voltage

It is the user’s responsibility to set this register correctly

to ensure proper output operation for a given meter

design.

• Power (Active, Reactive, Apparent)

Note that the Power Range Byte operates across both

the active and reactive output registers and sets the

same scale.

For further information and example usage, see

Section 9.3 “Single-Point Gain Calibrations at

Unity Power Factor”.

.

REGISTER 6-4:

RANGE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 31

bit 24

R/W-0

bit 23

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

POWER<7:0>

bit 16

R/W-0

bit 15

R/W-0

R/W-1

R/W-0

CURRENT<7:0>

bit 8

R/W-0

bit 7

R/W-1

R/W-0

VOLTAGE<7:0>

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 31-24

bit 23-16

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

POWER<7:0>: Sets the number of right-bit shifts for the Active and Reactive Power output registers

CURRENT<7:0>: Sets the number of right-bit shifts for the Current RMS output register

VOLTAGE<7:0>: Sets the number of right-bit shifts for the Voltage RMS output register

 2015 Microchip Technology Inc.

DS20005393B-page 37

MCP39F511

NOTES:

DS20005393B-page 38

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MCP39F511

7.2.2

VOLTAGE SAG AND VOLTAGE

SURGE DETECTION

7.0

7.1

EVENT OUTPUT PINS/EVENT

CONFIGURATION REGISTER

The event alarms for Voltage Sag and Voltage Surge

work differently compared to the Overcurrent and Over-

power events, which are tested against every computa-

tion cycle. These two event alarms are designed to

provide a much faster interrupt if the condition occurs.

Note that neither of these two events have a respective

Hold register associated with them, since the detection

time is less than one line cycle.

Event Pins

The MCP39F511 device has two event pins that can be

configured in three possible configurations. These

configurations are:

1. No event is mapped to the pin

2. Voltage Surge, Voltage Sag, Overcurrent, Over-

temperature or Overpower event is mapped to

the pin. More than one event can be mapped to

the same pin.

The calculation engine keeps track of a trailing mean

square of the input voltage, as defined by the following

equation:

3. Manual control of two pins, independently

EQUATION 7-1:

These three configurations allow for the control of

external interrupts or hardware that is dependent on

the measured power, current or voltage. The Event

Configuration Register below describes how these

events and pins can be configured.

2

2  f

0

LINE

V

= ------------------------- 

V



SA

n

f

SAMPLE

Note:

If an event is mapped to a pin, manual

control of the respective pin is not possible.

To enable manual control, no event has to

be mapped to the pin.

f

SAMPLE

n = – ------------------------- – 1

2  f

LINE

Therefore, at each data-ready occurrence, the value of

V_SAis compared to the programmable threshold set in

the Voltage Sag Limit register and Voltage Surge Limit

register to determine if a flag should be set. If either of

these events are masked to either the Event1 or

Event2 pin, a logic-high interrupt will be given on these

pins.

7.2

Limits

There are five limit registers associated with these

events:

• Overtemperature limit. The overtemperature

event is only available on system versions

0xFA14 and later.

The Sag or Surge events can be used to quickly

determine if a power failure has occurred in the system.

• Voltage Sag limit

• Voltage Surge limit

• Overcurrent limit

• Overpower limit

Each of these limits are compared to the respective

output registers of voltage, current and power. It is

recommended that they have the same unit for

comparison, e.g. 0.1V, or 0.01W.

7.2.1

OVERTEMPERATURE LIMIT

The Overtemperature Limit register is compared to the

10-bit SAR output (analog input voltage register) and is

a number between 0 and 1023.

When the threshold has been passed the

corresponding event flags and event pins (if mapped)

will be set.

 2015 Microchip Technology Inc.

DS20005393B-page 39

MCP39F511

REGISTER 7-1:

EVENT CONFIGURATION REGISTER

U-0

—

U-0

—

R/W-0

—

OVER-

OVERTEMP_CL^1,2OVERTEMP_LA¹OVERTEMP_T-

ST¹

TEMP_PIN2¹

TEMP_PIN1¹

bit 31

bit 24

R/W-0

OVER-

POW_PIN2

OVER-

CUR_PIN2

VSURGE_PIN

2

VSAG_PIN2

OVER-

POW_PIN1

OVERCUR_PIN1

VSURGE_PIN1

VSAG_PIN1

bit 23

U-0

bit 16

U-0

—

U-0

—

U-0

—

R/W-0

OVERCUR_CL²

R/W-0

OVERPOW_CL²

R/W-0

VSUR_CL²

R/W-0

—

VSAG_CL²

bit 15

bit 8

R/W-0

VSUR_LA

VSAG_LA

OVER-

OVERCUR_LA

VSUR_TST

VSAG_TST

OVERPOW_TST OVERCUR_TST

POW_LA

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bits 31-29 Unimplemented: Read as ‘0’

bit 28

bit 27

bit 26

bit 25

bit 24

bit 23

bit 22

bit 21

bit 20

OVERTEMP_PIN2: Event pin 2 operation for the Overtemperature event (Note 1)

1= Event mapped to Event2 pin only

0= Event not mapped to a pin (Default)

OVERTEMP_PIN1: Event pin 1 operation for the Overtemperature event (Note 1)

1= Event mapped to Event1 pin only

0= Event not mapped to a pin (Default)

OVERTEMP_CL: Reset or clear bit for the Overtemperature event (Notes 1, 2)

1= Event is cleared

0= Event is not cleared (Default)

OVERTEMP_LA: Latching control of the Overtemperature event (Note 1)

1= Event is latched and needs to be cleared to be reset

0= Event does not latch (Default)

OVERTEMP_TST: Test control of the Overtemperature event (Note 1)

1= Simulated event is turned on

0= Simulated event is turned off (Default)

OVERPOW_PIN2: Event pin 2 operation for the Overpower event

1= Event mapped to Event2 pin only

0= Event not mapped to a pin (Default)

OVERCUR_PIN2: Event pin 2 operation for the Overcurrent event

1= Event mapped to Event2 pin only

0= Event not mapped to a pin (Default)

VSURGE_PIN2: Event pin 2 operation for the Voltage Surge event

1= Event mapped to Event2 pin only

0= Event not mapped to a pin (Default)

VSAG_PIN2: Event pin 2 operation for the Voltage Sag event

1= Event mapped to Event2 pin only

0= Event not mapped to a pin (Default)

DS20005393B-page 40

 2015 Microchip Technology Inc.

MCP39F511

REGISTER 7-1:

EVENT CONFIGURATION REGISTER (CONTINUED)

bit 19

bit 18

bit 17

bit 16

OVERPOW_PIN1: Event pin 1 operation for the Overpower event

1= Event mapped to Event1 pin only

0= Event not mapped to a pin (Default)

OVERCUR_PIN1: Event pin 1 operation for the Overcurrent event

1= Event mapped to Event1 pin only

0= Event not mapped to a pin (Default)

VSURGE_PIN1: Event pin 1 operation for the Voltage Surge event

1= Event mapped to Event1 pin only

0= Event not mapped to a pin (Default)

VSAG_PIN1: Event pin 1 operation for the Voltage Sag event

1= Event mapped to Event1 pin only

0= Event not mapped to a pin (Default)

bits 15-12 Unimplemented: Read as ‘0’

OVERCUR_CL: Reset or clear bit for the Overcurrent event (Note 2)

bit 11

bit 10

bit 9

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

1= Event is cleared

0= Event is not cleared (Default)

OVERPOW_CL: Reset or clear bit for the Overpower event (Note 2)

1= Event is cleared

0= Event is not cleared (Default)

VSUR_CL: Reset or clear bit for the Voltage Surge event (Note 2)

1= Event is cleared

0= Event is not cleared (Default)

VSAG_CL: Reset or clear bit for the Voltage Sag event (Note 2)

1= Event is cleared

0= Event is not cleared (Default)

VSUR_LA: Latching control of the Voltage Surge event

1= Event is latched and needs to be cleared

0= Event does not latch (Default)

VSAG_LA: Latching control of the Voltage Sag event

1= Event is latched and needs to be cleared

0= Event does not latch (Default)

OVERPOW_LA: Latching control of the Overpower event

1= Event is latched and needs to be cleared

0= Event does not latch (Default)

OVERCUR_LA: Latching control of the Overcurrent event

1= Event is latched and needs to be cleared

0= Event does not latch (Default)

VSUR_TST: Test control of the Voltage Surge event

1= Simulated event is turned on

0= Simulated event is turned off (Default)

VSAG_TST: Test control of the Voltage Sag event

1= Simulated event is turned on

0= Simulated event is turned off (Default)

OVERPOW_TST: Test control of the Overpower event

1= Simulated event is turned on

0= Simulated event is turned off (Default)

OVERCUR_TST: Test control of the Overcurrent event

1= Simulated event is turned on

0= Simulated event is turned off (Default)

Note 1: The Overtemperature event bits (28-24) are only available on system versions 0xFA14 and later.

2: Writing a 1to the Clear bit clears the event, either real or simulated through test bits, and then returns to a

state of 0.

 2015 Microchip Technology Inc.

DS20005393B-page 41

MCP39F511

NOTES:

DS20005393B-page 42

 2015 Microchip Technology Inc.

MCP39F511

in the register, and the prescaler value is represented

by the least two significant bits. These two values

together create the PWM Period; see Figure 8-1.

8.0

8.1

PULSE WIDTH MODULATION

(PWM)

The 10-bit PWM Duty Cycle is controlled by a 16-bit

register where the most eight significant bits are the 8

MSB and the 2 LSB, corresponding to the 2 LSBs of the

10-bit value.

Overview

The PWM output pin gives up to a 10-bit resolution of a

pulse width modulated signal. The PWM output is con-

trolled by an internal timer inside the MCP39F511,

F_TIMERdescribed in this section, with a base frequency

of 16 MHz. The base period is defined as P_TIMERand

is 1/[16 MHz]. This 16 MHz time base is fixed due to the

4 MHz internal oscillator or 4 MHz external crystal.

An example of the register’s values are shown here

with 255 for PWM Frequency (8-bit value) and 1023 for

the Duty cycle (10-bit value), prescaler set to divide by

16 (1:0).

The output of the PWM is active only when the PWM

Control register has a value of 0x0001. The PWM out-

put is turned off when the register has a value of

0x0000.

Period

Prescaler

255

PWM PERIOD

(8-bit)

1111111100000010

PWM Period Register

The PWM output (Figure 8-2) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

MSB

LSB

1023

There are two registers that control the PWM output,

PWM Period and PWM Duty Cycle.

1111111100000011

PWM Duty Cycle Register

PWM DUTY

(10-bit)

The 8-bit PWM Period is controlled by a 16-bit register

that contains the period bits and also the prescaler bits.

The PWM Period bits are the most significant eight bits

FIGURE 8-1:

Duty-Cycle Registers.

PWM Period and

Period

Duty Cycle

FIGURE 8-2:

PWM Output.

 2015 Microchip Technology Inc.

DS20005393B-page 43

MCP39F511

8.2

PWM Period

The PWM period is specified by writing the PWM

Period bits of the PWM Period register. The PWM

period can be calculated using the following formula:

Equation 8-1:

PWM Period = [(PWM_Frequency) + 1] × 2 × P_TIMER× (Prescale Value)

The PWM Period is defined as 1/[PWM Frequency].

When P_TIMERis equal to PWM Period, the following

two events occur on the next increment cycle:

• the PWM timer is cleared

• the PWM pin is set. Exception: If the PWM Duty

Cycle equals 0%, the PWM pin will not be set.

8.3

PWM Duty Cycle

The PWM duty cycle is specified by writing to the PWM

Duty-Cycle register. Up to 10-bit resolution is available.

The PWM Duty-Cycle register contains the eight MSbs

and the two LSbs. The following equations are used to

calculate the PWM duty cycle as a percentage or as

time:

EQUATION 8-1:

PWM Duty Cycle (%) = (PWM_DUTY CYCLE>)/(4 × PWM_FREQUENCY)

PWM Duty Cycle (time in s) = (PWM_DUTY_CYCLE) × PWM_TIMER_PERIOD/2 × (Prescale Value)

PWM Duty Cycle can be written to at any time, but the

duty-cycle value is not latched until after a period is

complete.

The PWM registers and a two-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitch-less PWM

operation.

The maximum PWM resolution (bits) for a given PWM

frequency is shown in Equation 8-2.

EQUATION 8-2:

MAXIMUM PWM

RESOLUTION BASED ON

A FUNCTION OF PWM

FREQUENCY

2  F_TIMER





log -------------------------





F_PWM

= --------------------------------------- b i t s

log2

PWM Resolution (max)

Note:

If the PWM duty cycle value is longer than

the PWM period, the PWM pin will not be

cleared.

DS20005393B-page 44

 2015 Microchip Technology Inc.

MCP39F511

TABLE 8-2:

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS

WITH PWM_TIMER_FREQ = 16 MHz (DEFAULT)

PWM Frequency

1.95 kHz

31.25 kHz

62.5 kHz

125 kHz

2.67 MHz

4 MHz

Timer Prescaler

16

FFh

10

1

7Fh

9

1

3Fh

4

1

02h

3

1

01h

2

PWM Frequency Value

Maximum Resolution (bits)

FFh

10

REGISTER 8-1:

PWM PERIOD REGISTER

R/W-0

R/W-1

PWM_P<7:0>

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0 R/W-0

PRE<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-2

bit 1-0

PWM_P<7:0>: 8-bit PWM period value

Unimplemented: Read as ‘0‘

PRE<1:0>: PWM Prescaler

11= Unused

10= 1:16

01= 1:4

00= 1:1 (Default)

REGISTER 8-2:

PWM DUTY-CYCLE REGISTER

R/W-0

R/W-1

R/W-0

bit 8

DUTY<9:2>

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DUTY<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-2

bit 1-0

DUTY<9:2>: Upper 8 bits of 10-bit duty-cycle value

Unimplemented: Read as ‘0‘

DUTY<1:0>: Lower 2 bits of 10-bit duty-cycle value

 2015 Microchip Technology Inc.

DS20005393B-page 45

MCP39F511

REGISTER 8-3:

PWM CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

PWM_CNTRL

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bits 15-1

bit 0

Unimplemented: Read as ‘0‘

PWM_CNTRL: PWM Control

1= PWM is turned on

0= PWM is turned off (Default)

DS20005393B-page 46

 2015 Microchip Technology Inc.

MCP39F511

Setting the gain registers to properly produce the

desired outputs can be done manually by writing to the

appropriate register. The alternative method is to use

the auto-calibration commands described in this

section.

9.0

9.1

MCP39F511 CALIBRATION

Overview

Calibration compensates for ADC gain error,

component tolerances and overall noise in the system.

The device provides an on-chip calibration algorithm

that allows simple system calibration to be performed

quickly. The excellent analog performance of the

A/D converters on the MCP39F511 allows for a

9.3.1

USING THE AUTO-CALIBRATION

GAIN COMMAND

By applying stable reference voltages and currents that

are equivalent to the values that reside in the target

Calibration Current, Calibration Voltage and Calibration

Active Power registers, the Auto-Calibration

Gaincommand can then be issued to the device.

single-point calibration and

command to achieve accurate measurements.

a single calibration

Calibration can be done by either using the predefined

auto-calibration commands, or by writing directly to the

calibration registers. If additional calibration points are

required (AC offset, Phase Compensation, DC offset),

the corresponding calibration registers are available to

the user and will be described separately in this

section.

After a successful calibration (response = ACK), a

Save Registers to Flashcommand can then be

issued to save the calibration constants calculated by

the device.

The following registers are set when the

Auto-Calibration Gaincommand is issued:

• Gain Current RMS

• Gain Voltage RMS

• Gain Active Power

9.2

Calibration Order

The proper steps for calibration need to be maintained.

If the device has an external temperature sensor

attached, temperature calibration should be done first

by reading the value from the Thermistor Voltage

register and copying the value by writing to the Ambient

Temperature Reference Voltage register.

When this command is issued, the MCP39F511

attempts to match the expected values to the mea-

sured values for all three output quantities by changing

the gain register based on the following formula:

The single-point gain calibration at unity power factor

should be performed next.

EQUATION 9-1:

Expected

Measured

GAIN

= GAIN

 -------------------------

If nonunity displacement power factor measurements

are a concern, then the next step should be Phase

calibration, followed by Reactive Power Gain

calibration.

NEW

OLD

The same formula applies for Voltage RMS, Current

RMS and Active power. Since the gain registers for all

three quantities are 16-bit numbers, the ratio of the

expected value to the measured value (which can be

modified by changing the Range register) and the

previous gain must be such that the equation yields a

valid number. Here the limits are set to be from 25,000

to 65,535. A new gain within this range for all three

limits will return an ACK for a successful calibration,

otherwise the command returns a NAK for a failed

calibration attempt.

Here is a summary on the order of calibration steps:

1. Transfer of the ambient temperature value

during calibration to the Ambient Temperature

Calibration

register

for

temperature

compensation (optional)

2. Line Frequency Calibration

3. Gain Calibration at PF = 1

4. Phase Calibration at PF  1 (optional)

5. Reactive Gain Calibration at PF  1(optional)

It is the user’s responsibility to ensure that the proper

range settings, PGA settings and hardware design

settings are correct to allow for successful calibration

using this command.

Note:

Only needed if temperature compensation

is required. On system versions 0xFA14

and later this register transfer is done auto-

matically.

9.3

Single-Point Gain Calibrations at

Unity Power Factor

When using the device in AC mode with the high-pass

filters turned on, most offset errors are removed and

only a single-point gain calibration is required.

 2015 Microchip Technology Inc.

DS20005393B-page 47

MCP39F511

issue. The best approach is to choose a range value

that places the new gain in the middle of the bounds of

the gain registers described above.

9.3.2

EXAMPLE OF RANGE SELECTION

FOR VALID CALIBRATION

In this example, the user applies a calibration current

of 1A to an uncalibrated system. The indicated value

in the Current RMS register is 2300 with the system's

specific shunt value, PGA gain, etc. The user expects

to see a value of 1000 in the Current RMS register

when 1A current is applied, meaning 1.000A with

1 mA resolution. Other given values are:

In a second example, when applying 1A, the user

expects an output of 1.0000A with 0.1 mA resolution.

The example is starting with the same initial values:

EQUATION 9-4:

Expected

 --------------------------= 33480  --------------= 145565

OLD

10000

2300

GAIN

= GAIN

NEW

145565  65535

Measured

• the existing value for Gain Current RMS is 33480

• the existing value for Range is 12

By using Equation 9-1, the calculation for Gain_NEW

yields:

The Gain_NEWis much larger than the 16-bit limit of

65535, so fewer right-bit shifts must be introduced to

get the measured value closer to the expected value.

The user needs to compute the number of bit shifts

that will give a value lower than 65535. To estimate

this number:

EQUATION 9-2:

Expected

Measured

1000

2300

GAIN

= GAIN

 --------------------------= 33480  -----------= 14556

NEW

OLD

14556  25 000

EQUATION 9-5:

When using the Auto-Calibration Gain com-

mand, the result would be a failed calibration or a NAK

returned form the MCP39F511, because the resulting

Gain_NEWis less than 25,000.

145565

----------------- = 2.2

65535

2.2 rounds to the closest integer value of 2. The range

value changes to 12 – 2 = 10; there are 2 less right-bit

shifts.

The new measured value will be 2300 x 2²= 9200.

The solution is to use the Range register to bring the

measured value closer to the expected value, such

that a new gain value can be calculated within the

limits specified above.

The Range register specifies the number of right-bit

shifts (equivalent to divisions by 2) after the

multiplication with the Gain Current RMS register.

Refer to Section 5.0 “Calculation Engine (CE)

Description” for information on the Range register.

EQUATION 9-6:

Expected

 --------------------------= 33480  --------------= 36391

OLD

10000

9200

GAIN

= GAIN

NEW

Measured

25 000  36391  65535

Incrementing the Range register by 1 unit, an addi-

tional right-bit shift or ÷2 is included in the calculation.

Increasing the current range from 12 to 13 yields the

new measured Current RMS register value of 2300/2

= 1150. The expected (1000) and measured (1150)

are much closer now, so the expected new gain

should be within the limits:

The resulting new gain is within the limits and the

device successfully calibrates Current RMS and

returns an ACK.

EQUATION 9-3:

Expected

Measured

1000

1150

GAIN

= GAIN

 --------------------------= 33480  -----------= 29113

NEW

OLD

25 000  29113  65535

The resulting new gain is within the limits and the

device successfully calibrates Current RMS and

returns an ACK.

Notice that the range can be set to 14 and the result-

ing new gain will still be within limits

(Gain_NEW= 58226). However, since this gain value is

close to the limit of the 16-bit Gain register, variations

from system to system (component tolerances, etc.)

might create a scenario where the calibration is not

successful on some units and there would be a yield

DS20005393B-page 48

 2015 Microchip Technology Inc.

MCP39F511

9.4

Calibrating the Phase

Compensation Register

9.5

Offset/No-Load Calibrations

During offset calibrations, it is recommended that no

line voltage or current be applied to the system. The

system should be in a no-load condition.

Phase compensation is provided to adjust for any

phase delay between the current and voltage path.

This procedure requires sinusoidal current and voltage

waveforms, with a significant phase shift between

them, and significant amplitudes. The recommended

displacement power factor for calibration is 0.5. The

procedure for calculating the phase compensation

register is as follows:

9.5.1

AC OFFSET CALIBRATION

There are three registers associated with the AC Offset

Calibration:

• Offset Current RMS

• Offset Active Power

• Offset Reactive Power

1. Determine what the difference is between the

angle corresponding to the measured power

factor (PF_MEAS) and the angle corresponding to

the expected power factor (PF_EXP), in degrees.

When computing the AC offset values, the respective

gain and range registers should be taken into

consideration according to the block diagrams in

Figures 5-2 and 5-4.

EQUATION 9-7:

After

a

successful

offset

calibration,

a

Value in PowerFactor Register

PF_MEAS= --------------------------------------------------------------------------

32768

Save Registers to Flash command can then be

issued to save the calibration constants calculated by

the device.

180

ANGLE_MEAS = acosPF_MEAS  --------



180

ANGLE_EXP = acosPF_EXP  --------

9.5.2

DC OFFSET CALIBRATION



In DC applications, the high-pass filter on the current

and voltage channels is turned off. To remove any

residual DC value on the current, the DCOffsetCurrent

register adds to the A/D conversion immediately after

the ADC and prior to any other function.

2. Convert this from degrees to the resolution

provided in Equation 9-8:

EQUATION 9-8:

 = ANGLE

– ANGLE

  40

MEAS

EXP

9.6

Calibrating the Line Frequency

Register

3. Combine this additional phase compensation to

whatever value is currently in the phase

compensation, and update the register.

Equation 9-9 should be computed in terms of an

8-bit 2's complement-signed value. The 8-bit

result is placed in the least significant byte of the

16-bit Phase Compensation register.

The Line Frequency register contains a 16-bit number

with a value equivalent to the input-line frequency as it

is measured on the voltage channel. When in

DC mode, this calculation is turned off and the register

will be equal to zero.

The measurement of the line frequency is only valid

from 45 to 65 Hz.

EQUATION 9-9:

9.6.1

USING THE AUTO-CALIBRATE

FREQUENCY COMMAND

PhaseCompensation

= PhaseCompensation

+ 

OLD

NEW

By applying a stable reference voltage with a constant

line frequency that is equivalent to the value that

resides in the Line Frequency Ref, the

Auto-Calibrate Frequency command can then

be issued to the device.

Based on Equation 9-9, the maximum angle in degrees

that can be compensated is approximately ±3.2

degrees. If a larger phase shift is required, contact your

local Microchip sales office.

After a successful calibration (response = ACK), a

Save Registers to Flashcommand can then be

issued to save the calibration constants calculated by

the device.

The

following

register

is

set

when

the

Auto-Calibrate Frequency command is issued:

• Gain Line Frequency

Note that the command is only required when running

off the internal oscillator. The formula used to calculate

the new gain is shown in Equation 9-1.

 2015 Microchip Technology Inc.

DS20005393B-page 49

MCP39F511

9.7

Temperature Compensation

9.8

Retrieving Factory Default

Calibration Values

MCP39F511 measures the indication of the

temperature sensor and uses the value to compensate

the temperature variation of the shunt resistance and

the frequency of the internal RC oscillator.

After user calibration and a Save

to

Flash

command has been issued, it is possible to retrieve the

factory default calibration values. This can be done by

writing 0xA5A5 to the calibration delimiter register,

issuing a Save to Flash, and then resetting the part.

This procedure will retrieve all factory-default

calibration values and will remain in this state until

The same formula applies for Line Frequency, Current

RMS, Active Power and Reactive Power. The

temperature compensation coefficient depends on the

16-bit signed integer value of the corresponding

compensation register.

calibration has been performed again, and

Save to Flashcommand has been issued.

a

EQUATION 9-10:

y = x  1 + c  T – T



CAL

TemperatureCompensation Register

c = ----------------------------------------------------------------------------------------------

M

2

Where:

x

=

Uncompensated Output (corresponding to

Line Frequency, Current RMS, Active Power

and Reactive Power)

y

c

=

Compensated Output

Temperature

Compensation

Coefficient

(depending on the shunt's Temperature

Coefficient of Resistance or on the internal RC

oscillator temperature frequency drift). There

are three registers one for Line Frequency

compensation, one for Current compensation,

and one for power compensation (Active and

Reactive)

T

=

Thermistor Voltage (in 10-bit ADC units)

T

Ambient Temperature Reference Voltage. It

should be set at the beginning of the

calibration procedure, by reading the

thermistor voltage and writing its value to the

ambient temperature reference voltage

register.

CAL

M

=

26 (for Line Frequency compensation)

27 (for Current, Active Power and Reactive

Power)

At the calibration temperature, the effect of the com-

pensation coefficients is minimal. The coefficients need

to be tuned when the difference between the calibration

temperature and the device temperature is significant.

It is recommended to use the default values as starting

points.

DS20005393B-page 50

 2015 Microchip Technology Inc.

MCP39F511

There are three commands that support access to the

EEPROM array.

10.0 EEPROM

The data EEPROM is organized as 16-bit wide mem-

ory. Each word is directly addressable, and is readable

and writable across the entire V_DDrange. The

MCP39F511 has 256 16-bit words of EEPROM that is

organized in 32 pages for a total of 512 bytes.

• EEPROM Page Read(0x42)

• EEPROM Page Write(0x50)

• EEPROM Bulk Erase(0x4F)

TABLE 10-1: EXAMPLE EEPROM COMMANDS AND DEVICE RESPONSE

Command

Command ID BYTE 0

BYTE 1-N

# Bytes SuccessfulResponse

Page Read EEPROM

Page Write EEPROM

Bulk Erase EEPROM

0x42

0x50

0x4F

PAGE

PAGE + 16 BYTES OF DATA

None

2

18

1

ACK, Data, Checksum

ACK

TABLE 10-2: MCP39F511 EEPROM ORGANIZATION

Page

00

02

04

06

08

0A

0C

0E

0

0000

0010

0020

0030

0040

0050

0060

0070

0080

0090

00A0

00B0

00C0

00D0

00E0

00F0

0100

0110

0120

0130

0140

0150

0160

0170

0180

0190

01A0

01B0

01C0

01D0

01E0

01F0

FFFF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

 2015 Microchip Technology Inc.

DS20005393B-page 51

MCP39F511

NOTES:

DS20005393B-page 52

 2015 Microchip Technology Inc.

MCP39F511

11.0 PACKAGING INFORMATION

11.1 Package Marking Information

28-Lead QFN (5x5x0.9 mm)

Example

PIN 1

39F511

-E/MQ

020

e3

^^

1545256

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2015 Microchip Technology Inc.

DS20005393B-page 53

MCP39F511

28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

NOTE 1

1

2

(DATUM B)

(DATUM A)

2X

0.10 C

2X

TOP VIEW

0.10 C

A1

C

A

SEATING

PLANE

28X

A3

0.08 C

0.10

SIDE VIEW

C A B

0.10

D2

C A B

E2

28X K

2

1

NOTE 1

28X L

N

28X b

0.10

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing C04-140C Sheet 1 of 2

DS20005393B-page 54

 2015 Microchip Technology Inc.

MCP39F511

28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Pins

Pitch

Overall Height

Standoff

Contact Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

N

28

0.50 BSC

0.90

e

A

A1

A3

E

E2

D

D2

b

L

0.80

0.00

1.00

0.05

0.02

0.20 REF

5.00 BSC

3.25

5.00 BSC

3.25

0.25

0.40

-

3.15

3.35

3.15

0.18

0.35

0.20

3.35

0.30

0.45

-

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-140C Sheet 2 of 2

 2015 Microchip Technology Inc.

DS20005393B-page 55

MCP39F511

28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern

With 0.55 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Microchip Technology Drawing C04-2140A

DS20005393B-page 56

 2015 Microchip Technology Inc.

MCP39F511

APPENDIX A: REVISION HISTORY

Revision B (December 2015)

The following is the list of modifications:

• Document conforms to system version 0xFA14

• Overtemperature event added

• Selectable baud rate bits added to Register 6-2:

System Configuration Register

• Various typographical edits

Revision A (March 2015)

• Original release of this document

 2015 Microchip Technology Inc.

DS20005393B-page 57

MCP39F511

NOTES:

DS20005393B-page 58

 2015 Microchip Technology Inc.

MCP39F511

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(1)

PART NO.

Device

[X]

X

/XX

Examples:

a) MCP39F511-E/MQ:

Extended temperature,

28LD 5x5 QFN package

Tape and Temperature Package

Reel

Range

b) MCP39F511T-E/MQ: Tape and Reel,

Extended temperature,

28LD 5x5 QFN package

Device:

MCP39F511: Power-Monitoring IC with Calculation and

Energy Accumulation

Tape and Reel Option: Blank

= Standard packaging (tube or tray)

T

= Tape and Reel ⁽¹⁾

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This identi-

fier is used for ordering purposes and is not

printed on the device package. Check with

your Microchip sales office for package

availability for the Tape and Reel option.

Temperature Range:

Package:

E

= -40°C to +125°C

MQ = Plastic Quad Flat, No Lead Package – 5x5x0.9 mm

body (QFN), 28-lead

 2015 Microchip Technology Inc.

DS20005393B-page 59

MCP39F511

NOTES:

 2015 Microchip Technology Inc.

DS20005393B-page 60

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

32

OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,

Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-0068-4

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2015 Microchip Technology Inc.

DS20005393B-page 61

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

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Tel: 33-1-69-53-63-20

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Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

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Tel: 91-11-4160-8631

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Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

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Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

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Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

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Taiwan - Kaohsiung

Tel: 886-7-213-7828

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Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

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Tel: 66-2-694-1351

Fax: 66-2-694-1350

Canada - Toronto

Tel: 905-673-0699

Fax: 905-673-6509

07/14/15

DS20005393B-page 62

 2015 Microchip Technology Inc.


型号：	MCP39F511-E/MQ
厂家：	MICROCHIP
描述：	Power-Monitoring IC with Calculation and Energy Accumulation 监控
文件：	总62页 (文件大小：1070K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP39F511-E/MQ [MICROCHIP]

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