MT48V16M16LFFG [MICRON]
MOBILE SDRAM; 移动SDRAM
| 型号： | MT48V16M16LFFG |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | MOBILE SDRAM |
| 文件： | 总58页 (文件大小：1441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE‡
256Mb: x16
MOBILE SDRAM
MT48V16M16LFFG, MT48H16M16LFFG–
4 Meg x 16 x 4 banks
MOBILE SDRAM
For the latest data sheet revisions, please refer to the Micron
Website:www.micron.com/dramds
FEATURES
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on
positive edge of system clock
PINASSIGNMENT(TopView)
54-BallFBGA
• Internal pipelined operation; column address can
be changed every clock cycle
1
2
3
4
5
6
7
8
9
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
A
B
C
D
E
V
SS
DQ15
V
SS
Q
V
DDQ
DQ0
V
DD
DQ14 DQ13
DQ12 DQ11
V
DD
Q
VSSQ
DQ2
DQ4
DQ6
LDQM
RAS\
BA1
A1
DQ1
DQ3
DQ5
DQ7
WE\
CS\
V
SS
Q
VDDQ
DQ10
DQ8
DQ9
NC
V
DD
Q
VSSQ
V
SS
VDD
• Deep Power Down
• Partial Array Self Refresh power-saving mode
• Industrial operating temperature (-40oC to +85oC)
F
UDQM
NC/A12
A8
CK
CKE
A9
CAS\
BA0
A0
G
H
J
A11
A7
OPTIONS
• VDD/VDDQ
MARKING
A6
A10
VDD
2.5V/1.8V
V
1.8V/1.8V
H
V
SS
A5
A4
A3
A2
• Configurations
16 Meg x 16 (4 Meg x 16 x 4 banks)
• WRITE Recovery (tWR/tDPL)
tWR = 2 CLK
16M16
FG1
• Plastic Packages – OCPL1
54-ball FBGA (8mm x 14mm)
• Timing (Cycle Time)
8.0ns @ CL = 3 (125MHz)
10ns @ CL = 3 (100MHz)
16 Meg x 16
4Megx16x4banks
8K
Configuration
Refresh Count
-8
-10
Row Addressing
BankAddressing
ColumnAddressing
8K(A0–A12)
4 (BA0, BA1)
512(A0–A8)
NOTE: 1. See page 58 for FBGA Device Marking Table.
KEYTIMINGPARAMETERS
256Mb SDRAM PART NUMBERS
SPEED
CLOCK
ACCESSTIME
SETUP HOLD
PARTNUMBER
ARCHITECTURE
16 Meg x 16
16 Meg x 16
VDD
2.5V
1.8V
GRADE FREQUENCY CL=1* CL=2* CL=3* TIME TIME
MT48V16M16LFFG
MT48H16M16LFFG
-8
-10
-8
125MHz
100MHz
100MHz
83MHz
50 MHz
40 MHz
–
–
–
–
7ns
7ns
–
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
–
8ns
8ns
–
-10
-8
–
–
19ns
22ns
–
-10
–
–
*CL = CAS (READ) latency
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
1
‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.
ADVANCE
256Mb: x16
MOBILE SDRAM
256Mb SDRAM PART NUMBERS
PART NUMBER
VDD/VDDQ
ARCHITECTURE
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
PACKAGE
MT48V16M16LFFG-10
MT48V16M16LFFG-8
MT48H16M16LFFG-10
MT48H16M16LFFG-8
2.5V / 1.8V
2.5V / 1.8V
1.8V / 1.8V
1.8V / 1.8V
54-BALL FBGA
54-BALL FBGA
54-BALL FBGA
54-BALL FBGA
GENERALDESCRIPTION
The 256Mb SDRAM uses an internal pipelined ar-
chitecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
The 256Mb SDRAM is designed to operate in 2.5V
and 1.8V memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
The 256Mb SDRAM is a high-speed CMOS,
dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 67,108,864-bit banks is orga-
nized as 8,192 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank; A0–A12 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
2
ADVANCE
256Mb: x16
MOBILE SDRAM
TABLEOFCONTENTS
Functional Block Diagram – 16 Meg x 16 ..................
54-Ball FBGA Pin Description ....................................
4
5
Truth Table 2 (CKE) ...................................................... 27
Truth Table 3 (Current State, Same Bank) ...................... 28
Truth Table 4 (Current State, Different Bank) ................. 30
Absolute Maximum Ratings ....................................... 32
DC Electrical Characteristics
Functional Description ...............................................
Initialization ...........................................................
Register Definition ................................................
Mode Register ...................................................
Burst Length ................................................
Burst Type ...................................................
CAS Latency ................................................
Operating Mode ..........................................
Write Burst Mode ........................................
Extended Mode Register ...........................
Temperature Compensated Self Refresh
6
6
6
6
6
7
8
8
8
9
9
and Operating Conditions ..................................... 32
Capacitance.................................................................. 33
AC Electrical Characteristics (Timing Table) ......... 33
IDD Specifications and Conditions ............................. 35
Timing Waveforms
Initialize and Load mode register ........................ 37
Power-Down Mode ................................................ 38
Clock Suspend Mode ............................................ 39
Auto Refresh Mode ................................................ 40
Self Refresh Mode .................................................. 41
Reads
Partial Array Self Refresh ........................... 10
Deep Power Down ...................................... 10
Driver Strength ........................................... 10
Commands ................................................................... 11
TruthTable1(CommandsandDQMOperation) .............. 11
Command Inhibit .................................................. 12
No Operation (NOP) .............................................. 12
Load mode register ................................................ 12
Active ....................................................................... 12
Read ....................................................................... 12
Write ....................................................................... 12
Precharge ................................................................ 12
Auto Precharge ....................................................... 12
Auto Refresh ........................................................... 12
Self Refresh ............................................................. 13
Operation ..................................................................... 14
Bank/Row Activation ............................................. 14
Reads ....................................................................... 15
Writes ....................................................................... 21
Precharge ................................................................ 23
Power-Down ........................................................... 23
Deep Power-Down ................................................ 24
Clock Suspend........................................................ 24
Burst Read/Single Write ....................................... 24
Concurrent Auto Precharge ................................. 25
Read – Without Auto Precharge ..................... 42
Read – With Auto Precharge ........................... 43
Single Read – Without Auto Precharge ......... 44
Single Read – With Auto Precharge ............... 45
Alternating Bank Read Accesses .................... 46
Read – Full-Page Burst .................................... 47
Read – DQM Operation ................................... 48
Writes
Write – Without Auto Precharge..................... 49
Write – With Auto Precharge ........................... 50
Single Write - Without Auto Precharge ......... 51
Single Write - Without Auto Precharge ......... 52
Alternating Bank Write Accesses ................... 53
Write – Full-Page Burst .................................... 54
Write – DQM Operation ................................... 55
Package Dimensions
54-pin FBGA ............................................................ 56
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
3
ADVANCE
256Mb: x16
MOBILE SDRAM
FUNCTIONALBLOCKDIAGRAM
16 Meg x 16 SDRAM
CKE
CLK
CONTROL
LOGIC
CS#
WE#
BANK3
BANK2
CAS#
RAS#
BANK1
REFRESH
COUNTER
13
MODE REGISTER
12
BANK0
ROW-
ADDRESS
LATCH
&
ROW-
ADDRESS
MUX
13
BANK0
MEMORY
ARRAY
2
2
8192
DQML,
DQMH
13
(8,192 x 512 x 16)
DECODER
DATA
OUTPUT
REGISTER
SENSE AMPLIFIERS
8192
16
DQ0-
16
I/O GATING
2
DQ15
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
A0-A12,
BA0, BA1
ADDRESS
REGISTER
15
DATA
INPUT
REGISTER
2
16
512
(x16)
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
9
9
256Mb: x16MobileSDRAM
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©2002,MicronTechnology,Inc.
4
ADVANCE
256Mb: x16
MOBILE SDRAM
BALLDESCRIPTIONS
54-BALL FBGA
SYMBOL
TYPE
DESCRIPTION
F2
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter
and controls the output registers.
F3
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
DeactivatingtheclockprovidesPRECHARGEPOWER-DOWNandSELFREFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
G9
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
consideredpartofthecommandcode.
F7, F8, F9
E8, F1
CAS#, RAS#,
WE#
Input
Input
Command Inputs: CAS#, RAS#, and WE#(along with CS#) define the
commandbeingentered.
LDQM,
UDQM
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z state
(two-clocklatency)whenduringaREADcycle. LDQMcorrespondstoDQ0–DQ7,
UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered same
state when referenced as DQM.
G7, G8
BA0, BA1
A0–A12
Input
Input
BankAddressInput(s):BA0andBA1definetowhichbanktheACTIVE, READ,
WRITEor PRECHARGE command is being applied. These pins also provide the
op-codeduringaLOADMODEREGISTERcommand
H7, H8, J8, J7, J3, J2,
H3, H2, H1, G3, H9, G2,G1
AddressInputs:A0–A12aresampledduringtheACTIVEcommand(row-
addressA0–A12)andREAD/WRITEcommand(column-addressA0–A8;withA10
defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW).
The address inputs also provide the op-code during a LOAD MODE REGISTER
command.
A8, B9, B8, C9, C8, D9,
D8, E9, E1, D2, D1, C2,
C1, B2, B1, A2
DQ0–DQ15
I/O
–
DataInput/Output:Databus
E2,
NC
NoConnect:Thispinshouldbeleftunconnected.
A7, B3, C7, D3
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply PowerSupply:Voltagedependantonoption.
A3, B7, C3, D7,
A9, E7, J9
VSSQ
VDD
A1, E3, J1
VSS
Supply Ground.
256Mb: x16MobileSDRAM
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
MobileRamY26L_A.p65–Pub.5/02
©2002,MicronTechnology,Inc.
5
ADVANCE
256Mb: x16
MOBILE SDRAM
FUNCTIONALDESCRIPTION
REGISTERDEFINITION
In general, the 256Mb SDRAMs (4 Meg x 16 x 4 banks)
are quad-bank DRAMs that operate at 2.5V or 1.8V and
include a synchronous interface (all signals are regis-
tered on the positive edge of the clock signal, CLK).
Each of the x16’s 67,108,864-bit banks is organized as
8,192 rows by 512 columns by 16 bits.
Mode Register
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode and a write burst mode, as
shown in Figure 1. The mode register is programmed
via the LOAD MODE REGISTER command and will re-
tain the stored information until it is programmed again
or the device loses power.
Mode register bits M0–M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10, M11, and M12 should be set to zero.
M13and M14 should be set to zero to prevent extended
mode reister.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A12 select the row). The address
bits ( x16: A0–A8) registered coincident with the READ
or WRITE command are used to select the starting col-
umn location for the burst access.
The mode register must be loaded when all banks
are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
Prior to normal operation, the SDRAM must be ini-
tialized. The following sections provide detailed infor-
mation covering device initialization, register defini-
tion, command descriptions and device operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 1. The burst length determines the
maximum number of column locations that can be ac-
cessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-
page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to VDD and VDDQ (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than
a
COMMAND INHIBIT or NOP. CKE must be held high
during the entire initialization period until the
PRECHARGE command has been issued. Starting at
some point during this 100µs period and continuing at
least through the end of this period, COMMAND IN-
HIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at
least one COMMAND INHIBIT or NOP command hav-
ing been applied, a PRECHARGE command should be
applied. All banks must then be precharged, thereby
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1–A8 (x16) when the burst length is set to
two; by A2–A8 (x16) when the burst length is set to four;
and by A3–A8 (x16) when the burst length is set to
eight. The remaining (least significant) address bit(s)
is (are) used to select the starting location within the
block. Full-page bursts wrap within the page if the
boundary is reached.
256Mb: x16MobileSDRAM
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6
ADVANCE
256Mb: x16
MOBILE SDRAM
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.
Table 1
Burst Definition
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
A0
0
1
0-1
1-0
0-1
1-0
2
4
A1 A0
Figure 1
Mode Register Definition
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Address Bus
A10
A7
A3 A2
A0
BA0
A9
A8
A6 A5 A4
A1
BA1
A12 A11
A2 A1 A0
14 13
12
11
9
8
7
6
5
4
1
10
3
2
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Mode Register (Mx)
Reserved**
Reserved*
WB Op Mode CAS Latency
BT
Burst Length
8
Burst Length
*Should program
M12, M11, M10 = 0, 0, 0
to ensure compatibility
with future devices.
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
Full
Page
(y)
n=A0-8
8
** BA1, BA0 = 0, 0
to prevent Extended
Mode Register.
NotSupported
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
(location0-y)
Cn…
NOTE: 1. For full-page accesses: y = 512 (x16)
2. For a burst length of two, A1-A8 (x16) select the
block-of-two burst; A0 selects the starting column
within the block.
Burst Type
M3
0
Sequential
Interleaved
3. For a burst length of four, A2-A8 (x16) select the
block-of-four burst; A0-A1 select the starting
column within the block.
4. For a burst length of eight, A3-A8 (x16) select the
block-of-eight burst; A0-A2 select the starting
column within the block.
5. For a full-page burst, the full row is selected and
A0-A8 (x16) select the starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A8 (x16) select the
unique column to be accessed, and mode register
bit M3 is ignored.
1
CAS Latency
M6 M5 M4
Reserved
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
Reserved
Reserved
Reserved
Reserved
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
-
-
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
256Mb: x16MobileSDRAM
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ADVANCE
256Mb: x16
MOBILE SDRAM
CAS Latency
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
The CAS latency is the delay, in clock cycles, be-
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to two or three clocks.
Operating Mode
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 2. Table 2 below indicates the operat-
ing frequencies at which each CAS latency setting can
be used.
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-
M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.
Figure 2
CAS Latency
Table 2
T0
T1
T2
T3
T4
T5
CAS Latency
CLK
ALLOWABLE OPERATING
FREQUENCY (MHz)
READ
NOP
NOP
NOP
READ
NOP
COMMAND
X = 0 cycles
CAS
CAS
CAS
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3
D
OUT
D
n + 1
OUT
D
n + 2
OUT
DOUT
D
OUT
n
n + 3
b
- 8
≤ 50
≤ 40
≤ 100
≤ 83
≤ 125
≤ 100
CAS Latency = 1
T0
- 10
T1
T2
T3
T4
T5
T6
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
COMMAND
X = 1 cycle
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
D
n + 1
OUT
DOUT
D
n + 3
OUT
D
OUT
n
n + 2
b
CAS Latency = 2
T1
T0
T2
T3
T4
T5
T6
T7
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
COMMAND
X = 2 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
DOUT
D
n + 2
OUT
D
n + 3
OUT
DOUT
b
n
n + 1
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
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MOBILE SDRAM
EXTENDEDMODEREGISTER
BA1 BA0 A12 A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Extended Mode
Register (Ex)
1
0
All have to be set to "0" DS TCSR
PASR
A4 A3 Maximum Case Temp
1
0
1
0
85˚C
70˚C
A5 Driver Strength
Half Strength
Full Strength
0
1
0
1
1
0
45˚C
15˚C
A2
0
A1
0
A0
0
Self Refresh Coverage
Four Banks
0
0
1
Two Banks (BA1=0)
One Bank (BA1=BA0=0)
RFU
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
RFU
Half Bank (BA1=BA0=0)
Quarter Bank (BA1=BA0=0)
RFU
1
1
1
NOTE: 1. E14 and E13 (BA1 and BA0) must be “1, 0” to select the
Extended Mode Register (vs. the base Mode Register).
TEMPERATURE COMPENSATED SELF REFRESH
EXTENDED MODE REGISTER
Temperature Compensated Self Refresh allows the
controller to program the Refresh interval during SELF
REFRESH mode, according to the case temperature of
the BATRAM device. This allows great power savings
during SELF REFRESH during most operating tempera-
ture ranges. Only during extreme temperatures would
the controller have to select a TCSR level that will guar-
antee data during SELF REFRESH.
Every cell in the DRAM requires refreshing due to
the capacitor losing its charge over time. The refresh
rate is dependent on temperature. At higher tempera-
tures a capacitor loses charge quicker than at lower
temperatures, requiring the cells to be refreshed more
often. Historically, during Self Refresh, the refresh rate
has been set to accomodate the worst case, or highest
temperature range expected.
The Extended Mode Register controls the functions
beyond those controlled by the Mode Register. These
additional functions are special features of the
BATRAM device. They include Temperature Compen-
sated Self Refresh (TCSR) Control, and Partial Array
Self Refresh (PASR).
The Extended Mode Register is programmed via
the Mode Register Set command (BA1=1,BA0=0) and
retains the stored information until it is programmed
again or the device loses power.
The Extended Mode Register must be programmed
with M6 through M12 set to “0”. The Extended Mode
Register must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time before before initiating any subsequent
operation. Violating either of these requirements re-
sults in unspecified operation.
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MOBILE SDRAM
Thus, during ambiant temperatures, the power con-
sumed during refresh was unnecessarily high, because
the refresh rate was set to accommodate the higher
temperatures. Setting M4 and M3, allow the DRAM to
accomodate more specific temperature regions during
SELF REFRESH. There are four temperature settings,
which will vary the SELF REFRESH current according to
the selected temperature. This selectable refresh rate
will save power when the DRAM is operating at normal
temperatures.
DEEP POWER DOWN
Deep Power Down is an operating mode to achieve
maximum power reduction by eliminating the power
of the whole memory array of the devices. Data will not
be retained once the device enters Deep Power Down
Mode.
This mode is entered by having all banks idle then
/CS and /WE held low with /RAS and /CAS held high at
the rising edge of the clock, while CKE is low. This mode
is exited by asserting CKE high.
PARTIAL ARRAY SELF REFRESH
DRIVER STRENGTH
For further power savings during SELF REFRESH,
the PASR feature allows the controller to select the
amount of memory that will be refreshed during SELF
REFRESH. The refresh options are Four Bank;all four
banks, Two Bank;banks 0 and 1, One Bank;bank 0, Half
Bank; bank 0 with row address MSB 0; Quarter Bank;
bank 0 with row address 2 MSB’s 0. WRITE and READ
commands can still occur during standard operation,
but only the selected banks will be refreshed during
SELF REFRESH. Data in banks that are disabled will be
lost.
Bit A5 of the extended mode register can be used to
select the driver strength of the DQ outputs. This value
should be set according to the applications require-
ments. Full drive strength is suitable to drive outputs
on systems in which the SDRAM component is placed
on a module. Full drive strength will drive loads up to
50pF.
The half-drive strength can be used for point-to-
point applications. Point-to-point systems are usually
lightly loaded with a memory controller accessing one
to eight SDRAM components on the memory bus with
module stubs between these devices. Driver strength
chosen should be load dependent. The lighter the load,
the less driver strength that is needed for the outputs.
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MOBILE SDRAM
Commands
Truth Table 1 provides a quick reference of
Truth Tables appear following the Operation section;
these tables provide current state/next state
information.
available commands. This is followed by a written de-
scription of each command. Three additional
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Notes: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQM
ADDR
X
DQs NOTES
COMMAND INHIBIT (NOP)
H
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
NO OPERATION (NOP)
X
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
DEEP POWER DOWN
X
Bank/Row
Bank/Col
X
X
3
4
8
8
H
H
H
L
L/H
L/H
X
L
Bank/Col Valid
4
H
H
L
L
X
Code
X
Active
9
PRECHARGE (Deactivate row in bank or banks)
L
X
X
X
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L
H
X
6, 7
LOAD MODE REGISTER
L
–
L
–
–
L
–
–
L
–
–
X
L
Op-Code
X
2
8
8
Write Enable/Output Enable
Write Inhibit/Output High-Z
–
–
Active
High-Z
–
H
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register, and A12 should be driven LOW.
3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A8 (x16)provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW
disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
9. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate
command is assigned to the Deep Power Down function.
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MOBILE SDRAM
COMMAND INHIBIT
inputs A0-A8 (x16) selects the starting column location.
The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of
the WRITE burst; if auto precharge is not selected, the
row will remain open for subsequent accesses. Input
data appearing on the DQs is written to the memory
array subject to the DQM input logic level appearing
coincident with the data. If a given DQM signal is regis-
tered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, re-
gardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already
in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations already
in progress are not affected.
LOAD MODE REGISTER
PRECHARGE
The mode register is loaded via inputs A0-A12 (A13
and A14 should be driven LOW to prevent Extended
Mode Register.) See mode register heading in the Reg-
ister Definition section. The LOAD MODE REGISTER
command can only be issued when all banks are idle,
and a subsequent executable command cannot be is-
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0,
BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
t
sued until MRD is met.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before open-
ing a different row in the same bank.
AUTO PRECHARGE
Auto precharge is a feature which performs the
same individual-bank PRECHARGE function de-
scribed above, without requiring an explicit command.
This is accomplished by using A10 to enable auto
precharge in conjunction with a specific READ or WRITE
command. A PRECHARGE of the bank/row that is ad-
dressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode, where
AUTO PRECHARGE does not apply. Auto precharge is
nonpersistent in that it is either enabled or disabled for
each individual READ or WRITE command.
Auto precharge ensures that the precharge is initi-
ated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (tRP) is completed. This is
determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described
for each burst type in the Operation section of this data
sheet.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A8 (x16) selects the starting column location.
The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data
appears on the DQs subject to the logic level on the
DQM inputs two clocks earlier. If a given DQM signal
was registered HIGH, the corresponding DQs will be
High-Z two clocks later; if the DQM signal was regis-
tered LOW, the DQs will provide valid data.
WRITE
AUTO REFRESH
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
AUTO REFRESH is used during normal operation of
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This
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MOBILE SDRAM
command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be
precharged prior to issuing an AUTO REFRESH com-
mand. The AUTO REFRESH command should not be
issued until the minimum RP has been met after the
PRECHARGE command as shown in the operations sec-
tion.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 256Mb
SDRAM requires 8,192 AUTO REFRESH cycles every
64ms (tREF), regardless of width option. Providing a
distributed AUTO REFRESH command every 7.81µs
will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 8,192 AUTO REFRESH
commands can be issued in a burst at the minimum
cycle rate (tRC), once every 64ms.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become “Don’t Care” with
the exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
tRAS and may remain in self refresh mode for an indefi-
nite period beyond that.
The procedure for exiting self refresh requires a se-
quence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
tXSR because time is required for the completion of any
internal refresh in progress.
t
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 7.81µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
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256Mb: x16
MOBILE SDRAM
Operation
Figure 3
Activating a Specific Row in a
Specific Bank
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be is-
sued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated (see Figure 3).
CLK
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
CKE
CS#
HIGH
t
t
subject to the RCD specification. RCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a tRCD specifi-
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 4,
RAS#
t
which covers any case where 2 < RCD (MIN)/tCK ≤ 3.
CAS#
WE#
(The same procedure is used to convert other specifi-
cation limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
ROW
ADDRESS
t
A0-A12
mands to the same bank is defined by RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
tRRD.
BANK
ADDRESS
BA0, BA1
DON’T CARE
Figure 4
Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK 3
t
t
t
<
T0
T1
T2
T3
T4
CLK
READ or
WRITE
COMMAND
ACTIVE
NOP
NOP
t
RCD
DON’T CARE
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MOBILE SDRAM
READs
READ bursts are initiated with a READ command,
as shown in Figure 5.
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to the start address and
continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last ele-
ment of a completed burst or the last desired data ele-
ment of a longer burst that is being truncated. The new
READ command should be issued x cycles before the
clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one.
The starting column and bank addresses are pro-
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
each possible CAS latency setting.
Figure 5
READ Command
Figure 6
CAS Latency
CLK
CKE
CLK
CKE
CS#
HIGH
CONTROL
LOGIC
CS#
WE#
BANK3
CAS#
RAS#
BANK2
BANK1
REFRESH
COUNTER
13
MODE REGISTER
12
BANK0
ROW-
ADDRESS
LATCH
&
ROW-
ADDRESS
MUX
13
BANK0
MEMORY
ARRAY
x 256 x 32)
4
4
8192
DQM0-
DQM3
13
(8,192
DECODER
DATA
OUTPUT
REGISTER
SENSE AMPLIFIERS
8192
RAS#
32
DQ0-
DQ31
I/O GATING
2
32
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
A0-A12,
BA0, BA1
ADDRESS
REGISTER
15
DATA
INPUT
REGISTER
2
32
256
(x32)
CAS#
WE#
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
8
8
COLUMN
ADDRESS
A0-A8: x16
A9, A11: x16
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A10
BANK
ADDRESS
BA0,1
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This is shown in Figure 7 for CAS latencies of two and
three; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. The 256Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-
speed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
Figure 7
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
CLK
READ
NOP
NOP
NOP
READ
NOP
COMMAND
X = 0 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
D
n + 1
OUT
D
n + 2
OUT
DOUT
D
OUT
n
n + 3
b
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
COMMAND
X = 1 cycle
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
D
n + 1
OUT
DOUT
D
n + 3
OUT
D
OUT
n
n + 2
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
COMMAND
X = 2 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
DOUT
D
n + 2
OUT
D
n + 3
OUT
DOUT
b
n
n + 1
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
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MOBILE SDRAM
Figure 8
Random READ Accesses
T0
T1
T2
T3
T4
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
D
OUT
D
OUT
D
OUT
D
OUT
n
a
x
m
CAS Latency = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
D
OUT
D
OUT
D
OUT
D
OUT
n
a
x
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
READ
READ
READ
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
D
OUT
D
OUT
D
OUT
D
OUT
n
a
x
m
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
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MOBILE SDRAM
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by
data from a WRITE command (subject to bus turn-
around limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or last
desired) data element from the READ burst, provided
that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driv-
ing the input data will go Low-Z before the SDRAM DQs
go High-Z. In this case, at least a single-cycle delay
should occur between the last read data and the WRITE
command.
buffers) to suppress data-out from the READ. Once the
WRITE command is registered, the DQs will go High-Z
(or remain High-Z), regardless of the state of the DQM
signal; provided the DQM was active on the clock just
prior to the WRITE command that truncated the READ
command. If not, the second WRITE will be an invalid
WRITE. For example, if DQM was LOW during T4 in
Figure 10, then the WRITEs at T5 and T7 would be
valid, while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency al-
lows for bus contention to be avoided without adding a
NOP cycle, and Figure 10 shows the case where the
additional NOP is needed.
The DQM input is used to avoid I/O contention, as
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output
Figure 10
Figure 9
READ to WRITE With
Extra Clock Cycle
READ to WRITE
T0
T1
T2
T3
T4
CLK
T0
T1
T2
T3
T4
T5
CLK
DQM
DQM
READ
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
BANK,
COL n
BANK,
COL b
BANK,
COL b
BANK,
COL n
t
CK
t
t
HZ
HZ
DOUT
n
D
IN
b
DQ
D
OUT
n
DIN b
DQ
t
DS
t
DS
DON’T CARE
DON’T CARE
NOTE:
A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.
NOTE:
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
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ADVANCE
256Mb: x16
MOBILE SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not acti-
vated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until RP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
t
Figure 11
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 0 cycles
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
D
OUT
D
n + 1
OUT
DOUT
DOUT
n
n + 2
n + 3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK
(a or all)
BANK a,
BANK a,
ROW
COL
n
D
OUT
D
n + 1
OUT
DOUT
DOUT
n + 3
n
n + 2
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 2 cycles
BANK
(a or all)
BANK a,
BANK a,
ROW
COL
n
D
OUT
D
OUT
DOUT
D
n + 3
OUT
n
n + 1
n + 2
CAS Latency = 3
NOTE: DQM is LOW.
DON’T CARE
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ADVANCE
256Mb: x16
MOBILE SDRAM
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE
command, provided that auto precharge was not acti-
vated. The BURST TERMINATE command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 12 for each
possible CAS latency; data element n + 3 is the last
desired data element of a longer burst.
Figure 12
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
X = 0 cycles
BANK,
COL n
D
OUT
D
n + 1
OUT
D
n + 2
OUT
DOUT
n + 3
n
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK,
COL n
D
OUT
D
n + 1
OUT
DOUT
D
n + 3
OUT
n
n + 2
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
NOP
X = 2 cycles
BANK,
COL n
D
OUT
DOUT
D
n + 2
OUT
DOUT
n + 3
n
n + 1
CAS Latency = 3
NOTE: DQM is LOW.
DON’T CARE
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ADVANCE
256Mb: x16
MOBILE SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
ample is shown in Figure 15. Data n + 1 is either the last
of a burst of two or the last desired of a longer burst. The
256Mb SDRAM uses a pipelined architecture and there-
fore does not require the 2n rule associated with a
prefetch architecture. A WRITE command can be initi-
ated on any clock cycle following a previous WRITE
command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in
Figure 16, or each subsequent WRITE may be per-
formed to a different bank.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
During WRITE bursts, the first valid data-in ele-
ment will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to the start address
and continue.)
Figure 14
WRITE Burst
T0
T1
T2
T3
CLK
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command
can be issued on any clock following the previous WRITE
command, and the data provided coincident with the
new command applies to the new command. An ex-
WRITE
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
D
IN
DIN
n + 1
n
Figure 13
WRITE Command
Figure 15
WRITE to WRITE
CLK
CKE HIGH
T0
T1
T2
CS#
CLK
RAS#
WRITE
NOP
WRITE
COMMAND
ADDRESS
DQ
CAS#
WE#
BANK,
COL n
BANK,
COL b
DIN
D
IN
DIN
b
COLUMN
ADDRESS
A0-A8: x16
n
n + 1
A9, A11: x16
DON’T CARE
ENABLE AUTO PRECHARGE
NOTE: DQM is LOW. Each WRITE command may
A10
be to any bank.
DISABLE AUTO PRECHARGE
BANK
ADDRESS
BA0,1
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ADVANCE
256Mb: x16
MOBILE SDRAM
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
READ command. Once the READ command is regis-
tered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 17.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
tWR after the clock edge at which the last desired input
data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regardless
of frequency. In addition, when truncating a WRITE
burst, the DQM signal must be used to mask input data
for the clock edge prior to, and the clock edge coinci-
dent with, the PRECHARGE command. An example is
shown in Figure 18. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
t
the same bank cannot be issued until RP is met. The
precharge can be issued coincident with the first coin-
cident clock edge (T2 in Figure 18) on an A1 Version and
with the second clock on an A2 Version (Figure 18.)
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
Figure 16
Random WRITE Cycles
T0
T1
T2
T3
CLK
Figure 18
WRITE to PRECHARGE
WRITE
WRITE
WRITE
WRITE
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
T0
T1
T2
T3
T4
T5
T6
CLK
t
t
WR @ CLK ≥ 15ns
D
IN
D
IN
D
IN
DIN
x
m
n
a
DQM
t
RP
DON’T CARE
NOP
NOP
NOP
WRITE
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
NOTE: Each WRITE command may be to any bank. DQM is LOW.
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
D
n
IN
DIN
n + 1
Figure 17
DQ
WRITE to READ
t
t
WR = CLK < 15ns
T0
T1
T2
T3
T4
T5
DQM
CLK
t
RP
NOP
NOP
WRITE
NOP
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
WRITE
NOP
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
BANK,
COL n
BANK,
COL b
t
WR
D
n
IN
DIN
n + 1
DQ
D
IN
D
IN
D
OUT
DOUT
b + 1
n
n + 1
b
DON’T CARE
DON’T CARE
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
NOTE:
The WRITE command may be to any bank, and the READ command
may be to any bank. DQM is LOW. CAS latency = 2 for illustration.
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ADVANCE
256Mb: x16
MOBILE SDRAM
Fixed-length or full-page WRITE bursts can be trun-
cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coin-
cident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 19, where data n is the last
desired data element of a longer burst.
PRECHARGE
The PRECHARGE command (see Figure 20) is used
to deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (tRP) af-
ter the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. When
all banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
Figure 19
Terminating a WRITE Burst
T0
T1
T2
CLK
POWER-DOWN
Power-down occurs if CKE is registered LOW coinci-
dent with a NOP or COMMAND INHIBIT when no ac-
cesses are in progress. If power-down occurs when all
banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a row
active in any bank, this mode is referred to as active
power-down. Entering power-down deactivates the in-
put and output buffers, excluding CKE, for maximum
power savings while in standby. CKE must be held low
during power down. The device may not remain in the
power-down state longer than the refresh period
(64ms) since no refresh operations are performed in
this mode.
BURST
TERMINATE
NEXT
COMMAND
WRITE
COMMAND
ADDRESS
DQ
BANK,
COL n
(ADDRESS)
(DATA)
DIN
n
NOTE: DQMs are LOW.
DON’T CARE
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting CKS). See Figure 21.
Figure 20
PRECHARGECommand
t
CLK
CKE
CS#
HIGH
Figure 21
Power-Down
( (
) )
RAS#
CLK
( (
) )
> t
CKS
t
CKS
CKE
CAS#
WE#
( (
) )
( (
) )
( (
) )
COMMAND
NOP
NOP
ACTIVE
t
All banks idle
RCD
Input buffers gated off
t
RAS
A0-A9, A11, A12
A10
t
RC
Enter power-down mode.
Exit power-down mode.
DON’T CARE
All Banks
Bank Selected
BANK
ADDRESS
BA0, BA1
DON’T CARE
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ADVANCE
256Mb: x16
MOBILE SDRAM
DEEP POWER-DOWN
CLOCK SUSPEND
Deep Power Down mode is a maximum power sav-
ings feature achieved by shutting off the power to the
entire memory array of the device. Data will not be
retained once Deep Power Down mode is executed.
Deep Power Down mode is entered by having all banks
idle then /CS and /WE held low with /RAS and /CAS
high at the rising edge of the clock, while CKE is low.CKE
must be held low during Deep Power Down.
In order to exit Deep Power Down mode, CKE must
be asserted high. After exiting, the following sequence
is needed in order to enter a new command. Maintain
NOP input conditions for a minimum of 200us. Issue
PRECHARGE commands for all banks. Issue eight or
more AUTOREFRESH commands. Issue a MODE REG-
ISTER set command to initialize mode register. Issue a
EXTENDED MODE REGISTER set command to initial-
ize the extended mode register. See Figure 21A.
The clock suspend mode occurs when a column ac-
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is
sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the in-
put pins at the time of a suspended internal clock edge
is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in Fig-
ures 22 and 23.)
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
Figure 21A
DeepPower-Down
Figure 22
Clock Suspend During WRITE Burst
( (
) )
T0
T1
T2
T3
T4
T5
CLK
( (
) )
CLK
CKE
( (
) )
( (
) )
CKE
CS#
( (
) )
( (
) )
( (
) )
RAS#
( (
) )
INTERNAL
CLOCK
( (
) )
CAS#
WE#
( (
) )
( (
) )
( (
) )
NOP
WRITE
NOP
NOP
COMMAND
ADDRESS
BANK,
COL n
Enter deep power-down mode.
Exit deep power-down mode.
D
n
IN
D
n + 1
IN
DIN
n + 2
D
IN
DON T CARE
DON’T CARE
NOTE: For this example, burst length = 4 or greater, and DM
is LOW.
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ADVANCE
256Mb: x16
MOBILE SDRAM
BURST READ/SINGLE WRITE
Figure 23
Clock Suspend During READ Burst
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the pro-
grammed burst length and sequence, just as in the
normal mode of operation (M9 = 0).
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
DOUT
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
n
DON’T CARE
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
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ADVANCE
256Mb: x16
MOBILE SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs,
unless the SDRAM supports CONCURRENT AUTO
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered (Fig-
ure 25).
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
Figure 24
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
t
Idle
BANK n
t
RP - BANK n
RP - BANK m
Internal
States
Precharge
Page Active
READ with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
D
a
OUT
D
a + 1
OUT
D
OUT
DOUT
d + 1
d
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
DON’T CARE
Figure 25
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page
Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
Idle
WR - BANK m
BANK n
t
RP - BANK
n
Internal
States
Write-Back
WRITE with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
1
DQM
D
OUT
DIN
d
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
DQ
a
CAS Latency = 3 (BANK n)
OUT-a+1 from contending with DIN-d at T4.
NOTE: 1. DQM is HIGH at T2 to prevent
D
DON’T CARE
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ADVANCE
256Mb: x16
MOBILE SDRAM
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out ap-
pearing CAS latency later. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
the READ to bank m is registered. The last valid
WRITE to bank n will be data-in registered one clock
prior to the READ to bank m (Figure 26).
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a
WRITE on bank
n
when registered. The
t
PRECHARGE to bank n will begin after WR is met,
t
where WR begins when the WRITE to bank m is
registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to
bank m (Figure 27).
Figure 26
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
RP - BANK m
Page Active
READ with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
D
IN
D
a + 1
IN
D
OUT
DOUT
d + 1
a
d
CAS Latency = 3 (BANK m)
NOTE: 1. DQM is LOW.
DON’T CARE
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
WR - BANK m
Write-Back
Page Active
WRITE with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
DIN
D
a + 1
IN
D
a + 2
IN
DIN
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
a
d
NOTE: 1. DQM is LOW.
DON’T CARE
256Mb: x16MobileSDRAM
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TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKEn-1 CKEn
CURRENT STATE
COMMANDn
ACTIONn
NOTES
L
L
L
Power-Down
Self Refresh
X
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
X
Clock Suspend
Power-Down
X
COMMAND INHIBIT or NOP
X
H
5
8
6
7
Deep Power-Down
Self Refresh
Exit Deep Power-Down
Exit Self Refresh
COMMAND INHIBIT or NOP
X
Clock Suspend
All Banks Idle
All Banks Idle
All Banks Idle
Reading or Writing
Exit Clock Suspend
H
L
COMMAND INHIBIT or NOP
DEEP POWER DOWN
AUTO REFRESH
VALID
Power-Down Entry
Deep Power-Down Entry
Self Refresh Entry
8
Clock Suspend Entry
H
H
See Truth Table 3
NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
t
that CKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT
or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP
commands must be provided duringtXSRperiod.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
edge n + 1.
8. Deep Power-Down is a power savings feature of this Mobile SDRAM device. This command is Burst Terminate on
traditional SDRAM components. For Bat Ram devices, this command sequence is assigned to Deep Power Down.
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TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
Any
Idle
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
L
AUTO REFRESH
7
7
L
L
LOAD MODE REGISTER
L
H
L
L
PRECHARGE
11
10
10
8
H
H
L
H
L
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
DEEP POWER DOWN
Row Active
L
H
L
L
Read
(Auto
H
H
L
H
L
10
10
8
L
Precharge
Disabled)
Write
H
H
L
L
H
H
H
L
L
9
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
10
10
8
(Auto
L
Precharge
Disabled)
H
H
L
H
L
9
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
RowActive: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or
beenterminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met,
the bank will be in the idle state.
RowActivating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met,
the bank will be in the row active state.
Readw/Auto
PrechargeEnabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Writew/Auto
PrechargeEnabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
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NOTE(continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is
met, the SDRAM will be in the all banks idle state.
AccessingMode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been
met. Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Deep Power-Down is a power savings feature of this BAT-RAM device. This command is Burst Terminate on
traditional SDRAM components. For Bat Ram devices, this command sequence is assigned to Deep Power Down.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
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TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear on next page)
CURRENT STATE CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
L
X
H
X
H
H
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
Idle
Row
Activating,
Active, or
Precharging
Read
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
7
7
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
(Auto
H
H
L
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
7, 10
7, 11
9
Precharge
Disabled)
Write
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
(Auto
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
7, 12
7, 13
9
Precharge
Disabled)
Read
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
(With Auto
Precharge)
H
H
L
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
7, 8, 14
7, 8, 15
9
L
H
H
L
L
Write
L
H
H
L
ACTIVE (Select and activate row)
(With Auto
Precharge)
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
7, 8, 16
7, 8, 17
9
L
H
L
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
RowActive: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or
beenterminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Readw/Auto
PrechargeEnabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Writew/Auto
PrechargeEnabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
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NOTE:(continued)
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank nwill initiate the auto precharge command when its burst has been interrupted
by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE
commandtopreventbuscontention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last
valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).
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*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
ABSOLUTEMAXIMUMRATINGS*
Voltage on VDD/VDDQ Supply
Relative to VSS(2.5V) .......................... -0.5V to +3.6V
Relative to VSS(1.8V) ....................... -0.35V to +2.8V
Voltage on Inputs, NC or I/O Pins
Relative to VSS(1.8V) ...................... -0.35V to +2.8V
Operating Temperature,
TA (industrial; IT parts) ..................... -40°C to +85°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ........................................................ 1W
DCELECTRICALCHARACTERISTICSANDOPERATINGCONDITIONS-Vversion
(Notes: 1, 5, 6; notes appear on page 37; VDD = 2.5 0.2V, VDDQ = +1.8V 0.15V )
PARAMETER/CONDITION
SYMBOL MIN
MAX UNITS NOTES
SUPPLY VOLTAGE
VDD
VDDQ
VIH
2.3
1.65
1.25
-0.3
2.7
1.95
VDD + 0.3
0.55
–
V
V
I/O SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
DATA OUTPUT HIGH VOLTAGE: Logic 1; All inputs
DATA OUTPUT LOW VOLTAGE: LOGIC 0; All inputs
INPUT LEAKAGE CURRENT:
V
22
22
VIL
V
VOH
VOL
II
VDDQ -0.2
–
V
0.2
V
-1.0
1.0
µA
Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-1.5
1.5
µA
DCELECTRICALCHARACTERISTICSANDOPERATINGCONDITIONS-Hversion
(Notes: 1, 5, 6; notes appear on page 37; VDD = 1.8 0.15V, VDDQ = +1.8V 0.15V )
PARAMETER/CONDITION
SYMBOL MIN
MAX UNITS NOTES
SUPPLY VOLTAGE
VDD
VDDQ
VIH
1.65
1.65
1.95
1.95
V
V
I/O SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
DATA OUTPUT HIGH VOLTAGE: Logic 1; All inputs
DATA OUTPUT LOW VOLTAGE: LOGIC 0; All inputs
INPUT LEAKAGE CURRENT:
0.8*VDDQ VDD + 0.3
V
22
22
VIL
-0.3
VDDQ -0.2
–
0.3
–
V
VOH
VOL
II
V
0.2
1.0
V
-1.0
µA
Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-1.5
1.5
µA
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CAPACITANCE
(Note: 2; notes appear on page 37)
PARAMETER
SYMBOL
MIN
1.5
MAX UNITS NOTES
Input Capacitance: CLK
CI1
CI2
CIO
3.0
3.3
5.0
pF
pF
pF
29
30
31
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
1.5
3.0
ELECTRICALCHARACTERISTICSANDRECOMMENDEDACOPERATINGCONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 37)
ACCHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
-8
-10
SYMBOL MIN
MAX
MIN
MAX
UNITS NOTES
t
CL = 3
CL = 2
CL = 1
AC(3)
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
t
AC(2)
8
8
t
AC(1)
19
22
t
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
AH
1
1
t
AS
2.5
3
2.5
3
t
CH
D
t
CL
3
3
D
t
t
t
t
t
t
CL = 3
CL = 2
CL = 1
CK(3)
CK(2)
CK(1)
CKH
CKS
8
10
12
25
1
23
23
10
20
1
CKE hold time
CKE setup time
2.5
1
2.5
1
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
CMH
t
CMS
2.5
1
2.5
1
t
DH
t
Data-in setup time
DS
2.5
2.5
t
t
t
t
Data-out high-impedance time
CL = 3
CL = 2
CL = 1
HZ(3)
HZ(2)
HZ(1)
7
7
10
10
8
8
19
22
Data-outlow-impedancetime
Data-outholdtime(load)
LZ
1
1
t
OH
2.5
2.5
1.8
50
ns
t
Data-outholdtime(noload)
ACTIVEtoPRECHARGE command
ACTIVEtoACTIVEcommandperiod
ACTIVEtoREADorWRITEdelay
Refreshperiod(8,192rows)
AUTOREFRESHperiod
OH
1.8
ns
28
D
N
t
RAS
48
80
20
120,000
64
120,000
64
ns
t
RC
100
20
ns
D,E
D
t
RCD
ns
t
REF
ms
ns
t
RFC
80
20
100
20
D,E
D
t
PRECHARGEcmdperiod
RP
ns
ns
ns
ns
t
ACTIVE bank a to bank b command
Transition time
RRD
20
20
t
T
0.5
1CLK+
7ns
15
1.2
0.5
1.2
7
t
WRITE recovery time
WR
1CLK+
5ns
24
D,E
25,D
E
15
t
Exit SELF REFRESH to ACTIVE command
XSR
80
100
ns
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AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 37)
PARAMETER
SYMBOL -8
-10 UNITS NOTES
t
t
READ/WRITEcommandtoREAD/WRITEcommand
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
CCD
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
1
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
1
CK
17
14
14
17
17
17
17
t
t
CKED
CK
t
t
PED
CK
t
t
DQD
CK
t
t
DQM to data mask during WRITEs
DQM
CK
t
t
DQMtodatahigh-impedanceduringREADs
WRITE command to input data delay
Data-intoACTIVEcommand
DQZ
CK
t
t
DWD
CK
t
t
DAL
CK 15, 21
t
t
Data-intoPRECHARGEcommand
DPL
CK 16, 21
t
t
Last data-in to burst STOP command
Lastdata-intonewREAD/WRITEcommand
Lastdata-intoPRECHARGEcommand
LOADMODEREGISTERcommandtoACTIVEorREFRESHcommand
Data-outtohigh-impedancefromPRECHARGEcommand
BDL
CK
17
17
t
t
CDL
CK
t
t
RDL
CK 16, 21
t
t
MRD
CK
26
17
17
17
t
t
CL = 3 ROH(3)
CK
t
t
CL = 2 ROH(2)
CK
t
t
CL = 1 ROH(1)
CK
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IDD SPECIFICATIONSANDCONDITIONS
(Notes: 1, 5, 6, 11, 13; notes appear on page 37;VDD = 2.5 0.2V or +1.8V 0.15V, VDDQ = +1.8V 0.15V )
MAX
PARAMETER/CONDITION
SYMBOL -8
-10 UNITS NOTES
OPERATING CURRENT: Active Mode;
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD8
78
75
mA
19, 32
3, 18,
t
Burst = 2; READ or WRITE; tRC = RC (MIN)
STANDBY CURRENT: Power-Down Mode;
All banks idle; CKE = LOW
350 350
µA
mA
mA
mA
mA
µA
32
STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress
25
90
25
80
3, 12,
19, 32
OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; All banks active
3, 18,
19, 32
t
AUTO REFRESH CURRENT
CKE = HIGH; CS# = HIGH
tRFC = RFC (MIN)
160 150
2.5 2.5
3, 12,
18, 19,
32, 33
tRFC = 7.8µs
DEEP POWER DOWN
10
10
IDD7 - SELF REFRESH CURRENT OPTIONS (Temperature Compensated Self Refresh)
(Notes: 1, 6, 11, 13; notes appear on page 37) VDD = 2.5 0.2V or +1.8V 0.15V, VDDQ = +1.8V 0.15V
Temperature Compensated Self Refresh
Parameter/Condition
Max
Temperature
-8
-10
UNITS NOTES
Self Refresh
Current:
85°C
70°C
45°C
15°C
600
350
200
160
600
350
200
160
µA
µA
µA
µA
4
4
4
4
CKE < 0.2V
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MOBILE SDRAM
NOTES
1. All voltages referenced to VSS.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing param-
eter.
18. The IDD current will increase or decrease propor-
tionally according to the amount of frequency al-
teration for the test condition.
2. This parameter is sampled; f = 1 MHz, TJ = 25°C;
0.9V bias, 200mV swing, VDD = +2.5V, VDDQ = +1.8V.
3. IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C ≤ TA ≤ +70°C and
- 40°C ≤ TA ≤ +85°C for IT parts) is ensured.
6. An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously. VSS
and VSSQ must be at same potential.) The two
AUTO REFRESH command wake-ups should be
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times dur-
ing this period.
21. Based on tCK = 7.5ns for -75, tCK=8ns for -8,
tCK=10ns for -10 .
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width ≤ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width ≤ 1/3 tCK.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during ac-
cess or precharge states (READ, WRITE, including
tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
t
repeated any time the REF refresh requirement is
exceeded.
7. AC characteristics assume T = 1ns.
t
8. In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between VIH
and VIL (or between VIL and VIH) in a monotonic
manner.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins 7.5ns after the first clock de-
lay, after the last WRITE is executed. May not ex-
ceed limit set for precharge mode.
9. Outputs measured at 0.9V with equivalent load:
Q
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
30pF
t
27. AC for -75 at CL = 3 with no load is 5.4ns and is
guaranteed by design.
28. Parameter guaranteed by design.
A. Maximum capacitance can be 3.0 pF but not
desired.
t
10. HZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
B. Maximum capacitance can be 5.0pF but not
desired.
11. AC timing and IDD tests have VIL = 0.0V and VIH 1.65V,
with timing referenced to VIH/2 crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at VIL (MAX) and VIH (MIN)
and no longer at the ISV crossover point.
12. Other input signals are allowed to transition no
more than once every two clocks and are otherwise
at valid VIH or VIL levels.
C. Maximum capacitance can be 3.3pF but not
desired.
D. Target values listed with alternative values in
parantheses.
t
E. tRFC must be less than or equal to RC+1CLK
t
tXSR must be less than or equal to RC+1CLK
F. For full I/V relationships see IBIS Section.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -75, CL = 3 and tCK = 7.5ns; for -8, CL = 2 and tCK
= 10ns.
33. CKE is HIGH during refresh command period
tRFC (MIN) else CKE is LOW. The IDD6 limit is actu-
ally a nominal value and does not result in a fail
value.
13. IDD specifications are tested after the device is prop-
erly initialized.
t
14. Timing actually specified by CKS; clock(s) speci-
fied as a reference only at minimum cycle rate.
t
t
15. Timing actually specified by WR plus RP; clock(s)
specified as a reference only at minimum cycle rate.
t
16. Timing actually specified by WR.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
37
ADVANCE
256Mb: x16
MOBILE SDRAM
INITIALIZE AND LOAD MODE REGISTER
T1
T0
T3
T5
T7
T9
T19
T29
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CLK
CKE
t
CK
t
t
CKS CKH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
t
t
CMH CMS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
COMMAND6
4
4
3
4
4
4
ACT
NOP
PRE
LMR
LMR
PRE
AR
AR
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DQML/U (x16)
t
t
AS AH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9, A11, A12
A10
CODE
CODE
CODE
RA
RA
BA
ALL BANKS
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CODE
t
AS
t
AH
t
t
AH
t
AH
t
AS
AS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
BA0 = L,
BA1 = H
BA0 = L,
BA1 = L
BA0, BA1
DQ
High-Z
( (
((
))
((
))
((
))
((
))
((
))
((
))
)
)
T = 100µs
t
t
t
t
RP
t
t
RFC
RP
MRD
MRD
RFC
Power-up:
DD and
CK stable
Load Extended
Mode Register
Load Mode
Register
V
DON’T CARE
NOTE:
1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address,
BA = Bank Address
3. Optional refresh command.
4. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur prior to an Active command.
5. Device timing is -10 with 100MHz clock.
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MIN
MAX
MIN
1
MAX UNITS
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
1
2.5
3
ns
ns
ns
ns
ns
ns
ns
CKH
ns
ns
ns
ns
t
t
AS
2.5
3
CKS
2.5
1
2.5
1
t
t
CH
CMH
t
t
CL
3
3
CMS
2.5
2
2.5
2
t
t
t
t
3
t
CK (3)
8
10
12
25
MRD
RFC
CK
t
CK (2)
10
20
80
20
100
20
ns
ns
t
CK (1)
RP
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
38
ADVANCE
256Mb: x16
MOBILE SDRAM
1
POWER-DOWNMODE
T0
T1
T2
Tn + 1
Tn + 2
( (
) )
t
CK
t
CL
CLK
CKE
( (
t
CH
) )
t
t
CKS
CKS
( (
) )
t
t
CKS
CKH
t
t
CMS CMH
( (
) )
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
DQM/
DQML, DQMU
( (
) )
( (
) )
A0-A9, A11, A12
A10
ROW
ROW
ALL BANKS
( (
) )
( (
) )
SINGLE BANK
t
AS
t
AH
( (
) )
( (
) )
BA0, BA1
DQ
BANK
BANK(S)
High-Z
( (
) )
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL*
MIN
20
MAX
MIN
25
MAX UNITS
t
t
AH
ns
ns
ns
ns
ns
ns
CK (1)
ns
ns
ns
ns
ns
t
t
AS
2.5
3
2.5
3
CKH
1
2.5
1
1
t
t
CH
CKS
2.5
1
t
t
CL
3
3
CMH
t
t
CK (3)
8
10
12
CMS
2.5
2.5
t
CK (2)
10
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
39
ADVANCE
256Mb: x16
MOBILE SDRAM
1
CLOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
t
CMS
CMH
DQM/
DQML, DQMU
t
t
AH
AS
2
2
A0-A9, A11, A12
COLUMN m
COLUMN e
t
t
AH
AS
A10
t
t
AH
AS
BA0, BA1
BANK
BANK
t
AC
t
t
t
t
t
DH
AC
OH
HZ
DS
DOUT
m
D
OUT m + 1
DOUT
e
DOUT + 1
DQ
t
LZ
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
-8
-10
MAX UNITS
SYMBOL*
MIN
1
MAX
MIN
MAX UNITS
SYMBOL*
MIN
MAX
MIN
t
t
AC (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKH
1
2.5
1
ns
ns
ns
ns
ns
ns
t
t
AC (2)
CKS
2.5
1
t
t
AC (1)
19
22
CMH
t
t
AH
1
2.5
3
1
2.5
3
CMS
2.5
1
2.5
1
t
t
AS
DH
t
t
CH
DS
2.5
2.5
t
t
CL
3
3
HZ (3)
7
8
7
8
ns
ns
ns
ns
ns
t
t
CK (3)
8
10
12
HZ (2)
t
t
CK (2)
10
HZ (1)
19
22
t
t
LZ
1
1
CK (1)
20
25
ns
t
OH
2.5
2.5
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
40
ADVANCE
256Mb: x16
MOBILE SDRAM
1
AUTO REFRESH MODE
T0
T1
T2
Tn + 1
CL
To + 1
( (
) )
( (
) )
t
CLK
CKE
t
t
( (
( (
CK
CH
) )
) )
( (
) )
( (
) )
t
t
CKS
CKH
t
t
CMS
CMH
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
COMMAND
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
( (
) )
) )
( (
) )
( (
) )
DQM /
DQML, DQMU
( (
( (
) )
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9, A11, A12
A10
ROW
ROW
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
BANK(S)
BA0, BA1
DQ
BANK
( (
( (
) )
) )
High-Z
( (
) )
( (
) )
t
t
t
RFC
RP
RFC
Precharge all
active banks
DON’T CARE
NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL*
MIN
20
1
MAX
MIN
25
MAX UNITS
t
t
AH
ns
ns
ns
ns
ns
ns
CK (1)
ns
ns
ns
ns
ns
ns
ns
t
t
AS
2.5
3
2.5
3
CKH
1
t
t
CH
CKS
2.5
1
2.5
1
t
t
CL
3
3
CMH
t
t
CK (3)
8
10
12
CMS
2.5
80
20
2.5
100
20
t
t
CK (2)
10
RFC
t
RP
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
41
ADVANCE
256Mb: x16
MOBILE SDRAM
SELFREFRESHMODE
T0
T1
T2
( (
Tn + 1
To + 1
To + 2
( (
) )
( (
) )
t
CL
) )
( (
) )
CLK
CKE
t
t
CK
CH
t
CKS
> t
RAS
( (
) )
( (
) )
( (
) )
t
t
CKS
t
CKS
CKH
t
t
CMS
CMH
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
COMMAND
PRECHARGE
NOP
NOP
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DQM/
DQML, DQMH
( (
) )
( (
) )
( (
) )
( (
) )
A0-A12
A10
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
BA0, BA1
DQ
BANK(S)
High-Z
( (
) )
( (
) )
t
t
RP
XSR
Precharge all
active banks
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
TIMING PARAMETERS
-8
-10
MAX UNITS
-8
-10
SYMBOL*
MIN
MAX
MIN
1
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
t
t
t
t
t
t
t
AH
1
2.5
3
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
ns
ns
ns
ns
t
AS
2.5
3
2.5
1
2.5
1
t
CH
CMH
CMS
RAS
t
CL
3
3
2.5
48
20
80
2.5
50
t
CK (3)
8
10
12
25
120,000
120,000
ns
ns
ns
t
CK (2)
10
20
RP
20
t
t
CK (1)
XSR
100
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
42
ADVANCE
256Mb: x16
MOBILE SDRAM
1
READ – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMH
CMS
DQM/
DQML, DQMU
t
t
AH
AS
2
A0-A9, A11, A12
ROW
ROW
COLUMN m
t
t
AH
AS
ALL BANKS
ROW
ROW
A10
SINGLE BANK
DISABLE AUTO PRECHARGE
BANK
t
t
AH
AS
BA0, BA1
BANK
BANK
t
BANK
t
t
AC
AC
AC
t
t
t
t
t
OH
AC
OH
OH
OH
DOUT
m
DOUT m + 1
D
OUT m + 2
DOUT m + 3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
MAX UNITS
-8
-10
SYMBOL*
MIN
MAX
MIN
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AC (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
ns
ns
t
t
AC (2)
CMS
2.5
2.5
t
t
AC (1)
19
22
HZ (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AH
1
2.5
3
1
2.5
3
HZ (2)
t
t
AS
HZ (1)
19
22
t
t
CH
LZ
1
1
2.5
50
t
t
CL
3
3
OH
2.5
48
80
20
20
t
t
CK (3)
8
10
12
25
1
RAS
120,000
120,000
t
t
CK (2)
10
20
1
RC
100
20
t
t
CK (1)
RCD
t
t
CKH
RP
20
t
CKS
2.5
2.5
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
43
ADVANCE
256Mb: x16
MOBILE SDRAM
1
READ – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
CMH
DQM/
DQML, DQMU
t
t
AH
AS
2
A0-A9, A11, A12
ROW
ROW
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BA0, BA1
BANK
BANK
BANK
t
t
t
AC
AC
AC
t
t
t
t
t
AC
OH
OH
OH
OH
DOUT
m
D
OUT m + 1
D
OUT m + 2
D
OUT m + 3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
MAX UNITS
-8
-10
SYMBOL*
MIN
MAX
MIN
SYMBOL*
MIN
1
MAX
MIN
MAX UNITS
t
t
t
t
t
t
t
AC (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
1
ns
ns
t
AC (2)
2.5
2.5
t
AC (1)
19
22
HZ (3)
HZ (2)
HZ (1)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AH
1
2.5
3
1
2.5
3
t
AS
19
22
t
CH
LZ
1
1
t
t
CL
3
3
OH
2.5
48
80
20
20
2.5
50
70
20
20
t
t
CK (3)
8
10
12
25
1
RAS
RC
120,000
120,000
t
t
t
t
CK (2)
10
20
1
t
CK (1)
RCD
t
CKH
RP
t
CKS
2.5
2.5
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
44
ADVANCE
256Mb: x16
MOBILE SDRAM
1
SINGLE READ – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS CMH
2
2
COMMAND
PRECHARGE
ACTIVE
NOP
READ
NOP
NOP
NOP
ACTIVE
ROW
NOP
t
t
CMS CMH
DQM /
DQML, DQMU
t
t
AS
AH
COLUMN m3
A0-A9, A11,A12
ROW
t
t
AS
AH
ALL BANKS
ROW
ROW
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANKS
BANK(S)
t
t
AS
AH
BA0, BA1
BANK
BANK
t
t
OH
AC
D
OUT m
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. PRECHARGEcommandnotallowedelsetRASwouldbeviolated.
3. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
MAX UNITS
-8
-10
SYMBOL*
MIN
MAX
MIN
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AC (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
ns
ns
t
t
AC (2)
CMS
2.5
2.5
t
t
AC (1)
19
22
HZ (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AH
1
2.5
3
1
2.5
3
HZ (2)
t
t
AS
HZ (1)
19
22
t
t
CH
LZ
1
1
2.5
50
t
t
CL
3
3
OH
2.5
48
80
20
20
t
t
CK (3)
8
10
12
25
1
RAS
120,000
120,000
t
t
CK (2)
10
20
1
RC
100
20
t
t
CK (1)
RCD
t
t
CKH
RP
20
t
CKS
2.5
2.5
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
45
ADVANCE
256Mb: x16
MOBILE SDRAM
1
SINGLE READ – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS CMH
2
2
COMMAND
ACTIVE
NOP
NOP
NOP
READ
t
NOP
ACTIVE
NOP
NOP
t
CMS
CMH
DQM /
DQML, DQMU
t
t
AH
AS
3
A0-A9, A11
ROW
ROW
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BA0, BA1
BANK
BANK
BANK
t
AC
t
OH
D
OUT
m
DQ
t
CAS Latency
t
RCD
HZ
t
t
RP
RAS
t
RC
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
2. READ command not allowed elsetRAS would be violated since AUTO PRECHARGE is enabled.
3. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
MAX UNITS
-8
-10
SYMBOL*
MIN
MAX
MIN
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AC (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
ns
ns
t
t
AC (2)
CMS
2.5
2.5
t
t
AC (1)
19
22
HZ (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AH
1
2.5
3
1
2.5
3
HZ (2)
t
t
AS
HZ (1)
19
22
t
t
CH
LZ
1
1
2.5
50
t
t
CL
3
3
OH
2.5
48
80
20
20
t
t
CK (3)
8
10
12
25
1
RAS
120,000
120,000
t
t
CK (2)
10
20
1
RC
100
20
t
t
CK (1)
RCD
t
t
CKH
RP
20
t
CKS
2.5
2.5
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
46
ADVANCE
256Mb: x16
MOBILE SDRAM
1
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS
CMH
DQM/
DQML, DQMU
t
t
AH
AS
2
2
A0-A9, A11, A12
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BA0, BA1
BANK 0
BANK 0
BANK 3
t
BANK 3
BANK 0
t
t
t
t
AC
AC
AC
AC
AC
t
t
t
t
t
t
AC
OH
OH
OH
OH
OH
DOUT
m
D
OUT m + 1
D
OUT m + 2
DOUT m + 3
DOUT b
DQ
t
LZ
t
t
RCD - BANK 0
t
RCD - BANK 0
CAS Latency - BANK 0
RP - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
RCD - BANK 1
CAS Latency - BANK 1
RRD
DON’T CARE
UNDEFINED
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
MAX UNITS
-8
-10
SYMBOL*
MIN
MAX
MIN
SYMBOL*
MIN
2.5
1
MAX
MIN
2.5
1
MAX UNITS
t
t
AC (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
ns
ns
ns
ns
ns
t
t
AC (2)
CMH
t
t
AC (1)
19
22
CMS
2.5
1
2.5
1
t
t
AH
1
2.5
3
1
2.5
3
LZ
t
t
AS
OH
2.5
48
80
20
20
20
2.5
50
t
t
CH
RAS
120,000
120,000
ns
ns
ns
ns
ns
t
t
CL
3
3
RC
100
20
t
t
CK (3)
8
10
12
25
1
RCD
t
t
CK (2)
10
20
1
RP
20
t
t
CK (1)
RRD
20
t
CKH
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
47
ADVANCE
256Mb: x16
MOBILE SDRAM
1
READ – FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn + 1
Tn + 2
Tn + 3
Tn + 4
( (
) )
( (
) )
t
t
CK
CL
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS
CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
CMS
CMH
( (
) )
DQM/
DQML, DQMH
( (
) )
t
t
AH
AS
( (
) )
( (
) )
2
A0-A9, A11, A12
ROW
COLUMN m
t
t
AH
AS
( (
) )
( (
) )
ROW
A10
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
BANK
BANK
t
t
t
t
t
AC
AC
AC
AC
AC
( (
) )
t
t
t
t
t
t
t
OH
AC
OH
OH
OH
OH
OH
( (
) )
( (
) )
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m-1
Dout
m
D
OUT m+1
DQ
t
LZ
t
HZ
512 (x16) locations within same row
1,024 (x8) locations within same row
2,048 (x4) locations within same row
t
RCD
CAS Latency
Full page completed
DON’T CARE
UNDEFINED
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
3
NOTE: 1. For this example, the CAS latency = 2.
2. x16: A9, A11 and A12 = “Don’t Care”
3. Page left open; no tRP.
TIMING PARAMETERS
-8
-10
MAX UNITS
-8
-10
SYMBOL*
MIN
MAX
MIN
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AC (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKH
ns
ns
ns
ns
t
t
AC (2)
CKS
2.5
1
2.5
1
t
t
AC (1)
19
22
CMH
t
t
AH
1
2.5
3
1
2.5
3
CMS
2.5
2.5
t
t
AS
HZ (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
t
t
CH
HZ (2)
t
t
CL
3
3
HZ (1)
19
22
t
t
CK (3)
8
10
12
25
LZ
1
1
t
t
CK (2)
10
20
OH
2.5
20
2.5
20
t
t
CK (1)
RCD
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
48
ADVANCE
256Mb: x16
MOBILE SDRAM
1
READ – DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQM/
DQML, DQMU
t
t
AH
AS
2
A0-A9, A11, A12
A10
ROW
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
BANK
t
t
AH
AS
BA0, BA1
BANK
t
AC
t
t
t
t
t
OH
AC
OH
AC
OH
D
OUT
m
DOUT m + 2
DOUT m + 3
DQ
t
LZ
t
t
t
HZ
LZ
HZ
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
MAX UNITS
-8
-10
SYMBOL*
MIN
MAX
MIN
SYMBOL*
MIN
1
MAX
MIN
MAX UNITS
t
t
AC (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKH
1
2.5
1
ns
ns
ns
ns
t
t
AC (2)
CKS
2.5
1
t
t
AC (1)
19
22
CMH
t
t
AH
1
2.5
3
1
2.5
3
CMS
2.5
2.5
t
t
AS
HZ (3)
7
8
7
8
ns
ns
ns
ns
ns
ns
t
t
CH
HZ (2)
t
t
CL
3
3
HZ (1)
19
22
t
t
CK (3)
8
10
12
25
LZ
1
1
t
t
CK (2)
10
20
OH
2.5
20
2.5
20
t
t
CK (1)
RCD
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
49
ADVANCE
256Mb: x16
MOBILE SDRAM
1
WRITE – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
NOP
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
PRECHARGE
ACTIVE
t
t
CMS
CMH
DQM/
DQML, DQMU
t
t
t
t
AH
AS
2
A0-A9, A11, A12
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKs
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DQ
3
t
t
t
RP
RCD
WR
t
RAS
t
RC
DON’T CARE
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. x16: A9, A11 and A12 = “Don’t Care”
3. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MAX
1
MIN
MAX UNITS
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
1
2.5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
ns
ns
ns
ns
t
t
AS
2.5
3
CMS
2.5
1
2.5
1
t
t
CH
DH
t
t
CL
3
3
DS
2.5
48
80
20
20
15
2.5
50
t
t
CK (3)
8
10
12
25
1
RAS
120,000
120,000
ns
ns
ns
ns
ns
t
t
CK (2)
10
20
1
RC
100
20
t
t
CK (1)
RCD
t
t
CKH
RP
20
t
t
CKS
2.5
2.5
WR
15
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
50
ADVANCE
256Mb: x16
MOBILE SDRAM
1
WRITE – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM/
DQML, DQMU
t
t
AS
AH
2
A0-A9, A11, A12
ROW
ROW
ROW
BANK
COLUMN
m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
t
A10
t
AS
AH
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
D
IN
m
D
IN m + 1
D
IN m + 2
DIN m + 3
DQ
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
NOTE: 1. For this example, the burst length = 4.
2. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
MAX UNITS
-8
-10
SYMBOL*
MIN
1
MAX
MIN
1
SYMBOL*
MIN
2.5
MAX
MIN
2.5
1
MAX UNITS
t
t
AH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
ns
ns
ns
t
t
AS
2.5
3
2.5
3
DH
1
t
t
CH
DS
2.5
2.5
50
t
t
CL
3
3
RAS
48
120,000
120,000
ns
ns
ns
ns
–
t
t
CK (3)
8
10
12
25
1
RC
80
100
20
t
t
CK (2)
10
20
1
RCD
20
t
t
CK (1)
RP
20
20
t
t
CKH
WR
1 CLK +
7ns
1 CLK +
5ns
t
CKS
2.5
1
2.5
1
t
CMH
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
51
ADVANCE
256Mb: x16
MOBILE SDRAM
1
SINGLE WRITE – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
2
2
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
t
CMS
CMH
DQM /
DQML, DQMU
t
t
t
t
AH
AS
3
A0-A9, A11
ROW
t
COLUMN m
AS
AH
ALL BANKS
ROW
t
ROW
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
BANK
t
t
DH
DS
DIN
m
DQ
t
t
RP
4
t
RCD
WR
t
RAS
t
RC
DON’T CARE
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. PRECHARGEcommandnotallowedelsetRASwouldbeviolated.
3. x16: A9, A11 and A12 = “Don’t Care”
4. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. With a single write
tWR has been increased to meet minimum tRAS requirement.
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MIN
MAX
MIN
1
MAX UNITS
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
1
2.5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
ns
ns
ns
ns
t
t
AS
2.5
3
CMS
2.5
1
2.5
1
t
t
CH
DH
t
t
CL
3
3
DS
2.5
48
80
20
20
15
2.5
50
t
t
CK (3)
8
10
12
25
1
RAS
120,000
120,000
ns
ns
ns
ns
ns
t
t
CK (2)
10
20
1
RC
100
20
t
t
CK (1)
RCD
t
t
CKH
RP
20
t
t
CKS
2.5
2.5
WR
15
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
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ADVANCE
256Mb: x16
MOBILE SDRAM
1
SINGLE WRITE – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
2
2
2
NOP
COMMAND
ACTIVE
NOP
ACTIVE
NOP
NOP
WRITE
t
NOP
NOP
NOP
t
CMS
CMH
DQM/
DQML, DQMU
t
t
AS
AH
3
A0-A9, A11, A12
ROW
ROW
ROW
BANK
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
t
A10
t
AS
AH
BA0, BA1
BANK
BANK
t
t
DH
DS
D
IN m
DQ
t
4
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
NOTE: 1. For this example, the burst length = 1.
2. Requires one clock plus time (5ns to 7ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A9, A11 and A12 = “Don’t Care”
4. WRITE command not allowed else tRAS would be violated.
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MIN
MAX
MIN
1
MAX UNITS
SYMBOL*
MIN
2.5
MAX
MIN
MAX UNITS
t
t
AH
1
2.5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
2.5
1
ns
ns
ns
ns
ns
ns
ns
–
t
t
AS
2.5
3
DH
1
t
t
CH
DS
2.5
2.5
t
t
CL
3
3
RAS
48
120,000
50
120,000
t
t
CK (3)
8
10
12
25
1
RC
80
100
20
t
t
CK (2)
10
20
1
RCD
20
t
t
CK (1)
RP
20
20
t
t
CKH
WR
1 CLK +
7ns
1 CLK +
5ns
t
CKS
2.5
1
2.5
1
t
CMH
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
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53
ADVANCE
256Mb: x16
MOBILE SDRAM
1
ALTERNATINGBANKWRITEACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM/
DQML, DQMU
t
t
AH
AS
3
3
A0-A9, A11, A12
ROW
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
A10
t
t
AH
AS
BA0, BA1
BANK 0
BANK 0
BANK 1
t
BANK 1
BANK 0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
D
IN
m
DIN m + 1
DIN m + 2
D
IN m + 3
D
IN
b
DIN b + 1
DIN b + 2
D
IN b + 3
DQ
t
t
t
t
RP - BANK 0
RCD - BANK 0
WR - BANK 0
RCD - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
WR - BANK 1
t
RCD - BANK 1
RRD
DON’T CARE
NOTE: 1. For this example, the burst length = 4.
2. Requires one clock plus time (5ns or 7ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MIN
MAX
MIN
1
MAX UNITS
SYMBOL*
MIN
2.5
1
MAX
MIN
2.5
1
MAX UNITS
t
t
AH
1
2.5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
ns
ns
ns
t
t
AS
2.5
3
DH
t
t
CH
DS
2.5
48
2.5
50
t
t
CL
3
3
RAS
120,000
120,000
ns
ns
ns
ns
ns
–
t
t
CK (3)
8
10
12
25
1
RC
80
100
20
t
t
CK (2)
10
20
1
RCD
20
t
t
CK (1)
RP
20
20
t
t
CKH
RRD
20
20
t
t
CKS
2.5
1
2.5
1
WR
1 CLK +
7ns
1 CLK +
5ns
t
CMH
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
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ADVANCE
256Mb: x16
MOBILE SDRAM
WRITE–FULL-PAGEBURST
T0
T1
T2
T3
T4
T5
Tn + 1
Tn + 2
Tn + 3
( (
) )
( (
) )
t
t
CK
CL
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS
CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMH
CMS
( (
) )
DQM/
DQML, DQMH
( (
) )
t
t
AH
AS
( (
) )
( (
) )
1
A0-A9, A11, A12
ROW
COLUMN
m
t
t
AH
AS
( (
) )
( (
) )
ROW
A10
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
( (
) )
D
IN
m
D
IN m + 1
DIN m + 2
DIN m + 3
DIN m - 1
DQ
( (
) )
t
RCD
Full-page burst does
not self-terminate.
512 (x16) locations within same row
1,024 (x8) locations within same row
2,048 (x4) locations within same row
Can use BURST TERMINATE
command to stop.2, 3
Full page completed
DON’T CARE
NOTE: 1. x16: A9, A11 and A12 = “Don’t Care”
t
2. WR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MIN
MAX
MIN
1
MAX UNITS
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
1
2.5
3
ns
ns
ns
ns
ns
ns
ns
CKH
ns
ns
ns
ns
ns
ns
ns
t
t
AS
2.5
3
CKS
2.5
1
2.5
1
t
t
CH
CMH
t
t
CL
3
3
CMS
2.5
1
2.5
1
t
t
CK (3)
8
10
12
25
DH
t
t
CK (2)
10
20
DS
2.5
20
2.5
20
t
t
CK (1)
RCD
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
55
ADVANCE
256Mb: x16
MOBILE SDRAM
1
WRITE – DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQM/
DQML, DQMU
t
t
t
t
AH
AS
2
A0-A9, A11, A12
ROW
t
COLUMN m
AS
AH
ENABLE AUTO PRECHARGE
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DIN
m
D
IN m + 2
DIN m + 3
DQ
t
RCD
DON’T CARE
NOTE: 1. For this example, the burst length = 4.
2. x16: A9, A11 and A12 = “Don’t Care”
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL*
MIN
MAX
MIN
1
MAX UNITS
t
t
AH
ns
ns
ns
ns
ns
ns
ns
CKH
1
2.5
1
ns
ns
ns
ns
ns
ns
ns
t
t
AS
2.5
3
2.5
3
CKS
2.5
1
t
t
CH
CMH
t
t
CL
3
3
CMS
2.5
1
2.5
1
t
t
CK (3)
8
10
12
25
DH
t
t
CK (2)
10
20
DS
2.5
20
2.5
20
t
t
CK (1)
RCD
*CAS latency indicated in parentheses.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
56
ADVANCE
256Mb: x16
MOBILE SDRAM
FBGA “FG” PACKAGE
54-pin, 8mm x 14mm
0.700 0.075
SEATING PLANE
0.10 C
0.155 0.013
1.80 0.05
C
6.40
1.00 MAX
CTR
BALL A1 ID
0.80 TYP
54X ∅0.35
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS Ø 0.33
BALL A9
BALL A1 ID
BALL A1
0.80 TYP
C
6.40
14.00 0.10
L
3.20 0.05
7.00 0.05
C
L
3.20 0.05
4.00 0.05
8.00 0.10
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .27mm
(BottomView)
NOTE: 1. All dimensions are in millimeters.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
57
ADVANCE
256Mb: x16
MOBILE SDRAM
DBFCF
FBGADEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Speed Grade
B = -10
C = -8
Width ( I/Os)
D = x16
Device Density
H = 256
Product Type
R = 2.5V SDR SDRAM, Low Power version (54-ball, 8 x 14)
S = 1.8V SDR SDRAM, Low Power version (54-ball, 8 x 14)
Product Group
D = DRAM
Z = DRAM ENGINEERING SAMPLE
CROSS REFERENCE FOR FBGA DEVICE MARKING
ENGINEERING
PRODUCTION
MARKING
DSHDC
PART NUMBER
MT48V16M16LFFG-8
MT48V16M16LFFG-10
MT48V16M16LFFG-10
MT48H16M16LFF-8
ARCHITECTURE
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
FBGA
SAMPLE
ZSHDC
ZRHDB
ZSHDB
ZRHDC
54-ball, 8 x 14
54-ball, 8 x 14
54-ball, 8 x 14
54-ball, 8 x 14
DRHDB
DSHDB
DRHDC
DATASHEETDESIGNATION
Advance: This data sheet contains initial descriptions of products still under development.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail:prodmktg@micron.com,Internet:http://www.micron.com,CustomerCommentLine:800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
256Mb: x16MobileSDRAM
MobileRamY26L_A.p65–Pub.5/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
58
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