MT8HTF12864HDY [MICRON]
DDR2 SDRAM SODIMM;
| 型号： | MT8HTF12864HDY |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | DDR2 SDRAM SODIMM 动态存储器 双倍数据速率 |
| 文件： | 总19页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Features
DDR2 SDRAM SODIMM
MT8HTF3264HDY – 256MB
MT8HTF6464HDY – 512MB
MT8HTF12864HDY – 1GB
Figure 1: 200-Pin SODIMM (MO-224 R/C A)
Features
Module height: 30mm (1.18in)
200-pin, small-outline dual in-line memory module
(SODIMM)
•
•
•
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
256MB (32 Meg x 64), 512MB (64 Meg x 64), or 1GB
(128 Meg x 64)
VDD = 1.8V
•
•
•
•
•
•
VDDSPD = 1.7–3.6V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Options
Marking
Operating temperature
– Commercial (0°C ≤ TA ≤ +70°C)
– Industrial (–40°C ≤ TA ≤ +85°C)1
Package
•
Multiple internal device banks for concurrent opera-
tion
D
T
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Programmable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
•
•
•
•
•
•
•
•
•
•
•
•
200-pin DIMM (lead-free)
Frequency/CL2
Y
–
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-553)3
5.0ns @ CL = 3 (DDR2-400)3
-80E
-800
-667
-53E
-40E
–
–
–
–
–
On-die termination (ODT)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
1. Contact Micron for industrial temperature
module offerings.
Notes:
Dual rank
2. CL = CAS (READ) latency.
3. Not recommended for new designs.
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
tRCD
(ns)
tRP
(ns)
tRC
(ns)
CL = 6
CL = 5
800
667
667
–
CL = 4
533
CL = 3
400
-80E
-800
-667
-53E
-40E
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
800
800
–
12.5
15
12.5
15
55
55
55
55
55
533
400
553
400
15
15
553
400
15
15
–
400
400
15
15
–
–
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
© 2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Features
Table 2: Addressing
Parameter
256MB
8K
512MB
8K
1GB
8K
Refresh count
Row address
8K A[12:0]
4 BA[1:0]
8K A[12:0]
4 BA[1:0]
8K A[12:0]
8 BA[2:0]
1Gb (64 Meg x 16)
1K A[9:0]
2 S#[1:0]
Device bank address
Device configuration
Column address
Module rank address
256Mb (16 Meg x 16)
512 A[8:0]
2 S#[1:0]
512Mb (32 Meg x 16)
1K A[9:0]
2 S#[1:0]
Table 3: Part Numbers and Timing Parameters – 256MB Modules
Base device: MT47H16M16,1 256Mb DDR2 SDRAM
Module
Density
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Part Number2
Configuration
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
MT8HTF3264HDY-667__
MT8HTF3264HTY-667__
MT8HTF3264HDY-53E__
MT8HTF3264HTY-53E__
MT8HTF3264HDY-40E__
MT8HTF3264HTY-40E__
256MB
256MB
256MB
256MB
256MB
256MB
5.3 GB/s
5.3 GB/s
4.3 GB/s
4.3 GB/s
3.2 GB/s
3.2 GB/s
3.0ns/667 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
5-5-5
5-5-5
4-4-4
4-4-4
3-3-3
3-3-3
Table 4: Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H32M16,1 512Mb DDR2 SDRAM
Module
Density
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Part Number2
Configuration
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
MT8HTF6464HDY-80E__
MT8HTF6464HTY-80E__
MT8HTF6464HDY-800__
MT8HTF6464HTY-800__
MT8HTF6464HDY-667__
MT8HTF6464HTY-667__
MT8HTF6464HDY-53E__
MT8HTF6464HTY-53E__
MT8HTF6464HDY-40E__
MT8HTF6464HTY-40E__
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
6.4 GB/s
6.4 GB/s
6.4 GB/s
6.4 GB/s
5.3 GB/s
5.3 GB/s
4.3 GB/s
4.3 GB/s
3.2 GB/s
3.2 GB/s
2.5ns/800 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
5-5-5
5-5-5
6-6-6
6-6-6
5-5-5
5-5-5
4-4-4
4-4-4
3-3-3
3-3-3
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
© 2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Features
Table 5: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H64M16,1 1Gb DDR2 SDRAM
Module
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Part Number2
Density
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
Configuration
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
MT8HTF12864HDY-80E__
MT8HTF12864HTY-80E__
MT8HTF12864HDY-800__
MT8HTF12864HTY-800__
MT8HTF12864HDY-667__
MT8HTF12864HTY-667__
MT8HTF12864HDY-53E__
MT8HTF12864HTY-53E__
MT8HTF12864HDY-40E__
MT8HTF12864HTY-40E__
6.4 GB/s
6.4 GB/s
6.4 GB/s
6.4 GB/s
5.3 GB/s
5.3 GB/s
4.3 GB/s
4.3 GB/s
3.2 GB/s
3.2 GB/s
2.5ns/800 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
5-5-5
5-5-5
6-6-6
6-6-6
5-5-5
5-5-5
4-4-4
4-4-4
3-3-3
3-3-3
1. The data sheet for the base device can be found on Micron’s Web site.
Notes:
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT8HTF6464HDY-667D3.
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
3
© 2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 6: Pin Assignments
200-Pin DDR2 SODIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
200-Pin DDR2 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
VREF
VSS
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
DQS2
VSS
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
A1
VDD
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ42
DQ43
VSS
2
VSS
DQ4
DQ5
VSS
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DM2
VSS
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A0
VDD
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
VSS
3
4
5
DQ0
DQ1
VSS
DQ18
DQ19
VSS
A10
6
DQ22
DQ23
VSS
BA1
RAS#
S0#
7
BA0
DQ48
DQ49
VSS
8
DQ52
DQ53
VSS
9
WE#
VDD
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
DM0
VSS
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
DQS0#
DQS0
VSS
DQ24
DQ25
VSS
DQ28
DQ29
VSS
VDD
CAS#
S1#
NC
DQ6
DQ7
VSS
ODT0
NC
CK1
VSS
CK1#
VSS
DQ2
DQ3
VSS
DM3
NC
VDD
DQS6#
DQS6
VSS
DQS3#
DQS3
VSS
VDD
ODT1
VSS
DQ12
DQ13
VSS
NC
DM6
VSS
VSS
VSS
DQ8
DQ9
VSS
DQ26
DQ27
VSS
DQ32
DQ33
VSS
DQ50
DQ51
VSS
DQ30
DQ31
VSS
DQ36
DQ37
VSS
DQ54
DQ55
VSS
DM1
VSS
DQS1#
DQS1
VSS
CKE0
VDD
DQS4#
DQS4
VSS
DQ56
DQ57
VSS
CK0
CK0#
VSS
CKE1
VDD
DM4
VSS
DQ60
DQ61
VSS
NC
NC
DQ38
DQ39
VSS
DQ10
DQ11
VSS
85 NC/BA21 135
DQ34
DQ35
VSS
DM7
VSS
DQ14
DQ15
VSS
NC
DQS7#
DQS7
VSS
87
89
91
93
95
97
99
VDD
A12
A9
137
139
141
143
145
147
149
VDD
DQ58
DQ59
VSS
A11
A7
DQ44
DQ45
VSS
VSS
DQ40
DQ41
VSS
VSS
DQ62
DQ63
VSS
DQ16
DQ17
VSS
A8
DQ20
DQ21
VSS
A6
VDD
A5
SDA
VDD
DQS5#
DQS5
VSS
DM5
VSS
SCL
A4
SA0
DQS2#
A3
VDDSPD
NC
A2
SA1
1. Pin 85 is NC for 256MB and 512MB or BA2 for 1GB.
Note:
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
CKx,
CK#x
Input
Input
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
DMx,
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
S#x
Input
Input
Input
Input
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
SAx
SCL
Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
CBx
I/O
I/O
I/O
Check bits. Used for system error detection and correction.
Data input/output: Bidirectional data bus.
DQx
DQSx,
DQS#x
Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
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htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Pin Descriptions
Table 7: Pin Descriptions (Continued)
Symbol
Type
Description
SDA
I/O
Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
RDQSx,
RDQS#x
Output
Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disa-
bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Err_Out#
VDD/VDDQ
Output
(open drain)
Parity error output: Parity error found on the command and address bus.
Supply
Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
ule VDD
.
VDDSPD
VREF
VSS
Supply
SPD EEPROM power supply: 1.7–3.6V.
Supply
Reference voltage: VDD/2.
Supply
Ground.
NC
No connect: These pins are not connected on the module.
No function: These pins are connected within the module, but provide no functionality.
Not used: These pins are not used in specific module configurations/operations.
Reserved for future use.
–
–
–
–
NF
NU
RFU
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
S1#
S0#
CS#
CS#
CS#
CS#
UDQS
UDQS#
UDM
UDQS
UDQS#
UDM
LDQS
LDQS#
LDM
LDQS
LDQS#
LDM
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDQS#
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
UDQS
UDQS#
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
UDQS
UDQS#
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U1
U9
U3
U6
DQ
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
LDQS
LDQS#
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
CS#
CS#
CS#
CS#
UDQS
UDQS#
UDM
UDQS
UDQS#
UDM
LDQS
LDQS#
LDM
LDQS
LDQS#
LDM
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDQS#
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LDQS
LDQS#
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
UDQS
UDQS#
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
UDQS
UDQS#
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U2
U8
U4
U5
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
Rank 0: U1–U4
Rank 1: U5, U6, U8, U9
CK0
CK0#
SDA
BA[1/2:0]
A[12:0]
RAS#
BA[1/2:0]: DDR2 SDRAM
A[12:0]: DDR2 SDRAM
RAS#: DDR2 SDRAM
CAS#: DDR2 SDRAM
WE#: DDR2 SDRAM
CKE0: Rank 0
U1, U2, U8, U9
U3, U4, U5, U6
U7
SPD EEPROM
VDDSPD
SPD EEPROM
DDR2 SDRAM
DDR2 SDRAM
SCL
VDD
VREF
VSS
WP A0 A1 A2
CAS#
WE#
CKE0
CK1
CK1#
SA0 SA1 VSS
VSS
DDR2 SDRAM, EEPROM
CKE1
CKE1: Rank 1
ODT0
ODT1
ODT0: Rank 0
ODT1: Rank 1
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
General Description
General Description
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans-
mitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Serial Presence-Detect EEPROM Operation
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
ule type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
(WP) is connected to VSS, permanently disabling hardware write protection.
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in the device data sheet are not implied. Exposure to
absolutemaximumratingconditionsforextendedperiodsmayadverselyaffectreliability.
Table 8: Absolute Maximum Ratings
Symbol
VDD
Parameter
Min
–0.5
–0.5
–40
Max
2.3
2.3
40
Units
V
VDD supply voltage relative to VSS
Voltage on any pin relative to VSS
Input leakage current; Any input 0V ≤ VIN
VIN, VOUT
II
V
Address inputs, RAS#, CAS#,
WE#, S#, CKE, ODT, BA
µA
≤
VDD; VREF input 0V ≤ VIN ≤ 0.95V; (All other
pins not under test = 0V)
CK, CK#
–20
–10
–10
20
10
10
DM
IOZ
DQ, DQS, DQS#
;
µA
Output leakage current; 0V ≤ VOUT ≤ VDDQ
DQ and ODT are disabled
IVREF
TA
VREF leakage current; VREF = valid VREF level
Module ambient operating temperature
–16
0
16
70
85
85
95
µA
°C
°C
°C
°C
Commercial
Industrial
–40
0
1
TC
DDR2 SDRAM component operating tem-
perature2
Commercial
Industrial
–40
1. The refresh rate is required to double when TC exceeds 85°C.
Notes:
2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
able on Micron’s Web site.
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades cor-
relate with component speed grades.
Table 9: Module and Component Speed Grades
DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-1GA
-80E
-800
-667
-53E
-40E
-187E
-25E
-25
-3
-37E
-5E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
IDD Specifications
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 256MB
Values shown for MT47H16M16 DDR2 SDRAM only and are computed from values specified in the 256Mb (16 Meg x 16)
component data sheet
Parameter
Symbol -667
-53E
-40E Units
1
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD0
380
340
320
mA
1
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL
= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =
tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are switching; Data pattern is same as IDD4W
IDD1
420
380
360
mA
2
2
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD2P
40
40
40
mA
mA
mA
mA
IDD2Q
400
320
280
280
200
240
2
IDD2N
2
Active power-down current: All device banks open; tCK =
Fast PDN exit
IDD3P
240
48
200
48
160
48
tCK (IDD); CKE is LOW; Other control and address bus inputs are MR[12] = 0
stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
2
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
IDD3N
440
320
240
mA
mA
1
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
IDD4W
880
780
740
660
580
500
1
Operating burst read current: All device banks open; Continuous burst read, IDD4R
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
mA
2
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
)
IDD5
1440
40
1360
40
1320
40
mA
mA
2
IDD6
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 256MB (Continued)
Values shown for MT47H16M16 DDR2 SDRAM only and are computed from values specified in the 256Mb (16 Meg x 16)
component data sheet
Parameter
Symbol -667
-53E
-40E Units
940 mA
1
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
IDD7
1020
980
1. Value calculated as one module rank in this operating condition; all other module ranks
in IDD2P (CKE LOW) mode.
Notes:
2. Value calculated reflects all module ranks in this operating condition.
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
IDD Specifications
Table 11: DDR2 IDD Specifications and Conditions – 512MB
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)
component data sheet
-80E/-
Parameter
Symbol 800
-667 -53E -40E Units
1
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0
560
500
460
440
mA
1
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
IDD1
680
620
560
520
mA
2
2
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
IDD2P
56
56
56
56
mA
mA
mA
mA
IDD2Q
520
560
440
480
360
400
320
360
2
IDD2N
2
Active power-down current: All device banks open; tCK Fast PDN exit
= tCK (IDD); CKE is LOW; Other control and address bus in- MR[12] = 0
IDD3P
320
96
280
96
240
96
200
96
puts are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
2
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD3N
600
560
480
400
mA
mA
mA
1
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4W
1200 1020
840
800
640
620
1
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
IDD4R
1120
960
2
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5
1840 1480 1400 1360
mA
mA
2
IDD6
56
56
56
56
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
IDD Specifications
Table 11: DDR2 IDD Specifications and Conditions – 512MB (Continued)
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)
component data sheet
-80E/-
Parameter
Symbol 800
-667 -53E -40E Units
1
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK
= tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
IDD7
1500 1420 1380 1360
mA
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
IDD Specifications
Table 12: DDR2 IDD Specifications and Conditions – 1GB (Die Revision A)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
Parameter
Symbol -667
-53E
-40E Units
1
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD0
560
460
440
mA
1
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL
= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =
tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are switching; Data pattern is same as IDD4W
IDD1
540
500
460
mA
2
2
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD2P
56
56
56
mA
mA
mA
mA
IDD2Q
520
560
360
400
320
320
2
IDD2N
2
Active power-down current: All device banks open; tCK =
Fast PDN exit
IDD3P
320
112
600
280
112
480
280
112
440
tCK (IDD); CKE is LOW; Other control and address bus inputs are MR[12] = 0
stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
2
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
IDD3N
mA
mA
1
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
IDD4W
820
900
740
740
640
640
1
Operating burst read current: All device banks open; Continuous burst read, IDD4R
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
mA
mA
2
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD
)
IDD5
2160
2000
1920
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
2
1
IDD6
IDD7
24
24
24
mA
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
1420
1380
1320
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
IDD Specifications
Table 13: DDR2 IDD Specifications and Conditions – 1GB (Die Revision E and G)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
-80E/-
Parameter
Symbol 800
-667 -53E -40E Units
1
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0
628
568
468
468
mA
1
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
IDD1
728
548
508
488
mA
2
2
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
IDD2P
56
56
56
56
mA
mA
mA
mA
IDD2Q
600
640
520
560
360
400
320
320
2
IDD2N
2
Active power-down current: All device banks open; tCK Fast PDN exit
= tCK (IDD); CKE is LOW; Other control and address bus in- MR[12] = 0
IDD3P
320
80
240
80
240
80
240
80
puts are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
2
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD3N
680
600
480
440
mA
mA
mA
1
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4W
1288
1308
828
908
748
748
668
668
1
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
IDD4R
2
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5
2240 2160 2000 1920
mA
mA
2
IDD6
56
56
56
56
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
IDD Specifications
Table 13: DDR2 IDD Specifications and Conditions – 1GB (Die Revision E and G) (Continued)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
-80E/-
Parameter
Symbol 800
-667 -53E -40E Units
1
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK
= tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
IDD7
1788 1428 1348 1228
mA
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256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Serial Presence-Detect
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 14: SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
VDDSPD
VIH
Min
Max
Units
V
Supply voltage
1.7
3.6
Input high voltage: logic 1; All inputs
Input low voltage: logic 0; All inputs
Output low voltage: IOUT = 3mA
VDDSPD × 0.7
VDDSPD + 0.5
V
VIL
–0.6
–
VDDSPD × 0.3
V
VOL
0.4
3
V
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current
ILI
0.1
0.05
1.6
0.4
2
µA
µA
µA
mA
mA
ILO
3
ISB
4
Power supply current, READ: SCL clock frequency = 100 kHz
Power supply current, WRITE: SCL clock frequency = 100 kHz
ICCR
ICCW
1
3
Table 15: SPD EEPROM AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
0.9
–
Units
µs
Notes
SCL LOW to SDA data-out valid
Time bus must be free before a new transition can start
Data-out hold time
tAA
tBUF
tDH
tF
tR
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tSCL
tSU:DAT
tSU:STA
tSU:STO
tWRC
0.2
1.3
200
–
1
µs
ns
–
SDA and SCL fall time
300
300
–
ns
2
2
SDA and SCL rise time
ns
–
Data-in hold time
0
µs
Start condition hold time
Clock HIGH period
0.6
0.6
–
µs
–
µs
–
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
50
–
µs
1.3
–
µs
SCL clock frequency
400
–
kHz
ns
Data-in setup time
100
0.6
0.6
–
Start condition setup time
Stop condition setup time
WRITE cycle time
µs
3
4
–
µs
–
10
ms
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
Notes:
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistance, and the EEPROM does not respond to its slave address.
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
18
© 2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Module Dimensions
Module Dimensions
Figure 3: 200-Pin DDR2 SODIMM
3.8 (0.15)
MAX
Front view
67.75 (2.667)
67.45 (2.656)
2.0 (0.079) R
(2X)
U1
U2
U3
U4
31.15 (1.187)
29.85 (1.175)
1.8 (0.071)
(2X)
20.0 (0.787)
TYP
6.0 (0.236) TYP
1.1 (0.043)
0.9 (0.035)
1.0 (0.039)
0.45 (0.018)
TYP
0.6 (0.024)
TYP
2.0 (0.079)
TYP
TYP
Pin 1
Pin 199
63.6 (2.504)
TYP
Back view
U5
U6
U8
U9
U7
4.0 (0.157) TYP
Pin 2
4.2 (0.165)
TYP
Pin 200
47.4 (1.87)
TYP
11.4 (0.45)
TYP
15.35 (0.6)
TYP
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
Notes:
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for
additional design dimensions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
19
© 2006 Micron Technology, Inc. All rights reserved.
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