ZL30136GG2_技术文档

ZL30136

GbE and Telecom Rate

Network Interface Synchronizer

Short Form Data Sheet

February 2008

Features

Ordering Information

•

Provides synchronous clocks for network interface

ZL30136GGG

ZL30136GG2

64 Pin CABGA

64 Pin CABGA*

Trays

cards that support synchronous Ethernet (SyncE)

in addition to telecom interfaces (T1/E1, DS3/E3,

etc.)

*Pb Free Tin/Silver/Copper

-40°C to +85°C

•

Supports the requirements of ITU-T G.8262 for

Synchronous Ethernet equipment slave clocks

(EEC option 1 and 2)

•

Supports automatic hitless reference switching

and short term holdover during loss of reference

inputs

Synchronizes to telecom reference clocks (2 kHz,

N*8 kHz up to 77.76 MHz) or to Ethernet reference

clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz, and

155.52 MHz)

DPLL can be configured to provide synchronous or

asynchronous clock outputs

•

Generates Ethernet clocks (12.5 MHz, 25 MHz,

50 MHz, 62.5 MHz, or 125 MHz)

•

Configurable through a serial interface (SPI or I²C)

Supports IEEE 1149.1 JTAG Boundary Scan

Programmable telecom synthesizer generates

clock frequencies of any multiple of 8 kHz up to

100 MHz

Applications

•

Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,

or 0.1 Hz

•

GbE network interface cards that support

synchronous Ethernet (SyncE)

Generates several styles of output frame pulses

with selectable pulse width, polarity and frequency

•

GPON ONT/ONU

T1/E1 line cards

DS3/E3 line cards

Provides 3 sync inputs for output frame pulse

alignment

Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

osci

osco

/N1

ref0

Ethernet

APLL

ref1

ref2

/N2

eth_clk

ref

DPLL

Programmable

Synthesizer

N*8kHz

sync0

sync1

sync2

p_clk

p_fp

sync

hold

mode

lock

I²C/SPI

JTAG

Figure 1 - Functional Block Diagram

1

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ZL30136

Short Form Data Sheet

Pin Description

I/O

Type

Pin #

Name

Description

Input Reference

B1

A3

B4

ref0

ref1

ref2

I_u

Input References 2:0 (LVCMOS, Schmitt Trigger). These input references are

available to the DPLL for synchronizing output clocks. All three input references

can lock to 2 kHz or any multiple of 8 kHz up to 77.76 MHz including 25 MHz and

50 MHz. Input ref0 and ref1 have additional configurable pre-dividers allowing

input frequencies of 62.5 MHz, 125 MHz, and 155.52 MHz. These pins are

internally pulled up to V_dd.

A1

A2

A4

sync0

sync1

sync2

I_u

Frame Pulse Synchronization References 2:0 (LVCMOS, Schmitt Trigger).

These are optional frame pulse synchronization inputs associated with input

references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%

duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.

These pins are internally pulled up to V_dd.

Output Clocks and Frame Pulses

D8

G8

G7

eth_clk

p_clk

p_fp

O

Network Output Clock (LVCMOS). This output can be configured to provide

any of the Ethernet clock rates: 12.5 MHz, 25 MHz, 50 MHz, 62.5 MHz, or

125 MHz.

Programmable Telecom Synthesizer - Output Clock (LVCMOS). This output

can be configured to provide telecom clock rates in multiples of 8 kHz up to

77.76 MHz. The default frequency for this output is 2.048 MHz.

Programmable Telecom Synthesizer - Output Frame Pulse (LVCMOS). This

output can be configured to provide virtually any style of output frame pulse. The

default frequency for this frame pulse output is 8 kHz.

Control

G5

rst_b

I

Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To

ensure proper operation, the device must be reset after power-up. Reset should

be asserted for a minimum of 300 ns.

B2

mode

I_u

DPLL Mode Select (LVCMOS, Schmitt Trigger). During reset, the level on this

pin determines the default mode of operation for DPLL (Normal=0 or Freerun=1).

After reset, the mode of operation can be controlled directly with this pin, or by

accessing the dpll_modesel register (0x1F) through the serial interface. This pin

is internally pulled up to Vdd.

Status

E1

lock

hold

O

Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL. This output

goes high when the DPLL’s output is frequency and phase locked to the input

reference.

H1

Holdover Indicator (LVCMOS). This pin goes high when the DPLL enters the

holdover mode.

Serial Interface (SPI/I²C)

C1 sck/scl

I/B Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en = 0,

this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin acts

as the scl pin (bidirectional) for the I²C interface.

5

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ZL30136

Short Form Data Sheet

I/O

Type

Pin #

Name

Description

D2

si/sda

I/B Serial Interface Input (LVCMOS). Serial interface data pin. When i2c_en = 0,

this pin acts as the si pin for the serial interface. When i2c_en = 1, this pin acts as

the sda pin (bidirectional) for the I²C interface.

D1

C2

E2

H2

so

cs_b/asel0

int_b

O

I_u

O

I_u

Serial Interface Output (LVCMOS). Serial interface data output. When i2c_en =

0, this pin acts as the so pin for the serial interface. When i2c_en = 1, this pin is

unused and should be left unconnected.

Chip Select for SPI/Address Select 0 for I²C (LVCMOS). When i2c_en = 0, this

pin acts as the chip select pin (active low) for the serial interface. When i2c_en =

1, this pin acts as the asel0 pin for the I²C interface.

Interrupt Pin (LVCMOS). Indicates a change of device status prompting the

processor to read the enabled interrupt service registers (ISR). This pin is an

open drain, active low and requires an external pulled-up to Vdd.

i2c_en

I²C Interface Enable (LVCMOS). If set high, the I²C interface is enabled, if set

low the SPI interface is enabled. Internally pull-up to Vdd.

APLL Loop Filter

A5

B5

C5

apll_filter

filter_ref0

filter_ref1

A

External Analog PLL Loop Filter Terminal.

Analog PLL External Loop Filter Reference.

JTAG and Test

G4

G2

G3

tdo

O

I_u

Test Serial Data Out (Output). JTAG serial data is output on this pin on the

falling edge of tck. This pin is held in high impedance state when JTAG scan is

not enabled.

tdi

Test Serial Data In (Input). JTAG serial test instructions and data are shifted in

on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it

should be left unconnected.

trst_b

Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by

putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-

up to ensure that the device is in the normal functional state. This pin is internally

pulled up to Vdd. If this pin is not used then it should be connected to GND.

H3

F2

tck

I

Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not

used then it should be pulled down to GND.

tms

I_u

Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of

the TAP controller. This pin is internally pulled up to V_DD. If this pin is not used

then it should be left unconnected.

Master Clock

H4

osci

I

Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz

reference from a clock oscillator (XO) or crystal XTAL. The stability and accuracy

of the clock at this input determines the free-run accuracy and the long term

holdover stability of the output clocks.

H5

osco

O

Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected

when the osci pin is connected to a clock oscillator.

6

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ZL30136

Short Form Data Sheet

I/O

Type

Pin #

Name

Description

Miscellaneous

F5

H6

IC

Internal Connection. Leave unconnected.

Internal Connection. Connect to ground.

No Connection. Leave unconnected.

IC

A7

B3

B8

D7

H7

NC

Power and Ground

C3

C8

E8

F6

F8

G6

H8

V_DD

P

Positive Supply Voltage. +3.3V_DCnominal.

E6

F3

V_CORE

AV_DD

P

Positive Supply Voltage. +1.8V_DCnominal.

B7

C4

P

Positive Analog Supply Voltage. +3.3V_DCnominal.

Positive Analog Supply Voltage. +1.8V_DCnominal.

B6

C7

F1

AV_CORE

P

D3

D4

D5

D6

E3

E4

E5

E7

F4

F7

V_SS

G

Ground. 0 Volts.

A6

A8

C6

G1

AV_SS

G

Analog Ground. 0 Volts.

I -

Input

I_d-

I_u-

Input, Internally pulled down

Input, Internally pulled up

O - Output

A -

P -

Analog

Power

G - Ground

7

Zarlink Semiconductor Inc.

ZL30136

Short Form Data Sheet

1.0 Pin Diagram

TOP VIEW

2

3

4

5

6

7

8

1

A

sync0

ref0

sync1

mode

ref1

NC

sync2

ref2

apll_filter

filter_ref0

filter_ref1

AV_SS

AV_CORE

AV_SS

NC

AV_SS

NC

B

C

AV_DD

sck/

scl

cs_b/

asel0

V_DD

AV_DD

AV_CORE

V_DD

D

E

so

si/

sda

V_SS

NC

eth_clk

lock

int_b

V_SS

V_CORE

V_SS

V_DD

F

AV_CORE

tms

tdi

V_CORE

trst_b

tck

V_SS

IC

V_DD

IC

V_SS

p_fp

NC

V_DD

p_clk

V_DD

G

H

AV_SS

tdo

rst_b

osco

hold

i2c_en

osci

1

- A1 corner is identified by metallized markings.

8

Zarlink Semiconductor Inc.

ZL30136

Short Form Data Sheet

2.0 High Level Overview

The ZL30136 GbE and Telecom Rate Network Interface Synchronizer is a highly integrated device that provides

timing for network interface cards. The DPLL is capable of locking to one of three input references and provides

standard Ethernet clock rates for synchronizing Ethernet PHYs, and a highly programmable clock and frame pulse

for telecom interfaces such as T1/E1, DS3/E3, etc...

This device is ideally suited for systems with network interface cards that are synchronized to a centralized telecom

backplane. The ZL30136 synchronizes to backplane clocks and generates a synchronized and jitter attenuated

Ethernet clock and a PDH clock. A typical application is shown in Figure 2. In this application, the ZL30136

translates a 19.44 MHz clock from the telecom backplane to an Ethernet clock rate for the GbE PHY and filters the

jitter to ensure compliance with related clock standards. A programmable synthesizer provides PDH clocks with

multiples of 8 kHz for generating PDH interface clocks. The ZL30136 allows easy integration of Ethernet line rates

with today’s telecom backplanes.

BITS A

BITS B

Central

Timing

Card

Central

Timing

Card

XOVER

DPLL

ZL30121

19.44 MHz

A

B

Telecom Backplane

A

B

ZL30136

DPLL

APLL

N*8k

APLL

N*8k

125 MHz

GbE

25 MHz

1.544 MHz

GbE

PHY

1.544 MHz

PHY

GbE

Line Card

GbE

Line Card

Figure 2 - Typical Application of the ZL30136

9

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