PUMA84S32000L-70 [MOSAIC]
SRAM Module, 1MX32, 70ns, CMOS, PQCC84, PLASTIC, LCC-84;型号: | PUMA84S32000L-70 |
厂家: | MOSAIC |
描述: | SRAM Module, 1MX32, 70ns, CMOS, PQCC84, PLASTIC, LCC-84 静态存储器 内存集成电路 |
文件: | 总7页 (文件大小:163K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1M x 32 SRAM MODULE
PUMA 84S32000 - 70/85/10
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 2.1 : January 1999
Description
Features
The PUMA 84S32000 is a 32Mbit CMOS Static RAM
•
•
•
Access times of 70/85/100 ns.
organised as 1M x 32 in a JEDEC 84 pin surface mount
J-leaded PLCC, available with access times of 70, 85,
and 100ns. The output width is user configurable as 8,
16 or 32 bits using eight Chip Selects (CS1~8).
The PUMA 84S32000 offers a dramatic space saving
advantage over eight standard 512Kx8 devices. The -L
version has data retention capability and can be used in
battery backup applications.
High Density Package
JEDEC 84 'J' leaded plastic Surface Mount
Package.
•
•
•
Single 5.0 V±10% Power supply.
User Configurable as 8 / 16 / 32 bit wide output.
Operating Power
(32-BIT) 2.51 W (max)
Low Power Standby (-L)
Fully Static operation.
8.25 mW (max)
•
•
•
Data Retention Capability (-L version only).
Multiple ground pins for maximum noise immunity.
Block Diagram
Pin Definition
A0 - A18
WE
OE
11 10
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
NC
NC
D14
D13
D12
GND
D11
D10
D9
NC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
512K x 8
SRAM
512K x 8
SRAM
D0 - D7
NC
D17
D18
D19
GND
D20
D21
D22
D23
VCC
D24
D25
D26
D27
GND
D28
D29
D30
NC
73
72
D0 - D7
CS5
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
CS1
512K x 8
SRAM
512K x 8
SRAM
D8 - D15
CS6
D8 - D15
PUMA 84S32000
CS2
CS3
D8
VCC
D7
VIEW
FROM
ABOVE
512K x 8
SRAM
512K x 8
SRAM
D16 - D23
CS7
D16 - D23
D6
D5
D4
GND
D3
D2
512K x 8
SRAM
512K x 8
SRAM
D24 - D31
CS8
D24 - D31
D1
NC
NC
CS4
NC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Pin Functions
Address Inputs
Data Input/Output
Chip Select
A0 ~ A18
D0 ~ D31
CS1 ~ 8
WE
Package Details
Write Enable
Output Enable
No Connect
OE
Plastic 84 J-Leaded JEDEC PLCC
NC
Power (+5V)
Ground
VCC
GND
ISSUE 2.1 : January 1999
PUMA 84S32000 - 70/85/10
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Voltage on any pin relative to GND
Power Dissipation
VT
PT
-0.3V to 7.0
4.5
V
W
Storage Temperature
TSTG -55 to +125 °C
Notes (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
min
typ
max
Units
Supply Voltage
VCC
VIH
VIL
TA
TAI
4.5
2.2
-0.3
0
5.0
5.5
VCC+0.3
0.8
V
V
V
C
C
Input High Voltage
Input Low Voltage
Operating Temperature
-
-
-
-
(1)
°
70
85
°
-40
( Suffix I )
Notes: (1) Pulse width: -3.0V for less than 40ns.
DC Electrical Characteristics (VCC=5V±10%,TA=-40°C to +85°C)
Parameter
Symbol Test Condition
min typ max Unit
Input Leakage Current
Output Leakage Current
ILI1
ILO
VIN=0V to VCC
VI/O=0V to VCC
-8
-8
-
-
8
8
µA
µA
Operating Supply Current(2) 32 bit ICC32 Cycle time = min 100% duty II/O=0mA
CS=VIL VIN = VIH or VIL
-
-
-
-
456
244
mA
mA
16 bit ICC16 As above.
8 bit ICC8
As above.
-
-
138
mA
Standby Supply Current
(TTL) ISB
CS(1)=VIH, VIN=VILor VIH
CS≥VCC-0.2V,Other inputs = 0~VCC
-
-
-
-
32
2
mA
mA
-L Version (CMOS) ISB1
Output Voltage Low
Output Voltage High
VOL
VOH
IOL = 2.1mA,VCC=Min
IOH = -1.0mA,VCC=Min
-
-
-
0.4
-
V
V
2.2
Notes: (1) CS1~4 or CS5~8 inputs operate simultaneously for 32 bit mode.
Capacitance (VCC=5V, TA=25°C, F=1Mhz)
Parameter
Symbol
Test Condition
min
typ
max
Unit
Input Capacitance Address,OE,WE
CIN1
CI/O
VIN =0V
VI/O=0V
-
-
-
-
64
80
pF
pF
Output Capacitance 8-bit mode (worst case)
Note: These parameters are calculated, not measured.
2
PUMA 84S32000 - 70/85/10
ISSUE 2.1 : January 1999
AC Test Conditions
Output Load
I/O Pin
166Ω
*Input pulse levels: 0.8V to 2.4V
1.76V
*Input rise and fall times: 5 ns
*Input and Output timing reference levels: 1.5V
*Vcc=5V±10%
30pF
*PUMA module is tested in 32 bit mode.
Operation Truth Table
Below is the truth table which applies to each individual SRAM on the module. When operating the
module care should be taken to prevent any two SRAM components which are connected to the same
data byte from driving the bus simultaneously. This will prevent bus contention occurring on the module.
Please refer to the block diagram on the front page of this datasheet.
Mode
CS OE
WE
VCC Current
I/O Pin Reference Cycle
Not Selected
Output Disable
Read
1
0
0
0
X
1
X
1
1
0
ISB1,ISB2
ICC1
High Z
High Z
DOUT
Power Down
0
ICC1
Read Cycle
Write Cycle
Write
X
ICC1
DIN
1 = VIH,
0 = VIL,
X = Don't Care
Low VCC Data Retention Characteristics - L version only
Parameter
Symbol
VDR
Test Condition
CS=VCC-0.2V
min
typ
max
-
Unit
V
VCC for Data Retention
Data Retention Current
Data Retention Time
2.0
-
-
-
-
-
(1)
ICCDR1
VCC = 3.0VA, CS > VCC-0.2V, VIN >0V
See Retention Waveform
1.5 mA
tCDR
tR
0
5
-
-
ns
ms
Operation Recovery Time
See Retention Waveform
3
ISSUE 2.1 : January 1999
PUMA 84S32000 - 70/85/10
AC OPERATING CONDITIONS
Read Cycle
70
85
10
Parameter
Symbol
min
max
min
max
min
max Units
Read Cycle Time
tRC
tAA
70
-
-
85
-
-
100
-
-
100
100
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
35
-
85
85
45
-
Chip Select Access Time
tACS
tOE
-
-
-
Output Enable to Output Valid
Output Hold from Address Change
Output Enable to Output in Low Z
Output Disable to Output in High Z
Chip Disable to Output in High Z
Chip Enable to Output in Low Z
-
-
-
tOH
10
5
10
5
15
5
tOLZ
tOHZ
tCHZ
tCLZ
-
-
-
0
25
25
0
0
25
25
0
0
30
30
0
0
0
0
10
10
10
Write Cycle
70
85
10
Parameter
Symbol
min
max
min
max
min
max Units
Write Cycle Time
tWC
tCW
tAW
tAS
70
60
60
0
-
-
85
70
70
0
-
-
100
80
80
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
-
-
-
-
-
-
Write Pulse Width
tWP
tWR
tDW
tOW
tDH
50
0
-
60
0
-
70
0
-
Write Recovery Time
-
-
-
Data to Write Time Overlap
Output Active from End of Write
Data Hold from Write Time
Write to Output High Z
30
3
-
35
3
-
40
3
-
-
-
-
0
-
0
-
0
-
tWHZ
0
25
0
25
0
30
4
PUMA 84S32000 - 70/85/10
ISSUE 2.1 : January 1999
Read Cycle Timing Waveform(1,2)
t RC
Address
OE
tAA
tOE
tOLZ
tOH
CS1~
8
Don't
care.
tACS
tOHZ (3)
tCLZ (4,5)
Dout
Data Valid
tCHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
tWR(7)
tAS(6)
OE
tAW
tCW
CS1~48
Don't
Care
WE
tOHZ(3,9)
tOW
tWP(2)
(8)
High-Z
Dout
Din
tDW
Data Valid
tDH
High-Z
5
ISSUE 2.1 : January 1999
PUMA 84S32000 - 70/85/10
Write Cycle No.2 Timing Waveform (1,5)
tWC
Address
tAS(6)
tCW
tWR(7)
8
CS1~
tAW
tWP(2)
WE
Dout
Din
tOH
Don't
Care
tWHZ(3,9)
tOW
(4)
(8)
High-Z
tDH
tDW
High-Z
Data Valid
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS1~8 and WE low.
(3) If OE, CS1~8, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS1~8 and WE low, too avoid inadvertant writes.
(7) CS1~8 or WE must be high during address transitions.
(8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
2.2V
tCDR
tR
2.2V
VDR
8
CS1~4 > Vcc -0.2V
CS1~48
0V
6
PUMA 84S32000 - 70/85/10
ISSUE 2.1 : January 1999
Package Information
Dimensions in mm(inches)
Plastic 84 Pin JEDEC Surface mount PLCC
0.10 (0.004)
30.35 (1.195) sq.
30.10 (1.185) sq.
8.50
(0.335) max
1.27
(0.050) typ.
0.46
(0.018) typ.
0.90 (0.035) typ.
Ordering Information
PUMA 84S32000LI - 70
Speed
70
85
10
=
=
=
70 ns
85 ns
100 ns
Temperature Range
Power Consumption
Blank
I
=
=
Commercial Temperature
Industrial Temperature
Blank
L
=
=
Standard
Low Power
Organisation
32000
=
1M x 32 SRAM
configurable as 2M x 16
and 4M x 8
Memory Type
Package
S
=
=
Asynchronous SRAM
5V
PUMA 84
Memory Stack 84 pin 'J'
Leaded
Note :
Although this data is believed to be accurate, the information contained herein, is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express approval of a
company director.
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