PUMA84S32000LI-015 [MOSAIC]
SRAM Module, 1MX32, 15ns, CMOS, PLASTIC, LCC-84;
| 型号： | PUMA84S32000LI-015 |
| 厂家： | 
MOSAIC |
| 描述： | SRAM Module, 1MX32, 15ns, CMOS, PLASTIC, LCC-84 静态存储器 内存集成电路 |
| 文件： | 总7页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1M x 32 SRAM MODULE
PUMA 84S32000 - 012/015/020
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.2 : January 1999
Description
Features
•
•
Very fast access times of 12/15/20 ns .
JEDEC 84 'J' leaded plastic Surface Mount
Package.
The PUMA 84S32000 is a 32Mbit CMOS High Speed
Static RAM organised as 1M x 32 in a JEDEC 84 pin
surface mount J-leaded PLCC, available with access
times of 12, 15, and 20ns. The output width is user
configurable as 8, 16 or 32 bits using eight Chip Selects
(CS1~8).
•
•
Single 5V±10% Power supply.
User Configurable as 8 / 16 / 32 bit wide output.
The device features low power standby, multiple ground
pins for maximum noise immunity and TTL compatible
inputs and outputs. The PUMA 84S32000 offers a
dramatic space saving advantage over eight standard
512Kx8 devices.
•
Operating Power
(32-BIT) 5.28 W (max)
Low Power Standby CMOS
Fully Static operation.
550 mW (max)
•
•
Multiple ground pins for maximum noise immunity.
Block Diagram
Pin Definition
A0 - A18
WE
OE
11 10
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
NC
NC
D14
D13
D12
GND
D11
D10
D9
NC
NC
D17
D18
D19
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
512K x 8
SRAM
512K x 8
SRAM
D0 - D7
D0 - D7
CS5
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
CS1
GND
D20
D21
D22
D23
VCC
D24
D25
D26
D27
GND
D28
D29
D30
NC
512K x 8
SRAM
512K x 8
SRAM
D8 - D15
CS6
D8 - D15
PUMA 84S32000
CS2
CS3
D8
VCC
D7
VIEW
FROM
ABOVE
512K x 8
SRAM
512K x 8
SRAM
D16 - D23
CS7
D16 - D23
D6
D5
D4
GND
D3
D2
512K x 8
SRAM
512K x 8
SRAM
D24 - D31
CS8
D24 - D31
D1
NC
NC
CS4
NC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Pin Functions
Address Inputs
Data Input/Output
Chip Select
A0 ~ A18
D0 ~ D31
CS1 ~ 8
WE
Package Details
Plastic 84 J-Leaded JEDEC PLCC
Write Enable
Output Enable
No Connect
OE
NC
Power (+5V)
Ground
VCC
GND
ISSUE 1.2 : January 1999
PUMA 84S32000 - 012/015/020
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Parameter
Symbol
Min
Typ
Max
Unit
Voltage on any pin relative to VSS
Power Dissipation
VT(2)
PT
-0.5
-
-
-
-
7.0
5.0
150
V
W
oC
Storage Temperature
TSTG
-65
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) VT can be -2.0V pulse of less than 8ns.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
VIH
VIL
TA
4.5
2.2
-0.3
0
5.0
5.5
VCC+0.5
0.8
V
Input High Voltage
Input Low Voltage
Operating Temperature (Commercial)
(Industrial)
-
-
-
-
V
V
oC
70
TAI
-40
85
oC (Suffix I)
DC Electrical Characteristics
(VCC=5V±10%, -40 to 85 C)
Symbol Test Condition
Parameter
Min Typ max Unit
I/P Leakage Current
Address,OE,WE ILI
0V < VIN < VCC
-20
-20
-
-
20
20
µA
µA
Output Leakage Current
ILO
CS = VIH, VI/O = GND to VCC
Operating Supply Current 32-bitmode ICC32 Min. Cycle, CS = VIL, f=fMAX, IOUT = 0mA
16-bitmode ICC16 As Above.
-
-
-
-
-
-
960 mA
640 mA
480 mA
8-bitmode ICC8 As Above.
Standby Supply Current
Output Voltage
TTLlevels ISB1
CS = VIH, f=fMAX
-
-
-
-
-
-
320 mA
100 mA
CMOSlevels ISB2
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V, f=0
VOL IOL = 8.0mA
VOH IOH = -4.0mA
0.4
-
V
V
2.4
-
Notes :
1/ Typical values are at VCC=5.0V,TA=25oC and specified loading.
2/ CS above refers to CS1~4 / CS5~8 for 32 bit mode
3/ At f=fMAX address and data inputs are cycling at maximum frequency.
2
PUMA 84S32000 - 012/015/020
ISSUE 1.2 : January 1999
Capacitance (VCC=5V±10%,TA=25oC)
Note: Capacitance calculated, not measured.
Parameter
Symbol Test Condition
max
Unit
Input Capacitance
I/P Capacitance
I/O Capacitance
(Address,OE,WE)
(Other)
CIN1
CIN2
CI/O
VIN = 0V
VIN = 0V
VI/O = 0V
70
12
62
pF
pF
pF
Worst case (8-bit)
AC Test Conditions
Output Load
I/O Pin
166Ω
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 3ns
1.76V
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
30pF
* VCC=5V±10%
Operation Truth Table
CS
H
L
OE
X
WE
X
DATA PINS
High Impedance
Data Out
SUPPLY CURRENT
ISB1 , ISB2 , ISB3
MODE
Standby
Read
L
H
ICC32 , ICC16 , ICC8
ICC32 , ICC16 , ICC8
ICC32 , ICC16 , ICC8
ISB1 , ISB2 , ISB3
L
H
L
L
Data In
Write
L
L
Data In
Write
L
H
H
High-Impedance
High-Z
Notes : H = VIH : L =VIL : X = VIH or VIL
The above table reflects the operation of each of the RAM's on the module. Care should be taken to avoid
bus contention on data lines using chip select signals.
3
ISSUE 1.2 : January 1999
PUMA 84S32000 - 012/015/020
AC OPERATING CONDITIONS
Read Cycle
012
015
020
Parameter
Symbol min max min max min max
Unit
Read Cycle Time
tRC
12
-
-
12
12
6
15
-
-
15
15
7
20
-
-
20
20
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
Chip Select Access Time
tACS
tOE
-
-
-
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
-
-
-
tOH
3
3
0
0
0
-
3
3
0
0
0
-
3
3
0
0
0
-
tCLZ
tOLZ
tCHZ
tOHZ
-
-
-
-
-
-
6
7
9
6
7
9
Write Cycle
012
015
020
Parameter
Symbol min max min max min max
Unit
Write Cycle Time
tWC
tCW
tAW
tAS
12
10
10
0
-
-
-
-
-
-
6
-
-
-
15
12
12
0
-
-
-
-
-
-
7
-
-
-
20
15
15
0
-
-
-
-
-
-
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
tWP
tWR
tWHZ
tDW
tDH
10
0
12
0
12
0
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
0
0
0
6
7
9
0
0
0
tOW
3
3
3
4
PUMA 84S32000 - 012/015/020
ISSUE 1.2 : January 1999
Read Cycle Timing Waveform (1,2)
t RC
Address
OE
tAA
tOE
tOLZ
tOH
CS
Don't
care.
tACS
tOHZ (3)
tCLZ (4,5)
Dout
Data Valid
tCHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are
not referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
tWR(7)
tAS(6)
OE
tAW
tCW
CS
Don't
Care
WE
t OHZ(3,9)
tOW
tWP(2)
(8)
High-Z
Dout
Din
tDW
Data Valid
tDH
High-Z
5
ISSUE 1.2 : January 1999
PUMA 84S32000 - 012/015/020
Write Cycle No.2 Timing Waveform (1,5)
tWC
Address
tAS(6)
tWR(7)
tCW
CS
tAW
tWP(2)
WE
tOH
Don't
Care
tWHZ(3,9)
tOW
(4)
(8)
High-Z
Dout
tDH
tDW
High-Z
Din
Data Valid
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS and WE low.
(3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes.
(7) CS or WE must be high during address transitions.
(8) When CS are low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
6
PUMA 84S32000 - 012/015/020
ISSUE 1.2 : January 1999
Package Information
Dimensions in mm(inches)
Plastic 84 Pin JEDEC Surface mount PLCC
0.10 (0.004)
30.35 (1.195) sq.
30.10 (1.185) sq.
8.50
(0.335) max
1.27
(0.050) typ.
0.46
(0.018) typ.
0.90 (0.035) typ.
Ordering Information
PUMA 84S32000LI - 012
Speed
012
015
020
=
=
=
12 ns
15 ns
20 ns
Temperature Range
Power Consumption
Blank
I
=
=
Commercial Temperature
Industrial Temperature
Blank
L
=
=
Standard
Low Power
Organisation
32000
=
1M x 32 SRAM
configurable as 2M x 16
and 4M x 8
Memory Type
Package
S
=
=
Asynchronous SRAM
5V + 10% VCC
PUMA 84
Memory Stack 84 pin 'J'
Leaded
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director.
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