MC145202D [MOTOROLA]
Low-Voltage 2.0 GHz PLL Frequency Synthesizer Includes On-Board 64/65 Prescaler; 低电压2.0GHz的PLL频率合成器包括板载64/65预分频器
| 型号： | MC145202D |
| 厂家： | 
MOTOROLA |
| 描述： | Low-Voltage 2.0 GHz PLL Frequency Synthesizer Includes On-Board 64/65 Prescaler |
| 文件： | 总24页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MC145202/D
SEMICONDUCTOR TECHNICAL DATA
F SUFFIX
SOG PACKAGE
CASE 751J
Includes On–Board 64/65 Prescaler
20
The MC145202 is a low–voltage single–package synthesizer with serial
interface capable of direct usage up to 2.0 GHz.
1
The counters are programmed via a synchronous serial port which is SPI
compatible. The serial port is byte-oriented to facilitate control via an MCU. Due
to the innovative BitGrabber Plus registers, the MC145202 may be cascaded
with other peripherals featuring BitGrabber Plus without requiring leading
dummy bits or address bits in the serial data stream. In addition, BitGrabber
Plus peripherals may be cascaded with existing BitGrabber peripherals.
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
DT SUFFIX
TSSOP
CASE 948D
20
1
ORDERING INFORMATION
MC145202F
SOG Package
MC145202DT TSSOP
PIN ASSIGNMENT
Slew–rate control is provided by a special driver designed for the REF
pin.
out
This minimizes interference caused by REF
.
REF
1
2
3
4
5
6
20
19
18
17
16
15
REF
in
out
out
LD
This part includes a differential RF input that may be operated in a
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
D
in
CLK
φ
R
φ
V
ENB
OUTPUT A
OUTPUT B
V
PD
PD
out
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented to
the three counters (R, A, and N) simultaneously.
GND
Rx
V
7
14
13
12
11
DD
8
TEST 2
TEST 1
9
V
f
CC
10
f
in
in
•
•
•
•
•
Maximum Operating Frequency: 2000 MHz @ – 10 dBm
Operating Supply Current: 4 mA Nominal at 3.0 V
Operating Supply Voltage Range (V
and V
Pins): 2.7 to 5.5 V
DD
Operating Supply Voltage Range of Phase Detectors (V
CC
Pin): 2.7 to 5.5 V
PD
Current Source/Sink Phase Detector Output Capability: 1.7 mA @ 5.0 V
1.0 mA @ 3.0 V
•
Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
•
•
•
•
•
•
Operating Temperature Range: – 40 to + 85°C
R Counter Division Range: 1 and 5 to 8191
Dual–Modulus Capability Provides Total Division up to 262,143
High–Speed Serial Interface: 4 Mbps
OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices
Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)
with Four Output Modes
OUTPUT B: Open–Drain
•
Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30 µA
Evaluation Kit Available (Part Number MC145202EVK)
See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
•
•
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.
REV 3
1/98
TN98012300
Motorola, Inc. 1998
BLOCK DIAGRAM
DATA OUT
20
1
f
REF
in
R
OSC OR
4–STAGE
DIVIDER
16
13–STAGE R COUNTER
SELECT
LOGIC
OUTPUT A
PORT
f
V
(CONFIGURABLE)
13
REF
out
3
DOUBLE–BUFFERED
BitGrabber R REGISTER
16 BITS
2
LOCK DETECTOR
AND CONTROL
LD
Rx
18
19
8
6
CLK
SHIFT
REGISTER
AND
CONTROL
LOGIC
BitGrabber C REGISTER
8 BITS
PHASE/FREQUENCY
DETECTOR A AND CONTROL
D
in
PD
out
24
STANDBY
POR
LOGIC
3
4
17
φ
R
PHASE/FREQUENCY
DETECTOR B AND CONTROL
ENB
2
φ
V
BitGrabber A REGISTER
24 BITS
OUTPUT B
(OPEN–
DRAIN
6
12
15
INTERNAL
CONTROL
4
6–STAGE
12–STAGE
N COUNTER
OUTPUT)
A COUNTER
11
10
f
f
in
64/65
PRESCALER
MODULUS
CONTROL
LOGIC
INPUT
AMP
13
9
TEST 2
TEST 1
in
SUPPLY CONNECTIONS:
PIN 12 = V (V+ TO INPUT AMP AND 64/65 PRESCALER)
CC
(V+ TO PHASE/FREQUENCY DETECTORS A AND B)
PIN 5 = V
PD
PIN 14 = V
(V+ TO BALANCE OF CIRCUIT)
DD
PIN 7 = GND (COMMON GROUND)
MC145202
2
MOTOROLA
MAXIMUM RATINGS* (Voltages Referenced to GND, unless otherwise stated)
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any volt-
age higher than maximum rated voltages to this
high–impedance circuit.
Symbol
, V
Parameter
Value
Unit
V
V
DC Supply Voltage (Pins 12 and 14)
DC Supply Voltage (Pin 5)
– 0.5 to + 6.0
CC DD
V
PD
V
DD
– 0.5 to + 6.0
V
V
in
DC Input Voltage
– 0.5 to V
– 0.5 to V
+ 0.5
+ 0.5
V
DD
V
out
DC Output Voltage (except OUTPUT B,
V
DD
PD , φ , φ )
out
R
V
V
out
DC Output Voltage (OUTPUT B, PD
,
– 0.5 to V
+ 0.5
V
out
PD
φ , φ )
R
V
I , I
in PD
DC Input Current, per Pin (Includes
± 10
mA
V
)
PD
DC Output Current, per Pin
DC Supply Current, V and GND Pins
I
± 20
± 30
300
mA
mA
mW
°C
out
I
DD
DD
P
D
Power Dissipation, per Package
Storage Temperature
T
stg
– 65 to + 150
260
T
L
Lead Temperature, 1 mm from Case for
10 Seconds
°C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
ELECTRICAL CHARACTERISTICS
(V
DD
= V
= 2.7 to 5.5 V, Voltages Referenced to GND, unless otherwise stated; V = 2.7 to 5.5 V, T = – 40 to 85°C)
CC
PD A
Guaranteed
Limit
Symbol
Parameter
Maximum Low–Level Input Voltage
(D , CLK, ENB)
in
Test Condition
Unit
V
IL
0.3 x V
V
DD
DD
V
IH
Minimum High–Level Input Voltage
(D , CLK, ENB)
in
0.7 x V
V
mV
V
Hys
Minimum Hysteresis Voltage (CLK, ENB)
V
DD
V
DD
= 2.7 V
= 4.5 V
100
250
V
Maximum Low–Level Output Voltage
(REF , OUTPUT A)
out
I
= 20 µA, Device in Reference Mode
0.1
V
OL
OH
OL
OL
OL
OL
out
V
Minimum High–Level Output Voltage
(REF , OUTPUT A)
out
I
= – 20 µA, Device in Reference Mode
V
– 0.1
V
out
DD
I
I
I
I
Minimum Low–Level Output Current
(REF , LD)
out
V
= 0.3 V
= 0.3 V
= 0.4 V
0.36
mA
out
Minimum Low–Level Output Current
V
0.36
1.0
mA
out
(φ , φ )
R
V
Minimum Low–Level Output Current
(OUTPUT A)
V
V
mA
out
DD
= 4.5 V
Minimum Low–Level Output Current
(OUTPUT B)
V
= 0.4 V
1.0
mA
out
I
I
I
Minimum High–Level Output Current
(REF , LD)
out
V
= V
= V
= V
– 0.3 V
– 0.3 V
– 0.4 V
– 0.36
– 0.36
– 0.6
mA
OH
OH
OH
out
DD
PD
DD
Minimum High–Level Output Current
V
out
mA
(φ , φ )
R
V
Minimum High–Level Output Current
(OUTPUT A Only)
V
mA
out
V
DD
= 4.5 V
(continued)
MOTOROLA
MC145202
3
ELECTRICAL CHARACTERISTICS (continued)
Guaranteed
Limit
Symbol
Parameter
Test Condition
Unit
I
Maximum Input Leakage Current
V
V
= V
= V
or GND, Device in XTAL Mode
± 1.0
µA
in
in
DD
DD
(D , CLK, ENB, REF )
in
in
I
in
Maximum Input Current
(REF )
in
or GND, Device in Reference Mode
± 100
µA
in
I
Maximum Output Leakage Current (PD
)
V
= V
or GND, Output in Floating State
± 130
± 1
nA
µA
µA
OZ
out
out
PD
PD
(OUTPUT B)
Maximum Standby Supply Current
V
out
= V
or GND, Output in High–Impedance State
I
V
in
= V
or GND; Outputs Open; Device in Standby Mode,
DD
30
STBY
(V + V Pins)
Shut–Down Crystal Mode or REF –Static–Low Reference
DD
PD
out
per Figure 21
Mode; OUTPUT B Controlling V
CC
Bit C6 = High Which Selects Phase Detector A,
PD = Open, PD = Static State, Bit C4 = Low Which is
I
Maximum Phase Detector
Quiescent Current (V
750
30
µA
PD
Pin)
PD
out
out
not Standby, I = 170 µA, V
= 5.5 V
Rx
PD
Bit C6 = Low Which Selects Phase Detector B, φ and
R
φ
= Open, φ and φ = Static Low or High, Bit
R V
V
C4 = Low Which is not Standby
I
T
Total Operating Supply Current
f
= 2.0 GHz; REF = 13 MHz @ 1 Vp–p;
mA
*
in
in
(V
DD
+ V
+ V
Pins)
OUTPUT A = Inactive and No Connect; V
REF , φ , φ , PD , LD = No Connect;
D , ENB, CLK = V
(Bit C6 = Low)
= V
,
CC
PD
CC
DD
out
V
R
out
DD
or GND, Phase Detector B Selected
in
* The nominal values are:
4 mA at V
6 mA at V
These are not guaranteed limits.
= 3.0 V and V
= 5.0 V and V
= 3.0 V
= 5.0 V
DD
DD
PD
PD
ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — PD
out
(I
out
≤ 1 mA @ V
= 2.7 V and I
≤ 1.7mA @ V
≥ 4.5 V, V
= V
= 2.7 to 5.5 V, Voltages Referenced to GND)
DD
out
DD
DD
CC
Guaranteed
Limit
Parameter
Test Condition
V
PD
Unit
Maximum Source Current Variation (Part–to–Part)
Maximum Sink–vs–Source Mismatch (Note 3)
Output Voltage Range (Note 3)
NOTES:
V
= 0.5 x V
= 0.5 x V
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
± 15
± 15
%
out
PD
± 15
V
out
11
%
V
PD
11
11
I
I
I
Variation ≤ 15%
Variation ≤ 20%
Variation ≤ 22%
0.5 to 2.2
0.5 to 3.7
0.5 to 4.7
out
out
out
1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for a given temperature within – 40 to + 85°C.
MC145202
MOTOROLA
4
AC INTERFACE CHARACTERISTICS
(V
DD
= V
= 2.7 to 5.5 V, T = – 40 to + 85°C, C = 25 pF, Input t = t = 10 ns; V
= 2.7 to 5.5 V)
PD
CC
A
L
r
f
Figure
No.
Guaranteed
Limit
Symbol
Parameter
Serial Data Clock Frequency (Note: Refer to Clock t below)
Unit
MHz
ns
f
1
dc to 4.0
100
clk
w
t
t
, t
Maximum Propagation Delay, CLK to OUTPUT A (Selected as Data Out)
Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port)
Maximum Propagation Delay, ENB to OUTPUT B
1, 5
PLH PHL
, t
2, 5
150
ns
PLH PHL
t
, t
2, 6
150
ns
PZL PLZ
t
, t
Maximum Output Transition Time, OUTPUT A and OUTPUT B; t only, on OUTPUT B
THL
1, 5, 6
50
ns
TLH THL
C
Maximum Input Capacitance – D , ENB, CLK
in
10
pF
in
TIMING REQUIREMENTS
(V
DD
= V
= 2.7 to 5.5 V, T = – 40 to + 85°C, Input t = t = 10 ns, unless otherwise indicated)
CC A r f
Figure
No.
Guaranteed
Limit
Symbol
, t
Parameter
Unit
ns
t
su
Minimum Setup and Hold Times, D vs CLK
in
3
4
4
1
1
50
h
t
, t , t
su h
Minimum Setup, Hold and Recovery Times, ENB vs CLK
Minimum Pulse Width, ENB
100
ns
rec
t
w
cycles
ns
*
125
t
w
Minimum Pulse Width, CLK
t , t
r f
Maximum Input Rise and Fall Times, CLK
100
µs
* The minimum limit is 3 REF cycles or 195 f cycles, whichever is greater.
in in
MOTOROLA
MC145202
5
SWITCHING WAVEFORMS
t
t
r
f
V
DD
V
50%
DD
90%
50%
10%
ENB
CLK
GND
GND
t
t
PHL
PLH
t
t
w
w
1/f
clk
OUTPUT A
OUTPUT B
50%
t
t
PHL
PLH
t
t
PZL
PLZ
90%
50%
10%
OUTPUT A
(DATA OUT)
50%
10%
t
t
THL
TLH
Figure 1.
Figure 2.
t
t
w
w
V
DD
VALID
ENB
CLK
50%
V
DD
GND
50%
D
in
t
t
su
h
GND
t
rec
V
t
t
h
DD
su
V
DD
50%
50%
CLK
FIRST
CLK
LAST
CLK
GND
GND
Figure 3.
Figure 4.
+V
PD
TEST POINT
TEST POINT
7.5 k
Ω
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
*
*
C
C
L
L
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
Figure 5.
Figure 6.
MC145202
6
MOTOROLA
LOOP SPECIFICATIONS (V
DD
= V
= 2.7 to 5.5 V unless otherwise indicated, T = – 40 to + 85°C)
CC
A
Guaranteed
Operating
Range
Fig.
No.
Symbol
Parameter
Input Sensitivity Range, f
Test Condition
Unit
dBm*
MHz
Min
Max
P
in
500 MHz ≤ f ≤ 2000 MHz
in
7
8
– 10
4
in
f
Input Frequency, REF Externally Driven in
in
Reference Mode
V
in
≥ 400 mV p–p
2.7 ≤ V
4.5 ≤ V
< 4.5 V
≤ 5.5 V
1.5
1.5
20
30
ref
DD
DD
f
Crystal Frequency, Crystal Mode
C1 ≤ 30 pF, C2 ≤ 30 pF, Includes Stray
Capacitance
9
2
15
MHz
XTAL
f
Output Frequency, REF
C = 20 pF, V
L out
≥ 1 V p–p
10, 12
dc
dc
10
2
MHz
MHz
out
out
Operating Frequency of the Phase Detectors
Output Pulse Width (φ , φ , and LD)
f
t
w
f
in Phase with f , C = 20 pF, φ and φ
11, 12
R
V
R
V
L
R
V
active for LD measurement, **
= 2.7 to 5.5 V
V
PD
V
V
V
= 2.7 V
= 4.5 V
= 5.5 V
40
18
14
120
60
50
ns
DD
DD
DD
t
t
,
Output Transition Times (LD, φ , and φ )
C
= 20 pF, V
= 2.7 V,
11, 12
—
80
7
ns
TLH
V
R
L
PD
= V = 2.7 V
CC
V
DD
THL
C
Input Capacitance, REF
—
pF
in
in
*Power level at the input to the dc block.
**When PD
out
is active, LD minimum pulse width is approximately 5 ns.
SINE WAVE
GENERATOR
DC
BLOCK
TEST
POINT
50
Ω PAD
0.01
in
µF
OUTPUT A
TEST
POINT
f
f
SINE WAVE
GENERATOR
in
REF OUTPUT A
in
(f
)
V
50
Ω
DEVICE
UNDER
TEST
(f
)
R
DEVICE
UNDER
TEST
V
in
50
Ω
TEST
POINT
V
GND
V
REF
GND V
CC
DD
out
DD
V
V+
CC
V+
NOTE: Alternately, the 50 Ω pad may be a T network.
Figure 7. Test Circuit
Figure 8. Test Circuit — Reference Mode
TEST
POINT
REF OUTPUT A
in
1 / f REF
out
C1
C2
(f
)
R
DEVICE UNDER
TEST
REF
out
50%
REF
V
out
GND
V
Figure 10. Switching Waveform
CC
DD
V+
TEST POINT
Figure 9. Test Circuit — Crystal Mode
DEVICE
UNDER
TEST
t
C *
w
L
90%
10%
* Includes all probe and
fixture capacitance.
OUTPUT
50%
t
t
TLH
THL
Figure 12. Test Circuit
Figure 11. Switching Waveform
MOTOROLA
MC145202
7
f
(PIN 11)
in
SOG PACKAGE
4
4
1
1
3
3
2
2
3 V
5 V
Figure 13. Normalized Input Impedance at f — Series Format (R + jx)
in
Table 1. Input Impedence at f — Series Format (R + jx), V
in
= 3 V
CC
Frequency
(GHz)
Resistance
Reactance
Capacitance/
Inductance
(Ω)
(Ω)
Marker
1
2
3
4
0.5
1
11.4
12.4
19.8
18.1
– 168
– 59.4
– 34.9
9.43
1.9 pF
2.68 pF
3.04 pF
751 pH
1.5
2
Table 2. Input Impedence at f — Series Format (R + jx), V
in
= 5 V
CC
Frequency
(GHz)
Resistance
Reactance
Capacitance/
Inductance
(Ω)
(Ω)
Marker
1
2
3
4
0.5
1
11.8
11.5
22.2
18.4
–175
– 64.4
– 36.5
1.14
1.82 pF
2.47 pF
2.91 pF
90.4 pH
1.5
2
MC145202
8
MOTOROLA
CLK
PIN DESCRIPTIONS
Serial Data Clock Input (Pin 18)
DIGITAL INTERFACE PINS
Low–to–high transitions on CLK shift bits available at the
D
in
D
pin, while high–to–low transitions shift bits from OUT-
in
Serial Data Input (Pin 19)
PUT A (when configured as Data Out, see Pin 16). The
24–1/2–stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the R
register, or 3 bytes (24 bits) to access the A register (see
Table 3). The values in the C, R, and A registers do not
change during shifting because the transfer of data to the
registers is controlled by ENB.
Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty–four cycles are used to access the A regis-
ter. See Table 3 and Figures 14, 15, and 16. The number of
clocks required for cascaded devices is shown in Figures 23
through 25.
CAUTION
CLK typically switches near 50% of V
and has a
DD
Schmitt–triggered input buffer. Slow CLK rise and fall times
The value programmed for the N counter must be
greater than or equal to the value of the A counter.
are allowed. See the last paragraph of D for more informa-
in
tion.
The 13 least significant bits (LSBs) of the R register are
double–buffered. As indicated above, data is latched into the
first buffer on a 16–bit transfer. (The 3 MSBs are not double–
buffered and have an immediate effect after a 16–bit
transfer.) The second buffer of the R register contains the 13
bits for the R counter. This second buffer is loaded with the
contents of the first buffer when the A register is loaded (a
24–bit transfer). This allows presenting new values to the R,
A, and N counters simultaneously. If this is not required, then
the 16–bit transfer may be followed by pulsing ENB low with
no signal on the CLK pin. This is an alternate method of tran-
sferring data to the second buffer of the R register (see Fig-
ure 16).
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber Plus registers. Therefore, all bits
in the stream are available to be data for the three registers.
Random access of any register is provided (i.e., the registers
may be accessed in any sequence). Data is retained in the
registers over a supply range of 2.7 to 5.5 V. The formats are
shown in Figures 14, 15, and 16.
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
GND (with ENB being a don’t care) or ENB must
be held at the potential of the V+ pin (with CLK be-
ing a don’t care) during power–up. Floating, tog-
gling, or having these pins in the wrong state
during power–up does not harm the chip, but
causes two potentially undesirable effects. First,
the outputs of the device power up in an unknown
state. Second, if two devices are cascaded, the A
Registers must be written twice after power up.
Afterthesetwoaccesses, thetwocascadedchips
perform normally.
ENB
Active Low Enable Input (Pin 17)
D
typically switches near 50% of V
to maximize noise
in
DD
immunity. This input can be directly interfaced to CMOS de-
vices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 kΩ
to 10 kΩ must be used. Parameters to consider when sizing
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an inac-
tive high state, shifting is inhibited and the port is held in the
initialized state. To transfer data to the device, ENB (which
must start inactive high) is taken low, a serial transfer is
the resistor are worst–case I
mum tolerable power consumption, and maximum data rate.
of the driving device, maxi-
OL
made via D and CLK, and ENB is taken back high. The
in
low–to–high transition on ENB transfers data to the C or A
registers and first buffer of the R register, depending on the
data stream length per Table 3.
Table 3. Register Access
(MSBs are shifted in first; C0, R0, and A0 are the LSBs)
Transitions on ENB must not be attempted while CLK is
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs when ENB is high
and CLK is low.
Number
of Clocks
Accessed
Register
Bit
Nomenclature
8
16
24
C Register
R Register
A Register
Not Allowed
See Figures
22 – 25
C7, C6, C5, . . ., C0
R15, R14, R13, . . ., R0
A23, A22, A21, . . ., A0
This input is also Schmitt–triggered and switches near
50% of V , thereby minimizing the chance of loading erro-
DD
Other Values ≤ 32
Values > 32
neous data into the registers. See the last paragraph of D
for more information.
in
For POR information, see the note for the CLK pin.
MOTOROLA
MC145202
9
OUTPUT A
Configurable Digital Output (Pin 16)
nant crystal. Frequency–setting capacitors of appropriate
values, as recommended by the crystal supplier, are con-
nected from each of the two pins to ground (up to a maximum
of 30 pF each, including stray capacitance). An external re-
sistor of 1 MΩ to 15 MΩ is connected directly across the pins
to ensure linear operation of the amplifier. The required con-
nections for the components are shown in Figure 9.
OUTPUT A is selectable as f , f , Data Out, or Port. Bits
R V
A22 and A23 in the A register control the selection; see
Figure 15.
If A23 = A22 = high, OUTPUT A is configured as f . This
signal is the buffered output of the 13–stage R counter. The
R
To turn on the oscillator, bits R15, R14, and R13 must have
an octal value of one (001 in binary, respectively). This is the
active–crystal mode shown in Figure 16. In this mode, the
crystal oscillator runs and the R Counter divides the crystal
frequency, unless the part is in standby. If the part is placed in
standby via the C register, the oscillator runs, but the R
counter is stopped. However, if bits R15 to R13 have a value
of 0, the oscillator is stopped, which saves additional power.
This is the shut–down crystal mode (shown in Figure 16) and
can be engaged whether in standby or not.
f
signal appears as normally low and pulses high. The f
R
R
signal can be used to verify the divide ratio of the R counter.
This ratio extends from 5 to 8191 and is determined by the
binary value loaded into bits R0–R12 in the R register. Also,
direct access to the phase detectors via the REF pin is al-
lowed by choosing a divide value of 1 (see Figure 16). The
maximum frequency at which the phase detectors operate is
in
2 MHz. Therefore, the frequency of f should not exceed
2 MHz.
R
If A23 = high and A22 = low, OUTPUT A is configured as
In the reference mode, REF (Pin 20) accepts a signal
in
f . This signal is the buffered output of the 12–stage N
counter. The f signal appears as normally low and pulses
high. The f signal can be used to verify the operation of the
V
prescaler, A counter, and N counter. The divide ratio between
V
from an external reference oscillator, such as a TCXO. A sig-
V
nal swinging from at least the V to V levels listed in the
IL IH
Electrical Characteristics table may be directly coupled to the
pin. If the signal is less than this level, ac coupling must be
used as shown in Figure 8. Due to an on–board resistor
which is engaged in the reference modes, an external bias-
the f input and the f signal is N × 64 + A. N is the divide
in
V
ratio of the N counter and A is the divide ratio of the A
counter. These ratios are determined by bits loaded into the
A register. See Figure 15. The maximum frequency at which
the phase detectors operate is 2 MHz. Therefore, the fre-
ing resistor tied between REF and REF
With the reference mode, the REF
out
the output of a divider. As an example, if bits R15, R14, and
R13 have an octal value of seven, the frequency at REF is
the REF frequency divided by 16. In addition, Figure 16
in
is not required.
in
out
pin is configured as
quency of f should not exceed 2 MHz.
V
out
If A23 = low and A22 = high, OUTPUT A is configured as
Data Out. This signal is the serial output of the 24–1/2–stage
shift register. The bit stream is shifted out on the high–to–low
transition of the CLK input. Upon power up, OUTPUT A is
automatically configured as Data Out to facilitate cascading
devices.
If A23 = A22 = low, OUTPUT A is configured as Port. This
signal is a general–purpose digital output which may be used
as an MCU port expander. This signal is low when the Port
bit (C1) of the C register is low, and high when the Port bit is
high.
shows how to obtain ratios of eight, four, and two. A ratio of
one–to–one can be obtained with an octal value of three.
Upon power up, a ratio of eight is automatically initialized.
The maximum frequency capability of the REF
pin is listed
in the Loop Specifications table for an output swing of
out
1 V p–p and 20 pF loads. Therefore, for higher REF fre-
in
quencies, the one–to–one ratio may not be used for this
magnitude of signal swing and loading requirements. Like-
wise, for REF frequencies above two times the highest
in
rated frequency, the ratio must be more than two.
The output has a special on–board driver that has slew–
rate control. This feature minimizes interference in the ap-
plication.
OUTPUT B
Open–Drain Digital Output (Pin 15)
This signal is a general–purpose digital output which may
be used as an MCU port expander. This signal is low when
the Out B bit (C0) of the C register is low. When the Out B bit
is high, OUTPUT B assumes the high–impedance state.
OUTPUT B may be pulled up through an external resistor or
active circuitry to any voltage less than or equal to the poten-
If REF
is unused, an octal value of two should be used
for R15, R14, and R13 and the REF pin should be floated.
out
out
A value of two allows REF to be functional while disabling
in
REF , which minimizes dynamic power consumption.
out
LOOP PINS
tial of the V
pin. Note: the maximum voltage allowed on
PD
pin is 5.5 V.
the V
PD
Upon power–up, power–on reset circuitry forces OUTPUT
B to a low level.
f
and f
in
in
Frequency Inputs (Pins 11 and 10)
These pins are frequency inputs from the VCO. These pins
feed the on–board RF amplifier which drives the 64/65 pre-
scaler. These inputs may be fed differentially. However, they
are usually used in a single–ended configuration (shown in
REFERENCE PINS
REF and REF
in
out
Reference Input and Reference Output (Pins 20 and 1)
Configurable pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode or the reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 16.
In crystal mode, these pins form a reference oscillator
when connected to terminals of an external parallel–reso-
Figure 7). Note that f is driven while f must be tied to
ground via a capacitor.
in in
Motorola does not recommend driving f while terminating
in
because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the
Loop Specifications table.
f
in
MC145202
10
MOTOROLA
PD
ture. Note that when disabled or in standby, φ and φ are
R V
forced to their rest condition (high state).
out
Single–Ended Phase/Frequency Detector Output (Pin 6)
The φ and φ output signal swing is approximately from
R
V
This is a three–state current–source/sink output for use as
a loop error signal when combined with an external low–pass
filter. The phase/frequency detector is characterized by a lin-
ear transfer function. The operation of the phase/frequency
detector is described below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
GND to V
.
PD
LD
Lock Detector Output (Pin 2)
This output is essentially at a high level with narrow low–
going pulses when the loop is locked (f and f of the same
R
V
Frequency of f > f or Phase of f Leading f : current–
V
R
V
R
phase and frequency). The output pulses low when f and f
V
R
sinking pulses from a floating state
Frequency of f < f or Phase of f Lagging f : current–
are out of phase or different frequencies. LD is the logical
ANDing of φ and φ (see Figure 17).
V
R
V
R
R
V
sourcing pulses from a floating state
Frequency and Phase of f = f : essentially a floating
This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on–chip initializa-
tion circuitry disables LD to a static low logic level to prevent
a false “lock” signal. If unused, LD should be disabled and
left open.
V
R
state; voltage at pin determined by loop filter
POL bit (C7) = high
Frequency of f > f or Phase of f Leading f : current–
V
R
V
R
sourcing pulses from a floating state
Frequency of f < f or Phase of f Lagging f : current–
The LD output signal swing is approximately from GND to
V
R
V
R
V
.
DD
sinking pulses from a floating state
Frequency and Phase of f = f : essentially a floating
V
R
Rx
state; voltage at pin determined by loop filter
External Resistor (Pin 8)
This output can be enabled, disabled, and inverted via the
A resistor tied between this pin and GND, in conjunction
with bits in the C register, determines the amount of current
C register. If desired, PD
can be forced to the high–imped-
out
ance state by utilization of the disable feature in the C regis-
ter (bit C6). This is a patented feature. Similarly, PD is
that the PD
pin sinks and sources. When bits C2 and C3
out
are both set high, the maximum current is obtained at PD
out
;
out
forced to the high–impedance state when the device is put
into standby (STBY bit C4 = high).
see Tables 4 and 5 for other current values. The recom-
mended value for Rx is 3.9 kΩ. A value of 3.9 kΩ provides
The PD
circuit is powered by V . The phase detector
out
PD
current at the PD
and approximately 1.7 mA @ V
mode. Note that V , not V , is a factor in determining the
current.
pin of approximately 1 mA @ V
= 3 V
out
DD
= 5 V in the 100% current
gain is controllable by bits C3, C2, and C1: gain (in amps per
radian) = PD current divided by 2π.
DD
out
DD PD
When the φ and φ outputs are used, the Rx pin may be
floated.
R
V
φ
and φ (Pins 3 and 4)
V
R
Double–Ended Phase/Frequency Detector Outputs
Table 4. PD
Current*, C1 = Low with
These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented tech-
nique, the detector’s dead zone has been eliminated. There-
fore, the phase/frequency detector is characterized by a
linear transfer function. The operation of the phase/frequen-
cy detector is described below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
out
OUTPUT A not Selected as “Port”;
Also, Default Mode When OUTPUT A
Selected as “Port”
Bit C3
Bit C2
PD
Current*
out
0
0
1
1
0
1
0
1
70%
80%
90%
Frequency of f > f or Phase of f Leading f : φ = nega-
V
R
R
V
R
V
tive pulses, φ = essentially high
100%
Frequency of f < f or Phase of f Lagging f : φ = essen-
V
R
V
R V
* At the time the data sheet was printed, only the 100%
current mode was guaranteed. The reduced current
modes were for experimentation only.
tially high, φ = negative pulses
R
Frequency and Phase of f = f : φ and φ remain essen-
V
R
V
R
tially high, except for a small minimum time period when
both pulse low in phase
POL bit (C7) = high
Table 5. PD
Current*, C1 = High with
out
OUTPUT A not Selected as “Port”
Frequency of f > f or Phase of f Leading f : φ = nega-
V
V
R
V
R
R
Bit C3
Bit C2
PD
Current*
out
tive pulses, φ = essentially high
Frequency of f < f or Phase of f Lagging f : φ = essen-
V
R
V
R
R
0
0
1
1
0
1
0
1
25%
50%
75%
tially high, φ = negative pulses
V
Frequency and Phase of f = f : φ and φ remain essen-
V
R
V
R
100%
tially high, except for a small minimum time period when
both pulse low in phase
These outputs can be enabled, disabled, and inter-
changed via C register bits C6 or C4. This is a patented fea-
* At the time the data sheet was printed, only the 100%
current mode was guaranteed. The reduced current
modes were for experimentation only.
MOTOROLA
MC145202
11
TEST POINT PINS
For optimum performance, V
should be bypassed to
DD
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
TEST 1
Modulus Control Signal (Pin 9)
This pin may be used in conjunction with the Test 2 pin for
access to the on–board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64.
V
CC
Positive Power Supply (Pin 12)
This pin supplies power to the RF amp and 64/65 pres-
caler. The voltage range is +2.7 to +5.5 V with respect to the
CAUTION
GND pin. In standby mode, the V
liamps from the power supply. This current drain can be elim-
inated with the use of transistor Q1 as shown in Figure 21.
pin still draws a few mil-
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
CC
For optimum performance, V
should be bypassed to
CC
TEST 2
Prescaler Output (Pin 13)
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
This pin may be used to access the on–board 64/65 pres-
caler output.
V
PD
CAUTION
Positive Power Supply (Pin 5)
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
This pin supplies power to both phase/frequency detectors
A and B. The voltage applied on this pin may be more or less
than the potential applied to the V
and V
pins. The volt-
DD
CC
is 2.7 to 5.5 V with respect to the GND pin.
For optimum performance, V
PD
age range for V
PD
POWER SUPPLY PINS
should be bypassed to
V
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
DD
Positive Power Supply (Pin 14)
This pin supplies power to the main CMOS digital portion
of the device. Also, this pin, in conjunction with the Rx resis-
tor, determines the internal reference current for the PD
pin. The voltage range is +2.7 to +5.5 V with respect to the
GND pin.
GND
Ground (Pin 7)
out
Common ground.
MC145202
12
MOTOROLA
ENB
CLK
*
1
2
3
4
5
6
7
8
MSB
C7
LSB
C0
C6
C5
C4
C3
C2
C1
D
in
* At this point, the new byte is transferred to the C register and stored. No other registers
are affected.
C7 – POL: Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts PD
out
and interchanges the φ function with φ as depicted in Figure 17. Also see the phase detector output
R
V
pin descriptions for more information. This bit is cleared low at power up.
C6 – PDA/B: Selects which phase/frequency detector is to be used. When set high, enables the output of phase/fre-
quency detector A (PD ) and disables phase/frequency detector B by forcing φ and φ to the static
out
R
V
high state. When cleared low, phase/frequency detector B is enabled (φ and φ ) and phase/frequency
R
V
detector A is disabled with PD
up.
forced to the high–impedance state. This bit is cleared low at power
out
C5 – LDE: Enables the lock detector output when set high. When the bit is cleared low, the LD output is forced
to a static low level. This bit is cleared low at power up.
C4 – STBY: When set, places the CMOS section of device, which is powered by the V
and V
pins, in the
PD
DD
is forced to the high–impedance state, φ and
standby mode for reduced power consumption: PD
out
R
φ
are forced high, the A, N, and R counters are inhibited from counting, and the Rx current is shut
V
off. In standby, the state of LD is determined by bit C5. C5 low forces LD low (no change). C5 high
forces LD static high. During standby, data is retained in the A, R, and C registers. The condition
of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and R15. However,
if REF
= static low is selected, the internal feedback resistor is disconnected and the input is inhibited
out
when in standby; in addition, the REF input only presents a capacitive load. NOTE: Standby does
not affect the other modes of the REF/OSC circuitry.
in
When C4 is reset low, the part is taken out of standby in two steps. First, the REF (only in one
in
mode) resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any f and
R
f
V
signals are inhibited from toggling the phase/frequency detectors and lock detector. Second, when
the first f pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors
are initialized. Immediately after the jam load, the A, N, and R counters begin counting down together.
V
At this point, the f and f pulses are enabled to the phase and lock detectors. (Patented feature.)
R
V
C3, C2 – I2, I1: Controls the PD
out
source/sink current per Tables 4 and 5. With both bits high, the maximum current
is available. Also, see C1 bit description.
C1 – Port: When the OUTPUT A pin is selected as “Port” via bits A22 and A23, C1 determines the state of
OUTPUT A. When C1 is set high, OUTPUT A is forced high; C1 low forces OUTPUT A low. When
OUTPUT A is not selected as “Port,” C1 controls whether the PD
step size is 10% or 25%. (See
out
Tables 4 and 5.) When low, steps are 10%. When high, steps are 25%. Default is 10% steps when
OUTPUT A is selected as “Port.” The Port bit is not affected by the standby mode.
C0 – Out B: Determines the state of OUTPUT B. When C0 is set high, OUTPUT B is high–impedance; C0 low
forces OUTPUT B low. The Out B bit is not affected by the standby mode. This bit is cleared low
at power up.
Figure 14. C Register Access and Format (8 Clock Cycles are Used)
MOTOROLA
MC145202
13
Figure 15. A Register Access and Format (24 Clock Cycles are Used)
MC145202
14
MOTOROLA
ENB
CLK
NOTE NOTE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4
5
MSB
R15
LSB
R0
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D
in
0
1
2
CRYSTAL MODE, SHUT DOWN
CRYSTAL MODE, ACTIVE
0
0
0
0
0
0
0
0
0
·
0
0
0
0
0
0
0
0
0
·
0
0
1
2
3
4
5
6
7
8
·
NOT ALLOWED
0
0
0
0
0
0
0
0
·
R COUNTER =
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
÷
1 (NOTE 6)
REFERENCE MODE, REF ENABLED and REF
in
out
STATIC LOW
3
4
5
6
7
REFERENCE MODE, REF
REFERENCE MODE, REF
REFERENCE MODE, REF
REFERENCE MODE, REF
REFERENCE MODE, REF
= REF (BUFFERED)
in
out
out
out
out
out
R COUNTER =
R COUNTER =
R COUNTER =
R COUNTER =
÷
5
6
7
8
= REF /2
in
in
in
÷
÷
÷
= REF /4
= REF /8 (NOTE 3)
= REF /16
in
·
·
·
·
·
·
·
·
OCTAL VALUE
1
1
F
F
F
F
E
F
R COUNTER =
R COUNTER =
÷
÷
8190
8191
BINARY VALUE
HEXADECIMAL VALUE
NOTES:
1. Bits R15 through R13 control the configurable “OSC or 4–stage divider” block (see Block Diagram).
2. Bits R12 through R0 control the “13–stage R counter” block (see Block Diagram).
3. A power–on initialize circuit forces a default REF to REF
ratio of eight.
in
out
4. At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 – R12
are loaded into the first buffer in the double–buffered section of the R register. Therefore, the R counter divide ratio is not altered yet
and retains the previous ratio loaded. The C and A registers are not affected.
5. Optional load pulse. At this point, bits R0 – R12 are transferred to the second buffer of the R register. The R counter begins dividing
by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. The C and A
registers are not affected. The first buffer of the R register is not affected. Also, see note 3 of Figure 15 for an alternate method of loading
the second buffer in the R register.
6. Allows direct access to reference input of phase/frequency detectors.
Figure 16. R Register Access and Format (16 Clock Cycles are Used)
MOTOROLA
MC145202
15
f
R
REFERENCE
REF
V
V
H
L
÷
R
in
f
V
FEEDBACK
÷ (N x 64 + A)
V
V
H
L
f
in
*
SOURCING CURRENT
FLOAT
PD
out
SINKING CURRENT
V
V
H
L
φ
R
V
V
H
L
φ
V
V
V
H
L
LD
V
H
V
L
= High voltage level
= Low voltage level
*At this point, when both f and f are in phase, the output source and sink circuits are turned on for a short interval.
R
V
NOTE: The PD
either sources or sinks current during out–of–lock conditions. When locked in phase and frequency, the output is in
out
thefloatingconditionandthevoltageatthatpinisdeterminedbythelow–passfiltercapacitor. PD , φ , andφ areshownwith
out
R
V
the polarity bit (POL) = low; see Figure 14 for POL.
Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveforms
MC145202
16
MOTOROLA
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
shift in operating frequency. R1 in Figure 18 limits the drive
level. The use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a ref-
erence frequency to Motorola’s CMOS frequency synthe-
sizers.
frequency (f ) at OUTPUT A as a function of supply voltage.
R
Use of a Hybrid Crystal Oscillator
(REF
is not used because loading impacts the oscillator.)
out
The frequency should increase very slightly as the dc supply
voltage is increased. An overdriven crystal decreases in fre-
quency or becomes unstable with an increase in supply volt-
age. The operating supply voltage must be reduced or R1
must be increased in value if the overdriven condition exists.
The user should note that the oscillator start–up time is pro-
portional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have devel-
oped expertise in CMOS oscillator design with crystals. Dis-
cussions with such manufacturers can prove very helpful
(see Table 6).
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
dc coupled to REF . If the oscillator does not have CMOS
in
logic levels on the outputs, capacitive or ac coupling to REF
may be used (see Figure 8).
in
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Elec-
tronic Engineers Master Catalog, the Gold Book, or similar
publications.
Design an Off–Chip Reference
FREQUENCY SYNTHESIZER
The user may design an off–chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
REF
in
REF
out
R
f
REF (see Figure 8). For large amplitude signals (standard
CMOS logic levels), dc coupling may be used.
in
R1*
Use of the On–Chip Oscillator Circuitry
C1
C2
The on–chip amplifier (a digital inverter) along with an ap-
propriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 18.
* May be needed in certain cases. See text.
Figure 18. Pierce Crystal Oscillator Circuit
The crystal should be specified for a loading capacitance
(C ) which does not exceed approximately 20 pF when used
at the highest operating frequencies listed in the Loop Speci-
L
C
a
REF
in
REF
out
fications table. Assuming R1 = 0 Ω, the shunt load capaci-
tance (C ) presented across the crystal can be estimated to
be:
L
C
C
in
out
C C
in out
C1 • C2
C1 + C2
C =
L
+ C + C
+
stray
C
stray
a
C
+ C
in
out
where
Figure 19. Parasitic Capacitances of the
C
= 5 pF (see Figure 19)
= 6 pF (see Figure 19)
Amplifier and C
in
stray
C
out
C = 1 pF (see Figure 19)
a
C1 and C2 = external capacitors (see Figure 18)
C
C
= the total equivalent external circuit stray
capacitance appearing across the crystal
terminals
S
R
L
stray
S
e
S
1
2
1
2
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the REF
C
O
in
X
and REF
pins to minimize distortion, stray capacitance,
R
e
2
out
1
stray inductance, and startup stabilization time. Circuit stray
capacitance can also be handled by adding the appropriate
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
stray value to the values for C and C . For this approach,
in out
the term C
becomes 0 in the above expression for C .
L
stray
Power is dissipated in the effective series resistance of the
crystal, R , in Figure 20. The maximum drive level specified
Figure 20. Equivalent Crystal Networks
e
MOTOROLA
MC145202
17
RECOMMENDED READING
Control”, Electro–Technology, June 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May 1966.
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.
E. Hafner, “The Piezoelectric Crystal Unit–Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb.
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Table 6. Partial List of Crystal Manufacturers
Motorola — Internet Address http://motorola.com (Search for resonators)
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE: Motorola cannot recommend one supplier over another and in no way suggests
that this is a complete listing of crystal manufacturers.
MC145202
18
MOTOROLA
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
K
K
φ
VCO
PD
out
(A)
VCO
ω
=
=
n
NC
R
ω
RC
2
K
K
C
R
2
n
φ
VCO
N
ζ
=
C
1 + sRC
sC
Z(s) =
NOTE:
For(A),usingK inampsperradianwiththefilter’simpedancetransferfunction,Z(s),maintainsunitsofvoltsperradianforthedetector/filter
φ
combination.AdditionalsidebandfilteringcanbeaccomplishedbyaddingacapacitorC′ acrossR. Thecornerω =1/RC′ shouldbechosen
c
such that ω is not significantly affected.
n
R
2
K
K
φ
VCO
(B)
ω
=
=
n
NCR
R
1
1
C
φ
R
–
+
ω
R C
2
n
A
VCO
φ
ζ
V
2
R
1
R
2
ASSUMING GAIN A IS VERY LARGE, THEN:
R sC + 1
C
2
F(s) =
R sC
1
NOTE:
For(B),R isfrequentlysplitintotwoseriesresistors;eachresistorisequaltoR dividedby2.AcapacitorC isthenplacedfromthemidpoint
1
1
C
to ground to further filter the error pulses. The value of C should be such that the corner frequency of this network does not significantly
C
affect ω .
n
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
K
φ
K
φ
(Phase Detector Gain) = I
(Phase Detector Gain) = V /2π volts per radian for φ and φ
/2π amps per radian for PD
PDout
PD
out
R
V
2π∆f
VCO
K
VCO
(VCO Transfer Function) =
radians per volt
∆V
VCO
For a nominal design starting point, the user might consider a damping factor ζ ≈ 0.7 and a natural loop frequency ω ≈ (2πf /50) where f
R
n
R
is the frequency at the phase detector input. Larger ω values result in faster loop lock times and, for similar sideband filtering, higher f –related
n
R
VCO sidebands.
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate f –related VCO sidebands. This additional
R
filtering may be active or passive.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1253, An Improved PLL Design Method Without ω and ζ, Motorola Semiconductor Products, Inc., 1995.
n
MOTOROLA
MC145202
19
THRESHOLD
DETECTOR
+ 3 V
MCU
20
1
2
REF
LD
REF
D
out
in
19
18
INTEGRATOR
in
3
φ
R
CLK
ENB
17
16
4
φ
V
5
GENERAL–PURPOSE
DIGITAL OUTPUT
+ 3 V
V
OUTPUT A
OUTPUT B
PD
6
15
14
LOW–PASS
FILTER
PD
out
+ 3 V
7
V
GND
DD
8
13
12
11
NC
Rx
Q1
TEST 2
NOTE 2
9
V
NC
TEST 1
CC
10
f
f
in
in
1000 pF
UHF
VCO
UHF OUTPUT
BUFFER
NOTES:
1. When used, the φ and φ outputs are fed to an external combiner/loop filter. See the Phase–
R
V
Locked Loop — Low–Pass Filter Design page for additional information.
2. Transistor Q1 is required only if the standby feature is needed. Q1 permits the bipolar section
of the device to be shut down via use of the general–purpose digital pin, OUTPUT B. If the stand-
by feature is not needed, tie Pin 12 directly to the power supply.
3. Foroptimumperformance,bypasstheV ,V ,andV
pacitors.
pinstoGNDwithlow–inductanceca-
CC DD
PD
4. TheR counter is programmed for a divide value = REF /f . Typically, f is the tuning resolution
in
R
R
required for the VCO. Also, the VCO frequency divided by f = N = N x 64 + A; this determines
R
T
the values (N, A) that must be programmed into the N and A counters, respectively.
Figure 21. Example Application
DEVICE #1
DEVICE #2
OUTPUT A
OUTPUT A
(DATA OUT)
(DATA OUT)
D
CLK
ENB
D
CLK
ENB
in
in
CMOS
MCU
OPTIONAL
NOTE: See related Figures 23, 24, and 25.
Figure 22. Cascading Two Devices
MC145202
20
MOTOROLA
*
*
Figure 23. Accessing the C Registers of Two
Cascaded MC145202 Devices
Figure 24. Accessing the A Registers of Two
Cascaded MC145202 Devices
MOTOROLA
MC145202
21
Figure 25. Accessing the R Registers of Two Cascaded
MC145202 Devices
MC145202
22
MOTOROLA
PACKAGE DIMENSIONS
F SUFFIX
SOG (SMALL OUTLINE GULL–WING) PACKAGE
CASE 751J–01
NOTES:
–A
–
1. DIMENSIONS “A” AND “B” ARE DATUMS AND
“T” IS A DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
3. CONTROLLING DIM: MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
20
1
11
10
–B
–
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
G
S
10 PL
MILLIMETERS
MIN MAX
12.55 12.80
INCHES
M
M
DIM
A
MIN
MAX
0.504
0.213
0.079
0.018
0.13 (0.005)
B
0.494
0.201
—
B
C
D
G
J
K
L
M
S
5.10
—
0.35
5.40
2.00
0.45
0.014
J
1.27 BSC
0.050 BSC
C
0.18
0.55
0.05
0.23
0.85
0.20
0.007
0.022
0.002
0.009
0.033
0.008
0.10 (0.004)
M
D
20 PL
L
K
SEATING
–T
–
0
°
7°
0°
7°
PLANE
7.40
8.20
0.291
0.323
M
S
S
A
0.13 (0.005)
T
B
DT SUFFIX
TSSOP (THIN SHRUNK SMALL OUTLINE PACKAGE)
CASE 948D–03
A
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
0.200 (0.004)
T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
20
11
10
L
B
PIN 1
IDENTIFICATION
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE –U–.
C
MILLIMETERS
INCHES
-U-
DIM
A
B
C
D
MIN
–––
4.30
–––
0.05
0.45
MAX
6.60
4.50
1.20
0.25
0.55
MIN
MAX
0.260
0.177
0.047
0.010
0.022
–––
0.169
–––
0.100 (0.004)
H
G
D
SEATING
PLANE
-T-
0.002
0.018
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
A
0.275
0.09
0.09
0.16
0.16
6.30
0.375
0.24
0.18
0.32
0.26
6.50
0.011
0.004
0.004
0.006
0.006
0.248
0.015
0.009
0.007
0.013
0.010
0.256
K
K1
J1
J
M
M
0
°
10
°
0
°
10°
A
F
SECTION A-A
MOTOROLA
MC145202
23
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
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