MC14538BDW [MOTOROLA]
Dual Precision Retriggerable/Resettable Monostable Multivibrator; 双路精密可重触发/复式单稳态多谐振荡器
| 型号： | MC14538BDW |
| 厂家： | 
MOTOROLA |
| 描述： | Dual Precision Retriggerable/Resettable Monostable Multivibrator |
| 文件： | 总10页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14538B is a dual, retriggerable, resettable monostable multivibra-
tor. It may be triggered from either edge of an input pulse, and produces an
accurate output pulse over a wide range of widths, the duration and accuracy
P SUFFIX
PLASTIC
CASE 648
of which are determined by the external timing components, C and R .
X
X
•
•
•
•
•
•
•
Unlimited Rise and Fall Time Allowed on the A Trigger Input
Pulse Width Range = 10 µs to 10 s
Latched Trigger Inputs
Separate Latched Reset Inputs
3.0 Vdc to 18 Vdc Operational Limits
Triggerable from Positive (A Input) or Negative–Going Edge (B–Input)
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–pin Compatible with MC14528B and CD4528B (CD4098)
Use the MC54/74HC4538A for Pulse Widths Less Than 10 µs with
Supplies Up to 6 V.
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
*MC14XXXBDW
Plastic
Ceramic
SOIC
•
•
T
A
= – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
BLOCK DIAGRAM
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
C
X
R
X
V
DD
– 0.5 to + 18.0
V
DD
V , V
in out
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
1
2
I , I
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
A
4
5
Q1
Q1
RESET
6
7
B
P
D
Power Dissipation, per Package†
Storage Temperature
500
mW
C
T
stg
– 65 to + 150
260
T
L
Lead Temperature (8–Second Soldering)
C
3
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
C
X
R
X
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
V
DD
15
14
A
B
12
11
ONE–SHOT SELECTION GUIDE
Q2
Q2
10
9
100 ns
MC14528B
1
µs
10
µs
100
µs
1 ms
10 ms 100 ms 1 s
10 s
RESET
MC14536B
MC14538B
23 HR
5 MIN.
13
R
AND C ARE EXTERNAL COMPONENTS.
X
X
MC14541B
MC4538A*
V
V
= PIN 16
DD
SS
= PIN 8, PIN 1, PIN 15
*LIMITED OPERATING VOLTAGE (2 – 6 V)
* Consult factory for possible “D” suffix SOIC
Case 751B.
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
DD
Vdc
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ #
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current, Pin 2 or 14
Input Current, Other Inputs
I
I
15
15
—
—
—
—
—
—
±0.05
±0.1
—
—
—
—
—
±0.00001
±0.00001
25
±0.05
±0.1
—
—
—
—
—
±0.5
±1.0
—
µAdc
µAdc
pF
in
in
Input Capacitance, Pin 2 or 14
Input Capacitance, Other Inputs
C
C
in
in
—
5.0
7.5
—
pF
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
mAdc
µAdc
DD
Q = Low, Q = High
Quiescent Current, Active State
(Both) (Per Package)
I
5.0
10
15
—
—
—
2.0
2.0
2.0
—
—
—
0.04
0.08
0.13
0.20
0.45
0.70
—
—
—
2.0
2.0
2.0
DD
Q = High, Q = Low
–2
= (3.5 x 10 ) R C f + 4C f + 1 x 10 C f
X X
–5
**Total Supply Current at an
external load capacitance (C ) and
at external timing network (R , C )
I
T
5.0
10
I
T
I
T
I
T
X
L
–2
–1
where: I in µA (one monostable switching only),
–5
= (8.0 x 10 ) R C f + 9C f + 2 x 10 C f
X X X L
L
X
–5
= (1.25 x 10 ) R C f + 12C f + 3 x 10 C f
X X
X
X
L
T
X
where: C in µF, C in pF, R in k ohms, and
where: f in Hz is the input frequency.
L
X
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautionsmust be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, V and V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
be left open.
should be constrained to the range V
≤ (V or V ) ≤ V
.
in out
SS
in
out
DD
or V ). Unused outputs must
SS
DD
MC14538B
MOTOROLA CMOS LOGIC DATA
2
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
All Types
Typ #
V
Vdc
DD
Characteristic
Symbol
Unit
Min
Max
Output Rise Time
t
ns
TLH
t
t
t
= (1.35 ns/pF) C + 33 ns
= (0.60 ns/pF) C + 20 ns
= (0.40 ns/pF) C + 20 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH
TLH
TLH
L
L
L
Output Fall Time
t
ns
ns
THL
t
t
t
= (1.35 ns/pF) C + 33 ns
= (0.60 ns/pF) C + 20 ns
= (0.40 ns/pF) C + 20 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
THL
THL
THL
L
L
L
Propagation Delay Time
A or B to Q or Q
t
t
,
PLH
PHL
t
t
t
, t
= (0.90 ns/pF) C + 255 ns
= (0.36 ns/pF) C + 132 ns
= (0.26 ns/pF) C + 87 ns
L
5.0
10
15
—
—
—
300
150
100
600
300
220
PLH PHL
L
L
, t
PLH PHL
, t
PLH PHL
Reset to Q or Q
ns
t
t
t
, t
= (0.90 ns/pF) C + 205 ns
5.0
10
15
—
—
—
250
125
95
500
250
190
PLH PHL
L
, t
= (0.36 ns/pF) C + 107 ns
PLH PHL
L
, t
PLH PHL
= (0.26 ns/pF) C + 82 ns
L
Input Rise and Fall Times
Reset
t , t
r f
5
10
15
—
—
—
—
—
—
15
5
4
µs
ms
—
B Input
A Input
5
10
15
—
—
—
300
1.2
0.4
1.0
0.1
0.05
5
10
15
No Limit
Input Pulse Width
A, B, or Reset
t
t
,
5.0
10
15
170
90
80
85
45
40
—
—
—
ns
ns
µs
WH
WL
Retrigger Time
t
rr
5.0
10
15
0
0
0
—
—
—
—
—
—
Output Pulse Width — Q or Q
Refer to Figures 8 and 9
T
C
C
C
= 0.002 µF, R = 100 kΩ
5.0
10
15
198
200
202
210
212
214
230
232
234
X
X
X
X
= 0.1 µF, R = 100 kΩ
5.0
10
15
9.3
9.4
9.5
9.86
10
10.14
10.5
10.6
10.7
ms
s
X
= 10 µF, R = 100 kΩ
5.0
10
15
0.91
0.92
0.93
0.965
0.98
0.99
1.03
1.04
1.06
X
Pulse Width Match between circuits in
the same package.
100
[(T – T )/T ]
5.0
10
15
—
—
—
± 1.0
± 1.0
± 1.0
± 5.0
± 5.0
± 5.0
%
1
2
1
C
= 0.1 µF, R = 100 kΩ
X
X
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
OPERATING CONDITIONS
External Timing Resistance
External Timing Capacitance
R
C
—
—
5.0
0
—
—
kΩ
µF
X
X
No
Limit†
* The maximum usable resistance R is a function of the leakage of the capacitor C , leakage of the MC14538B, and leakage due to board layout
X
X
and surface resistance. Susceptibility to externally induced noise signals may occur for R > 1 MΩ..
X
†If C > 15 µF, use discharge protection diode per Fig. 11.
X
MOTOROLA CMOS LOGIC DATA
MC14538B
3
V
V
DD
DD
P1
R
X
2
1
(14)
(15)
ENABLE
C2
+
+
C1
–
V
–
R
Q
6 (10)
(9)
V
C
ref1
ref2
X
ENABLE
OUTPUT
LATCH
S
Q
7
N1
V
SS
CONTROL
4
5
(12)
(11)
A
B
NOTE: Pins 1, 8 and 15 must
be externally grounded
Q
S
Q
R
R
R
3
(13)
RESET LATCH
RESET
Figure 1. Logic Diagram
(1/2 of DevIce Shown)
V
DD
0.1 µF
CERAMIC
500 pF
I
D
R
R ′
X
X
V
C
C ′
X
SS
X
V
SS
V
in
C
/R
X
X
A
B
Q
Q
20 ns
20 ns
C
L
RESET
V
DD
90%
10%
C
L
A
′
′
Q′
C
L
V
0 V
B
Q′
in
C
L
RESET
′
V
SS
Figure 2. Power Dissipation Test Circuit and Waveforms
V
DD
INPUT CONNECTIONS
R
R
′
Characteristics
Reset
A
B
X
X
* C = 50 pF
L
C
C
′
t
, t , t , t
,
,
V
PG1
V
DD
X
X
PLH PHL TLH THL
DD
V
V
SS
SS
T, t
, t
WH WL
C
/R
X
t
, t , t
, t
V
DD
V
SS
PG2
PG2
X
PLH PHL TLH THL
A
B
PULSE
GENERATOR
T, t
, t
WH WL
Q
Q
t
, t
PLH(R) PHL(R)
,
PG3
PG1
C
L
t
, t
WH WL
RESET
PULSE
GENERATOR
C
L
A′
Q′
* Includes capacitance of probes,
wiring, and fixture parasitic.
PG1 =
C
L
B
′
Q′
PULSE
GENERATOR
PG2 =
PG3 =
NOTE: Switching test waveforms
C
L
RESET
′
for PG1, PG2, PG3 are shown
In Figure 4.
V
SS
Figure 3. Switching Test Circuit
MC14538B
4
MOTOROLA CMOS LOGIC DATA
90%
10%
50%
50%
V
V
V
DD
DD
DD
A
B
t
t
t
THL
TLH
WH
t
t
TLH
THL
90%
10%
50%
t
WL
t
t
THL
90%
10%
PHL
RESET
50%
t
WL
t
t
t
THL
t
TLH
PLH
T
t
t
rr
t
t
PLH
PHL
90%
10%
50%
50%
50%
50%
Q
t
THL
TLH
t
t
PHL
PLH
PHL
Q
90%
10%
50%
50%
50%
50%
Figure 4. Switching Test Waveforms
T
R
C
= 25°C
= 100 kΩ
= 0.1 µF
A
X
X
0% POINT PULSE WIDTH
R
C
= 100 kΩ
= 0.1 µF
X
X
V
V
V
= 5.0 V, T = 9.8 ms
= 10 V, T = 10 ms
= 15 V, T = 10.2 ms
DD
DD
DD
1.0
0.8
0.6
2
1
0
1
2
0.4
0.2
0
–4
–2
0
2
4
5
6
7
8
9
10
11
12
13
14
15
T, OUTPUT PULSE WIDTH (%)
V , SUPPLY VOLTAGE (VOLTS)
DD
Figure 5. Typical Normalized Distribution
of Units for Output Pulse Width
Figure 6. Typical Pulse Width Variation as
a Function of Supply Voltage V
DD
1000
100
10
FUNCTION TABLE
Inputs
A
Outputs
R
= 100 kΩ, C = 50 pF
L
X
Reset
B
Q
Q
ONE MONOSTABLE SWITCHING ONLY
H
H
H
L
V
= 15 V
DD
H
H
L
Not Triggered
Not Triggered
5.0 V
H
10 V
H
H
L, H,
L
H
L, H,
Not Triggered
Not Triggered
1.0
0.1
L
X
X
X
X
L
H
Not Triggered
0.001
0.1
1.0
OUTPUT DUTY CYCLE (%)
10
100
Figure 7. Typical Total Supply Current
versus Output Duty Cycle
MOTOROLA CMOS LOGIC DATA
MC14538B
5
R
C
= 100 k
Ω
F
X
X
= .002
µ
R
C
= 100 kΩ
= 0.1 µF
X
X
3.0
2.0
V
V
= 15 V
DD
2
1
V
V
= 15 V
= 10 V
1.0
0
DD
= 10 V
= 5 V
DD
0
V
DD
DD
–1
–2
–1.0
–2.0
–3.0
V
= 5.0 V
DD
–60 –40 –20
0
20
40
60
80
100
120 140
–60 –40 –20
0
20
40
60
80
100
120 140
T , AMBIENT TEMPERATURE (
°C)
T , AMBIENT TEMPERATURE (°C)
A
A
Figure 8. Typical Error of Pulse Width
Equation versus Temperature
Figure 9. Typical Error of Pulse Width
Equation versus Temperature
THEORY OF OPERATION
1
3
4
A
B
2
5
RESET
V
V
ref 2
V
ref 2
V
T
ref 2
ref 2
C
/R
X
X
V
V
V
ref 1
V
ref 1
ref 1
ref 1
Q
T
T
1
4
5
Positive edge trigger
Positive edge re–trigger (pulse lengthening)
Positive edge re–trigger (pulse lengthening)
2
3
Negative edge trigger
Positive edge trigger
Figure 10. Timing Operation
TRIGGER OPERATION
comparator C2 turns on. With transistor N1 off, the capacitor
C
V
begins to charge through the timing resistor, R , toward
X
X
The block diagram of the MC14538B is shown in Figure 1,
with circuit operation following.
As shown in Figure 1 and 10, before an input trigger
occurs, the monostable is in the quiescent state with the Q
. When the voltage across C equals V , comparator
ref 2
DD
X
C2 changes state, causing the output latch to reset (Q goes
low) while at the same time disabling comparator C2 ➁. This
ends at the timing cycle with the monostable in the quiescent
state, waiting for the next trigger.
output low, and the timing capacitor C completely charged
X
to V
. When the trigger input A goes from V
to V
In the quiescent state, C is fully charged to V
causing
DD
(while inputs B and Reset are held to V
SS
DD
X
DD
) a valid trigger is
the current through resistor R to be zero. Both comparators
DD
X
recognized, which turns on comparator C1 and N–channel
are “off” with total device current due only to reverse junction
leakages. An added feature of the MC14538B is that the out-
put latch is set via the input trigger without regard to the
capacitor voltage. Thus, propagation delay from trigger to Q
is independent of the value of C , R , or the duty cycle of the
input waveform.
transistor N1 ➀. At the same time the output latch is set. With
transistor N1 on, the capacitor C rapidly discharges toward
X
V
until V
is reached. At this point the output of
SS
ref1
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time
X X
MC14538B
6
MOTOROLA CMOS LOGIC DATA
RETRIGGER OPERATION
change. Since the Q output is reset when an input low level is
detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width specifi-
cation.
The MC14538B is retriggered if a valid trigger occurs ➂ fol-
lowed by another valid trigger ➃ before the Q output has
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
POWER–DOWN CONSIDERATIONS
V , but has not yet reached V , will cause an increase
ref 1 ref 2
in output pulse width T. When a valid retrigger is initiated ➃,
the voltage at C /R will again drop to V before
progressing along the RC charging curve toward V . The Q
DD
output will remain high until time T, after the last valid retrig-
ger.
Large capacitance values can cause problems due to the
large amount of energy stored. When a system containing
the MC14538B is powered down, the capacitor voltage may
X
X
ref 1
discharge from V
at pin 2 or 14. Current through the protection diodes should
be limited to 10 mA and therefore the discharge time of the
through the standard protection diodes
DD
RESET OPERATION
V
supply must not be faster than (V
). (C)/(10 mA). For
DD
example, if V
DD
= 10 V and C = 10 µF, the V supply
DD
The MC14538B may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on Reset sets the reset latch and causes the capacitor to be
DD
X
should discharge no faster than (10 V) x (10 µF)/(10 mA) =
10 ms. This is normally not a problem since power supplies
are heavily filtered and cannot discharge at this rate.
fast charged to V
by turning on transistor P1 ➄. When the
DD
voltage on the capacitor reaches V
, the reset latch will
ref 2
When a more rapid decrease of V
to zero volts occurs,
DD
the MC14538B can sustain damage. To avoid this possibility
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
use an external clamping diode, D , connected as shown in
X
Fig. 11.
D
x
PIN ASSIGNMENT
C
V
V
x
DD
R
x
V
1
2
16
15
V
SS
DD
V
SS
C
/R
A
V
X
X
SS
DD
RESET A
3
4
5
6
7
8
14
13
12
11
10
9
C /R B
X X
A
A
RESET B
Q
Q
B
Q
Q
A
B
A
A
A
B
B
RESET
Q
B
B
V
Q
SS
Figure 11. Use of a Diode to Limit
Power Down Current Surge
MOTOROLA CMOS LOGIC DATA
MC14538B
7
TYPICAL APPLICATIONS
C
X
R
X
C
X
R
X
V
DD
V
RISING–EDGE
TRIGGER
DD
Q
A
B
RISING–EDGE
TRIGGER
Q
Q
A
B
Q
B = V
RESET = V
DD
DD
C
RESET = V
X
R
X
DD
C
X
V
DD
R
X
Q
A = V
SS
V
A
DD
B
Q
Q
FALLING–EDGE
TRIGGER
B
Q
FALLING–EDGE
TRIGGER
RESET = V
DD
RESET = V
DD
Figure 12. Retriggerable
Monostables Circuitry
Figure 13. Non–Retriggerable
Monostables Circuitry
NC
Q
Q
NC
NC
A
B
C
D
V
DD
V
DD
Figure 14. Connection of Unused Sections
MC14538B
8
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MOTOROLA CMOS LOGIC DATA
MC14538B
9
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
–B–
8X P
0.010 (0.25)
M
M
B
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
J
16X D
M
S
S
0.010 (0.25)
T
A
B
F
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
MAX
0.411
0.299
0.104
0.019
0.035
0.400
0.292
0.093
0.014
0.020
R X 45
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
M
SEATING
14X G
K
PLANE
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
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MC14538B/D
◊
相关型号：
MC14538BFR2
4000/14000/40000 SERIES, DUAL MONOSTABLE MULTIVIBRATOR, PDSO16, EIAJ, PLASTIC, SOIC-16
ONSEMI
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