MC145406P [MOTOROLA]
Driver/Receiver(EIA 232-E and CCITT V.28(Formerly RS-232-D); 驱动器/接收器（ EIA 232 - E和CCITT V.28 （前身为RS- 232 -D ）
| 型号： | MC145406P |
| 厂家： | 
MOTOROLA |
| 描述： | Driver/Receiver(EIA 232-E and CCITT V.28(Formerly RS-232-D) |
| 文件： | 总12页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MC145406/D
SEMICONDUCTOR TECHNICAL DATA
EIA 232–E and CCITT V.28 (Formerly RS–232–D)
P SUFFIX
PLASTIC
CASE 648
The MC145406 is a silicon–gate CMOS IC that combines three drivers
and three receivers to fulfill the electrical specifications of standards
EIA 232–E and CCITT V.28. The drivers feature true TTL input
compatibility, slew–rate–limited output, 300–Ω power–off source imped-
ance, and output typically switching to within 25% of the supply rails. The
receivers can handle up to ± 25 V while presenting 3 to 7 kΩ impedance.
Hysteresis in the receivers aids reception of noisy signals. By combining
both drivers and receivers in a single CMOS chip, the MC145406 provides
efficient, low–power solutions for EIA 232–E and V.28 applications.
16
1
DW SUFFIX
SOG
CASE 751G
16
Drivers
•
•
•
•
•
± 5 V to ±12 V Supply Range
300–Ω Power–Off Source Impedance
Output Current Limiting
TTL Compatible
Maximum Slew Rate = 30 V/µs
1
SD SUFFIX
SSOP
CASE 940B
Receivers
•
•
•
± 25 V Input Voltage Range When V
= 12 V, V
= – 12 V
DD
SS
3 to 7 kΩ Input Impedance
Hysteresis on Input Switchpoint
PIN ASSIGNMENT
BLOCK DIAGRAM
V
V
1
2
16
15
CC
DD
RECEIVER
V
DD
V
DD
R
R
R
DO1
DI1
Rx1
Tx1
V
CC
V
CC
*
3
4
5
6
7
14
13
12
11
10
15 k
Ω
D
D
D
Rx
+
DO
–
DO2
5.4 k
Rx2
Tx2
V
1.0 V
1.8 V
SS
DI2
DO3
Rx3
Tx3
HYSTERESIS
V
DI3
V
DD
DRIVER
GND
V
8
9
SS
CC
D = DRIVER
R = RECEIVER
300
Ω
+
–
DI
LEVEL
SHIFT
Tx
1.4 V
V
SS
*Protection circuit
REV 4
1/95
Motorola, Inc. 1995
MAXIMUM RATINGS (Voltage polarities referenced to GND)
This device contains protection circuitry to pro-
tect the inputs against damage due to high static
voltages or electric fields; however, it is advised
that normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high impedance circuit. For proper
operation, it is recommended that the voltages at
the DI and DO pins be constrained to the range
Rating
Symbol
Value
Unit
DC Supply Voltages (V
≥ V
)
V
DD
– 0.5 to + 13.5
+ 0.5 to – 13.5
– 0.5 to + 6.0
V
DD
CC
V
V
SS
CC
Input Voltage Range
Rx1–3 Inputs
V
IR
V
(V
SS
– 15) to (V
+ 15)
DD
+ 0.5)
DI1–3 Inputs
– 0.5 to (V
CC
GND≤V ≤V
andGND≤V
≤V .Also,the
DI CC
DO CC
voltage at the Rx pin should be constrained to
(V – 15 V) ≤ V ≤ (V + 15 V), and Tx
DC Current Per Pin
Power Dissipation
mA
± 100
SS Rx1–3 DD
should be constrained to V ≤ V
≤ V .
P
D
1.0
W
°C
°C
SS
Tx1–3
DD
Unused inputs must always be tied to an ap-
Operating Temperature Range
Storage Temperature Rate
T
A
– 40 to + 85
propriate logic voltage level (e.g., GND or V
DI and Ground for Rx.)
for
CC
T
stg
– 85 to + 150
DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GND = 0 V, T = – 40 to +85°C)
A
Parameter
Symbol
Min
Typ
Max
Unit
DC Supply Voltage
V
V
V
V
V
4.5
– 4.5
4.5
5 to 12
– 5 to – 12
5.0
13.2
– 13.2
5.5
DD
SS
CC DD
DD
V
SS
CC
(V
≥ V
)
V
CC
Quiescent Supply Current (Outputs unloaded, inputs low)
µA
V
DD
V
SS
V
CC
= + 12 V
= – 12 V
= + 5 V
I
—
—
—
140
340
300
400
600
450
DD
I
SS
CC
I
RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V, V
= + 5 to + 12 V, V
= – 5 to – 12 V, V
≥ V , T = – 40 to + 85°C)
CC A
DD
SS
DD
Characteristic
= 5.0 V ± 5%
= 5.0 V ± 5%
Symbol
Min
1.35
Typ
Max
Unit
Input Turn–on Threshold
= V , V
Rx1–Rx3
Rx1–Rx3
Rx1–Rx3
Rx1–Rx3
V
on
1.80
2.35
V
V
DO1–DO3
OL CC
Input Turn–off Threshold
= V , V
V
off
0.75
0.6
1.00
0.8
1.25
—
V
V
V
DO1–DO3
OH CC
Input Threshold Hysteresis
= 5.0 V ± 5%
V
–V
on off
V
CC
Input Resistance
(V – 15 V) ≤ V
R
3.0
5.4
7.0
kΩ
V
in
≤ (V + 15 V)
DD
SS
Rx1–Rx3
High–Level Output Voltage (V
= – 3 V to (V
– 15 V))*
V
OH
Rx1–Rx3
SS
DO1–DO3
4.9
3.8
4.9
4.3
—
—
I
I
= – 20 µA, V
= + 5.0 V
CC
= + 5.0 V
OH
OH
= –1 mA, V
CC
Low–Level Output Voltage (V
= + 3 V to (V
+ 15 V))* DO1–DO3
V
OL
V
Rx1–Rx3
= + 5.0 V
DD
I
I
I
= + 20 µA, V
= + 2 mA, V
—
—
—
0.01
0.02
0.5
0.1
0.5
0.7
OL
OL
OL
CC
CC
= + 5.0 V
= + 5.0 V
= + 4 mA, V
CC
* This is the range of input voltages as specified by EIA 232–E to cause a receiver to be in the high or low logic state.
MC145406
2
MOTOROLA
ELECTRICAL SPECIFICATIONS (Voltage polarities referenced to GND = 0 V, V
= + 5 V ± 5%, T = – 40 to + 85°C)
A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
Digital Input Voltage
Logic 0
DI1–DI3
DI1–DI3
V
V
—
2.0
—
—
0.8
—
IL
Logic 1
V
IH
Input Current
I
in
—
—
± 1.0
µA
V
= V
CC
DI1–DI3
Output High Voltage (V
= Logic 0, R = 3.0 kΩ)
Tx1–Tx3
= – 5.0 V
= – 6.0
SS
= – 12.0 V
V
OH
V
DI1–3
L
V
= + 5.0 V, V
3.5
4.3
9.2
3.9
4.7
9.5
—
—
—
DD
SS
= + 6.0 V, V
V
DD
= + 12.0 V, V
V
DD
= Logic 1, R = 3.0 kΩ)
SS
Output Low Voltage* (V
Tx1–Tx3
= – 5.0 V
= – 6.0 V
V
OL
V
DI1–3
L
V
V
= + 5.0 V, V
= + 6.0 V, V
= + 12.0 V, V
– 4.0
– 4.5
– 10.0
– 4.3
– 5.2
– 10.3
—
—
—
DD
DD
SS
SS
SS
V
= – 12.0 V
DD
Off Source Resistance (Figure 1)
= V = GND = 0 V, V
Tx1–Tx3
300
—
—
Ω
V
= ± 2.0 V
DD
SS
Tx1–Tx3
Output Short–Circuit Current (V
= + 12.0 V, V
= – 12.0 V)
Tx1–Tx3
I
SC
mA
DD
SS
Tx1–Tx3 shorted to GND**
Tx1–Tx3 shorted to ± 15.0 V***
—
—
± 22
± 60
± 60
± 100
*The voltage specifications are in terms of absolute values.
**Specificationis for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits will be exceeded.
***This condition could exceed package limitations.
SWITCHING CHARACTERISTICS (V
= + 5 V ± 5%, T = – 40 to + 85°C; See Figures NO TAG and NO TAG)
A
CC
Drivers
Characteristic
Symbol
Min
Typ
Max
Unit
Propagation Delay Time
Low–to–High
Tx1–Tx3
= 3 kΩ, C = 50 pF
ns
R
t
t
—
—
300
300
500
500
L
L
PLH
High–to–Low
PHL
R
= 3 kΩ C = 50 pF
L
L
Output Slew Rate
Minimum Load
Tx1–Tx3
SR
V/µs
R
= 7 kΩ, C = 0 pF, V
= + 6 to + 12 V, V
= – 6 to – 12 V
—
± 9
± 30
L
L
DD
SS
Maximum Load
R
= 3 kΩ, C = 2500 pF
L
L
V
= + 12 V, V
= – 12 V
4
—
—
—
—
—
DD
V
SS
= + 5 V, V
= – 5 V
SS
DD
Receivers (C = 50 pF)
L
Characteristic
Symbol
Min
Typ
Max
Unit
Propagation Delay Time
Low–to–High
DO1–DO3
ns
t
t
—
—
—
—
150
150
250
40
425
425
400
100
PLH
High–to–Low
Output Rise Time
Output Fall Time
PHL
DO1–DO3
DO1–DO3
t
r
ns
ns
t
f
MOTOROLA
MC145406
3
PIN DESCRIPTIONS
1
16
V
V
CC
DD
V
DD
14
3
Positive Power Supply (Pin 1)
DI1
Tx1
The most positive power supply pin, which is typically + 5
to + 12V.
V
12
10
5
7
in =
± 2 V
DI2
Tx2
V
SS
Negative Power Supply (Pin 8)
The most negative power supply pin, which is typically – 5
to – 12 V.
DI3
Tx3
V
CC
Digital Power Supply (Pin 16)
V
8
V
in
I
SS GND
9
R
=
out
The digital supply pin, which is connected to the logic
power supply (maximum + 5.5 V). V
must be less than
CC
or equal to V
.
DD
GND
Figure 1. Power–Off Source Resistance (Drivers)
Ground (Pin 9)
Ground return pin is typically connected to the signal
ground pin of the EIA 232–E connector (Pin 7) as well as to
the logic power supply ground.
DRIVERS
Rx1, Rx2, Rx3
3 V
DI1–DI3
50%
Receive Data Input (Pins 2, 4, 6)
These are the EIA 232–E receive signal inputs whose
0 V
voltages can range from (V
+ 15 V) to (V
– 15 V). A volt-
DD
+ 15 V) is decoded as a space
SS
t
t
f
r
age between + 3 and (V
DD
and causes the corresponding DO pin to swing to ground (0
V); a voltage between – 3 and (V – 15 V) is decoded as a
V
OH
90%
Tx1–Tx3
DD
10%
t
V
mark and causes the DO pin to swing up to V . The actual
CC
OL
turn–on input switchpoint is typically biased at 1.8 V above
ground, and includes 800mV of hysteresis for noise rejec-
tion. The nominal input impedance is 5 kΩ. An open or
grounded input pin is interpreted as a mark, forcing the DO
t
PLH
PHL
RECEIVERS
+ 3 V
0 V
pin to V
.
CC
Rx1–Rx3
50%
DO1, DO2, DO3
Data Output (Pins 11, 13, 15)
t
t
PLH
PHL
These are the receiver digital output pins, which swing
V
OH
90%
DO1–DO3
from V
to GND. A space on the Rx pin causes DO to pro-
CC
50%
10%
duce a logic 0; a mark produces a logic 1. Each output pin is
capable of driving one LSTTL input load.
V
OL
t
t
r
f
DI1, DI2, DI3
Data Input (Pins 10, 12,14)
Figure 2. Switching Characteristics
These are the high–impedance digital input pins to the
drivers. TTL compatibility is accomplished by biasing the in-
put switchpoint at 1.4 V above GND. However, 5–V CMOS
compatibility is maintained as well. Input voltage levels on
these pins must be between V
and GND.
CC
DRIVERS
Tx1–Tx3
Tx1, Tx2, Tx3
Transmit Data Output(Pins 3, 5, 7)
3 V
3 V
These are the EIA 232–E transmit signal output pins,
which swing toward V
causes the corresponding Tx output to swing toward V . A
logic 0 causes the output to swing toward V
– 3 V
– 3 V
t
and V . A logic 1 at a DI input
DD
SS
t
SHL
SLH
SS
– 3 V – (3 V)
3 V – ( – 3 V)
(the output
or V dependingupon
DD
SLEW RATE (SR) =
OR
t
t
voltages will be slightly less than V
SLH
SHL
DD
SS
the output load). Output slew rates are limited to a maximum
of 30 V per µs. When the MC145406 is off (V = V = V
DD
= GND), the minimum output impedance is 300 Ω.
SS
CC
Figure 3. Slew–Rate Characterization
MC145406
MOTOROLA
4
APPLICATIONS INFORMATION
The MC145406 has been designed to meet the electrical
bias forces the appropriate DO pin to a logic 1 when its Rx
input is open or grounded as called for in the EIA 232–E
specification. Notice that TTL logic levels can be applied to
the Rx inputs in lieu of normal EIA 232–E signal levels. This
might be helpful in situations where access to the modem or
computer through the EIA 232–E connector is necessary
with TTL devices. However, it is important not to connect the
EIA 232–E outputs (Tx1–Tx3) to TTL inputs since TTL oper-
ates off + 5 V only, and may be damaged by the high output
voltage of the MC145406.
specifications of standards EIA 232–E and CCITT V.28.
EIA 232–E defines the electrical and physical interface be-
tween Data Communication Equipment (DCE) and Data
Terminal Equipment (DTE). A DCE is connected to a DTE
using a cable that typically carries up to 25 leads. These
leads, referred to as interchange circuits, allow the transfer
of timing, data, control, and test signals. Electrically this
transfer requires level shifting between the TTL/CMOS log-
ic levels of the computer or modem and the high voltage lev-
els of EIA 232–E, which can range from ± 3 to ± 25 V. The
MC145406 provides the necessary level shifting as well as
meeting other aspects of the EIA 232–E specification.
The DO outputs are to be connected to a TTL or CMOS
input (such as an input to a modem chip). These outputs
will swing from V
to ground, allowing the designer to op-
CC
erate the DO and DI pins from digital power supply. The Tx
and Rx sections are independently powered by V and
DRIVERS
DD
so that one may run logic at + 5 V and the EIA 232–E
V
SS
As defined by the specification, an EIA 232–E driver pres-
ents a voltage of between ± 5 to ± 15 V into a load of be-
tween 3 to 7 kΩ. A logic 1 at the driver input results in a
voltage of between – 5 to – 15 V. A logic 0 results in a voltage
signals at ± 12 V.
POWER SUPPLY CONSIDERATIONS
between + 5 to + 15V. When operating V
and V
at ± 7 to
Figure 4 shows a technique to guard against excessive
device current.
The diode D1 prevents excessive current from flowing
DD
SS
± 12 V, the MC145406 meets this requirement. When operat-
ing at ± 5 V, the MC145406 drivers produce less than
± 5 V at the output (when terminated), which does not meet
EIA 232–E specification. However, the output voltages when
using a ± 5 V power supply are high enough (around
± 4 V) to permit proper reception by an EIA 232–E receiver,
and can be used in applications where strict compliance to
EIA 232–E is not required.
Another requirement of the MC145406 drivers is that
they withstand a short to another driver in the EIA 232–E
cable. The worst–case condition that is permitted by
EIA 232–E is a ± 15 V source that is current limited to 500
mA. The MC145406 drivers can withstand this condition
momentarily. In most short circuit conditions the source
driver will have a series 300 Ω output impedance needed
to satisfy the EIA 232–E driver requirements. This will re-
duce the short circuit current to under 40 mA which is an
acceptable level for the MC145406 to withstand.
through an internal diode from the V
pin to the V
pin
CC
by approximately 0.6 V. This high current
DD
when V
< V
DD
CC
condition can exist for a short period of time during power
up/down. Additionally, if the + 12 V supply is switched off
while the + 5 V is on and the off supply is a low impedance
to ground, the diode D1 will prevent current flow through
the internal diode.
The diode D2 is used as a voltage clamp, to prevent V
SS
from drifting positive to V , in the event that power is re-
CC
(Pin 12). If V
moved from V
power is removed, and the
SS
impedance from the V
SS
pin to ground is greater than
SS
approximately 3 kΩ, this pin will be pulled to V
circuitry causing excessive current in the V
If by design, neither of the above conditions are allowed
to exist, then the diodes D1 and D2 are not required.
by internal
CC
pin.
CC
ESD PROTECTION
Unlike some other drivers, the MC145406 drivers feature
an internally–limited output slew–rate that does not exceed
30 V per µs.
ESD protection on IC devices that have their pins accessi-
ble to the outside world is essential. High static voltages ap-
plied to the pins when someone touches them either directly
or indirectly can cause damage to gate oxides and transistor
junctions by coupling a portion of the energy from the I/O pin
to the power supply buses of the IC. This coupling will usually
occur through the internal ESD protection diodes. The key to
protecting the IC is to shunt as much of the energy to ground
as possible before it enters the IC. Figure 4 shows a tech-
nique which will clamp the ESD voltage at approximately ±
15 V using the MMVZ15VDLT1. Any residual voltage which
appears on the supply pins is shunted to ground through the
capacitors C1–C3. This scheme has provided protection to
the interface part up to ± 10 kV, using the human body model
test.
RECEIVERS
The job of an EIA 232–E receiver is to level–shift voltages
in the range of – 25 to + 25 V down to TTL/CMOS logic lev-
els (0 to + 5 V). A voltage of between – 3 and – 25 V on Rx1
is defined as a mark and produces a logic 1 at DO1. A volt-
age between + 3 and + 25 V is a space and produces a logic
zero. While receiving these signals, the Rx inputs must pres-
ent a resistance between 3 and 7 kΩ. Nominally, the input re-
sistance of the Rx1–Rx3 inputs is 5.4 kΩ.
The input threshold of the Rx1–Rx3 inputs is typically
biased at 1.8 V above ground (GND) with typically 800 mV of
hysteresis included to improve noise immunity. The 1.8 V
MOTOROLA
MC145406
5
V
DD
D1
MMBZ15VDLT
× 6
IN4001
0.1
V
CC
µF
0.1 µF
C1
C2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RxI
TxO
RxI
TO
MC145406
CONNECTOR
TxO
RxI
TxO
IN5818
D2
C3
V
0.1 µF
SS
Figure 4. ESD and Power Supply Networks
MC145406
MOTOROLA
6
+ 5 V
0.1
16
µF
0.1 µF
1
6
V
20 k
Ω
9
V
V
CC
TLA
DSI
DD
DD
MC145406
X
in
C
R
DSI
TLA**
3.579
MHz
R
DSI
DTMF
INPUT
1
MC145442/3
8
3
3
14
15
12
Tx1
8
X
out
DI1
20 k
Ω
17
15
0.1
µF
TxA
CD
TxD
RxD
RxA2
11
5
2
5
4
DO1
2
3
Rx1
Tx2
R
600
Tx
EIA 232–E
DB–25
CONNECTOR
10 kΩ
10 kΩ
10
µ
F
+
16
DI2
TIP
RxA1
14
2
SQT
LB
*
7
600:600
NC 13 DO2
Rx2
Tx3
10 k
Ω
RING
18
10
10
7 NC
6
ExI
FB
V
DI3
DD
C
FB
10 k
Ω
10 k
0.1
µF
DO3
NC11
Rx3
13
7
0.1
µF
MODE
CDA
19
4
V
BYPASS
DD
V
AG
V
CDT
GND
12
GND
9
SS
C
CDA**
0.1
0.1
µF
0.1
C
µ
CDT
F
8
µF
V
BYPASS
SS
0.1
– 5 V
µF
*Line protection circuit
**Refer to the applications information for values of C
and R
CDA
TLA
Figure 5. 5–V 300–Baud Modem with EIA 232–E Interface
MOTOROLA
MC145406
7
1
4
7
*
2
5
8
0
3
6
9
#
MC34119
SPEAKER
DRIVER
MC145412/13/16
PULSE/TONE
DIALER
HOOKSWITCH
LINE
INTERFACE
(TRANSFORMER
AND
RINGING
MC145503
FILTER/
CODEC
MC145426
UDLT
TWISTED
PAIR
PROTECTION)
SYNC
MC34129
SWITCHING
POWER
SUPPLY
(ISOLATED)
+ 5 V
GND
– 5 V
CONNECTION
TO EXTERNAL
TERMINAL
OR PC
MC145406
RS–232
DRIVER
MC145428
DATA
SET
LINE
FILTER
RECEIVER
INTERFACE
Figure 6. Line–Powered Voice/Data Telephone with Electrically Isolated EIA 232–E Interface
MC145406
8
MOTOROLA
TR1
Figure 7. 80–kbps Limited Distance Modem with EIA 232–E Interface (Master)
MOTOROLA
MC145406
9
PACKAGE DIMENSIONS
P SUFFIX
CASE 648–08
NOTES:
-A-
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
0.070
MIN
18.80
6.35
3.69
0.39
1.02
2.54 BSC
1.27 BSC
0.21
MAX
19.55
6.85
4.44
0.53
1.77
F
C
L
0.740
0.250
0.145
0.015
0.040
0.100 BSC
0.050 BSC
0.008
S
SEATING
PLANE
-T-
M
K
0.015
0.130
0.305
0.38
3.30
7.74
H
J
0.110
0.295
2.80
7.50
G
D 16 PL
M
S
0°
10°
0°
10°
M
M
0.25 (0.010)
T
A
0.020
0.040
0.51
1.01
STYLE 1:
PIN 1. CATHODE
2. CATHODE
STYLE 2:
PIN 1. COMMON DRAIN
2. COMMON DRAIN
3. COMMON DRAIN
4. COMMON DRAIN
5. COMMON DRAIN
6. COMMON DRAIN
7. COMMON DRAIN
8. COMMON DRAIN
9. GATE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. SOURCE
11. GATE
12. SOURCE
13. GATE
14. SOURCE
15. GATE
16. SOURCE
DW SUFFIX
CASE 751G–02
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
16
1
9
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
-B- P 8 PL
M
M
0.25 (0.010)
B
8
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
G 14 PL
J
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
MAX
0.411
0.299
0.104
0.019
0.035
F
0.400
0.292
0.093
0.014
0.020
R X 45°
F
1.27 BSC
0.050 BSC
G
J
K
M
P
R
C
0.25
0.10
0.32
0.25
0.010
0.004
0.012
0.009
-T-
0°
7
°
0°
7°
SEATING
PLANE
M
K
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
D 16 PL
0.25 (0.010)
M
S
S
T
A
B
MC145406
10
MOTOROLA
SD SUFFIX
CASE 940B–02
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION IS THE LENGTH OF TERMINAL
FOR SOLDERING TO A SUBSTRATE.
5. TERMINAL POSITIONS ARE SHOWN FOR
REFERENCE ONLY.
16
8
7
L
B
-R-
M
M
0.250 (0.010)
R
1
6. THE LEAD WIDTH DIMENSION DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION.
M
A
-P-
J
F
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
L
MIN
6.10
5.20
1.75
0.25
0.65
MAX
6.30
5.38
1.99
0.38
1.00
MIN
MAX
0.248
0.212
0.078
0.015
0.039
NOTE 4
0.240
0.205
0.069
0.010
0.026
C
-T-
G
0.076 (0.003)
N
D
H
0.65 BSC
0.026 BSC
0.73
0.10
7.65
0
0.90
0.20
7.90
8
0.029
0.004
0.301
0
0.035
0.008
0.311
8
M
S
0.120 (0.005)
T P
M
N
0.05
0.21
0.002
0.008
MOTOROLA
MC145406
11
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