MC54HC162AJ [MOTOROLA]
Presettable Counters; 可预置计数器
| 型号： | MC54HC162AJ |
| 厂家： | 
MOTOROLA |
| 描述： | Presettable Counters |
| 文件： | 总15页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC54/74HC160A and HC162A are identical in pinout to the LS160
and LS162, respectively. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with LSTTL
outputs.
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
The HC160A and HC162A are programmable BCD counters with
asynchronous and synchronous Reset inputs, respectively.
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
16
1
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
•
Chip Complexity: 234 FETs or 58.5 Equivalent Gates
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
Ceramic
Plastic
SOIC
LOGIC DIAGRAM
3
4
5
6
14
13
12
11
Q0
Q1
Q2
Q3
P0
P1
P2
P3
PRESENT
DATA
INPUTS
BCD
OUTPUTS
PIN ASSIGNMENT
RESET
CLOCK
1
2
16
15
V
CC
RIPPLE
CARRY OUT
3
4
14
13
Q0
P0
P1
P2
P3
RIPPLE
CARRY
OUT
2
15
CLOCK
Q1
5
6
12
11
10
9
Q2
Q3
7
8
ENABLE T
LOAD
ENABLE P
GND
RESET
LOAD
ENABLE P
ENABLE T
COUNT
ENABLES
PIN 16 = V
PIN 8 = GND
CC
FUNCTION TABLE
Inputs
Clock Reset* Load Enable P Enable T
Output
Q
Count
Mode
L
X
L
H
H
H
X
X
H
L
X
X
H
X
L
Reset
Load Preset Data
Count
Device
Reset Mode
H
H
H
H
HC160
HC162
BCD
BCD
Asynchronous
Synchronous
No Count
No Count
X
* HC162A only. HC160A is an Asynchronous Reset Device
H = high level
L = low level
X = don’t care
This document contains information on a product under development. Motorola reserves the right to
change or discontinue this product without notice.
9/96
REV 0
Motorola, Inc. 1996
MC54/74HC160A MC54/74HC162A
MAXIMUM RATINGS*
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
CC
– 0.5 to + 7.0
V
in
– 0.5 to V
+ 0.5
V
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
in
± 20
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
DC Supply Current, V
and GND Pins
CC
range GND (V or V
)
V
.
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
MOTOROLA
2
MC54/74HC160A MC54/74HC162A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
– 55 to
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
IL
IL
IL
IL
|I
|
20 µA
out
V
in
= V or V
IH
|I
|
|
2.4 m
4.0 mA
5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
out
|I
|I
|
|
out
out
V
OL
Maximum Low–Level Output
Voltage
V
V
= V or V
IH
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
in
|I
|
20 µA
out
V
in
= V or V
IH
|I
2.4 m
4.0 mA
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
out
|I
|I
|
|
out
out
I
Maximum Input Leakage Current
V
V
= V
= V
or GND
or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
in
CC
CC
I
Maximum Quiescent Supply
Current (per Package)
4
40
160
CC
in
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
3
MOTOROLA
MC54/74HC160A MC54/74HC162A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)*
(Figures 1 and 7)
2.0
3.0
4.5
6.0
6.0
TBD
30
4.8
TBD
24
4.0
TBD
20
MHz
max
PLH
PHL
PHL
PLH
PHL
PLH
PHL
PHL
35
28
24
t
t
t
t
t
t
t
t
Maximum Propagation Delay, Clock to Q
(Figures 1 and 7)
2.0
3.0
4.5
6.0
170
TBD
34
215
TBD
43
255
TBD
51
ns
29
37
43
2.0
3.0
4.5
6.0
205
TBD
41
255
TBD
51
310
TBD
62
35
43
53
Maximum Propagation Delay, Reset to Q (HC160A Only)
(Figures 2 and 7)
2.0
3.0
4.5
6.0
210
TBD
42
265
TBD
53
315
TBD
63
ns
ns
36
45
54
Maximum Propagation Delay, Enable T to Ripple Carry Out
(Figures 3 and 7)
2.0
3.0
4.5
6.0
160
TBD
32
200
TBD
40
240
TBD
48
27
34
41
2.0
3.0
4.5
6.0
195
TBD
39
245
TBD
49
295
TBD
59
33
42
50
Maximum Propagation Delay, Clock to Ripple Carry Out
(Figures 1 and 7)
2.0
3.0
4.5
6.0
175
TBD
35
220
TBD
44
265
TBD
53
ns
30
37
45
2.0
3.0
4.5
6.0
215
TBD
43
270
TBD
54
325
TBD
65
37
46
55
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC160A Only)
(Figures 2 and 7)
2.0
3.0
4.5
6.0
220
TBD
44
275
TBD
55
330
TBD
66
ns
ns
pF
37
47
56
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 7)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
TLH
THL
19
C
Maximum Input Capacitance
—
10
10
10
in
* Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine f . However,
max
in the table above is applicable.
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the f
max
See Applications Information in this data sheet.
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Package)*
pF
60
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
MOTOROLA
4
MC54/74HC160A MC54/74HC162A
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
V
CC
V
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
t
t
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 5)
2.0
3.0
4.5
6.0
150
TBD
30
190
TBD
38
225
TBD
45
ns
su
su
su
su
26
33
38
Minimum Setup Time, Load to Clock
(Figure 5)
2.0
3.0
4.5
6.0
135
TBD
27
170
TBD
34
205
TBD
41
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23
29
35
Minimum Setup Time, Reset to Clock (HC162A only)
(Figure 4)
2.0
3.0
4.5
6.0
160
TBD
32
200
TBD
40
240
TBD
48
27
34
41
Minimum Setup Time, Enable T or Enable P to Clock
(Figure 6)
2.0
3.0
4.5
6.0
200
TBD
40
250
TBD
50
300
TBD
60
34
43
51
t
t
t
t
Minimum Hold Time, Clock to Preset Data Inputs
(Figure 5)
2.0
3.0
4.5
6.0
50
TBD
10
65
TBD
13
75
TBD
15
h
h
h
h
9
11
13
Minimum Hold Time, Clock to Load
(Figure 5)
2.0
3.0
4.5
6.0
3
TBD
3
3
TBD
3
3
TBD
3
3
3
3
Minimum Hold Time, Clock to Reset (HC162A only)
(Figure 4)
2.0
3.0
4.5
6.0
3
TBD
3
3
TBD
3
3
TBD
3
3
3
3
Minimum Hold Time, Clock to Enable T or Enable P
(Figure 6)
2.0
3.0
4.5
6.0
3
TBD
3
3
TBD
3
3
TBD
3
3
3
3
t
t
Minimum Recovery Time, Reset Inactive to Clock (HC160A only)
(Figure 2)
2.0
3.0
4.5
6.0
125
TBD
25
155
TBD
31
190
TBD
38
rec
21
26
32
Minimum Recovery Time, Load Inactive to Clock
(Figure 5)
2.0
3.0
4.5
6.0
125
TBD
25
155
TBD
31
190
TBD
38
rec
21
26
32
t
t
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
80
TBD
16
100
TBD
20
120
TBD
24
w
14
17
20
Minimum Pulse Width, Reset (HC160A only)
(Figure 2)
2.0
3.0
4.5
6.0
80
TBD
16
100
TBD
20
120
TBD
24
w
14
17
20
t , t
r f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
5
MOTOROLA
MC54/74HC160A MC54/74HC162A
CONTROL FUNCTIONS
Resetting
FUNCTION DESCRIPTION
The HC160A/162A are programmable 4–bit synchronous
counters that feature parallel Load, synchronous or asynch-
ronous Reset, a Carry Output for cascading, and count–
enable controls.
The HC160A and HC162A are BCD counters with asynch-
ronous Reset, and synchronous Reset, respectively.
A low level on the Reset pin (pin 1) resets the internal flip–
flops and sets the outputs (Q0 through Q3) to a low level.
The HC160A resets asynchronously and the HC162A resets
with the rising edge of the Clock input (synchronous reset).
Loading
With the rising edge of the Clock, a low level on Load (pin
9) loads the data from the Preset Data Input pins (P0, P1, P2,
P3) into the internal flip–flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load is
low.
Although the HC160A and HC162A are BCD counters,
they may be programmed to any state. If they are loaded with
a state disallowed in BCD code, they will return to their nor-
mal count sequence within two clock pulses (see the Output
State Diagram).
INPUTS
Clock (Pin 2)
The internal flip–flops toggle and the output count ad-
vances with the rising edge of the Clock input. In addition,
control functions, such as resetting (HC162A) and loading
occur with the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the in-
ternal flip–flops and appear at the counter outputs. P0 (pin 3)
is the least–significant bit and P3 (pin 6) is the most–signifi-
cant bit.
Count Enable/Disable
These devices have two count–enable control pins: En-
able P (pin 7) and Enable T (pin 10). The devices count when
these two pins and the Load pin are high. The logic equation
is:
OUTPUTS
Count Enable = Enable P Enable T Load
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
The count is either enabled or disabled by the control in-
puts according to Table 1. In general, Enable P is a count–
enable control; Enable T is both a count–enable and a
Ripple–Carry Output control.
These are the counter outputs (BCD or binary). Q0 (pin 14)
is the least–significant bit and Q3 (pin 11) is the most–signifi-
cant bit.
Table 1. Count Enable/Disable
Ripple Carry Out (Pin 15)
Control Inputs
Result at Outputs
When the counter is in its maximum state (1001 for the
BCD counters or 1111 for the binary counters), this output
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Rip-
ple Carry Out remains high only during the maximum count
state. The logic equation for this output is:
Load Enable P Enable T Q0 – Q3
Ripple Carry Out
H
L
H
H
L
H
H
H
Count
High when Q0–Q3
are maximum*
No Count
X
No Count High when Q0–Q3
are maximum*
X
X
L
No Count
L
Ripple Carry Out = Enable T Q0 Q1 Q2 Q3
for BCD counters HC160A and
HC162A
* Q0 through Q3 are maximum for the HC160A and HC162A when
Q3 Q2 Q1 Q0 = 1001.
OUTPUT STATE DIAGRAMS
HC160A and HC162A BCD Counters
0
1
2
3
4
5
6
7
8
15
14
13
12
11
10
6
9
MOTOROLA
MC54/74HC160A MC54/74HC162A
SWITCHING WAVEFORMS
t
t
t
f
w
r
V
V
CC
CC
90%
CLOCK
50%
RESET
50%
10%
GND
GND
t
PHL
t
w
1/fmax
50%
ANY
OUTPUT
t
t
PHL
PLH
90%
50%
10%
t
ANY
OUTPUT
rec
V
CC
50%
CLOCK
t
t
THL
TLH
GND
Figure 1.
Figure 2.
t
t
f
r
V
CC
50%
RESET
CLOCK
90%
ENABLE T
50%
10%
GND
t
t
t
t
PHL
h
su
PLH
90%
RIPPLE
CARRY
OUT
V
CC
50%
10%
50%
GND
t
t
THL
TLH
Figure 3.
Figure 4. HC162A Only
VALID
INPUTS
P0, P1,
P2, P3
V
CC
50%
GND
t
t
t
su
h
VALID
50%
V
CC
50%
LOAD
ENABLE T
OR
V
CC
GND
ENABLE P
GND
t
t
rec
su
h
t
t
su
h
V
CC
V
CC
50%
CLOCK
CLOCK
50%
GND
GND
Figure 5.
Figure 6.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
* Includes all probe and jig capacitance
Figure 7.
7
MOTOROLA
MC54/74HC160A MC54/74HC162A
MOTOROLA
8
MC54/74HC160A MC54/74HC162A
HC160A, HC162A TIMING DIAGRAM
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine, zero, one, two, and three.
4. Inhibit.
RESET (HC160A)
(ASYNCHRONOUS)
RESET (HC162A)
(SYNCHRONOUS)
LOAD
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK
(HC160A)
CLOCK
(HC162A)
ENABLE P
ENABLE T
Q0
COUNT
ENABLES
Q1
OUTPUTS
Q2
Q3
RIPPLE
CARRY
OUT
7
8
9
0
1
2
3
COUNT
INHIBIT
RESET
LOAD
9
MOTOROLA
MC54/74HC160A MC54/74HC162A
MOTOROLA
10
MC54/74HC160A MC54/74HC162A
TYPICAL APPLICATIONS
CASCADING
N–Bit Synchronous Counters
LOAD
INPUTS
INPUTS
INPUTS
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
ENABLE P
H = COUNT
L = DISABLE
ENABLE P
RIPPLE
ENABLE P
RIPPLE
TO
MORE
SIGNIFICANT
STAGES
RIPPLE
H = COUNT
L = DISABLE
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
ENABLE T
CLOCK
CARRY
OUT
CLOCK
CLOCK
R
Q0 Q1 Q2 Q3
OUTPUTS
R
Q0 Q1 Q2 Q3
OUTPUTS
R
Q0 Q1 Q2 Q3
RESET
CLOCK
OUTPUTS
NOTE: When used in these cascaded configurations the clock f
guaranteed limits may not apply. Actual performance will depend on
max
number of stages. This limitation is due to set up times between Enable (Port) and Clock.
Nibble Ripple Counter
INPUTS
INPUTS
INPUTS
LOAD
ENABLE P
ENABLE T
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
ENABLE P
RIPPLE
ENABLE P
RIPPLE
ENABLE P
RIPPLE
TO
MORE
SIGNIFICANT
STAGES
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
CLOCK
RESET
CLOCK
CLOCK
CLOCK
R
Q0 Q1 Q2 Q3
R
Q0 Q1 Q2 Q3
R
Q0 Q1 Q2 Q3
OUTPUTS
OUTPUTS
OUTPUTS
11
MOTOROLA
MC54/74HC160A MC54/74HC162A
TYPICAL APPLICATION
HC162A
OTHER
Q0
Q1
Q2
Q3
OPTIONAL BUFFER
FOR NOISE REJECTION
INPUTS
OUTPUT
RESET
Modulo–5 Counter
The HC162A facilitates designing counters of any modulus with minimal external logic. The output is glitch–free due to the
synchronous Reset.
MOTOROLA
12
MC54/74HC160A MC54/74HC162A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
NOTES:
16
1
9
8
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
–B
–
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.93
7.49
5.08
0.50
0.750
0.240
—
0.015
0.050 BSC
–T
SEAT
–
ING
N
K
PLANE
F
G
J
K
L
M
N
0.055
0.100 BSC
0.008
0.125
0.065
1.40
2.54 BSC
0.21
3.18
1.65
E
M
0.015
0.170
0.38
4.31
J 16 PL
F
G
0.300 BSC
15
0.040
7.62 BSC
15
1.01
0.51
M
S
0.25 (0.010)
T
B
D 16 PL
°
°
0
°
0
°
M
S
0.25 (0.010)
T
A
0.020
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
9
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
1
8
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
PLANE
–T
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
–
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
0.25 (0.010)
M
S
0°
10°
0°
10°
M
M
T
A
0.020
0.040
0.51
1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
0.050 BSC
0.008
0.004
F
K
R X 45°
C
1.25
1.27 BSC
–T
0.19
0.10
0.25
0.25
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
13
MOTOROLA
MC54/74HC160A MC54/74HC162A
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