MC74HC374N [MOTOROLA]
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20;型号: | MC74HC374N |
厂家: | MOTOROLA |
描述: | HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20 触发器 |
文件: | 总8页 (文件大小:257K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
20
The MC54/74HC374A is identical in pinout to the LS374. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising edge
of the clock. The Output Enable input does not affect the states of the
flip–flops, but when Output Enable is high, the outputs are forced to the
high–impedance state; thus, data may be stored even when the outputs are
not enabled.
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
The HC374A is identical in function to the HC574A which has the input
pins on the opposite side of the package from the output. This device is
similar in function to the HC534A which has inverting outputs.
20
20
20
1
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
1
Low Input Current: 1.0 µA
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
1
•
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
ORDERING INFORMATION
MC54HCXXXAJ
Ceramic
Plastic
SOIC
SSOP
TSSOP
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXASD
MC74HCXXXADT
LOGIC DIAGRAM
2
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
5
6
4
7
PIN ASSIGNMENT
8
9
DATA
INPUTS
OUTPUT
ENABLE
NONINVERTING
OUTPUTS
1
20
V
CC
13
14
17
18
12
15
16
19
Q0
D0
D1
2
3
4
19
18
17
Q7
D7
D6
Q1
Q2
5
16
15
14
13
12
11
Q6
11
CLOCK
6
Q5
D2
7
D5
D3
8
D4
1
PIN 20 = V
PIN 10 = GND
CC
OUTPUT ENABLE
Q3
9
Q4
GND
10
CLOCK
FUNCTION TABLE
Inputs
Output
Output
Enable Clock
D
Q
L
L
H
L
H
L
L
H
L,H,
X
X
X
No Change
Z
X = don’t care
Z = high impedance
8/96
REV 7
Motorola, Inc. 1996
MC54/74HC374A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
.
DC Supply Current, V
and GND Pins
CC
in out
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
450
level (e.g., either GND or V ).
CC
SSOP or TSSOP Package†
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)
L
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
SSOP or TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
2.0
4.5
6.0
1.90
4.40
5.90
1.90
4.40
5.90
1.90
4.40
5.90
in
IL
20 µA
|I
|
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
2.48
2.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IL out
out
out
MOTOROLA
3–2
MC54/74HC374A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IL
2.0
4.5
6.0
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
V
in
IH
20 µA
|I
|
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
IL out
V
out
out
I
Maximum Input Leakage Current
V
= V or GND
CC
6.0
6.0
± 0.1
± 0.5
± 1.0
± 5.0
± 1.0
± 10
µA
µA
in
in
Output in High–Impedance State
= V or V
I
Maximum Three–State
Leakage Current
OZ
V
in
IL
= V
IH
or GND
V
out
CC
or GND
I
Maximum Quiescent Supply
Current (per Package)
V
= V
6.0
4
40
160
µA
CC
in
CC
= 0 µA
I
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)
2.0
3.0
4.5
6.0
6
5
4
8
20
24
MHz
max
15
30
35
10
24
28
t
t
Maximum Propagation Delay, Input Clock to Q
(Figures 1 and 5)
2.0
3.0
4.5
6.0
125
80
25
155
110
31
190
130
38
ns
ns
ns
ns
PLH
PHL
21
26
32
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PLZ
t
PHZ
26
33
38
t
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PLZ
PHZ
26
33
38
t
t
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
TLH
THL
19
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
34
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
3–3
MOTOROLA
MC54/74HC374A
TIMING REQUIREMENTS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
85 C
– 55 to 25 C
125 C
Max
V
Volts
CC
Symbol
Parameter
Fig.
Unit
Min
Max
Min
Max
Min
t
su
Minimum Setup Time, Data to Clock
3
2.0
3.0
4.5
6.0
50
40
10
9
65
50
13
11
75
60
15
13
ns
t
Minimum Hold Time, Clock to Data
Minimum Pulse Width, Clock
3
1
1
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5 0
5.0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
h
t
w
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
t , t
r
Maximum Input Rise and Fall Times
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
SWITCHING WAVEFORMS
t
t
f
V
r
CC
V
CC
OUTPUT
ENABLE
90%
50%
10%
50%
GND
CLOCK
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
t
W
50%
1/f
max
Q
Q
10%
90%
V
OL
t
t
PHL
PLH
t
t
PHZ
PZH
90%
50%
10%
V
Q
OH
50%
HIGH
IMPEDANCE
t
t
THL
TLH
Figure 1.
Figure 2.
VALID
V
CC
50%
DATA
GND
t
t
h
su
V
CC
CLOCK
50%
GND
Figure 3.
MOTOROLA
3–4
MC54/74HC374A
TEST CIRCUITS
TEST POINT
TEST POINT
1 k
OUTPUT
CONNECT TO V
WHEN
.
PZL
CC
AND t
Ω
OUTPUT
TESTING t
PLZ
CONNECT TO GND WHEN
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
TESTING t
AND t
.
PZH
PHZ
C *
C *
L
L
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 4.
Figure 5.
EXPANDED LOGIC DIAGRAM
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
C
C
C
C
C
C
C
C
11
1
Clock
Output
Enable
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
3–5
MOTOROLA
MC54/74HC374A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
20
1
11
10
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
C
MILLIMETERS
INCHES
A
DIM
A
B
C
D
F
MIN
23.88
6.60
3.81
0.38
1.40
MAX
25.15
7.49
5.08
0.56
1.65
MIN
MAX
0.990
0.295
0.200
0.022
0.065
0.940
0.260
0.150
0.015
0.055
L
F
G
H
J
K
L
2.54 BSC
0.100 BSC
0.51
0.20
3.18
1.27
0.30
4.06
0.020
0.008
0.125
0.050
0.012
0.160
N
J
7.62 BSC
0.300 BSC
H
K
M
G
M
N
0
15
0
15
D
0.25
1.02
0.010
0.040
SEATING
PLANE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
MOTOROLA
3–6
MC54/74HC374A
OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE B
Y14.5M, 1982.
20X K REF
0.12 (0.005)
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
0.25 (0.010)
M
S
S
T
U
V
N
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR INTRUSION SHALL NOT
REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.
M
20
11
10
L/2
N
B
F
L
DETAIL E
K
PIN 1
IDENT
1
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
–U–
A
–V–
J
J1
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
J1
K
MIN
7.07
5.20
1.73
0.05
0.63
MAX
7.33
5.38
1.99
0.21
0.95
MIN
MAX
0.288
0.212
0.078
0.008
0.037
K1
M
S
0.20 (0.008)
T U
0.278
0.205
0.068
0.002
0.024
SECTION N–N
–W–
0.65 BSC
0.026 BSC
C
0.59
0.09
0.09
0.25
0.25
7.65
0
0.75
0.20
0.16
0.38
0.33
7.90
8
0.023
0.003
0.003
0.010
0.010
0.301
0
0.030
0.008
0.006
0.015
0.013
0.311
8
0.076 (0.003)
SEATING
PLANE
–T–
D
G
DETAIL E
K1
L
M
H
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
T
U
V
S
0.15 (0.006)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
0.15 (0.006)
T U
M
A
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
6.40
4.30
–––
0.05
0.50
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
–V–
0.252
0.169
–––
0.002
0.020
N
F
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
3–7
MOTOROLA
MC54/74HC374A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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MC74HC374A/D
◊
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