MC74HC377ADWG [ROCHESTER]
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, LEAD FREE, SOIC-20;
| 型号： | MC74HC377ADWG |
| 厂家： | 
Rochester Electronics |
| 描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, LEAD FREE, SOIC-20 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC377A
Octal D Flip-Flop with
Common Clock and Enable
High−Performance Silicon−Gate CMOS
The MC74HC377A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of eight D flip−flops with common Clock and
Enable (E) inputs. Each flip−flop is loaded with a low−to−high
transition of the Clock input. Enable (E) is active low.
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MARKING
DIAGRAMS
20
Features
SOIC−20
DW SUFFIX
CASE 751D
20
HC377A
AWLYYWWG
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
1
1
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 264 FETs or 66 Equivalent Gates
• These are Pb−Free Devices
20
HC
377A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G
G
= Pb−Free Package
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
E
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
GND 10
11 CLOCK
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
February, 2010 − Rev. 1
MC74HC377A/D
MC74HC377A
2
5
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FUNCTION TABLE
D0
D1
D2
D3
D4
D5
D6
D7
4
Inputs
Outputs
7
6
Operating
Modes
Clock
E
l
Dn
Qn
H
8
9
DATA
NONINVERTING
OUTPUTS
13
14
17
18
INPUTS
12
15
16
19
Load “1”
↑
↑
h
l
Load “0”
l
L
Hold (Do Nothing)
↑
X
h
H
X
X
No Change
No Change
11
CLOCK
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the LOW−to−
HIGH CP transition
L = LOW voltage level
PIN 20 = V
CC
PIN 10 = GND
1
E
l = LOW voltage level one setup time prior to the LOW−to−HIGH
CP transition
Figure 1. Logic Diagram
↑ = LOW−to−HIGH CP transition
X = Don’t Care
Design Criteria
Internal Gate Count*
Value
66
Units
ea
Internal Gate Propagation Delay
Internal Gate Power Dissipation
1.5
ns
5.0
mW
pJ
Speed Power Product
.0075
*Equivalent to a two−input NAND gate.
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC377ADWG
SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HC377ADWR2G
SOIC−20 WIDE
(Pb−Free)
1000 Tape & Reel
MC74HC377ADTG
TSSOP−20*
TSSOP−20*
75 Units / Rail
MC74HC377ADTR2G
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HC377A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
–0.5 to + 7.0
CC
V
–0.5 to V + 0.5
V
in
CC
V
out
–0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
†
†
P
D
Power Dissipation in Still Air
SOIC Package
TSSOP Package
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
–65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating
−
SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
–55
+125
°C
ns
t , t
Input Rise and Fall Time
(Figure 2)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
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3
MC74HC377A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
–55 to
V
V
CC
25°C
v 85°C
1.5
2.1
v 125°C
Symbol
Parameter
Test Conditions
= V – 0.1 V
Unit
V
IH
Minimum High−Level Input Voltage
V
out
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
3.15
4.2
V
CC
|I | ≤ 20 mA
out
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input Voltage
V
= 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
|I | ≤ 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
|I | ≤ 20 mA
out
V
in
= V
|I | ≤ 4.0 mA
|I | ≤ 5.2 mA
out
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
IH
out
V
OL
Maximum Low−Level Output
Voltage
V
= V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IL
|I | ≤ 20 mA
out
V
= V
|I | ≤ 4.0 mA
|I | ≤ 5.2 mA
out
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
in
in
IL
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
0.1
4.0
1.0
40
1.0
mA
mA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
160
CC
in
CC
I
= 0 mA
out
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4
MC74HC377A
AC Electrical Characteristics (C = 50 pF, Input t , t = 6.0 ns)
L
r f
Guaranteed Limits
−555C to
255
160
32
27
75
15
13
80
16
4
≤ 855C
200
40
34
95
19
16
100
20
17
75
15
13
75
15
13
3
≤ 1255C
240
48
41
110
22
19
120
24
20
90
18
15
90
18
15
3
Symbol
, t
Parameter
Test Conditions
V
CC
(V)
Unit
t
Maximum Propagation Delay Figures 2, 4
Clock to Qn
2.0
ns
PHL PLH
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
−
t
, t
Maximum Output Transition
Time
Figures 2, 4
Figure 2
ns
ns
ns
ns
ns
ns
ns
THL TLH
t
Minimum Clock Pulse Width
High or Low
W
su
su
t
t
Minimum Set−up Time
D to Clock
Figure 3
60
12
10
60
12
10
3
n
Minimum Set−up Time
Enable to Clock
Figure 3
t
t
Minimum Hold Time
D to Clock
Figure 3
h
n
3
3
3
3
3
3
Minimum Hold Time
Enable to Clock
Figure 3
4
4
4
h
4
4
4
4
4
4
f
Maximum Clock Pulse
Frequency (50% duty cycle)
Figures 2, 4
6
5
4
max
30
35
10
24
28
10
20
24
10
C
in
Maximum Input Capacitance
pF
pF
Typical @ 255C, V = 5.0 V
C
PD
CC
(Note 1)
Power Dissipation Capacitance
35
1. C is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from:
PD
I
(operating) [ C x V x f x N
CC
where N
= total number of outputs switching and f = switching frequency.
PD
CC
IN
SW
SW
IN
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5
MC74HC377A
SWITCHING WAVEFORMS
E
t
r
t
f
50%
50%
V
CC
90%
50%
10%
CLOCK
t
su
t
t
h
GND
V
t
CC
w
DATA
50%
1/f
max
GND
t
su
h
t
t
PHL
PLH
V
CC
90%
50%
10%
Q
CLOCK
50%
GND
t
t
TLH
THL
Figure 3.
Figure 2.
C
C
C
C
C
C
C
C
2
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
3
0
1
2
3
4
5
6
7
D0
D1
D2
D3
D4
D5
D6
D
D
D
D
D
D
D
D
5
4
6
7
TEST POINT
9
OUTPUT
8
NONINVERTING
OUTPUTS
DEVICE
UNDER
TEST
DATA
INPUTS
C *
L
12
15
16
19
13
14
17
*Includes all probe and jig capacitance
Figure 4. Test Circuit
18
11
1
D7
CLOCK
E
Figure 5. Expanded Logic Diagram
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6
MC74HC377A
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
0.25
T A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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7
MC74HC377A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
20X K REF
NOTES:
1.DIMENSIONING AND TOLERANCING PER
M
S
S
V
0.10 (0.004)
T
U
S
T U
0.15 (0.006)
ANSI Y14.5M, 1982.
K
K1
2.CONTROLLING DIMENSION: MILLIMETER.
3.DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL
NOT EXCEED 0.15 (0.006) PER SIDE.
4.DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5.DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
S
0.15 (0.006)
T U
6.TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7.DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
A
−V−
N
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
−W−
F
C
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
J
G
D
J1
K
H
DETAIL E
0.100 (0.004)
−T− SEATING
K1
L
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MC74HC377A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74HC377A/D
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