MMBTA13LT1 [MOTOROLA]
Darlington Amplifier Transistors; 达林顿晶体管放大器
| 型号： | MMBTA13LT1 |
| 厂家： | 
MOTOROLA |
| 描述： | Darlington Amplifier Transistors |
| 文件： | 总8页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MMBTA13LT1/D
SEMICONDUCTOR TECHNICAL DATA
NPN Silicon
COLLECTOR 3
*Motorola Preferred Device
BASE
1
3
EMITTER 2
1
MAXIMUM RATINGS
2
Rating
Collector–Emitter Voltage
Collector–Base Voltage
Symbol
Value
30
Unit
Vdc
V
CES
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
V
V
30
Vdc
CBO
Emitter–Base Voltage
10
Vdc
EBO
Collector Current — Continuous
THERMAL CHARACTERISTICS
Characteristic
I
300
mAdc
C
Symbol
Max
Unit
(1)
Total Device Dissipation FR–5 Board
P
225
mW
D
T
= 25°C
A
Derate above 25°C
1.8
556
300
mW/°C
°C/W
mW
Thermal Resistance Junction to Ambient
Total Device Dissipation
R
JA
D
P
(2)
Alumina Substrate,
T
A
= 25°C
Derate above 25°C
2.4
417
mW/°C
°C/W
°C
Thermal Resistance Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
R
JA
T , T
J stg
–55 to +150
MMBTA13LT1 = 1M; MMBTA14LT1 = 1N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Max
Unit
Collector–Emitter Breakdown Voltage
V
30
—
—
—
Vdc
nAdc
nAdc
(BR)CES
(I = 100 Adc, V
C BE
= 0)
Collector Cutoff Current
(V = 30 Vdc, I = 0)
I
100
100
CBO
CB
Emitter Cutoff Current
(V = 10 Vdc, I = 0)
E
I
EBO
EB
1. FR–5 = 1.0
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
C
0.75 0.062 in.
Thermal Clad is a trademark of the Bergquist Company
Preferred devices are Motorola recommended choices for future use and best overall value.
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)
A
Characteristic
Symbol
Min
Max
Unit
(3)
ON CHARACTERISTICS
DC Current Gain
(I = 10 mAdc, V
C CE
h
FE
—
= 5.0 Vdc)
MMBTA13
MMBTA14
5000
10,000
—
—
(I = 100 mAdc, V
C CE
= 5.0 Vdc)
MMBTA13
MMBTA14
10,000
20,000
—
—
Collector–Emitter Saturation Voltage
(I = 100 mAdc, I = 0.1 mAdc)
V
—
1.5
Vdc
Vdc
CE(sat)
C
B
Base–Emitter On Voltage
(I = 100 mAdc, V = 5.0 Vdc)
V
BE
—
2.0
C
CE
SMALL–SIGNAL CHARACTERISTICS
(4)
Current–Gain — Bandwidth Product
f
T
125
—
MHz
(I = 10 mAdc, V = 5.0 Vdc, f = 100 MHz)
C
CE
3. Pulse Test: Pulse Width
4. f = |h | • f
300 s, Duty Cycle
2.0%.
.
T
fe test
R
S
i
n
e
n
IDEAL
TRANSISTOR
Figure 1. Transistor Noise Model
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
NOISE CHARACTERISTICS
(V
= 5.0 Vdc, T = 25°C)
CE
A
500
2.0
BANDWIDTH = 1.0 Hz
BANDWIDTH = 1.0 Hz
R
≈ 0
S
1.0
0.7
0.5
200
100
50
I
= 1.0 mA
C
0.3
0.2
10 µA
100 µA
100
10
µA
0.1
20
0.07
0.05
µ
A
I
= 1.0 mA
C
10
0.03
0.02
5.0
10 20
50 100 200 500 1 k 2 k
f, FREQUENCY (Hz)
5 k 10 k 20 k 50 k 100 k
10 20
50 100 200 500 1 k 2 k
5 k 10 k 20 k 50 k 100 k
f, FREQUENCY (Hz)
Figure 2. Noise Voltage
Figure 3. Noise Current
200
14
12
BANDWIDTH = 10 Hz TO 15.7 kHz
BANDWIDTH = 10 Hz TO 15.7 kHz
100
70
10
8.0
6.0
4.0
2.0
I
= 10
µA
10 µA
C
50
100 µA
100
µ
A
30
20
I
= 1.0 mA
C
1.0 mA
10
0
1.0
2.0
5.0
10
20
50
100 200
500
100
0
1.0
2.0
5.0
10
20
50 100
200
500 100
0
R
, SOURCE RESISTANCE (k
Ω)
R
, SOURCE RESISTANCE (kΩ)
S
S
Figure 4. Total Wideband Noise Voltage
Figure 5. Wideband Noise Figure
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3
SMALL–SIGNAL CHARACTERISTICS
20
10
4.0
V
= 5.0 V
CE
f = 100 MHz
T
= 25°C
J
T
= 25°C
J
2.0
7.0
5.0
C
ibo
1.0
0.8
C
obo
0.6
0.4
3.0
2.0
0.04
0.2
0.5
0.1
0.2
0.4
1.0 2.0
4.0
10
20
40
1.0
2.0
0.5
I , COLLECTOR CURRENT (mA)
C
10
20
50
100 200
500
V
, REVERSE VOLTAGE (VOLTS)
R
Figure 6. Capacitance
Figure 7. High Frequency Current Gain
200 k
3.0
2.5
2.0
1.5
T
= 125°C
J
T
= 25°C
J
100 k
70 k
50 k
I
=
50 mA
250 mA
500 mA
10 mA
C
25°C
30 k
20 k
10 k
7.0 k
5.0 k
–55°C
1.0
0.5
V
= 5.0 V
CE
3.0 k
2.0 k
500
0.1 0.2 0.5 1.0 2.0
5.0 10 20
50 100 200 500 1000
I , BASE CURRENT (µA)
B
5.0 7.0 10
20
30
50 70 100
200 300
I
, COLLECTOR CURRENT (mA)
C
Figure 8. DC Current Gain
Figure 9. Collector Saturation Region
1.6
1.4
–1.0
–2.0
–3.0
*APPLIES FOR I /I
C B
≤
h
/3.0
FE
25°C TO 125°C
T
= 25°C
J
*R
FOR V
CE(sat)
VC
V
@ I /I = 1000
C B
–55°C TO 25°C
BE(sat)
1.2
1.0
0.8
0.6
V
@ V = 5.0 V
CE
BE(on)
25°C TO 125°C
–4.0
–5.0
–6.0
FOR V
BE
VB
–55°C TO 25°C
V
@ I /I = 1000
C B
CE(sat)
5.0 7.0
10
20
30
50 70 100 200 300
500
5.0 7.0 10
20 30
I , COLLECTOR CURRENT (mA)
C
50 70 100
200 300
500
I
, COLLECTOR CURRENT (mA)
C
Figure 10. “On” Voltages
Figure 11. Temperature Coefficients
4
Motorola Small–Signal Transistors, FETs and Diodes Device Data
1.0
0.7
0.5
D = 0.5
0.2
0.3
0.2
SINGLE PULSE
0.05
0.1
0.1
0.07
SINGLE PULSE
0.05
0.03
0.02
Z
Z
= r(t)
= r(t)
•
•
R
R
T
T
– T = P
Z
(pk) θJC(t)
θ
θ
JC(t)
JA(t)
θ
JC
J(pk)
J(pk)
C
– T = P
Z
θ
JA
A
(pk)
θJA(t)
0.01
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
100
200
500
1.0 k
2.0 k
5.0 k
10 k
t, TIME (ms)
Figure 12. Thermal Response
1.0 k
700
FIGURE A
1.0 ms
100
500
t
P
T
= 25°C
300
200
C
µs
T
= 25°C
A
P
P
P
P
1.0 s
100
70
50
t
1
30
20
CURRENT LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
1/f
DUTY CYCLE
t
1
t
f
10
0.4 0.6
1
t
P
40
1.0
2.0
4.0
6.0
10
20
PEAK PULSE POWER = P
P
V
, COLLECTOR–EMITTER VOLTAGE (VOLTS)
CE
Figure 13. Active Region Safe Operating Area
Design Note: Use of Transient Thermal Resistance Data
Motorola Small–Signal Transistors, FETs and Diodes Device Data
5
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
SOLDERING PRECAUTIONS
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
by T
, the maximum rated junction temperature of the
, the thermal resistance from the device junction to
J(max)
die, R
θJA
ambient, and the operating temperature, T . Using the
A
values provided on the data sheet for the SOT–23 package,
P
can be calculated as follows:
D
•
•
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
T
– T
A
J(max)
P
=
D
R
θJA
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T of 25°C, one can
A
calculate the power dissipation of the device which in this
case is 225 milliwatts.
•
•
•
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
150°C – 25°C
556°C/W
P
=
= 225 milliwatts
D
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad . Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
•
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
6
Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE DIMENSIONS
NOTES:
A
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
3
S
B
1
2
INCHES
MIN MAX
MILLIMETERS
DIM
A
B
C
D
G
H
J
MIN
2.80
1.20
0.89
0.37
1.78
0.013
0.085
0.45
0.89
2.10
0.45
MAX
3.04
1.40
1.11
0.50
2.04
0.100
0.177
0.60
1.02
2.50
0.60
V
G
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0180 0.0236
0.0350 0.0401
0.0830 0.0984
0.0177 0.0236
C
K
L
S
H
J
D
V
K
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
CASE 318–08
ISSUE AE
SOT–23 (TO–236AB)
Motorola Small–Signal Transistors, FETs and Diodes Device Data
7
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MMBTA13LT1/D
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