MPC93R52FAR2 [MOTOROLA]
PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32;
| 型号： | MPC93R52FAR2 |
| 厂家： | 
MOTOROLA |
| 描述： | PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总16页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order Number: MPC93R52/D
Rev 2, 04/2003
SEMICONDUCTOR TECHNICAL DATA
The MPC93R52 is a 3.3V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output
frequencies up to 240 MHz and output skews lower than 200 ps the
device meets the needs of most demanding clock applications.
LOW VOLTAGE
3.3V LVCMOS 1:11
CLOCK GENERATOR
Features
• Configurable 11 outputs LVCMOS PLL clock generator
• Fully integrated PLL
• Wide range of output clock frequency of 16.67 MHz to 240 MHz
• Multiplication of the input reference clock frequency by 3, 2, 1, 3 2,
2
3, 1 3 and 1
2
• 3.3V LVCMOS compatible
• Maximum output skew of 200 ps
• Supports zero–delay applications
• Designed for high–performance telecom, networking and computing
applications
• 32 lead LQFP package
• Ambient Temperature Range – 0°C to +70°C
• Pin and function compatible to the MPC952
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
Functional Description
The MPC93R52 is a fully 3.3V compatible PLL clock generator and
clock driver. The device has the capability to generate output clock
signals of 16.67 to 240 MHz from external clock sources. The internal PLL
optimized for its frequency range and does not require external look filter
components. One output of the MPC93R52 has to be connected to the
PLL feedback input FB_IN to close the external PLL feedback path. The
output divider of this output setting determines the PLL frequency
multiplication factor. This multiplication factor, F_RANGE and the
reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be
configured individually for all three output banks by the FSELx pins
supporting systems with different but phase-aligned clock frequencies.
The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50Ω transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC93R52 is package in a 32 ld LQFP.
Motorola, Inc. 2003
MPC93R52
Bank A
CCLK
VCO
QA0
1
0
1
0
÷2
÷6
÷4
÷2
1
0
QA1
QA2
CCLK
FB_IN
Ref
FB
PLL
QA3
QA4
200 – 480 MHz
PLL_EN
Bank B
QB0
1
0
F_RANGE
QB1
QB2
QB3
FSELA
FSELB
Bank C
1
0
QC0
QC1
FSELC
MR/OE
POWER–ON RESET
(all input resistors have a value of 25k
)
Figure 1. MPC93R52 Logic Diagram
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
VCC
VCC
QB2
QB3
GND
GND
QC0
QC1
VCC
15
14
13
12
11
10
9
QA2
QA1
GND
QA0
MPC93R52
VCC
VCCA
PLL_EN
1
2
3
4
5
6
7
8
It is recommended to use an external RC filter for the analog power supply pin VCCA. Please see application section for details.
Figure 2. MPC93R52 32–Lead Package Pinout (Top View)
MOTOROLA
2
TIMING SOLUTIONS
MPC93R52
Table 1: PIN CONFIGURATION
Pin
I/O
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Function
CCLK
FB_IN
Input
Input
Input
Input
Input
Input
PLL reference clock signal
PLL feedback signal input, connect to an output
PLL frequency range select
F_RANGE
FSELA
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
FSELB
FSELC
PLL_EN
MR/OE
Input
Input
LVCMOS
PLL enable/disable
LVCMOS
LVCMOS
Ground
VCC
Output enable/disable (high–impedance tristate) and device reset
Clock outputs
QA0–4, QB0–3, QC0–1 Output
GND
Supply
Supply
Negative power supply
VCCA
PLL positive power supply (analog power supply). It is recommended to use an
external RC filter for the analog power supply pin V
applications section for details.
. Please see
CCA
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2: FUNCTION TABLE
Control
Default
0
1
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 1 and Table 2 for supported frequency ranges and output to input frequency ratios.
F_RANGE
FSELA
0
0
0
0
VCO ÷ 1 (High input frequency range)
Output divider ÷ 4
VCO ÷ 2 (Low input frequency range)
Output divider ÷ 6
FSELB
Output divider ÷ 4
Output divider ÷ 2
FSELC
Output divider ÷ 2
Output divider ÷ 4
MR/OE
0
Outputs enabled (active)
Outputs disabled (high–impedance state) and
reset of the device. During reset, the PLL
feedback loop is open and the VCO is operating
at its lowest frequency. The MPC93R52 requires
reset after any loss of PLL lock. Loss of PLL
lock may occur when the external feedback path
is interrupted. The length of the reset pulse
should be greater than two reference clock
cycles (CCLK). The device is reset by the
internal power–on reset (POR) circuitry during
power–up.
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is
substituted for the internal VCO output.
MPC93R52 is fully static and no minimum
frequency limit applies. All PLL related AC
characteristics are not applicable.
TIMING SOLUTIONS
3
MOTOROLA
MPC93R52
Table 3: GENERAL SPECIFICATIONS
Symbol
Characteristics
Output Termination Voltage
Min
Typ
Max
Unit
V
Condition
V
TT
V
2
CC
MM
HBM
LU
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch–Up Immunity
200
2000
200
V
V
mA
pF
pF
C
Power Dissipation Capacitance
Input Capacitance
10
Per output
Inputs
PD
C
4.0
IN
a
Table 4: ABSOLUTE MAXIMUM RATINGS
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
3.9
Unit
V
Condition
V
CC
Supply Voltage
V
IN
DC Input Voltage
V
V
+0.3
V
CC
V
OUT
DC Output Voltage
DC Input Current
+0.3
V
CC
I
IN
±20
mA
mA
°C
I
DC Output Current
Storage Temperature
±50
OUT
T
S
-65
125
a. Absolutemaximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 5: DC CHARACTERISTICS (V
CC
= 3.3V ± 5%, T = 0° to 70°C)
A
Symbol
Characteristics
Input high voltage
Min
Typ
Max
V + 0.3
CC
Unit
V
Condition
LVCMOS
LVCMOS
V
IH
2.0
V
IL
Input low voltage
0.8
V
a
=-24 mA
OH
V
Output High Voltage
Output Low Voltage
2.4
V
I
OH
V
0.55
0.30
V
V
I = 24 mA
OL
I = 12 mA
OL
OL
Z
OUT
Output impedance
14 - 17
b
I
Input Current
±200
5.0
µA
mA
mA
V
=V
IN CC
or V =GND
IN
IN
I
Maximum PLL Supply Current
3.0
7.0
V Pin
CCA
CCA
I
c
Maximum Quiescent Supply Current
10
All V
Pins
CC
CCQ
a
The MPC93R52 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.
TT
b
c
Inputs have pull-down resistors affecting the input current.
I
is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
CCQ
MOTOROLA
4
TIMING SOLUTIONS
MPC93R52
a
= 3.3V ± 5%, T = 0° to 70°C)
A
Table 6: AC CHARACTERISTICS (V
CC
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
bc
f
Input reference frequency in PLL mode
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
50.0
33.3
25.0
120.0
80.0
60.0
40.0
MHz
MHz
MHz
MHz
ref
16.67
d
Input reference frequency in PLL bypass mode
50.0
200
250.0
480
MHz
MHz
e
f
f
VCO lock frequency range
VCO
f
Output Frequency
÷2 output
100
50
33.3
25
240
120
80
60
40
MHz
MHz
MHz
MHz
MHz
MAX
÷4 output
÷6 output
÷8 output
÷12 output
16.67
t
Minimum Reference Input Pulse Width
2.0
ns
ns
PWMIN
tr, tf
g
CCLK Input Rise/Fall Time
1.0
0.8 to 2.0V
PLL locked
t
(
Propagation Delay CCLK to FB_IN
(static phase offset)
(f = 50MHz)
ref
-100
+200
ps
ps
)
h
t
Output-to-output Skew
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
150
100
100
50
ps
ps
ps
ps
sk(O)
DC
Output duty cycle
47
50
53
1.0
8
%
ns
ns
ns
t , t
r f
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
0.1
0.55 to 2.4V
t
PLZ, HZ
t
10
PZL, LZ
t
output frequencies mixed
all outputs same frequency
450
100
ps
ps
JIT(CC)
t
Period Jitter
output frequencies mixed
all outputs same frequency
450
100
ps
ps
JIT(PER)
i
t
I/O Phase Jitter
÷4 feedback divider RMS (1 σ)
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
40
50
60
80
ps
ps
ps
ps
JIT(
)
÷12 feedback divider RMS (1 σ)
j
BW
PLL closed loop bandwidth
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
2.0–8.0
1.0–4.0
0.8–2.5
0.6–1.5
MHz
MHz
MHz
MHz
t
Maximum PLL Lock Time
10
ms
LOCK
a
b
c
d
e
f
AC characteristics apply for parallel output termination of 50Ω to V
PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation.
The PLL may be unstable with a divide by 2 feedback ratio.
.
TT
In PLL bypass mode, the MPC93R52 divides the input reference clock.
The input frequency f on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f = f
÷ FB.
ref
ref VCO
See Table 9 and Table 10 for output divider configurations.
g
The MPC93R52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t , can only be guaranteed if
tr/tf are within the specified range.
( )
h
i
j
See application section for part-to-part skew calculation.
See application section for a jitter calculation for other confidence factors than 1
-3 dB point of PLL transfer characteristics.
.
TIMING SOLUTIONS
5
MOTOROLA
MPC93R52
APPLICATIONS INFORMATION
Programming the MPC93R52
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2
as well as 2:3, 3:1 and 2:1. Table 1 illustrates the various
output configurations and frequency ratios supported by the
MPC93R52. See also Table 9, Table 10 and Figure 3 to
Figure 6 for further reference. A ÷2 output divider cannot be
used for feedback.
The MPC93R52 supports output clock frequencies from
16.67 to 240 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 480 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
Table 9: MPC93R52 Example Configuration (F_RANGE = 0)
a
PLL Feedback
fref [MHz] FSELA FSELB FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
(50-120 MHz) fref 2 (100-240 MHz)
(50-120 MHz) fref (50-120 MHz)
(50-120 MHz) fref 2 (100-240 MHz)
(50-120 MHz) fref (50-120 MHz)
QC[0:1]:fref ratio
b
VCO ÷ 4
50-120
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
fref
fref
(50-120 MHz) fref
(50-120 MHz) fref
fref 2÷3 (33-80 MHz) fref
fref 2÷3 (33-80 MHz) fref
c
VCO ÷ 6
33.3-80
fref
fref
fref
fref
(33-80 MHz) fref 3÷2 (50-120 MHz) fref 3 (100-240 MHz)
(33-80 MHz) fref 3÷2 (50-120 MHz) fref 3÷2 (50-120 MHz)
(33-80 MHz) fref 3 (100-240 MHz) fref 3 (100-240 MHz)
(33-80 MHz) fref 3 (100-240 MHz) fref 3÷2 (50-120 MHz)
a. fref is the input clock reference frequency (CCLK)
b. QAx connected to FB_IN and FSELA=0
c. QAx connected to FB_IN and FSELA=1
Table 10: MPC93R52 Example Configurations (F_RANGE = 1)
a
PLL Feedback
fref [MHz] FSELA FSELB FSELC
QA[0:4]:fref ratio
fref (25-60 MHz) fref
fref (25-60 MHz) fref
QB[0:3]:fref ratio
QC[0:1]:fref ratio
b
VCO ÷ 8
25-60
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
(25-60 MHz) fref
(25-60 MHz) fref
(25-60 MHz) fref
(25-60 MHz) fref
2
2
3
(50-120 MHz)
(25-60 MHz)
(50-120 MHz)
(25-60 MHz)
(50-120 MHz)
fref 2÷3 (16-40 MHz) fref
fref 2÷3 (16-40 MHz) fref
fref
c
VCO ÷ 12
16.67-40
(16-40 MHz) fref 3÷2 (25-60 MHz)
fref
fref
fref
fref
(16-40 MHz) fref 3÷2 (25-60 MHz)
fref 3÷2 (25-60 MHz)
fref (50-120 MHz)
(16-40 MHz) fref
(16-40 MHz) fref
3
3
(50-120 MHz)
(50-120 MHz)
3
fref 3÷2 (25-60 MHz)
a. fref is the input clock reference frequency (CCLK)
b. QAx connected to FB_IN and FSELA=0
c. QAx connected to FB_IN and FSELA=1
MOTOROLA
6
TIMING SOLUTIONS
MPC93R52
Example Configurations for the MPC93R52
Figure 3. MPC93R52 Default Configuration
Figure 4. MPC93R52 Zero Delay Buffer Configuration
QA0
QA0
fref = 100 MHz
fref = 62.5 MHz
CCLK
CCLK
FB_IN
QA1
QA2
QA3
QA4
QA1
QA2
QA3
QA4
100 MHz
62.5 MHz
FB_IN
QB0
QB1
QB2
QB3
QB0
QB1
QB2
QB3
FSELA
FSELB
FSELC
FSELA
FSELB
FSELD
62.5 MHz
62.5 MHz
100 MHz
200 MHz
VCC
F_RANGE
F_RANGE
QC0
QC1
QC0
QC1
MPC93R52
MPC93R52
100 MHz (Feedback)
62.5 MHz (Feedback)
MPC93R52 default configuration (feedback of QB0 = 100
MHz). All control pins are left open.
MPC93R52 zero–delay (feedback of QB0 = 62.5 MHz).
All control pins are left open except FSELC = 1. All out-
puts are locked in frequency and phase to the input clock.
Frequency range
Input
Min
Max
Frequency range
Input
Min
Max
50 MHz
50 MHz
50 MHz
100 MHz
120 MHz
120 MHz
120 MHz
240 MHz
50 MHz
50 MHz
50 MHz
50 MHz
120 MHz
120 MHz
120 MHz
120 MHz
QA outputs
QB outputs
QC outputs
QA outputs
QB outputs
QC outputs
Figure 5. MPC93R52 Default Configuration
Figure 6. MPC93R52 Zero Delay Buffer Config. 2
QA0
QA0
fref = 33.3 MHz
fref = 33.3 MHz
CCLK
CCLK
QA1
QA2
QA3
QA4
QA1
QA2
QA3
QA4
33.3 MHz
33.3 MHz
FB_IN
FB_IN
QB0
QB1
QB2
QB3
QB0
QB1
QB2
QB3
VCC
VCC
FSELA
FSELB
FSELC
FSELA
FSELB
FSELC
33.3 MHz
33.3 MHz
50 MHz
VCC
VCC
F_RANGE
F_RANGE
VCC
QC0
QC1
QC0
QC1
100 MHz
MPC93R52
MPC93R52
33.3 MHz (Feedback)
33.3 MHz (Feedback)
MPC93R52 configuration to multiply the reference frequen-
cy by 3, 3÷2 and 1. PLL feedback of QA4 = 33.3 MHz.
MPC93R52 zero–delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a
lower input and output clock frequency.
Frequency range
Input
Min
Max
Frequency range
Input
Min
Max
25 MHz
50 MHz
50 MHz
100 MHz
60 MHz
120 MHz
120 MHz
240 MHz
25 MHz
25 MHz
25 MHz
25 MHz
60 MHz
60 MHz
60 MHz
60 MHz
QA outputs
QB outputs
QC outputs
QA outputs
QB outputs
QC outputs
TIMING SOLUTIONS
7
MOTOROLA
MPC93R52
Power Supply Filtering
Using the MPC93R52 in zero–delay applications
The MPC93R52 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Nested clock trees are typical applications for the
MPC93R52. Designs using the MPC93R52 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC93R52 clock driver allows for its use as a zero delay
buffer. One example configuration is to use a ÷4 output as a
feedback to the PLL and configuring all other outputs to a
divide-by-4 mode. The propagation delay through the device
is virtually eliminated. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a
near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This
effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Random noise on the V
device characteristics, for instance I/O jitter. The MPC93R52
(PLL) power supply impacts the
CCA
provides separate power supplies for the output buffers (V
)
CC
) of the device. The purpose
and the phase-locked loop (V
CCA
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it is
more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the V
CCA
pin for the MPC93R52. Figure 7. illustrates a typical power
supply filter scheme. The MPC93R52 frequency and phase
stability is most susceptible to noise with spectral content in
the 100kHz to 20MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
Calculation of part-to-part skew
across the series filter resistor R . From the data sheet the
F
I
current (the current sourced through the V
pin) is
CCA
typically 3 mA (5 mA maximum), assuming that a minimum of
2.98V must be maintained on the V pin. The resistor R
PowerSupplyFilter”shouldhavea
CCA
resistance of 5–25 to meet the voltage drop criteria.
CCA
The MPC93R52 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC93R52 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
CCA
F
shown in Figure 7. “V
R = 5–25Ω
F
C = 22 µF
F
t
= t
+ t
+ t
+ t
CF
This maximum timing uncertainty consist of 4
SK(PP)
( )
SK(O)
PD, LINE(FB)
JIT( )
R
F
VCCA
VCC
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
C
F
10 nF
MPC93R52
VCC
33...100 nF
CCLK
Common
t
PD,LINE(FB)
–t
(
)
Figure 7. V
CCA
Power Supply Filter
QFB
Device 1
t
JIT(
)
The minimum values for R and the filter capacitor C are
F
F
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
Any Q
Device 1
+t
SK(O)
filter shown in Figure 7. “V
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
Power Supply Filter”, the filter
CCA
+t
(
)
QFB
Device2
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R52 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
t
JIT(
)
Any Q
Device 2
+t
SK(O)
Max. skew
t
SK(PP)
Figure 8. MPC93R52 max. device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1 ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 11.
MOTOROLA
8
TIMING SOLUTIONS
MPC93R52
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC93R52 clock driver. For the series
terminated case however there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 10. “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme the fanout of the MPC93R52 clock driver is
effectively doubled due to its capability to drive multiple lines.
Table 11: Confidence Facter CF
CF
± 1
± 2
± 3
± 4
± 5
± 6
Probability of clock edge within the distribution
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3 ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of -445 ps to 395 ps relative to CCLK:
MPC93R52
OUTPUT
BUFFER
Z
= 50Ω
O
R = 36Ω
S
14Ω
IN
IN
OutA
t
=
=
[–200ps...150ps] + [–200ps...200ps] +
[(15ps –3)...(15ps 3)] + t
SK(PP)
MPC93R52
OUTPUT
BUFFER
PD, LINE(FB)
[–445ps...395ps] + t
PD, LINE(FB)
Z
O
= 50Ω
= 50Ω
R = 36Ω
S
t
SK(PP)
OutB0
OutB1
Due to the frequency dependence of the I/O jitter,
Figure 9. “Max. I/O Jitter versus frequency” can be used for a
more precise timing performance analysis.
14Ω
Z
O
R = 36Ω
S
Figure 10. Single versus Dual Transmission Lines
The waveform plots in Figure 11. “Single versus Dual
Line Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both cases
the drive capability of the MPC93R52 output buffer is more
than sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC93R52. The output waveform in Figure 11.
“Single versus Dual Line Termination Waveforms” shows a
step in the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
Figure 9. Max. I/O Jitter versus frequency
Driving Transmission Lines
The MPC93R52 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
V
Z
R
R
V
= V ( Z ÷ (R +R +Z ))
S 0 S 0 0
L
0
S
0
L
= 50Ω || 50Ω
= 36Ω || 36Ω
= 14Ω
= 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
50Ω resistance to V ÷2.
CC
TIMING SOLUTIONS
9
MOTOROLA
MPC93R52
3.0
match the impedances when driving multiple lines the
situation in Figure 12. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
OutA
= 3.8956
OutB
= 3.9386
t
D
2.5
2.0
1.5
1.0
0.5
0
t
D
In
MPC93R52
OUTPUT
Z
O
= 50Ω
= 50Ω
R = 22Ω
S
BUFFER
14Ω
Z
O
R = 22Ω
S
14Ω + 22Ω 22Ω = 50Ω 50Ω
25Ω = 25Ω
2
4
6
8
10
12
14
TIME (nS)
Figure 12. Optimized Dual Line Termination
Figure 11. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
MPC93R52
DUT
Pulse
Generator
Z = 50
Z
O
= 50Ω
Z = 50Ω
O
R = 50Ω
T
R = 50Ω
T
V
TT
V
TT
Figure 13. CCLK MPC93R52 AC test reference for V = 3.3V and V = 2.5V
cc cc
MOTOROLA
10
TIMING SOLUTIONS
MPC93R52
V
CC
V
2
2
CC
GND
V
CC
CCLK
FB_IN
V
2
2
CC
GND
V
CC
V
CC
GND
V
CC
V
CC
GND
t
SK(O)
The pin–to–pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
t
(
)
Figure 14. Output–to–output Skew t
SK(O)
Figure 15. Propagation delay (t , static phase
( )
offset) test reference
V
CC
CCLK
V
CC
GND
2
t
P
FB_IN
T
0
DC = t /T x 100%
P 0
T
JIT(
= |T –T mean|
0 1
)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The deviation in t for a controlled edge with respect to a t mean in a
random sample of cycles
0
0
Figure 16. Output Duty Cycle (DC)
Figure 17. I/O Jitter
T
= |T –T
N+1
|
T
= |T –1/f |
JIT(CC)
N
JIT(PER) N 0
T
N
T
N+1
T
0
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
Figure 18. Cycle–to–cycle Jitter
Figure 19. Period Jitter
V =3.3V
CC
2.4
0.55
t
F
t
R
Figure 20. Output Transition Time Test Reference
TIMING SOLUTIONS
11
MOTOROLA
MPC93R52
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-03
ISSUE B
4X
0.20
H
A–B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
25
1
F
F
A
B
E1/2
6
E1
E
4
DETAIL G
E/2
DETAIL G
17
8
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
D
4
D/2
4X
D
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
0.20
C A–B D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08–mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07–mm.
H
28X e
32X
0.1 C
SEATING
PLANE
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25–mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1–mm AND
0.25–mm FROM THE LEAD TIP.
C
DETAIL AD
BASE
PLATING
METAL
b1
c
c1
MILLIMETERS
DIM MIN
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
A
A1
A2
b
b1
c
1.40
0.05
1.35
0.30
0.30
0.09
0.09
b
5
8
8X ( 1 )
M
0.20
C A–B D
R R2
SECTION F–F
R R1
c1
D
9.00 BSC
D1
e
E
E1
L
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
0.25
GAUGE PLANE
0.50
0.70
L1
θ
θ1
R1
R2
S
1.00 REF
0
12 REF
(S)
7
A1
L
0.08
0.08
0.20
–––
(L1)
0.20 REF
DETAIL AD
MOTOROLA
12
TIMING SOLUTIONS
MPC93R52
NOTES
TIMING SOLUTIONS
13
MOTOROLA
MPC93R52
NOTES
MOTOROLA
14
TIMING SOLUTIONS
MPC93R52
NOTES
TIMING SOLUTIONS
15
MOTOROLA
MPC93R52
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specificallydisclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical”parameterswhichmaybeprovidedinMotorola
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Motorola Inc. 2003
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81–3–3440–3569
◊
MPC93R52/D
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