MPC948L [MOTOROLA]
LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP; 低电压1:12时钟分配芯片
| 型号： | MPC948L |
| 厂家： | 
MOTOROLA |
| 描述： | LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP |
| 文件： | 总6页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MPC948L is a 1:12 low voltage clock distribution chip. The device
is pin and function compatible with the MPC948 with the added feature of
2.5V output capabilities. The device features the capability to select either
a differential LVPECL or a LVTTL compatible input. The 12 outputs are
2.5V LVCMOS or LVTTL compatible and feature the drive strength to
drive 50Ω series terminated transmission lines. With output–to–output
skews of 350ps, the MPC948L is ideal as a clock distribution chip for the
most demanding of synchronous systems.
LOW VOLTAGE
1:12 CLOCK
DISTRIBUTION CHIP
• Clock Distribution for Intel Microprocessors
• LVPECL or LVCMOS/LVTTL Clock Input
• 350ps Maximum Output–to–Output Skew
• Drives Up to 24 Independent Clock Lines
• Maximum Output Frequency of 150MHz
• Synchronous Output Enable
• Tristatable Outputs
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
• 32–Lead TQFP Packaging
• 2.5V Output Capability
With an output impedance of approximately 7Ω, in both the HIGH and
LOW logic states, the output buffers of the MPC948L are ideal for driving
series terminated transmission lines. More specifically, each of the 12
MPC948L outputs can drive two series terminated 50Ω transmission
lines. With this capability, the MPC948L has an effective fanout of 1:24 in
applications where each line drives a single load.
The differential LVPECL inputs of the MPC948L allow the device to interface directly with a LVPECL fanout buffer like the
MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the TTL_CLK_Sel pin will select the TTL level clock input.
All of the control inputs are LVCMOS/LVTTL compatible. The MPC948L provides a synchronous output enable control to allow
for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control
is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,
the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into
high impedance. Note that all of the MPC948L inputs have internal pullup resistors.
The 32–lead TQFP package was chosen to optimize performance, board space and cost of the device. The 32–lead TQFP
has a 7x7mm body size with a conservative 0.8mm pin spacing.
The MPC948L features two independent power supplies; VCCI and VCCO. The VCCI pin powers the internal core logic and
must be tied to 3.3V. The VCCO pin powers the output buffer and can be tied to either 2.5V or 3.3V.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
4/97
REV 0
Motorola, Inc. 1997
MPC948L
VCCI
VCCO
PECL_CLK
PECL_CLK
0
1
12
Q0–Q11
TTL_CLK
TTL_CLK_Sel
Sync_OE
Tristate
Figure 1. Logic Diagram
24
23
22
21
20
19
18
17
FUNCTION TABLES
Q3
VCCO
Q2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
GND
Q8
TTL_CLK_Sel
Input
0
1
PECL_CLK
TTL_CLK
VCCO
Q9
GND
Q1
Sync_OE
Outputs
MPC948L
GND
Q10
VCCO
Q11
0
1
Disabled
Enabled
VCCO
Q0
Tristate
Outputs
0
1
Tristate
Enabled
GND
1
2
3
4
5
6
7
8
Figure 2. 32–Lead Pinout (Top View)
TTL_CLK
Sync_OE
Q
Figure 3. Sync_OE Timing Diagram
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — Rev 6
MPC948L
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
V
Supply Voltage
Input Voltage
Input Current
4.6
CC
V
+ 0.3
V
I
DD
I
IN
±20
mA
°C
T
Stor
Storage Temperature Range
–40
125
*
Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
DC CHARACTERISTICS (T = 0° to 70°C, V
= 3.3V ±5%; V
= 2.5V ±5% or 3.3V ±5%)
CCO
A
CCI
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
V
V
Input HIGH Voltage
PECL_CLK
2.135
2.0
2.42
3.60
V
Single Ended Spec
IH
Other
Input LOW Voltage
PECL_CLK
Other
1.49
1.825
0.8
V
Single Ended Spec
IL
V
V
V
Peak–to–Peak Input Voltage
Common Mode Range
Output HIGH Voltage
PECL_CLK
PECL_CLK
300
1000
mV
V
PP
V
– 2.0
V
– 0.6
Note 1.
CMR
OH
CC
CC
VCCO = 3.3V
VCCO = 2.5V
2.5
2.0
V
I
I
= –20mA (Note 2.)
= 20mA (Note 2.)
OH
V
OL
Output LOW Voltage
Input Current
0.4
±100
4
V
OL
I
IN
µA
pF
pF
mA
Note 3.
C
C
Input Capacitance
IN
pd
Power Dissipation Capacitance
25
22
Per Output
I
Maximum Quiescent Supply Current
30
CC
1. V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
range and the input swing lies within the V specification.
the V
CMR
PP
2. The MPC948L outputs can drive series or parallel terminated 50Ω (or 50Ω to V /2) transmission lines on the incident edge (see Applications
CC
Info section).
3. Inputs have pull–up resistors which affect input current, PECL_CLK has a pull–down resistor.
AC CHARACTERISTICS (T = 0° to 70°C, V
= 3.3V ±5%; V
= 2.5V ±5% or 3.3V ±5%)
CCO
A
CCI
Symbol
Characteristic
Maximum Input Frequency
Propagation Delay
Min
Typ
Max
Unit
MHz
ns
Condition
Note 4.
F
150
max
t
PECL_CLK to Q
TTL_CLK to Q
7.0
7.9
Note 4.
pd
t
t
Output–to–Output Skew
Part–to–Part Skew
350
ps
ns
Note 4.
sk(o)
PECL_CLK to Q
TTL_CLK to Q
1.5
2.0
Notes 4., 5.
sk(pr)
t
t
t
Output Pulse Width
t
/2–
t
/2+
ps
ns
ns
Notes 4., 6.
Measured at V /2
pwo
CYCLE
800
CYCLE
800
CC
Setup Time
Hold Time
Sync_OE to PECL_CLK
Sync_OE to TTL_CLK
1.0
0.0
Notes 4., 7.
Notes 4., 7.
s
PECL_CLK to Sync_OE
TTL_CLK to Sync_OE
0.0
1.0
h
t
,t
PZL PZH
Output Enable Time
Output Disable Time
Output Rise/Fall Time
3
3
11
11
ns
ns
ns
t ,t
PLZ PHZ
t , t
r f
0.20
1.0
0.8V to 2.0V
4. Driving 50Ω transmission lines
5. Part–to–part skew at a given temperature and voltage
6. Assumes 50% input duty cycle.
7. Setup and Hold times are relative to the falling edge of the input clock
3
MOTOROLA
MPC948L
APPLICATIONS INFORMATION
Driving Transmission Lines
combination of the line impedances. The voltage wave
launched down the two lines will equal:
The MPC948L clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC948L clock driver. For
the series terminated case however there is no DC current
draw, thus the outputs can drive multiple series terminated
lines. Figure 4 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC948L clock
driver is effectively doubled due to its capability to drive
multiple lines.
OutA
= 3.8956
OutB
= 3.9386
t
D
2.5
2.0
1.5
1.0
0.5
0
t
D
In
2
4
6
8
10
12
14
TIME (nS)
MPC948L
OUTPUT
BUFFER
Figure 5. Single versus Dual Waveforms
Z
= 50
Ω
O
R
= 43
Ω
S
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
7
Ω
IN
OutA
MPC948L
OUTPUT
BUFFER
Z
Z
= 50
= 50
Ω
Ω
O
O
R
R
= 43
= 43
Ω
Ω
S
OutB0
OutB1
7Ω
IN
S
MPC948L
OUTPUT
Z
Z
= 50
= 50
Ω
Ω
O
O
R
= 36
= 36
Ω
Ω
S
S
BUFFER
7Ω
Figure 4. Single versus Dual Transmission Lines
R
The waveform plots of Figure 5 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC948L output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC948L. The output
waveform in Figure 5 shows a step in the waveform, this step
is caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 43Ω series resistor
plus the output impedance does not match the parallel
7Ω + 36Ω 36Ω = 50Ω 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — Rev 6
MPC948L
OUTLINE DIMENSIONS
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A
A1
0.20 (0.008) AB T–U
Z
32
25
1
–U–
V
–T–
B
AE
AE
P
B1
DETAIL Y
–Z–
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T–U
Z
9
NOTES:
S1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
–AB–
–AC–
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
8X M
MILLIMETERS
MIN MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
R
J
DIM
A
A1
B
B1
C
D
E
F
G
H
J
SECTION AE–AE
E
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
0.300
1.350
0.300
0.012
0.053
0.012
W
0.800 BSC
0.031 BSC
Q
H
K
X
0.050
0.090
0.500
0.150
0.200
0.700
0.002
0.004
0.020
0.006
0.008
0.028
K
M
N
P
12 REF
12 REF
DETAIL AD
0.090
0.160
0.004
0.006
0.400 BSC
0.016 BSC
Q
R
1
5
1
5
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
V1
W
X
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
5
MOTOROLA
MPC948L
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
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Mfax is a trademark of Motorola, Inc.
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MPC948L/D
◊
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