MPC958FAR2 [MOTOROLA]

MPC900 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32;


型号：	MPC958FAR2
厂家：	MOTOROLA
描述：	MPC900 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32 PC 驱动输出元件逻辑集成电路
文件：	总5页 (文件大小：104K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SEMICONDUCTOR TECHNICAL DATA

Order this document

by MPC958/D

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See Upgrade Product – MPC9658

The MPC958 is a 3.3V compatible, PLL based clock driver device tar-

geted for high performance clock tree designs. With output frequencies of

up to 200MHz and output skews of 200ps the MPC958 is ideal for the

most demanding clock tree designs. The devices employ a fully differen-

tial PLL design to minimize cycle–to–cycle and phase jitter.

• Fully Integrated PLL

LOW VOLTAGE

PLL CLOCK DRIVER

• Output Frequency up to 200MHz

• Outputs Disable in High Impedance

• LQFP Packaging

• 100ps Cycle–to–Cycle Jitter

The MPC958 has a differential LVPECL reference input along with an

external feedback input. These features make the MPC958 ideal for use

as a zero delay, low skew fanout buffer. The device performance has

been tuned and optimized for zero delay performance. The MR/OE input

pin will tristate the output buffers when driven “high”.

The MPC958 is fully 3.3V compatible and requires no external loop

filter components. All control inputs accept LVCMOS or LVTTL compat-

ible levels while the outputs provide LVCMOS levels with the ability to

drive terminated 50Ω transmission lines. For series terminated 50Ω lines,

each of the MPC958 outputs can drive two traces giving the device an

effective fanout of 1:22. The device is packaged in a 7x7mm 32–lead

LQFP package to provide the optimum combination of board density and

performance.

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A

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Figure 1. Logic Diagram

Rev 1

462

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

MPC958

FUNCTION TABLES

BYPASS

Function

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PLL Enabled

PLL Bypass

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MR/OE

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Outputs Disabled

Outputs Enabled

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MPC958

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VCO_SEL

Function

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PLL_EN

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Figure 2. 32–Lead Pinout (Top View)

ABSOLUTE MAXIMUM RATINGS*

Symbol

Parameter

Min

–0.3

Max

Unit

Supply Voltage

Input Voltage

Input Current

4.6

+ 0.3

°C

Stor

Storage Temperature Range

–40

125

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or condi-

tions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not im-

plied.

THERMAL CHARACTERISTICS

Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive capa-

bility products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die

power, the corresponding die temperature and the relationship to longterm reliability is addressed in the Motorola application

note AN1545.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

463

MPC958

DC CHARACTERISTICS (T_A= 0° to 70°C, V_CC= 3.3V 5%)

Symbol

Characteristic

Input HIGH Voltage

Min

Typ

Max

3.6

Unit

Condition

LVCMOS Inputs

PECL_CLK

2.0

Input LOW Voltage

Peak–to–Peak Input Voltage

Common Mode Range

Output HIGH Voltage

Output LOW Voltage

Input Current

0.8

300

1.0

2.4

1000

3.0

CMR

PECL_CLK

Note 1.

= –20mA, Note 2.

= 20mA, Note 2.

0.5

120

µA

Input Capacitance

Power Dissipation Capacitance

Maximum Quiescent Supply Current

Maximum PLL Supply Current

Per Output

All VCC Pins

VCCA Pin Only

CCPLL

1. V

is the center of the differential input signal. Normal operation is obtained when the input crosspoint is within the V

range and the input

CMR

swing lies within the V specification.

2. The MPC958 outputs can drive series or parallel terminated 50Ω (or 50Ω to V /2) transmission lines on the incident edge (see Applications

Info section).

PLL INPUT REFERENCE CHARACTERISTICS (T_A= 0 to 70°C)

Symbol

Characteristic

Reference Input Frequency

Reference Input Duty Cycle

Min

Note 1.

Max

Note 1.

Unit

MHz

Condition

ref

refDC

3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.

AC CHARACTERISTICS (T_A= 0°C to 70°C, V_CC= 3.3V 5%)

Symbol

Characteristic

Output Rise/Fall Time

Min

Typ

Max

Unit

Condition

t , t

0.10

1.0

0.8 to 2.0V

Note 1.

Output Duty Cycle

PLL Mode tcycle/2 –

400

tcycle/2 +

400

Note 1.

Output–to–Output Skews (Relative to QFB)

PLL VCO Lock Range

200

400

Note 1.

sk(O)

VCO

max

200

MHz

Maximum Output Frequency

(Note 1.)

PLL Mode

100

200

VCO_SEL = ‘1’

VCO_SEL = ‘0’

Bypass Mode

(lock)

Input to Ext_FB Delay (with PLL Locked @ 100MHz)

Input to Q Delay

–70

3.0

130

7.0

Note 1.

(bypass)

PLL Bypassed

Output Disable Time

PLZ HZ

PZL

Output Enable Time

Cycle–to–Cycle Jitter (Peak–to–Peak)

Maximum PLL Lock Time

100

Note 1.

jitter

lock

4. Termination of 50W to V /2.

464

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

MPC958

Power Supply Filtering

schemes discussed in this section should be adequate to elim-

inate power supply noise related problems in most designs.

The MPC958 is a mixed analog/digital product and as such

it exhibits some sensitivities that would not necessarily be

seen on a fully digital product. Analog circuitry is naturally sus-

ceptible to random noise, especially if this noise is seen on the

power supply pins. The MPC958 provides a separate power

supply for the phase–locked loop (VCCA) of the device. The

purpose of this design technique is to try and isolate the high

switching noise digital outputs from the relatively sensitive in-

ternal analog phase–locked loop. In a controlled environment

such as an evaluation board this level of isolation is sufficient.

However, in a digital system environment where it is more diffi-

cult to minimize noise on the power supplies a second level of

isolation may be required. The simplest form of isolation is a

power supply filter on the VCCA pin for the MPC958.

Driving Transmission Lines

The MPC958 clock driver was designed to drive high speed

signals in a terminated transmission line environment. To pro-

vide the optimum flexibility to the user the output drivers were

designed to exhibit the lowest impedance possible. With an

output impedance of approximately 20Ω the drivers can drive

either parallel or series terminated transmission lines. For

more information on transmission lines the reader is referred to

application note AN1091 in the Timing Solutions data book

(DL207/D).

In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a point–to–

point scheme either series terminated or parallel terminated

transmission lines can be used. The parallel technique termi-

nates the signal at the end of the line with a 50Ω resistance to

VCC/2. This technique draws a fairly high level of DC current

and thus only a single terminated line can be driven by each

output of the MPC958 clock driver. For the series terminated

case however there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 4 illustrates

an output driving a single series terminated line vs two series

terminated lines in parallel. When taken to its extreme the fan-

out of the MPC958 clock driver is effectively doubled due to its

capability to drive multiple lines.

Figure 3 illustrates a typical power supply filter scheme. The

MPC958 is most susceptible to noise with spectral content in

the 1kHz to 1MHz range. Therefore the filter should be de-

signed to target this range. The key parameter that needs to be

met in the final filter design is the DC voltage drop that will be

seen between the V_CCsupply and the VCCA pin of the

MPC958. From the data sheet the I_VCCAcurrent (the current

sourced through the VCCA pin) is typically 15mA (20mA maxi-

mum), assuming that a minimum of 3.0V must be maintained

on the VCCA pin very little DC voltage drop can be tolerated

when a 3.3V V_CCsupply is used. The resistor shown in

Figure 3 must have a resistance of 10–15Ω to meet the voltage

drop criteria. The RC filter pictured will provide a broadband

filter with approximately 100:1 attenuation for noise whose

spectral content is above 20kHz. As the noise frequency

crosses the series resonant point of an individual capacitor it’s

overall impedance begins to look inductive and thus increases

with increasing frequency. The parallel capacitor combination

shown ensures that a low impedance path to ground exists for

frequencies well above the bandwidth of the PLL. It is recom-

mended that the user start with an 8–10Ω resistor to avoid

potential V_CCdrop problems and only move to the higher value

resistors when a higher level of attenuation is shown to be

needed.

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Figure 4. Single versus Dual Transmission Lines

The waveform plots of Figure 5 show the simulation results

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of an output driving a single line vs two lines. In both cases the

drive capability of the MPC958 output buffers is more than suf-

ficient to drive 50Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta

of only 43ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used exclu-

sively to maintain the tight output–to–output skew of the

MPC958. The output waveform in Figure 5 shows a step in the

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Figure 3. Power Supply Filter

Although the MPC958 has several design features to mini- waveform, this step is caused by the impedance mismatch

mize the susceptibility to power supply noise (isolated power seen looking into the driver. The parallel combination of the

and grounds and fully differential PLL) there still may be ap- 43Ω series resistor plus the output impedance does not match

plications in which overall performance is being degraded due the parallel combination of the line impedances. The voltage

to system power supply noise. The power supply filter wave launched down the two lines will equal:

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

465

MPC958

VL = VS ( Zo / (Rs + Ro +Zo))

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 6 should be used. In this case the series terminating

resistors are reduced such that when the parallel combination

is added to the output buffer impedance the line impedance is

perfectly matched.

Zo = 50Ω || 50Ω

Rs = 36Ω || 36Ω

Ro = 14Ω

VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)

= 1.31V

At the load end the voltage will double, due to the near unity

reflection coefficient, to 2.62V. It will then increment towards

the quiescent 3.0V in steps separated by one round trip delay

(in this case 4.0ns).

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14Ω + 22Ω ꢀ 22Ω = 50Ω ꢀ 50Ω

25Ω = 25Ω

Figure 6. Optimized Dual Line Termination

SPICE level output buffer models are available for engi-

neers who want to simulate their specific interconnect

schemes. In addition IV characteristics are in the process of

being generated to support the other board level simulators in

general use.

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Figure 5. Single versus Dual Waveforms

466

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

MPC958FAR2 [MOTOROLA]

相关型号：

MPC9600

MPC9600AE

MPC9600FA

MPC9600FAR2

MPC9600FAR2

MPC9608

MPC9608AC

MPC9608AC

MPC9608ACR2

MPC9608ACR2

MPC9608FA

MPC9608FA