MTB50N06VLT4 [MOTOROLA]
42A, 60V, 0.032ohm, N-CHANNEL, Si, POWER, MOSFET;
| 型号： | MTB50N06VLT4 |
| 厂家： | 
MOTOROLA |
| 描述： | 42A, 60V, 0.032ohm, N-CHANNEL, Si, POWER, MOSFET 开关 脉冲 晶体管 |
| 文件： | 总10页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MTB50N06VL/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
TMOS POWER FET
42 AMPERES
60 VOLTS
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance
area product about one–half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
R
= 0.032 OHM
DS(on)
TM
D
New Features of TMOS V
G
•
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R Technology
DS(on)
Faster Switching than E–FET Predecessors
CASE 418B–02, Style 2
S
2
•
D PAK
Features Common to TMOS V and TMOS E–FETs
•
•
•
Avalanche Energy Specified
and V Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS E–FET
I
DSS
DS(on)
•
Surface Mount Package Available in 16 mm 13–inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
60
Unit
Drain–to–Source Voltage
V
DSS
Vdc
Vdc
Drain–to–Gate Voltage (R
= 1.0 MΩ)
Gate–to–Source Voltage — Continuous
V
DGR
60
GS
V
±15
±20
Vdc
Vpk
GS
Gate–Source Voltage — Non–Repetitive (t ≤ 10 ms)
V
GSM
p
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
I
I
42
30
147
Adc
D
D
Drain Current — Single Pulse (t ≤ 10 µs)
I
Apk
p
DM
Total Power Dissipation @ 25°C
Derate above 25°C
P
D
125
0.83
3.0
Watts
W/°C
Watts
Total Power Dissipation @ T = 25°C (1)
A
Operating and Storage Temperature Range
T , T
stg
– 55 to 175
265
°C
J
Single Pulse Drain–to–Source Avalanche Energy — STARTING T = 25°C
E
AS
mJ
J
(V
DD
= 25 Vdc, V = 5 Vdc, PEAK I = 42 Apk, L = 0.3 mH, R = 25 Ω)
GS L G
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R
θJC
R
θJA
R
θJA
1.2
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds
T
L
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
V
(BR)DSS
(V
GS
= 0 Vdc, I = .25 mAdc)
60
—
—
64
—
—
Vdc
mV/°C
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
µAdc
DSS
(V
DS
(V
DS
= 60 Vdc, V
= 60 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 150°C)
—
—
—
—
10
100
GS
GS
J
Gate–Body Leakage Current (V
= ±15 Vdc, V
DS
= 0 Vdc)
I
—
—
100
nAdc
GS
GSS
ON CHARACTERISTICS (1)
Gate Threshold Voltage
V
GS(th)
(V
DS
= V , I = 250 µAdc)
1.0
—
1.4
4.3
2.0
—
Vdc
mV/°C
GS
D
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance (V
Drain–to–Source On–Voltage
= 5 Vdc, I = 21 Adc)
R
V
—
0.025
0.032
Ohms
Vdc
GS
D
DS(on)
DS(on)
(V
GS
(V
GS
= 5 Vdc, I = 42 Adc)
—
—
—
—
1.6
1.5
D
= 5 Vdc, I = 21 Adc, T = 150°C)
D
J
Forward Transconductance (V
= 6 Vdc, I = 20 Adc)
g
FS
17
28
—
Mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
1570
508
2200
710
iss
(V
DS
= 25 Vdc, V = 0 Vdc,
GS
f = 1.0 MHz)
Output Capacitance
C
oss
Transfer Capacitance
C
135
270
rss
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
16
355
80
30
701
160
320
60
ns
d(on)
(V
= 30 Vdc, I = 42 Adc,
D
Rise Time
DD
DS
t
r
V
= 5 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
d(off)
R
= 9.1 Ω)
t
f
160
40
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
nC
11
—
(V
= 48 Vdc, I = 42 Adc,
D
V
GS
= 5 Vdc)
20
—
16
—
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
V
Vdc
ns
SD
(I = 42 Adc, V
(I = 42 Adc, V
GS
= 0 Vdc)
= 0 Vdc, T = 150°C)
S
GS
—
—
1.03
0.94
2.5
—
S
J
Reverse Recovery Time
t
—
—
—
—
91.1
63.8
—
—
—
—
rr
t
a
(I = 42 Adc, V
= 0 Vdc,
dI /dt = 100 A/µs)
S
GS
S
t
27.3
b
Reverse Recovery Stored Charge
Q
0.299
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
D
nH
—
—
3.5
4.5
—
—
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
nH
—
7.5
—
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
90
80
70
60
50
40
30
20
10
0
90
T
= 25°C
5 V
J
V
= 10 V
V
≥ 10 V
GS
DS
T
= –55°C
80
70
60
50
40
30
20
10
0
J
8 V
7 V
6 V
25°C
100°C
4 V
3 V
2
0
0.5
1
1.5
2
2.5
3
0
1
3
4
5
6
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V
, GATE–TO–SOURCE VOLTAGE (VOLTS)
DS
GS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.06
0.04
V
= 5 V
GS
T
= 25°C
J
0.035
0.05
0.04
0.03
T
= 100°C
25°C
V
= 5 V
J
GS
0.025
0.02
10 V
0.03
0.02
0.015
0.01
– 55°C
0.01
0
0.005
0
0
9
18
27
36
45
54
63
72
81
90
0
10
20
30
I , DRAIN CURRENT (AMPS)
D
40
50
60
70
80
90
I
, DRAIN CURRENT (AMPS)
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2
1.8
1.6
1.4
1.2
1
1000
100
10
V
= 0 V
V
= 5 V
GS
GS
= 21 A
I
D
T
= 125°C
J
0.8
0.6
0.4
100°C
0.2
0
– 50
– 25
0
25
50
75
100
125
C)
150
175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (
°
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
J
DS
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also compli-
cates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
the drive circuit so that
) can be made from a rudimentary analysis of
G(AV)
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
= the gate drive resistance
GG
GG
R
G
and Q and V
GSP
are read from the gate charge curve.
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)
)]
d(on)
G
iss
GSP
In (V
/V
GG GSP
d(off)
G
iss
6000
5000
V
= 0 V
GS
T
= 25°C
J
C
iss
4000
3000
2000
C
rss
C
iss
C
C
oss
1000
0
V
= 0 V
DS
rss
10
10
5
0
5
15
20
25
V
V
DS
GS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
1000
100
12
10
8
30
25
T
= 25°C
= 42 A
QT
J
I
D
t
t
r
V
V
= 30 V
= 5 V
DD
GS
V
f
GS
20
15
10
t
t
d(off)
6
Q2
Q1
d(on)
10
1
4
T
I
= 25°C
= 42 A
J
D
2
0
5
0
Q3
V
DS
1
10
R , GATE RESISTANCE (OHMS)
G
100
0
10
20
30
40
50
Q , TOTAL CHARGE (nC)
T
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
25
T
V
= 25°C
J
= 0 V
GS
20
15
10
5
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
current (I
), the energy rating is specified at rated
DM
(I
) nor rated voltage (V
) is exceeded and the transition
DM
DSS
continuous current (I ), in accordance with industry custom.
D
time (t ,t ) do not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
r f
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
(T
– T )/(R ).
J(MAX)
C
θJC
currents below rated continuous I can safely be assumed to
A Power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For
Motorola TMOS Power MOSFET Transistor Device Data
equal the values indicated.
5
SAFE OPERATING AREA
1000
100
300
V
= 20 V
GS
SINGLE PULSE
= 25 C
R
LIMIT
DS(on)
I
= 42 A
D
THERMAL LIMIT
PACKAGE LIMIT
T
°
250
200
150
100
C
10 µs
100 µs
10
1
1 ms
10 ms
50
0
dc
0.1
1
10
100
25
50
75
100
125
150
C)
175
V
DS
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.00
D = 0.5
0.2
0.1
P
0.05
(pk)
0.10
0.01
R
(t) = r(t) R
JC θJC
θ
0.02
0.01
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
SINGLE PULSE
t
1
1
t
T
– T = P
R (t)
(pk) θJC
2
J(pk)
C
DUTY CYCLE, D = t /t
1 2
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
1.0E+01
t, TIME (s)
Figure 13. Thermal Response
3
R
= 50°C/W
θJA
Board material = 0.065 mil FR–4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils
2.5
2.0
1.5
1
di/dt
I
S
t
rr
t
t
a
b
TIME
0.5
0
0.25 I
t
S
p
25
50
75
100
125
150
175
I
S
T , AMBIENT TEMPERATURE (
°C)
A
Figure 14. Diode Reverse Recovery Waveform
2
Figure 15. D PAK Power Derating Curve
6
Motorola TMOS Power MOSFET Transistor Device Data
2
INFORMATION FOR USING THE D PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.33
8.38
0.08
2.032
0.42
0.24
10.66
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by T
junction temperature of the die, R
θJA
, the maximum rated
, the thermal resistance
R
versus drain pad area is shown in Figure 16.
J(max)
θJA
70
from the device junction to ambient, and the operating
temperature, T . Using the values provided on the data sheet,
Board Material = 0.0625
″
A
G–10/FR–4, 2 oz Copper
T
= 25°C
A
P
can be calculated as follows:
D
60
50
2.5 Watts
3.5 Watts
T
– T
A
J(max)
P
=
D
R
θJA
40
30
20
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T of 25°C, one can
5 Watts
A
2
calculate the power dissipation of the device. For a D PAK
device, P is calculated as follows.
D
0
2
4
6
8
10
12
14
16
A, AREA (SQUARE INCHES)
175°C – 25°C
= 3.0 Watts
P
=
D
Figure 16. Thermal Resistance versus Drain Pad
50°C/W
2
Area for the D PAK Package (Typical)
2
The50°C/WfortheD PAKpackageassumestheuseofthe
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 3.0 Watts. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad . Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
Motorola TMOS Power MOSFET Transistor Device Data
7
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
SOLDER PASTE
OPENINGS
STENCIL
2
registration. This is not the case with the DPAK and D PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 17. Typical Stencil for DPAK and
2
D PAK Packages
2
Figure 17 shows a typical stencil for the DPAK and D PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• Mechanical stress or shock should not be applied during
cooling.
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height to
2
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
incorporate other surface mount components, the D PAK is
not recommended for wave soldering.
8
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
18 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
typeofsolderused, andthetypeofboardorsubstratematerial
being used. This profile shows temperature versus time. The
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
STEP 4
HEATING
ZONES 3 & 6 ZONES 4 & 7
“SOAK”
STEP 5
HEATING
STEP 6
VENT
STEP 7
COOLING
205
PEAK AT
SOLDER JOINT
° TO 219°C
“SPIKE”
170°C
200
150
100
50
°C
°C
°C
°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160°
C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 18. Typical Solder Heating Profile
Motorola TMOS Power MOSFET Transistor Device Data
9
PACKAGE DIMENSIONS
C
E
V
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
4
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
MILLIMETERS
STYLE 2:
PIN 1. GATE
A
DIM
A
B
C
D
E
MIN
MAX
0.380
0.405
0.190
0.035
0.055
MIN
8.64
9.65
4.06
0.51
1.14
MAX
9.65
10.29
4.83
0.89
1.40
S
0.340
0.380
0.160
0.020
0.045
2. DRAIN
3. SOURCE
4. DRAIN
1
2
3
–T–
SEATING
PLANE
K
G
H
J
K
S
0.100 BSC
2.54 BSC
0.080
0.018
0.090
0.575
0.045
0.110
0.025
0.110
0.625
0.055
2.03
0.46
2.79
0.64
J
G
2.29
2.79
H
14.60
1.14
15.88
1.40
D 3 PL
V
M
0.13 (0.005)
T
CASE 418B–02
ISSUE B
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA / EUROPE: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MTB50N06VL/D
◊
相关型号：
©2020 ICPDF网 联系我们和版权申明