MP8736DL [MPS]
High Efficiency, Fast Transient, 6A, 19V Synchronous Buck Converter in a Tiny QFN20 (3x4mm) Package;
| 型号： | MP8736DL |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | High Efficiency, Fast Transient, 6A, 19V Synchronous Buck Converter in a Tiny QFN20 (3x4mm) Package 开关 |
| 文件： | 总23页 (文件大小：1146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP8736
High Efficiency, Fast Transient, 6A, 19V
Synchronous Buck Converter in a
Tiny QFN20 (3x4mm) Package
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP8736 is a fully integrated high frequency
synchronous rectified step-down switch mode
converter. This device integrates a 12mΩ low-
side FET and a 30mΩ high-side FET in a
monolithic die. The MP8736 operates with high
efficiency over a wide output current load range.
•
•
•
Wide 4.5V to 19V Operating Input Range
6A Output Current
Integrated 30mꢀ High-Side, 12mꢀ Low-
Side Power MOSFETs
Proprietary Switching Loss Reduction
Technique
•
•
•
•
•
1% Reference Voltage
Programmable Soft Start Time
Soft Shutdown
SCP, OCP, OVP, UVP Protection and
Thermal Shutdown
Available in a QFN20 (3x4mm) Package
100kHz to 2.5MHz switching frequency*
Constant-On-Time
(COT)
control
mode
provides fast transient response and eases loop
stabilization. The MP8736 has a programmable
frequency pin to optimize system performance.
Full protection features include SCP, OCP, OVP,
UVP and thermal shut down.
•
•
The MP8736 requires a minimum number of
readily available standard external components
and is available in a space saving QFN20
(3x4mm) package.
APPLICATIONS
•
•
Networking Systems
Broadband/Optical Communication
Systems
•
Distributed Power and Point of Load
Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
*switching frequency is only limited by on-time and is application specific
TYPICAL APPLICATION
Efficiency
8,19
7
100
IN
VIN
BST
SW
C3
R7
CIN
L2
90
80
70
60
50
40
30
20
10
0
V
=8V
IN
MP8736
9,10,17,18
2
FREQ
VOUT 1.05V
20
VCC
R4
C4
100pF
C10
V
=12V
IN
R14
100
R1
V
=19V
IN
PGOOD
EN
3
5
EN
FB
R2
40.2
SS AGND PGND
4
1
11-16
CSS
10nF
0.01
0.1
1
6
I
(A)
O
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
1
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP8736DL
QFN20 (3x4mm)
8736
* For Tape & Reel, add suffix –Z (e.g. MP8736DL–Z)
For RoHS compliant packaging, add suffix –LF (e.g. MP8736DL–LF–Z)
PACKAGE REFERENCE
TOP VIEW
VCC IN SW
SW
20
19
18
17
16
15
14
13
12
PGND
PGND
PGND
PGND
PGND
AGND
FREQ
FB
1
2
3
4
5
6
IN
IN
SW
SS
SW
EN
IN
11 PGND
PGOOD
7
8
9
10
BST IN SW SW
EXPOSED PAD
ON BACKSIDE
Thermal Resistance (4)
QFN20 (3x4mm)......................48 ...... 10...°C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 23V
V
V
SW........................................-0.3V to VIN + 0.3V
BS .......................................................VSW + 6V
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
I
V
VIN (RMS)........................................................ 3.5A
PGOOD...............................-0.3V to + VCC + 0.6V
All Other Pins..................................-0.3V to +6V
(2)
Continuous Power Dissipation (TA = +25°C)
…………………………………………………2.6W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (3)
Supply Voltage VIN ...........................4.5V to 19V
Operating Junction Temp. (TJ). -40°C to +125°C
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
2
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Supply Current (Shutdown)
IIN
VEN = 0V
0
μA
V
V
EN = 2V
FB = 1V
Supply Current (Quiescent)
IIN
500
μA
HS Switch On Resistance (5)
LS Switch On Resistance (5)
HSRDS-ON
LSRDS-ON
30
12
mꢀ
mꢀ
V
EN = 0V
Switch Leakage
Current Limit
SWLKG
ILIMIT
0
10
μA
A
VSW = 0V or 12V
12
R7=301kꢀ
One-Shot On Time
TON
250
ns
VOUT=1.2V
Minimum Off Time (5)
Fold-back Off Time (5)
OCP hold-off time (5)
TOFF
TFB
100
1.4
ns
μs
ILIM=1(HIGH)
ILIM=1(HIGH)
TOC
40
823
50
μs
Feedback Voltage
VFB
807
815
10
mV
nA
μA
μA
VFB
VFB
ms
ms
ms
V
Feedback Current
IFB
VFB = 815mV
VSS=0V
Soft Start Charging Current
Soft Stop Charging Current
Power Good Rising Threshold
Power Good Falling Threshold
Power Good Rising delay
Power Good Rising delay
Power Good Rising delay
EN Rising Threshold
ISS
8.5
8.5
0.9
0.85
1
ISS
VSS=0.815V
PGOODVth-Hi
PGOODVth-Lo
TPGOOD
TPGOOD
TPGOOD
ENVth-Hi
ENVth-Hys
IEN
TSS= 1ms
TSS =2ms
TSS =3ms
1.5
2
1.05
250
1.35
420
2
1.60
550
EN Threshold Hysteresis
EN Input Current
mV
μA
VEN = 2V
VIN
Under-Voltage
Lockout
Lockout
INUVVth
3.8
4.0
4.2
V
Threshold Rising
VIN
Under-Voltage
INUVHYS
VCC
880
mV
Threshold Hysteresis
VCC Regulator
5
5
V
VCC Load Regulation
ICC=5mA
%
Vo
Threshold
Over-Voltage
Protection
Detection
VOVP
VUVP
1.25
0.7
VFB
VFB
Vo
Threshold
Under-Voltage
Thermal Shutdown
TSD
150
25
°C
°C
Thermal Shutdown Hysteresis
Note
TSD-HYS
5) Guaranteed by design.
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
3
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
PIN FUNCTIONS
Pin #
Name
Description
1
AGND
Analog Ground.
Frequency Set during CCM operation. The ON period is determined by the input
voltage and the frequency-set resistor connected to FREQ pin. Connect a resistor
to IN for line feed forward. Decouple with a 1nF capacitor.
2
3
FREQ
FB
Feedback. An external resistor divider from the output to GND, tapped to the FB
pin, sets the output voltage.
Soft Start. Connect an external SS capacitor to program the soft start time for the
switch mode regulator. When the EN pin becomes high, an internal current source
(8.5uA) charges up the SS capacitor and the SS voltage slowly ramps up from 0 to
VFB smoothly. When the EN pin becomes low, an internal current source (8.5μA)
discharges the SS capacitor and the SS voltage slowly ramps down.
4
SS
EN=1 to enable the MP8736. For automatic start-up, connect EN pin to IN with a
100kꢀ resistor. Includes an internal 1Mꢀ pull-down.
5
6
EN
Power Good Output. The output of this pin is an open drain and is high if the
output voltage is higher than 90% of the nominal voltage. There is delay from FB ≥
90% to PGOOD high, which is 50% of SS time plus 0.5ms.
PGOOD
Bootstrap. A 0.1μF to 1μF capacitor connected between SW and BST pins is
required to form a floating supply across the high-side switch driver.
7
BST
IN
Supply Voltage. The MP8736 operates from a +4.5V to +19V input rail. CIN is
needed to decouple the input rail. Use wide PCB traces and multiple vias to make
the connection.
8, 19
9, 10, 17, 18
11-16
SW
Switch Output. Use wide PCB traces and multiple vias to make the connection.
System Ground. This pin is the reference ground of the regulated output voltage.
For this reason care must be taken in PCB layout.
PGND
Internal Bias Supply. Decouple with a 1µF capacitor as close to the pin as
possible.
20
VCC
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
4
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=12V, VOUT =1.05V, L=1.2µH, TA=+25°C, unless otherwise noted.
Efficiency
SW
Efficiency
Line Regulation
F
=600kHz
V
=12V
IN
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
1.0
0.8
F
=300kHz
SW
V
=8V
IN
0.6
0.4
F
=600kHz
SW
V
=12V
IN
0.2
0.0
V
=19V
IN
-0.2
-0.4
-0.6
-0.8
-1.0
0.01
0.1
1
6
0.01
0.1
1
6
4
6
8
10 12 14 16 18 20
(V)
I
(A)
I
(A)
V
IN
O
O
Load Regulation
Thermal Test
Frequency vs. Temperature
1.0
0.8
90
80
70
60
50
40
30
20
10
0
500
450
400
350
300
0.6
0.4
V
=12V
IN
0.2
0.0
250
200
150
100
50
V
=19V
IN
-0.2
-0.4
-0.6
-0.8
-1.0
V
=8V
IN
0
0
1
2
3
4
5
6
0
2
4
6
8
10
-40 -20
0
20 40 60 80 100120140
Temp (oC)
I
(A)
I (A)
O
O
Frequency vs. Input Voltage
Frequency vs. Load Current
500
450
400
1000
100
350
300
250
200
150
100
50
10
1
I
=6A
O
0
4
6
8
10 12 14 16
(V)
0.01
0.1
1
10
V
I
(A)
O
IN
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
5
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.05V, L=1.2µH, TA=+25°C, unless otherwise noted.
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
6
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.05V, L=1.2µH, TA=+25°C, unless otherwise noted.
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
7
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=5V, VOUT =1.0V, FS=1.5MHz, unless otherwise noted.
Efficiency
Case Temperature vs.
Load Current
Line Regulation @ I =6A
OUT
90
85
80
75
70
65
60
60
50
40
30
20
10
0
1
0.8
0.6
0.4
0.2
0
V
=4.5V
IN
V
=5V
IN
-0.2
-0.4
-0.6
-0.8
-1
V
=5.5V
IN
0
1
2
3
4
5
6
0
1
2
3
4
5
6
4.5
4.7
4.9
5.1
(V)
5.3
5.5
I
OUT
(A)
I
(A)
V
IN
OUT
Load Regulation
Frequency vs. Temperature
F vs. Load
S
I
=6A
OUT
0.25
0.2
1.95
1.9
2
1.8
1.6
1.4
1.2
1
0.15
0.1
1.85
1.8
V
=5.5V
IN
V
=5V
IN
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
0.8
0.6
0.4
0.2
0
V
=4.5V
IN
1.75
1.7
1.65
0.5 1.5 2.5 3.5 4.5 5.5
-30 -10 10 30 50 70 90 110
0.01
0.1
1
10
I
(A)
I
(A)
OUT
OUT
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
8
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=5V, VOUT =1.0V, FS=1.5MHz, unless otherwise noted.
Steady State
Steady State
I
=0.6A
I
=6A
OUT
OUT
V
V
OUT
OUT
10mV/div
10mV/div
V
OUT
V
V
IN
IN
20mV/div
100mV/div
100mV/div
V
V
SW
SW
5V/div
5V/div
I
I
OUT
I
OUT
OUT
2A/div
1A/div
5A/div
PGOOD, Startup Through EN
PGOOD, Startup Through EN
PGOOD, Shutdown Through EN
I
=0A
I
=6A
I
=0A
OUT
OUT
OUT
V
EN
5V/div
V
V
EN
EN
5V/div
5V/div
V
OUT
V
V
OUT
OUT
1V/div
1V/div
1V/div
V
V
V
PGOOD
5V/div
PGOOD
5V/div
PGOOD
5V/div
I ind
-
2A/div
I ind
-
2A/div
I ind
-
2A/div
Startup Through V
IN
OUT
Startup Through V
IN
OUT
PGOOD, Shutdown Through EN
I
=0A
I
=6A
=6A
I
OUT
V
V
V
SW
5V/div
SW
EN
5V/div
5V/div
V
V
OUT
OUT
1V/div
V
OUT
1V/div
1V/div
V
IN
5V/div
V
V
IN
PGOOD
5V/div
5V/div
I ind
-
5A/div
I ind
-
2A/div
I ind
-
2A/div
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
9
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=5V, VOUT =1.0V, FS=1.5MHz, unless otherwise noted.
Shutdown Through V
IN
OUT
Shutdown Through V
IN
OUT
Over-current Protection
I
=0A
I
=6A
V
SW
5V/div
V
V
SW
SW
5V/div
5V/div
V
OUT
1V/div
V
V
OUT
OUT
1V/div
1V/div
V
IN
5V/div
V
V
IN
IN
5V/div
5V/div
I ind
-
2A/div
I ind
-
2A/div
I ind
-
2A/div
Short Circuit Protection
Startup Through EN
Startup Through EN
I
=0A
I
=6A
OUT
OUT
V
V
SW
V
SW
SW
5V/div
5V/div
5V/div
V
V
OUT
V
OUT
OUT
1V/div
1V/div
1V/div
V
V
IN
V
IN
IN
5V/div
5V/div
5V/div
I ind
-
2A/div
I ind
-
2A/div
I ind
-
5A/div
Shutdown Through EN
Shutdown Through EN
I
=6A
=0A
I
OUT
OUT
V
V
SW
SW
5V/div
5V/div
V
V
OUT
OUT
1V/div
1V/div
V
V
IN
IN
5V/div
5V/div
I ind
-
5A/div
I ind
-
5A/div
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
10
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=5V, VOUT =1.0V, FS=1.5MHz, unless otherwise noted.
Noisy Input Voltage
Output Voltage with Noisy
Input Voltage
V
=5V, V =1.24V
IN NOISEPP
I
=6A
OUT
V
IN
V
1V/div
IN
1V/div
V
V
OUT
IN
2V/div
20mV/div
V
OUT
20mV/div
I
OUT
2A/div
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
11
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
BLOCK DIAGRAM
IN
Current Sense
Amplifer
FREQ
VCC
+
-
RSEN
5V LDO
OC
Over-Current
Timer
BST
Refresh
Timer
BSTREG
ILIM
+
-
OFF
Timer
REFERENCE
EN
SS
HS_FET
HS Ilimit
Comparator
HS
Driver
PWM
0.4V
1.0V
0.815V
1MEG
xS
Q
0
xR
SW
LOGIC
SOFT
START/STOP
VCC
ON
Timer
START
+
+
-
LS_FET
FB
LS
Driver
Loop
Comparator
Current
Modulator
PGOOD
+
-
UV
+
-
GND
PGOOD
Comparator
UV Detect
Comparator
0
AGND
OV
+
-
0
OV Detect
Comparator
Figure 1—Functional Block Diagram
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
12
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
OPERATION
PWM Operation
As Figure 2 shows, when the output current is
high, the HS-FET and LS-FET repeat on/off as
described above. In this operation, the inductor
current will never go to zero. It’s called
continuous-conduction-mode (CCM) operation. In
CCM operation, the switching frequency (FSW) is
fairly constant.
The MP8736 is a fully integrated synchronous
rectified step-down switch mode converter.
Constant-on-time (COT) control is employed to
provide fast transient response and easy loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) is turned ON when
the feedback voltage (VFB) is below the reference
voltage (VREF), which indicates insufficient output
voltage. The ON period is determined by the
input voltage and the frequency-set resistor as
follows:
Light-Load Operation
At light load or no load condition, the output
drops very slowly and the MP8736 reduces the
switching frequency automatically to maintain
high efficiency. The light load operation is shown
in Figure 3. The VFB does not reach VREF when
the inductor current is approaching zero. The LS-
FET driver turns into tri-state (high Z) whenever
the inductor current reaches zero. A current
modulator takes over the control of LS-FET and
limits the inductor current to less than -1mA.
Hence, the output capacitors discharge slowly to
GND through LS-FET. As a result, the efficiency
at light load condition is greatly improved. At light
load condition, the HS-FET is not turned ON as
frequently as at heavy load condition. This is
called skip mode.
6×R7 kΩ
(
(1)
TON ns =
+ 40 ns
(
)
(
)
V
V − 0.4
IN ( )
After the ON period elapses, the HS-FET is
turned off, or becomes OFF state. It is turned ON
again when VFB drops below VREF. By repeating
operation this way, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) is turned on when the HS-FET is in its
OFF state to minimize the conduction loss. There
will be a dead short between input and GND if
both HS-FET and LS-FET are turned on at the
same time. It’s called shoot-through. In order to
avoid shoot-through,
a
dead-time (DT) is
internally generated between HS-FET off and LS-
FET on, or LS-FET off and HS-FET on.
Heavy-Load Operation
Figure 3—Light Load Operation
As the output current increases from the light
load condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned ON more frequently.
Hence, the switching frequency increases
correspondingly. The output current reaches the
critical level when the current modulator time is
zero. The critical level of the output current is
determined as follows:
(VIN − VOUT)× VOUT
2×L×FSW × VIN
Figure 2—Heavy Load Operation
(2)
IOUT
=
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
13
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
Switching Frequency
Constant on-time (COT) control is used in the
MP8736 and there is no dedicated oscillator in
the IC. The input voltage is feed-forwarded to the
on-time one-shot timer through the resistor R7.
The duty ratio is kept as VOUT/VIN. Hence, the
switching frequency is fairly constant over the
input voltage range. The switching frequency
can be set as follows:
Figure 5—Jitter in Skip Mode
Ramp with Large ESR Cap
In the case of POSCAP or other types of
capacitor with larger ESR is applied as output
capacitor. The ESR ripple dominates the output
ripple, and the slope on the FB is quite ESR
related. Figure 6 shows an equivalent circuit in
PWM mode with the HS-FET off and without an
external ramp circuit. Turn to application
information section for design steps with large
ESR caps.
106
(3)
F
kHz =
(
)
SW
6×R7 kΩ
V
V
(
)
(
)
IN
×
+ T DEALY ns
(
)
V
V − 0.4 VOUT
)
V
(
(
)
IN
Where TDELAY is the comparator delay. It’s about
40ns.
Jitter and FB Ramp Slope
SW
Figure 4 and Figure 5 show jitter occurring in
both PWM mode and skip mode. When there is
noise in the VFB downward slope, the ON time of
HS-FET deviates from its intended location and
produces jitter. It is necessary to understand that
there is a relationship between a system’s
stability and the steepness of the VFB ripple’s
downward slope. The slope steepness of the VFB
ripple dominates in noise immunity. The
magnitude of the VFB ripple doesn’t directly affect
the noise immunity directly.
L
Vo
ESR
POSCAP
R1
R2
FB
Figure 6—Simplified Circuit in PWM Mode
without External Ramp Compensation
To realize the stability when no external ramp is
used, usually the ESR value should be chosen
as follow:
TSW
TON
2
+
0.7× π
(4)
RESR
≥
COUT
Tsw is the switching period.
Ramp with small ESR Cap
Figure 4—Jitter in PWM Mode
When the output capacitors are ceramic ones,
the ESR ripple is not high enough to stabilize the
system, and external ramp compensation is
needed. Skip to application information section
for design steps with small ESR caps.
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
14
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
circuit of the skip mode when both the HS-FET
and LS-FET are off.
Figure 7—Simplified Circuit in PWM Mode
Figure 8—Simplified Circuit in skip Mode
with External Ramp Compensation
The downward slope of the VFB ripple in skip
mode can be determined as follow:
In PWM mode, an equivalent circuit with HS-FET
off and the use of an external ramp
compensation circuit (R4, C4) is simplified in
Figure 7. The external ramp is derived from the
inductor ripple current. If one chooses C4, R9,
R1 and R2 to meet the following condition:
−VREF
(10)
VSLOPE2
=
( R +R //Ro)×C
(
)
1
2
OUT
Where Ro is the equivalent load resistor.
As described in Fig.6, VSLOPE2 in the skip mode is
lower than that is in the PWM mode, so it is
reasonable that the jitter in the skip mode is
larger. If one wants a system with less jitter
during ultra light load condition, the values of the
⎛
⎜
⎝
⎞
⎟
⎠
1
1
5
R1 ×R2
R1 + R2
(5)
<
×
+ R9
2π×FSW ×C4
Where:
V
FB resistors should not be too big, however, that
will decrease the light load efficiency.
IR4 = IC4 +IFB ≈ IC4
(6)
Soft Start/Stop
And the ramp on the VFB can then be estimated
as:
The MP8736 employs soft start/stop (SS)
mechanism to ensure smooth output during
power-up and power shutdown. When the EN pin
becomes high, an internal current source (8.5μA)
charges up the SS CAP. The SS CAP voltage
takes over the REF voltage to the PWM
comparator. The output voltage smoothly ramps
up with the SS voltage. Once the SS voltage
reaches the same level as the REF voltage, it
keeps ramping up while VREF takes over the
PWM comparator. At this point, the soft start
finishes and it enters into steady state operation.
When the EN pin becomes low, the SS CAP
voltage is discharged through an 8.5uA internal
current source. Once the SS voltage reaches
REF voltage, it takes over the PWM comparator.
The output voltage will decrease smoothly with
SS voltage until zero level. The SS CAP value
can be determined as follows:
V − VO
R4 ×C4
R1 //R2
IN
(7)
VRAMP
=
×TON ×
R1 //R2 +R9
The downward slope of the VFB ripple then
follows
−VRAMP
−VOUT
R4 ×C4
(8)
VSLOPE1
=
=
T
off
As can be seen from equation 8, if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation 5, then we can only
reduce R4. For a stable PWM operation, the
V
slope1 should be design follow equation 9.
TSW
T
+
ON -RESRCOUT
Io×10-3
TSW -Ton
0.7×π
2
(9)
-Vslope1
≥
VO+
2×L×COUT
TSS ms ×I μA
Io is the load current.
(
SS
(11)
CSS nF =
(
)
VREF
V
(
)
In skip mode, the downward slope of the VFB
ripple is almost the same whether the external
ramp is used or not. Fig.9 shows the simplified
If the output capacitors have large capacitance
value, it’s not recommended to set the SS time
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
15
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
too small. Otherwise, it’s easy to hit the current
If short circuit happens, then the current limit will
be hit immediately and the FB voltage will
become lower than 50% of the REF voltage.
When the current limit is hit and the FB voltage is
lower than 50% of the REF voltage (0.815V), the
device considers this as a dead short on the
output and triggers SCP latch-off immediately.
This is short circuit protection (SCP).
limit during SS. A minimum value of 4.7nF should
be used if the output capacitance value is larger
than 330μF.
Power Good (PGOOD)
The MP8736 has power-good (PGOOD) output.
The PGOOD pin is the open drain of a MOSFET.
It should be connected to VCC or other voltage
source through a resistor (e.g. 100k). After the
input voltage is applied, the MOSFET is turned
on so that the PGOOD pin is pulled to GND
before SS is ready. After FB voltage reaches
90% of REF voltage, the PGOOD pin is pulled
high after a delay.
Over/Under-voltage Protection (OVP/UVP)
The MP8736 monitors the output voltage through
a resistor divider feedback (FB) voltage to detect
overvoltage and undervoltage on the output.
When the FB voltage is higher than 125% of the
REF voltage (0.815V), it’ll trigger OVP latch-off.
Once it triggers OVP, the LS-FET is always on
while the HS-FET is always off. It needs power
cycle to power up again. When the FB voltage is
below 50% of the REF voltage (0.815V), it is
recognized as UV (under-voltage). Usually, UVP
accompanies a hit in current limit and this results
in SCP.
The PGOOD delay time is determined as follows:
TPGOOD(ms) = 0.5× TSS(ms) + 0.5
(12)
When the FB voltage drops to 85% of REF
voltage, the PGOOD pin will be pulled low.
Over-Current Protection (OCP) and Short-
Circuit Protection (SCP)
UVLO protection
The MP8736 has cycle-by-cycle over-current limit
control. The inductor current is monitored during
the ON state. Once it detects that the inductor
current is higher than the current limit, the HS-
FET is turned off. At the same time, the OCP
timer is started. The OCP timer is set as 40μs. If
in the following 40μs, the current limit is hit for
every cycle, then it’ll trigger OCP latch-off. The
converter needs power cycle to restart after it
triggers OCP.
The MP8736 has under-voltage lock-out
protection (UVLO). When the input voltage is
higher than the UVLO rising threshold voltage,
the MP8736 will be powered up. It shuts off when
the input voltage is lower than the UVLO falling
threshold voltage. This is non-latch protection.
Thermal Shutdown
Thermal shutdown is employed in the MP8736.
The junction temperature of the IC is internally
monitored. If the junction temperature exceeds
the threshold value (typically 150ºC), the
converter shuts off. This is a non-latch protection.
There is about 25ºC hysteresis. Once the
junction temperature drops to about 125ºC, it
initiates a SS.
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
16
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
current loss while too large R2 makes the FB
APPLICATION INFORMATION
Setting the Output Voltage-Large ESR Caps
noise sensitive. It is recommended to choose a
value within 5kꢀ-50kꢀ for R2, using
a
For applications that electrolytic capacitor or POS
capacitor with a controlled output of ESR is set
as output capacitors. The output voltage is set by
feedback resistors R1 and R2. As figure 9 shows.
comparatively larger R2 when Vo is low,
etc.,1.05V, and a smaller R2 when Vo is high.
And the value of R1 then is determined as follow:
R2
(14)
R1=
V
R2
FB(AVG)
-
(VOUT -VFB(AVG) ) R4 +R9
The VFB(AVG) is the average value on the FB,
VFB(AVG) varies with the Vin, Vo, and load
condition, etc., its value on the skip mode would
be lower than that of the PWM mode, which
means the load regulation is strictly related to the
Figure 9—Simplified Circuit of POS Capacitor
VFB(AVG). Also the line regulation is related to the
VFB(AVG) ,if one wants to gets a better load or line
regulation, a lower Vramp is suggested once it
meets equation 9.
First, choose a value for R2. R2 should be
chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kꢀ-
50kꢀ for R2, using a comparatively larger R2
when Vout is low, etc.,1.05V, and a smaller R2
when Vout is high. Then R1 is determined as
follow with the output ripple considered:
For PWM operation, VFB(AVG) value can be
deduced from equation 15.
1
R1 //R2
V
= VREF + VRAMP
×
(15)
FB(AVG)
2
R1 //R2 +R9
Usually, R9 is set to 0ꢀ, and it can also be set
following equation 16 for a better noise immunity.
It should also set to be 5 timers smaller than
R1//R2 to minimize its influence on Vramp.
1
VOUT
−
ΔVOUT − VREF
2
(13)
R1 =
R2
VREF
ΔVOUT is the output ripple determined by equation
1
R9 ≤
(16)
22.
2π×C4 ×2F
SW
Setting the Output Voltage-Small ESR Caps
Using equation 14 to calculate the output voltage
can be complicated. To simplify the calculation of
R1 in equation 14, a DC-blocking capacitor Cdc
can be added to filter the DC influence from R4
and R9. Figure 11 shows a simplified circuit with
external ramp compensation and a DC-blocking
capacitor. With this capacitor, R1 can easily be
obtained by using equation 17 for PWM mode
operation.
Figure10—Simplified Circuit of Ceramic
Capacitor
1
(VOUT − VREF − VRAMP
)
2
(17)
R1 =
R2
When low ESR ceramic capacitor is used in the
output, an external voltage ramp should be
added to FB through resistor R4 and capacitor
C4.The output voltage is influenced by ramp
voltage VRAMP besides R divider as shown in
figure 10. The VRAMP can be calculated as shown
in equation 7. R2 should be chosen reasonably,
a small R2 will lead to considerable quiescent
1
VREF + VRAMP
2
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
should also not larger than 0.47uF considering
start up performance. In case one wants to use
larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
17
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
Cdc in a reasonable value without affecting the
The input voltage ripple can be estimated as
follows:
system start up. Be noted that even when the
Cdc is applied, the load and line regulation are
still Vramp related.
IOUT
SW ×CIN
VOUT
VOUT
(20)
ΔV =
×
×(1−
)
IN
F
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT,
where:
IOUT
4 FSW ×CIN
1
(21)
ΔV =
×
IN
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
Figure11—Simplified Circuit of Ceramic
Capacitor with DC blocking capacitor
Input Capacitor
The input current to the step-down converter is
discontinuous. Therefore, a capacitor is required
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance. In the layout, it’s recommended to
put the input capacitors as close to the IN pin as
possible.
VOUT
V
1
(22)
)
ΔVOUT
=
×(1− OUT )×(RESR
+
FSW ×L
V
8×FSW ×COUT
IN
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
The capacitance varies significantly over
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over temperature.
VOUT
VOUT
(23)
ΔVOUT
=
×(1−
)
8×F 2 ×L×COUT
V
SW
IN
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4
following equation 5, 8 and 9.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value around 12mꢀ is required to
ensure stable operation of the converter. For
simplification, the output ripple can be
approximated as:
VOUT
VOUT
ICIN = IOUT
×
×(1−
)
(18)
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
,
where:
IOUT
ICIN
=
(19)
2
For simplification, choose the input capacitor
whose RMS current rating is greater than half of
the maximum load current.
VOUT
V
ΔVOUT
=
×(1− OUT )×RESR
(24)
FSW ×L
V
IN
The input capacitance value determines the input
voltage ripple of the converter. If there is input
voltage ripple requirement in the system design,
choose the input capacitor that meets the
specification
Inductor
The inductor is required to supply constant
current to the output load while being driven by
the switching input voltage. A larger value
inductor will result in less ripple current that will
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
18
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
result in lower output ripple voltage. However, a
Where ΔIL is the peak-to-peak inductor ripple
larger value inductor will have a larger physical
size, higher series resistance, and/or lower
saturation current. A good rule for determining
the inductor value is to allow the peak-to-peak
ripple current in the inductor to be approximately
30~40% of the maximum switch current limit.
Also, make sure that the peak inductor current is
below the maximum switch current limit. The
inductance value can be calculated as:
current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated as:
VOUT
VOUT
(26)
ILP = IOUT
+
×(1−
)
2FSW ×L
V
IN
The inductors listed in Table 1 are highly
recommended for the high efficiency they can
provide.
VOUT
SW × ΔIL
VOUT
(25)
L =
×(1−
)
F
V
IN
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
19
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
Table 1—Inductor Selection Guide
Switching
Inductance DCR
Current
Dimensions
L
Part Number
Manufacturer
Frequency
(kHz)
(µH)
(mΩ) Rating (A)
x W x H (mm3)
PCMC-135T-
R68MF
Cyntec
0.68
1.7
34
13.5 x 12.6 x 4.8
600
FDA1254-1R0M
FDA1254-1R2M
TOKO
TOKO
1
2
25.2
20.2
13.5 x 12.6 x 5.4
13.5 x 12.6 x 5.4
300~600
300~600
1.2
2.05
we-744314047
Wurth
0.47
1.35
20
7.00 x 6.90 x 4.80
600~2MHz
Typical Design Parameter Tables
Table 4—700kHz, 12VIN
VOUT
(V)
L
(μH)
R1
(kꢀ)
R2
(kꢀ)
R7
(kꢀ)
The following tables include recommended
component values for typical output voltages
1.2V, 2.5V, 3.3V) and switching frequencies
(300kHz, 500kHz, and 700kHz). Refer to Tables
2-4 for design cases without external ramp
compensation and Tables 5-7 for design cases
with external ramp compensation. External ramp
is not needed when high-ESR capacitors, such
as electrolytic or POSCAPs are used. External
ramp is needed when low-ESR capacitors, such
as ceramic capacitors are used. For cases not
listed in this datasheet, a calculator in excel
spreadsheet can also be requested through a
local sales representative to assist with the
calculation.
1.2
2.5
3.3
1
1
1
12.1
30
26.1
14.3
13.3
316
590
806
40.2
Table 5—300kHz, 12VIN
VOUT
(V)
L
R1
(kꢀ)
R2
(kꢀ)
R4
C4
R7
(μH)
(kꢀ) (pF)
(kꢀ)
1.2
2.5
3.3
2.2
2.2
2.2
12.1
30
26.1
14.3
12.4
330
402
422
220
220
220
750
1500
1600
40.2
Table 6—500kHz, 12VIN
VOUT
(V)
L
R1
(kꢀ)
R2
(kꢀ)
R4
C4
R7
(μH)
(kꢀ) (pF)
(kꢀ)
Table 2—300kHz, 12VIN
1.2
2.5
3.3
1
1
1
12.1
30
26.1
14.3
12.4
374
412
422
220
220
220
442
845
VOUT
(V)
L
(μH)
R1
(kꢀ)
R2
(kꢀ)
R7
(kꢀ)
40.2
1000
1.2
2.5
3.3
2.2
2.2
1
12.1
30
26.1
14.3
13.3
750
1500
1600
Table 7—700kHz, 12VIN
40.2
VOUT
(V)
L
R1
(kꢀ)
R2
(kꢀ)
R4
C4
R7
(μH)
(kꢀ) (pF)
(kꢀ)
Table 3—500kHz, 12VIN
1.2
2.5
3.3
1
1
1
12.1
30
26.1
14.3
12.4
240
412
422
220
220
220
316
590
806
VOUT
(V)
L
R1
R2
R7
(kꢀ)
(μH)
(kꢀ)
(kꢀ)
40.2
1.2
2.5
3.3
1
1
1
12.1
30
26.1
14.3
13.3
442
845
Table 8—1.5MHz, 5VIN
VOUT
(V)
L
(μH)
R1
R2
R4
C4
R7
(kꢀ)
40.2
1000
(kꢀ)
(kꢀ)
(kꢀ) (pF)
0.9
1
0.47
0.47
0.47
1.8
20
20
20
200
200
200
270
270
270
89.8
100
115
4.37
9.92
1.2
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
20
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
TYPICAL APPLICATION
8,19
7
IN
BST
SW
VIN
C3
R7
100nF
MP8736
9,10,17,18
2
FREQ
VCC
VOUT 1.05V
20
R6
R5
PGOOD
EN
+
6
5
PGOOD
EN
3
FB
C2A
10nF
AGND PGND
SS
4
1
11-16
C5
10nF
Figure12—Typical Application Circuit with No External Ramp
8,19
7
IN
BST
VIN
C3
100nF
R7
MP8736 SW
9,10,17,18
2
FREQ
VCC
VOUT 1.05V
20
C4
R6
R5
100pF
PGOOD
EN
6
5
PGOOD
EN
3
FB
AGND PGND
SS
4
1
11-16
C5
10nF
Figure13—Typical Application Circuit with Low ESR Ceramic Capacitor
8,19
7
IN
BST
VIN
C3
100nF
R7
MP8736 SW
9,10,17,18
2
FREQ
VCC
VOUT 1.05V
20
C4
R6
R5
100pF
C6
10nF
PGOOD
EN
6
5
PGOOD
EN
3
FB
AGND PGND
SS
4
1
11-16
C5
10nF
Figure 14—Typical Application Circuit with Low ESR Ceramic Capacitor
and DC-Blocking Capacitor.
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
21
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
Layout Recommendation
1. The high current paths (GND, IN, and SW)
should be placed very close to the device
with short, direct, and wide traces.
2. Put the input capacitors as close to the IN
and GND pins as possible.
3. Put the decoupling capacitor as close to the
VCC and GND pins as possible.
4. Keep the switching node SW short and away
from the feedback network.
5. The external feedback resistors should be
placed next to the FB pin. Make sure that
there is no via on the FB trace.
Inner1 Layer
6. Keep the BST voltage path (BST, C3, and SW)
as short as possible.
7. Keep the bottom IN and SW pads connected
with large copper to achieve better thermal
performance.
8. Four-layer layout is strongly recommended to
achieve better thermal performance.
Inner2 Layer
Top Layer
Bottom Layer
Figure 15—PCB Layout
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
22
MP8736 – HIGH EFFICIENCY, FAST TRANSIENT, 6A, 19V SYNCHRONOUS BUCK CONVERTER IN A TINY 3X4mm PACKAGE
PACKAGE INFORMATION
QFN20 (3x4mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP8736 Rev. 1.34
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
23
©2020 ICPDF网 联系我们和版权申明