MX25U4035ZUI-25G [Macronix]
4M-BIT [x 1/x 2/x 4] 1.8V CMOS SERIAL FLASH; 4M- BIT [ ×1 / ×2 / ×4 ] 1.8V的CMOS串行闪存型号: | MX25U4035ZUI-25G |
厂家: | MACRONIX INTERNATIONAL |
描述: | 4M-BIT [x 1/x 2/x 4] 1.8V CMOS SERIAL FLASH |
文件: | 总54页 (文件大小:2237K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MX25U4035
MX25U8035
MX25U4035/MX25U8035
DATASHEET
P/N: PM1394
REV. 1.0, MAR. 09, 2009
1
MX25U4035
MX25U8035
Contents
FEATURES ..................................................................................................................................................................5
GENERAL DESCRIPTION .........................................................................................................................................7
Table 1. Additional Feature Comparison...................................................................................................................7
PIN CONFIGURATIONS .............................................................................................................................................8
PIN DESCRIPTION......................................................................................................................................................8
BLOCK DIAGRAM.......................................................................................................................................................9
DATA PROTECTION..................................................................................................................................................10
Table 2. Protected Area Sizes................................................................................................................................. 11
Table 3. 512-bit Secured OTP Definition ................................................................................................................ 11
Memory Organization...............................................................................................................................................12
Table 4-1. Memory Organization (4Mb) .................................................................................................................12
Table 4-2. Memory Organization (8Mb) .................................................................................................................13
DEVICE OPERATION................................................................................................................................................14
Figure 1. Serial Modes Supported..........................................................................................................................14
COMMAND DESCRIPTION.......................................................................................................................................15
Table 5. Command Set ...........................................................................................................................................15
(1) Write Enable (WREN) .......................................................................................................................................17
(2) Write Disable (WRDI)........................................................................................................................................17
(3) Read Identification (RDID) ................................................................................................................................17
(4) Read Status Register (RDSR)...........................................................................................................................18
(5) Write Status Register (WRSR)..........................................................................................................................19
Table 6. Protection Modes ......................................................................................................................................19
(6) Read Data Bytes (READ)..................................................................................................................................20
(7) Read Data Bytes at Higher Speed (FAST_READ)............................................................................................20
(8) 2 x I/O Read Mode (2READ).............................................................................................................................20
(9) 4 x I/O Read Mode (4READ).............................................................................................................................21
(10) Sector Erase (SE) ...........................................................................................................................................21
(11) Block Erase (BE32K).......................................................................................................................................22
(12) Block Erase (BE).............................................................................................................................................22
(13) Chip Erase (CE) ..............................................................................................................................................22
(14) Page Program (PP).........................................................................................................................................23
(15) 4 x I/O Page Program (4PP) ...........................................................................................................................23
(16) Continuously program mode (CP mode).........................................................................................................23
(17) Deep Power-down (DP) ..................................................................................................................................24
(18) Release from Deep Power-down (RDP), Read Electronic Signature (RES)................................................... 24
(19) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)................................................. 25
Table 7. ID Definitions ............................................................................................................................................25
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(20) Enter Secured OTP (ENSO) ...........................................................................................................................26
(21) Exit Secured OTP (EXSO) ..............................................................................................................................26
(22) Read Security Register (RDSCUR).................................................................................................................26
Table 8. Security Register Definition.......................................................................................................................27
(23) Write Security Register (WRSCUR)................................................................................................................27
(24) HOLD# pin function enable (HDE) ..................................................................................................................27
POWER-ON STATE...................................................................................................................................................28
ELECTRICAL SPECIFICATIONS..............................................................................................................................29
ABSOLUTE MAXIMUM RATINGS .........................................................................................................................29
Figure 2.Maximum Negative Overshoot Waveform................................................................................................29
CAPACITANCE TA = 25°C, f = 1.0 MHz.................................................................................................................29
Figure 3. Maximum Positive Overshoot Waveform.................................................................................................29
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL.................................................................. 30
Figure 5. OUTPUT LOADING................................................................................................................................30
Table 9. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V) .................................... 31
°
°
Table 10. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V) .................................. 32
°
°
Timing Analysis........................................................................................................................................................34
Figure 6. Serial Input Timing...................................................................................................................................34
Figure 7. Output Timing ..........................................................................................................................................34
Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 ....................................................... 35
Figure 9. Hardware Reset Timing...........................................................................................................................35
Figure 10. Write Enable (WREN) Sequence (Command 06) ................................................................................. 36
Figure 11. Write Disable (WRDI) Sequence (Command 04) ..................................................................................36
Figure 12. Read Identification (RDID) Sequence (Command 9F) .......................................................................... 36
Figure 13. Read Status Register (RDSR) Sequence (Command 05)..................................................................... 37
Figure 14. Write Status Register (WRSR) Sequence (Command 01)................................................................... 37
Figure 15. Read Data Bytes (READ) Sequence (Command 03)........................................................................... 37
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)....................................................... 38
Figure 17. 2 x I/O Read Mode Sequence (Command BB) .....................................................................................39
Figure 18. 4 x I/O Read Mode Sequence (Command EB) .....................................................................................39
Figure 19. 4 x I/O Read enhance performance Mode Sequence (Command EB) ................................................. 40
Figure 20. Page Program (PP) Sequence (Command 02)....................................................................................41
Figure 21. 4 x I/O Page Program (4PP) Sequence (Command 38) ...................................................................... 41
Figure 22. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) ....................... 42
Figure 23. Sector Erase (SE) Sequence (Command 20) ......................................................................................42
Figure 24. Block Erase 32KB (BE32K) Sequence (Command 52)........................................................................ 43
Figure 25. Block Erase (BE) Sequence (Command D8) .......................................................................................43
Figure 26. Chip Erase (CE) Sequence (Command 60 or C7) ...............................................................................43
Figure 27. Deep Power-down (DP) Sequence (Command B9)............................................................................. 44
Figure 28. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) .. 44
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Figure 29. Release from Deep Power-down (RDP) Sequence (Command AB).................................................... 45
Figure 30. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF) .............. 45
Figure 31. Power-up Timing....................................................................................................................................46
Table 11. Power-Up Timing and VWI Threshold.....................................................................................................46
INITIAL DELIVERY STATE.....................................................................................................................................46
RECOMMENDED OPERATING CONDITIONS.........................................................................................................47
Figure A. AC Timing at Device Power-Up...............................................................................................................47
ERASE AND PROGRAMMING PERFORMANCE....................................................................................................48
LATCH-UP CHARACTERISTICS..............................................................................................................................48
ORDERING INFORMATION......................................................................................................................................49
PART NAME DESCRIPTION.....................................................................................................................................50
PACKAGE INFORMATION........................................................................................................................................51
REVISION HISTORY .................................................................................................................................................53
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MX25U4035
MX25U8035
4M-BIT [x 1/x 2/x 4] 1.8V CMOS SERIAL FLASH
8M-BIT [x 1/x 2/x 4] 1.8V CMOS SERIAL FLASH
FEATURES
GENERAL
•
Serial Peripheral Interface compatible -- Mode 0 and Mode 3
•
4M: 4,194,304 x 1 bit structure or 2,097,152 x 2 bits (two I/O read mode) structure or 1,048,576 x 4 bits (four I/
O read mode) structure
8M: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two I/O read mode) structure or 2,097,152 x 4 bits (four I/
O read mode) structure
•
•
•
Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
•
High Performance
- Fast read
- 1 I/O: 40MHz with 8 dummy cycles (30pF+1TTL Load)
- 2 I/O: 40MHz with 4 dummy cycles (30pF+1TTL Load), equivalent to 80MHz
- 4 I/O: 33MHz with 6 dummy cycles (30pF+1TTL Load), equivalent to 132MHz
- Fast program time: 2ms(typ.) and 7ms(max.)/page (256-byte per page)
- Byte program time: 30us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 90ms (typ.)/sector (4K-byte per sector); 0.8s(typ.) /block (32K-byte per block); 1.5s(typ.) /block
(64K-byte per block); 7.5s(typ.) /chip for 4M; 15s(typ.) /chip for 8M
Low Power Consumption
•
- Low active read current: 12mA(max.) at 40MHz, 6mA(max.) at 25MHz
- Low active erase/programming current: 22mA (max.)
- Low standby current: 5uA (max.)
•
•
•
Deep Power Down: 5uA(max.)
Typical 100,000 erase/program cycles
10 years data retention
SOFTWARE FEATURES
•
Input Data Format
- 1-byte Command code
•
Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instruc-
tions
- Additional 512-bit secured OTP for unique identifier
Auto Erase and Auto Program Algorithm
•
Automatically erases and verifies data at selected sector or block
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
-
-
•
•
Status Register Feature
Electronic Identification
JEDEC 1-byte manufacturer ID and 2-byte device ID
-
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- RES command for 1-byte Device ID
- Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID
HARDWARE FEATURES
•
•
•
•
•
•
SCLK Input
Serial clock input
SI/SIO0
-
Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
SO/SIO1
-
Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
WP#/SIO2
-
Hardware write protection or serial data Input/Output for 4 x I/O read mode
RESET#/HOLD#/SIO3
-
Hardware Reset/HOLD/Serial input & Output for 4 x I/O read mode, the pin defaults to be RESET#
PACKAGE
-
- 8-land USON (4x4mm) for 4M/8M
8-pin SOP (150mil) for 4M/8M
- All Pb-free devices are RoHS Compliant
-
P/N: PM1394
REV. 1.0, MAR. 09, 2009
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MX25U4035
MX25U8035
GENERAL DESCRIPTION
The MX25U4035 are 4,194,304 bit serial Flash memory, which is configured as 524,288 x 8 internally. When it is in
two or four I/O read mode, the structure becomes 2,097,152 bits x 2 or 1,048,576 bits x 4. The MX25U8035 are 8,388,608
bit serial Flash memory, which is configured as 1,048,576 x 8 internally. When it is in two or four I/O read mode, the
structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. When it is in two or four I/O read mode, the structure
becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25U4035/MX25U8035 feature a serial peripheral inter-
face and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in-
put and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and RESET#/HOLD# pin become
SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U4035/MX25U8035 provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte),
block (32K-byte), or block (64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 5uA DC current.
The MX25U4035/MX25U8035 utilizes MXIC's proprietary memory cell, which reliably stores memory contents even
after 100,000 program and erase cycles.
Table 1. Additional Feature Comparison
Protection and
Read Performance
Identifier
Additional
Features
Security
Flexible
Block
Protection
(BP0-BP3)
512-bit
secured
OTP
2 I/O
4 I/O
RES
REMS
REMS2
REMS4
RDID
Part
Name
Read
Read
(command: (command: (command: (command: (command:
(75 MHz) (75 MHz)
AB hex)
33 (hex)
34 (hex)
90 hex)
EF hex)
DF hex)
9F hex)
C2 33 (hex) C2 33 (hex) C2 33 (hex) C2 25 33
MX25U4035
V
V
V
V
V
V
V
V
(if ADD=0) (if ADD=0) (if ADD=0) (hex)
C2 34 (hex) C2 34 (hex) C2 34 (hex) C2 25 34
(if ADD=0) (if ADD=0) (if ADD=0) (hex)
MX25U8035
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MX25U8035
PIN CONFIGURATIONS
8-LAND USON (4x4mm)
8-PIN SOP (150mil)
1
2
3
4
VCC
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
8
7
6
5
RESET#/HOLD#/SIO3
SCLK
RESET#/HOLD#/SIO3
SCLK
SI/SIO0
SI/SIO0
PACKAGE OPTIONS
PIN DESCRIPTION
4M
V
V
8M
V
V
SYMBOL DESCRIPTION
150mil 8-SOP
4x4mm USON
CS#
Chip Select
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SI/SIO0
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SO/SIO1
SCLK
Clock Input
Write protection: connect to GND or
WP#/SIO2 Serial Data Input & Output (for 4xI/O
read mode)
RESET#/HOLD# or Serial Data Input
RESET#/
& Output (for 4xI/O read mode)
HOLD#/SIO3
(default RESET# for Single & Daul I/O)
VCC
GND
+ 1.8V Power Supply
Ground
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BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Data
Register
SI/SIO0
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
Mode
Logic
WP#/SIO2
RESET#/
HOLD#/SIO3
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
SO/SIO1
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DATA PROTECTION
The MX25U4035/MX25U8035 is designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transition. During power up the device automatically
resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific command sequences.
•
•
Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase 32KB (BE32K) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
Advanced Security Features: there are some protection and securuity features which protect content from inad-
vertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
If the system goes into four I/O read mode, the feature of HPM will be disabled.
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Table 2. Protected Area Sizes
Status bit
Protect Level
BP3 BP2 BP1 BP0
4Mb
8Mb
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (none)
0 (none)
1 (1 block, 1/8 area, block#7)
2 (2 blocks, 1/4 area, block#6-7)
3 (4 blocks, 1/2 area, block#4-7)
4 (8 blocks, ALL)
1 (1 block, 1/16 area, block#15)
2 (2 blocks, 1/8 area, block#14-15)
3 (4 blocks, 1/4 area, block#12-15)
4 (8 blocks, 1/2 area, block#8-15)
5 (16 blocks, ALL)
5 (8 blocks, ALL)
6 (8 blocks, ALL)
6 (16 blocks, ALL)
7 (8 blocks, ALL)
7 (16 blocks, ALL)
8 (none)
8 (none)
9 (1 block, 1/8 area, block#0)
10 (2 blocks, 1/4 area, block#0-1)
11 (4 blocks, 1/2 area, block#0-3)
12 (8 blocks, ALL)
9 (1 block, 1/16 area, block#0)
10 (2 blocks, 1/8 area, block#0-1)
11 (4 blocks, 1/4 area, block#0-3)
12 (8 blocks, 1/2 area, block#0-7)
13 (16 blocks, ALL)
13 (8 blocks, ALL)
14 (8 blocks, ALL)
14 (16 blocks, ALL)
15 (8 blocks, ALL)
15 (16 blocks, ALL)
II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting
device unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512-bit
secured OTP definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and go-
ing through normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security
register bit definition and table of "512-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit se-
cured OTP mode, array access is not allowed.
Table 3. 512-bit Secured OTP Definition
Address range
xxxx00~xxxx0F
xxxx10~xxxx3F
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
128-bit
384-bit
Determined by customer
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MX25U8035
Memory Organization
Table 4-1. Memory Organization (4Mb)
Block
(64KB)
Block
(32KB)
Sector
Address Range
07F000h 07FFFFh
(4KB)
127
:
15
|
7
6
5
4
3
2
1
:
:
14
112
111
:
96
95
:
80
79
:
64
63
:
48
47
:
32
31
:
070000h
06F000h
:
060000h
05F000h
:
050000h
04F000h
:
040000h
03F000h
:
030000h
02F000h
:
020000h
01F000h
:
070FFFh
06FFFFh
:
060FFFh
05FFFFh
:
050FFFh
04FFFFh
:
040FFFh
03FFFFh
:
030FFFh
02FFFFh
:
020FFFh
01FFFFh
:
13
|
12
11
|
10
9
|
8
7
|
6
5
|
4
3
|
2
16
15
:
2
1
010000h
00F000h
:
002000h
001000h
000000h
010FFFh
00FFFFh
:
002FFFh
001FFFh
000FFFh
1
|
0
0
0
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MX25U8035
Table 4-2. Memory Organization (8Mb)
Block
(64KB)
Block
(32KB)
Sector
(4KB)
255
:
Address Range
0FF000h 0FFFFFh
31
|
15
14
13
12
11
10
9
:
:
30
240
239
:
224
223
:
208
207
:
192
191
:
176
175
:
160
159
:
0F0000h
0EF000h
:
0E0000h
0DF000h
:
0D0000h
0CF000h
:
0C0000h
0BF000h
:
0B0000h
0AF000h
:
0A0000h
09F000h
:
0F0FFFh
0EFFFFh
:
0E0FFFh
0DFFFFh
:
0D0FFFh
0CFFFFh
:
0C0FFFh
0BFFFFh
:
0B0FFFh
0AFFFFh
:
0A0FFFh
09FFFFh
:
29
|
28
27
|
26
25
|
24
23
|
22
21
|
20
19
|
18
144
143
:
090000h
08F000h
:
090FFFh
08FFFFh
:
17
|
8
16
128
127
:
080000h
07F000h
:
080FFFh
07FFFFh
:
15
|
7
14
112
111
:
070000h
06F000h
:
070FFFh
06FFFFh
:
13
|
6
12
96
95
:
060000h
05F000h
:
060FFFh
05FFFFh
:
11
|
5
10
80
79
:
050000h
04F000h
:
050FFFh
04FFFFh
:
9
|
4
8
64
63
:
040000h
03F000h
:
040FFFh
03FFFFh
:
7
|
3
6
48
47
:
030000h
02F000h
:
030FFFh
02FFFFh
:
5
|
2
4
32
31
:
020000h
01F000h
:
020FFFh
01FFFFh
:
3
|
1
2
16
15
:
2
1
010000h
00F000h
:
002000h
001000h
000000h
010FFFh
00FFFFh
:
002FFFh
001FFFh
000FFFh
1
|
0
0
0
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MX25U4035
MX25U8035
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as Figure 1. "Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS,
REMS2 and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data
being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE,
CE, PP, 4PP, CP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary;
otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
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COMMAND DESCRIPTION
Table 5. Command Set
RDID
(read
identific-
ation)
2READ (2
RDSR
WRSR
FAST READ
(fast read
data)
Command WREN (write WRDI (write
READ (read
x I/O read
command)
Note1
(read status (write status
(byte)
enable)
disable)
data)
register)
05 (hex)
register)
01 (hex)
Values
1st byte
2nd byte
06 (hex)
04 (hex)
9F (hex)
03 (hex)
AD1
(A23-A16)
0B (hex)
AD1
BB (hex)
ADD(2)
AD2
(A15-A8)
AD3
ADD(2) &
Dummy(2)
3rd byte
AD2
4th byte
5th byte
AD3
(A7-A0)
Dummy
sets the
(WEL) write (WEL) write
resets the
outputs
JEDEC
to read out to write new n bytes read n bytes read n bytes read
the values values of out until CS# out until CS# out by 2 x I/
enable latch enable latch ID: 1-byte of the status the status
goes high
goes high
O until CS#
goes high
Action
bit
bit
Manufact-
urer ID &
2-byte Device
ID
register
register
CP
4READ (4
x I/O read
command)
4PP (quad
page
program)
Command
(byte)
SE (sector BE 32K (block BE (block
CE (chip
erase)
PP (page (continuously
erase)
erase 32K)
erase)
program)
program
mode)
1st byte
2nd byte
EB (hex)
ADD(4) &
Dummy(4)
ADD(4))
38 (hex)
AD1
20 (hex)
AD1
52 (hex)
AD1
D8 (hex) 60 or C7 (hex) 02 (hex)
AD (hex)
AD1
AD1
AD1
3rd byte
4th byte
AD2
AD3
AD2
AD3
AD2
AD3
AD2
AD3
AD2
AD3
n bytes read quad input to erase the to erase the to erase the
to erase
to program continously
out by 4 x I/ to program
O until CS# the selected
selected
sector
selected 32K
block
selected
block
whole chip the selected
page
program
whole
goes high
page
chip, the
Action
address is
automatically
increase
RDP
(Release
REMS (read
electronic
REMS2 (read REMS4 (read ENSO (enter EXSO (exit
Command
(byte)
DP (Deep
RES (read
ID for 2x I/O ID for 4x I/O
secured
OTP)
secured
OTP)
power down) from deep electronic ID) manufacturer
mode)
mode)
power down)
& device ID)
1st byte
2nd byte
3rd byte
4th byte
B9 (hex)
AB (hex)
AB (hex)
90 (hex)
EF (hex)
DF (hex)
B1 (hex)
C1 (hex)
x
x
x
x
x
x
x
x
x
ADD (Note 2) ADD (Note 2) ADD (Note 2)
enters deep release from to read out
power down deep power 1-byte Device Manufacturer Manufacturer Manufacturer the 512-bit
mode down mode ID
output the output the output the
to enter
to exit the
512-bit
ID & Device ID & Device ID & Device secured OTP secured OTP
ID ID ID mode mode
Action
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ESRY
(enable SO
to output RY/ to output RY/
BY#)
70 (hex)
DSRY
(disable SO
RDSCUR
(read security (write security
WRSCUR
Command
(byte)
HDE (HOLD#
Enable)
register)
2B (hex)
register)
2F (hex)
BY#)
80 (hex)
1st byte
2nd byte
3rd byte
4th byte
AA (hex)
to read value to set the lock- to enable SO to disable SO
to enable
HOLD# pin
function
of security
register
down bit as
to output RY/ to output RY/
"1" (once lock- BY# during CP BY# during CP
down, cannot
be update)
mode
mode
Action
Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different from
1 x I/O condition.
Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hid-
den mode.
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(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
CP, SE, BE32K, BE, CE, and WRSR, which are intended to change the device content, should be set every time af-
ter the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see
Figure 10)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see
Figure 11)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Quad Page Program (4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase 32KB (BE32K) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
- Continuously program mode (CP) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 25(hex) as the first-byte device ID, and the individual device ID
of second-byte ID are listed as table of "ID Definitions". (see table 7)
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→ 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (see Figure 12)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
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(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (see Figure 13)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
not affect value of WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, volatile bits, indicate the protected area(as
defined in table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase(CE) instructions (only if Block Protect bits (BP2:BP0)
set to 0, the CE instruction can be executed).
The BP3, BP2, BP1, BP0 bits dfault to be "1". Which is protected.
QE bit. The Quad Enable (QE) bit, volatile bit, performs Quad when it is reset to "0" (factory default) to enable WP#
or is set to "1" to enable Quad SIO2 and SIO3.
SRWD bit. The Status Register Write Disable (SRWD) bit, volatile bit, is operated together with Write Protection (WP#/
SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only.
The SRWD bit defaults to be "0".
Status Register
bit7
bit6
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1=Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
1=write
operation
1=status
register write
disable
(note 1)
(note 1)
(note 1)
(note 1)
enable
operation
Note 1: see the table 2 "Protected Area Size".
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(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the pro-
tected area of memory (as shown in table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the statur register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI-> CS# goes high. (see Figure 14)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 6. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
Software protection
mode (SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
WP#=0, SRWD bit=1
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
-
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
-
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software pro-
tected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
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Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O read mode, the feature of HPM will be disabled.
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on
SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure 15)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code→3-
byte address on SI→1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can
use CS# to high at any time during data out. (see Figure 16)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(8) 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low sending 2READ instruction 24-bit address inter-
→
→
leave on SIO1 & SIO0 4-bit dummy cycle on SIO1 & SIO0 data out interleave on SIO1 & SIO0 to end 2READ
→
→
→
operation can use CS# to high at any time during data out (see Figure 17 for 2 x I/O Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
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on the Program/Erase/Write Status Register current cycle.
(9) 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before seding the 4READ instruction.The address is latched on rising edge of SCLK,
and data of every four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The ad-
dress counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the fol-
lowing address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low
sending 4READ instruction
24-bit address in-
→
→
terleave on SIO3, SIO2, SIO1 & SIO0
6 dummy cycles
data out interleave on SIO3, SIO2, SIO1 & SIO0
to
→
→
→
end 4READ operation can use CS# to high at any time during data out (see Figure 18 for 4 x I/O Read Mode Tim-
ing Waveform).
Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low sending
→
4 READ instruction 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance toggling bit
→
→
P[7:0] 4 dummy cycles data out still CS# goes high
CS# goes low (reduce 4 Read instruction) 24-bit ran-
→
→
→
→
dom access address (see figure 19 for 4x I/O read enhance performance mode timing waveform).
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like-
wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from
performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see table of memory organization) is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high. (see Figure 23)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sec-
tor.
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(11) Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE32K). Any address of the block (see table of memory organization) is
a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the latest
eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code→ 3-byte address
on SI→ CS# goes high. (see Figure 24)
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Block Erase cycle is in progress. The WIP sets 1 during the
tBE32K timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (tBE32K) instruction will not be executed on the
block.
(12) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see table of memory organization) is a valid ad-
dress for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of ad-
dress byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI
→CS# goes high. (see Figure 25)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Block Erase cycle is in progress. The WIP sets 1 during the tBE
timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block
is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block.
(13) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. (see Fig-
ure 26)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip
is protected by BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed
when BP2, BP1, BP0 all set to "0".
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(14) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device pro-
grams only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-
A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are
not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of
the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the
last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are
sent to the device, the data is programmed at the requested address of the page without effect on other address of
the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high. (see Figure 20)
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex-
ecuted.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(15) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before
sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3 as address and data input, which can improve programer performance and the effectiveness of application
of lower clock less than 20MHz. For system with faster clock, the Quad page program cannot provide more actual
favors, because the required internal page program time is far more than the time data flows in. Therefore, we sug-
gest that while executing this command (especially during sending data), user can slow the clock speed down to
20MHz below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→sending 4PP instruction code→3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. (see Figure 21)
(16) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address
after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction
must execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction.
CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of
data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address
range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If
more than two bytes data are input, the additional data will be ignored and only two byte data are valid. The CP
program instruction will be ignored and not affect the WEL bit if it is applied to a protected memory area. Any byte to
be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unpro-
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tected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP
mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction.
During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cy-
cle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# high to low-> sending CP instruction code→ 3-byte address on
SI→ Data Byte on SI→CS# goes high to low→ sending CP instruction......→ last desired byte programmed or send-
ing Write Disable (WRDI) instruction to end CP mode-> sending RDSR instruction to verify if CP mode is ended. (see
Figure 22 of CP mode timing waveform)
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is
enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indi-
cates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to
disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the
ESRY/DSRY command are not accepted unless the completion of CP mode.
(17) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-
tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→CS# goes high. (see Fig-
ure 27)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode.
(18) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in Table 10.AC Characteristics. Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The
RDP instruction is only for releasing from Deep Power Down Mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions on next page. This is not the same as RDID instruction. It is not recommended to use for new design.
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For new design, please use RDID instruction.
The sequence is shown as Figure 28,29. Even in Deep power-down mode, the RDP and RES are also allowed to
be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current
program/erase/write cycle in progress.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
(19) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)
The REMS, REMS2 & REMS4 instruction is an alternative to the Release from Power-down/Device ID instruction
that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS4 instruction is rec-
ommended to use for 4 I/O identification and REMS2 instruction is recommended to use for 2 I/O identification.
The REMS, REMS2 & REMS4 instruction is very similar to the Release from Power-down/Device ID instruction. The
instruction is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" or "DFh"followed by
two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device
ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in figure 30. The Device
ID values are listed in Table 7 of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will
be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously,
alternating from one to the other. The instruction is completed by driving CS# high.
Table 7. ID Definitions
Command Type
MX25U4035
memory type
MX25U8035
memory
type
25
electronic ID
34
memory
density
33
memory
density
34
manufactuer ID
C2
manufacturer ID
RDID (JEDEC ID)
25
electronic ID
33
C2
RES
manufacturer ID
C2
device ID
33
manufacturer ID device ID
C2 34
REMS/REMS2/
REMS4
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(20) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 512-bit secured OTP mode. The additional 512-bit secured OTP
is independent from main array, which may use to store unique serial number for system identifier. After entering the
Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The
Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once se-
curity OTP is lock down, only read related commands are valid.
(21) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 512-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
(22) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ send ing RDSCUR instruction →Security Regis-
ter data out on SO→ CS# goes high.
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or
not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for custom-
er lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512-bit Secured OTP
area cannot be update any more. While it is in 512-bit secured OTP mode, main array access is not allowed.
Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
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Table 8. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Continuously
Program mode
(CP mode)
LDSO
(indicate if
lock-down
Secrured OTP
indicator bit
x
x
x
x
x
0 = not lock-
down
1 = lock-down
(cannot
program/erase
OTP)
0=normal
Program mode
1=CP mode
(default=0)
0 = non-factory
lock
reserved
reserved
reserved
reserved
reserved
1 = factory
lock
volatile bit volatile bit volatile bit
volatile bit
volatile bit
volatile bit non-volatile bit non-volatile bit
(23) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 512-bit Secured OTP area. Once the LDSO bit is set to "1", the Se-
cured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→sending WRSCUR instruction→ CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
(24) HOLD# pin function enable (HDE)
The HDE instruction is for enabling the HOLD# pin function. The RESET#/HOLD#/SIO# pin defaults to be as RE-
SET# pin function. When HDE instruction is writing to the Flash, and then pin is set to be HOLD# pin. The HOLD
mode will continue until power off. The pin is RESET# pin while power on stage. The HDE instruction is invalid dur-
ing deep power down mode.
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POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
-40°C to 85°C
Ambient Operating Temperature
Storage Temperature
-65°C to 150°C
-0.5V to VCC+0.5V
-0.5V to VCC+0.5V
-0.5V to VCC+0.5V
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V to VCC or -0.5V to GND for period up to 20ns.
Figure 3. Maximum Positive Overshoot Waveform
Figure 2.Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
-0.5V
VCC
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL PARAMETER
CIN Input Capacitance
COUT Output Capacitance
MIN.
TYP
MAX.
UNIT
pF
CONDITIONS
VIN = 0V
6
8
pF
VOUT = 0V
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Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level
Output timing referance level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 5. OUTPUT LOADING
25K ohm
DEVICE UNDER
TEST
+1.8V
CL
25K ohm
CL=30pF Including jig capacitance
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Table 9. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V)
°
°
SYMBOL PARAMETER
NOTES
MIN.
TYP.
MAX.
UNITS TEST CONDITIONS
VCC = VCC Max,
uA
ILI
Input Load Current
1
± 1
VIN = VCC or GND
VCC = VCC Max,
uA
ILO
Output Leakage Current
1
1
± 1
5
VIN = VCC or GND
VIN = VCC or GND,
CS# = VCC
ISB1 VCC Standby Current
1
1
uA
Deep Power-down
Current
VIN = VCC or GND,
CS# = VCC
ISB2
5
uA
f=40MHz,
fQ=33MHz (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
12
6
mA
ICC1 VCC Read
1
1
f=25MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
VCC Program Current
Program in Progress,
CS# = VCC
ICC2
(PP)
15
15
22
22
mA
VCC Write Status
ICC3
Program status register in
mA
Register (WRSR) Current
progress, CS#=VCC
VCC Sector/Block (32K,
ICC4 64K) Erase Current
(SE/BE/BE32K)
Erase in Progress,
CS#=VCC
1
1
15
15
22
22
mA
VCC Chip Erase Current
Erase in Progress,
CS#=VCC
ICC5
(CE)
mA
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.3VCC
VCC+0.4
0.2
V
V
0.7VCC
V
V
IOL = 100uA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
Notes :
1. Typical values at VCC = 1.8V, T = 25 C. These currents are valid for all product versions (package and speeds).
°
2. Typical value is calculated by simulation.
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Table 10. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V)
°
°
Symbol Alt. Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
fC FAST_READ, PP, SE, BE, CE, DP, RES,RDP
WREN, WRDI, RDID, RDSR, WRSR
fR Clock Frequency for READ instructions
fT Clock Frequency for 2READ instructions
40
fSCLK
fRSCLK
fTSCLK
1KHz
MHz
(Condition:30pF)
1KHz
1KHz
25
40
33
MHz
MHz
fQ Clock Frequency for 4READ instructions
1KHz
MHz
(Condition:30pF)
25MHz
16
12
10
16
12
10
0.1
0.1
16
12
8
10
5
3
2
5
ns
ns
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
tCH(1) tCLH Clock High Time
33MHz
40MHz
25MHz
33MHz
40MHz
tCL(1)
tCLL Clock Low Time
Clock Rise Time (3) (peak to peak)
tCLCH(2)
tCHCL(2)
Clock Fall Time (3) (peak to peak)
25MHz
33MHz
40MHz
CS# Active Setup Time
(relative to SCLK)
tSLCH tCSS
tCHSL
CS# Not Active Hold Time (relative to SCLK)
25MHz
tDVCH tDSU Data In Setup Time
33MHz
40MHz
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
25MHz
33MHz
40MHz
16
12
8
10
30
CS# Active Hold Time
(relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
tSHSL(3) tCSH CS# Deselect Time
25MHz
33MHz
40MHz
20
19
19
10
9
tSHQZ(2) tDIS Output Disable Time
Loading: 30pF
Single I/O
Multi-I/O
Loading: 15pF
Loading: 30pF
Loading: 15pF
tCLQV
tV Clock Low to Output Valid
12
10
tCLQX
tWHSL
tSHWL
tDP(2)
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
0
20
100
CS# High to Deep Power-down Mode
10
CS# High to Standby Mode without Electronic
Signature Read
CS# High to Standby Mode with Electronic Signature
Read
tRES1(2)
tRES2(2)
8.8
us
us
8.8
tRESET
tRCR
tRCP
tRCE
tREHZ
Pulse width of RESET
Recovery Time to Read
Recovery Time to Program
Recovery Time to Erase
Time from RESET to High-Z output
100
ns
ns
us
ms
ns
100
10
1
100
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Symbol Alt. Parameter
Min.
Typ.
Max.
200
300
7
220
1.6
3
Unit
ns
us
ms
ms
s
s
s
s
tW
tBP
Write Status Register Cycle Time
Byte-Program
30
2
tPP
tSE
tBE32
tBE
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase (32KB) Cycle Time
Block Erase (64KB) Cycle Time
90
0.8
1.5
7.5
15
4Mb
8Mb
13
25
tCE
Chip Erase Cycle Time
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Value guaranteed by characterization, not 100% tested in production.
3. tSHSL=30ns for read instruction, tSHSL=50ns for Write/Erase/Program instruction.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 4, 5.
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Timing Analysis
Figure 6. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 7. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
SO
tCLQX
LSB
tQLQH
tQHQL
ADDR.LSB IN
SI
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Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
Figure 9. Hardware Reset Timing
tRESET
RESET#
tRCR
tRCP
tRCE
CS#
SCLK
SO
tREHZ
SI
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Figure 10. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06
SI
High-Z
SO
Figure 11. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04
SI
High-Z
SO
Figure 12. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9F
Manufacturer Identification
Device Identification
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
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Figure 13. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 14. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCLK
command
01
Status
Register In
SI
7
6
5
4
3
2
0
1
MSB
High-Z
SO
Figure 15. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
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Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0B
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Configurable
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
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Figure 17. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
9
10 11
18 19 20 21 22 23 24 25 26 27
SCLK
4 dummy
cycle
8 Bit Instruction
12 BIT Address
Data Output
data
address
BB(hex)
dummy
dummy
SI/SIO0
bit6, bit4, bit2...bit0, bit6, bit4....
bit22, bit20, bit18...bit0
High Impedance
address
bit23, bit21, bit19...bit1
data
SO/SIO1
bit7, bit5, bit3...bit1, bit7, bit5....
Figure 18. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
4 dummy
cycles
8 Bit Instruction
6 Address cycles
Data Output
Performance
enhance
indicator (Note)
data
address
P4 P0
P5 P1
P6 P2
P7 P3
EB(hex)
SI/SIO0
bit4, bit0, bit4....
bit20, bit16..bit0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
WP#/SIO2
NC/SIO3
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
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Figure 19. 4 x I/O Read enhance performance Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
4 dummy
cycles
8 Bit Instruction
6 Address cycles
Data Output
Performance
enhance
indicator (Note)
data
address
P4 P0
P5 P1
P6 P2
P7 P3
EB(hex)
SI/SIO0
bit4, bit0, bit4....
bit20, bit16..bit0
High Impedance
High Impedance
High Impedance
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
WP#/SIO2
NC/SIO3
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
CS#
n+1
...........
n+7......n+9 ........... n+13
...........
SCLK
4 dummy
cycles
6 Address cycles
Data Output
Performance
enhance
indicator (Note)
data
address
P4 P0
P5 P1
P6 P2
P7 P3
SI/SIO0
bit4, bit0, bit4....
bit20, bit16..bit0
address
bit21, bit17..bit1
data
bit5 bit1, bit5....
SO/SIO1
WP#/SIO2
NC/SIO3
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Note: Performance enhance mode, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling), ex: A5, 5A, 0F
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
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Figure 20. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
Figure 21. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
10 11 12 13 14 15 16 17 18 19 20 21
Data Data Data Data
0
1
2
3
4
5
6
7
8
9
SCLK
Command
38
6 Address cycle
Byte 1 Byte 2 Byte 3 Byte 4
16 12
8
9
4
0
20
4
0
4
0
4
0
4
0
SI/SIO0
21 17 13
5
6
7
1
2
3
SO/SIO1
WP#/SIO2
NC/SIO3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
22 18 14 10
23 19 15 11
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Figure 22. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
20 2122 23 24
0
1
30 31 31 32
47 48
0
7
7
8
0
6
7 8
0
1
6 7 8 9
SCLK
Command
AD (hex)
data in
Byte n-1, Byte n
Valid
Command (1)
data in
Byte 0, Byte1
04 (hex)
05 (hex)
24-bit address
SI
high impedance
status (2)
S0
Note: (1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR com-
mand (05 hex), and RDSCUR command (2B hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and
CS# goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI)
command (04 hex) may achieve it and then it is recommended to send RDSCUR command (2B hex) to verify
if CP mode is ended
Figure 23. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20
24 Bit Address
SI
7
6
2
1
0
MSB
Note: SE command is 20(hex).
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Figure 24. Block Erase 32KB (BE32K) Sequence (Command 52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
52
24 Bit Address
2
SI
23 22
MSB
0
1
Note: BE32K command is 52(hex).
Figure 25. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
D8
24 Bit Address
2
SI
23 22
MSB
0
1
Note: BE command is D8(hex).
Figure 26. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60 or C7
Note: CE command is 60(hex) or C7(hex).
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Figure 27. Deep Power-down (DP) Sequence (Command B9)
CS#
t
DP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9
Stand-by Mode
Deep Power-down Mode
Figure 28. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
AB
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
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Figure 29. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
t
RES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
AB
High-Z
SO
Deep Power-down Mode
Stand-by Mode
Figure 30. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
90
2 Dummy Bytes
SI
15 14 13
3
2
1
0
High-Z
SO
CS#
47
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
ADD (1)
7
6
5
4
3
2
0
1
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
X
SO
MSB
MSB
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
(2) Instruction is either 90(hex) or EF(hex) or DF(hex).
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Figure 31. Power-up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
tVSL
Device is fully
accessible
time
Note: VCC (max.) is 2.0V and VCC (min.) is 1.65V.
Table 11. Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
50
us
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
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RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Figure A. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVSL
tSHSL
tVR
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
tVR
tVSL
Parameter
VCC Set Up Time
VCC (min) to CS# low
Notes
Min.
20
50
Max.
500000
Unit
us/V
us
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
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ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Min.
TYP. (1)
Max. (2)
200
220
1.6
3
UNIT
Write Status Register Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
ns
ms
s
90
0.8
1.5
s
4M
8M
7.5
13
s
Chip Erase Cycle Time
15
25
s
Byte Program Time (via page program command)
Page Program Cycle Time
30
300
7
us
ms
cycles
2
Erase/Program Cycle
100,000
Note:
1. Typical program and erase time assumes the following conditions: 25 C, 1.8V, and checker board pattern.
°
2. Under worst conditions of 85 C and 1.65V.
°
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
4. The maximum chip programming time is evaluated under the worst conditions of 0C, VCC=1.8V, and 100K cycle
with 90% confidence level.
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
2 VCCmax
VCC + 1.0V
+100mA
-1.0V
Current
-100mA
Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time.
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ORDERING INFORMATION
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (uA)
CLOCK
(MHz)
PART NO.
TEMPERATURE PACKAGE
Remark
8-SOP
(150mil)
8-SOP
(150mil)
8-USON
(4x4mm)
8-USON
(4x4mm)
MX25U4035MI-25G*
MX25U8035MI-25G
MX25U4035ZUI-25G*
MX25U8035ZUI-25G
40
12
12
12
12
5
5
5
5
-40 C~85 C
Pb-free
Pb-free
Pb-free
Pb-free
°
°
40
-40 C~85 C
° °
40
-40 C~85 C
° °
40
-40 C~85 C
° °
* Preliminary Information
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MX25U4035
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PART NAME DESCRIPTION
MX 25
U
4035
M
I
25 G
OPTION:
G: Pb-free
SPEED:
25: 40MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M: 150mil 8-SOP
ZU: USON
DENSITY & MODE:
4035: 4Mb
8035: 8Mb
TYPE:
U: 1.8V
DEVICE:
25: Serial Flash
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PACKAGE INFORMATION
P/N: PM1394
REV. 1.0, MAR. 09, 2009
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MX25U8035
P/N: PM1394
REV. 1.0, MAR. 09, 2009
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REVISION HISTORY
Revision No. Description
Page
P5
Date
MAR/09/2009
1.0
1. Removed title of "Advanced Information"
2. Revised 4KB erase time
3. Modified erase/program cycle to be typical 100,000 times
4. Revised QE bit attribute from non-volatile to volatile
P48
P1,48
P18
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Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substan-
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injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
Copyright© Macronix International Co. Ltd. 2008~2009. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX
Logo, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands
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companies.
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M
I
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54
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