MX25U5121EMI14G [Macronix]
512K-BIT [x 1/x 4] CMOS MXSMIOï SERIAL FLASH MEMORY;
| 型号： | MX25U5121EMI14G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 512K-BIT [x 1/x 4] CMOS MXSMIOï SERIAL FLASH MEMORY |
| 文件： | 总42页 (文件大小：951K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
MX25U5121E, MX25U1001E
DATASHEET
P/N: PM1980
REV. 0.00, OCT. 11, 2013
1
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Contents
1. FEATURES ..............................................................................................................................................................4
GENERAL..................................................................................................................................................4
PERFORMANCE.......................................................................................................................................4
SOFTWARE FEATURES...........................................................................................................................4
HARDWARE FEATURES..........................................................................................................................5
2. GENERAL DESCRIPTION .....................................................................................................................................5
3. PIN CONFIGURATIONS .........................................................................................................................................6
8-LAND USON (2x3mm) ...........................................................................................................................6
4. PIN DESCRIPTION..................................................................................................................................................6
5. BLOCK DIAGRAM...................................................................................................................................................7
6. MEMORY ORGANIZATION.....................................................................................................................................8
Table 1. Memory Organization (512Kb).....................................................................................................8
Table 2. Memory Organization (1Mb) ........................................................................................................8
7. DEVICE OPERATION..............................................................................................................................................9
Figure 1. Serial Modes Supported................................................................................................................9
8. HOLD FEATURE....................................................................................................................................................10
Figure 2. Hold Condition Operation ...........................................................................................................10
9. DATA PROTECTION.............................................................................................................................................. 11
Table 3. Protected Area Sizes................................................................................................................. 11
10. COMMAND DESCRIPTION.................................................................................................................................12
Table 4. Command Set ............................................................................................................................12
10-1. Write Enable (WREN)..............................................................................................................................13
10-2. Write Disable (WRDI) ..............................................................................................................................13
10-3.ꢀ ReadꢀIdentificationꢀ(RDID).......................................................................................................................13
Tableꢀ5.ꢀIDꢀDefinitionsꢀ.............................................................................................................................13
10-4. Read Status Register (RDSR).................................................................................................................14
Table 6. Status Register...........................................................................................................................14
10-5. Write Status Register (WRSR) ................................................................................................................15
Table 7. Protection Modes ......................................................................................................................15
10-6. Read Data Bytes (READ) ........................................................................................................................16
10-7. Read Data Bytes at Higher Speed (FAST_READ) ..................................................................................16
10-8. Dual Read Mode (DREAD)......................................................................................................................16
10-9. 4 x I/O Read Mode (4READ) ...................................................................................................................16
10-10. Sector Erase (SE)....................................................................................................................................17
10-11. Block Erase (BE) .....................................................................................................................................17
10-12. Chip Erase (CE).......................................................................................................................................17
10-13. Page Program (PP) .................................................................................................................................18
10-14. Deep Power-Down (DP) ..........................................................................................................................18
10-15. Release from Deep Power-Down (RDP) .................................................................................................18
11. POWER-ON STATE .............................................................................................................................................19
P/N: PM1980
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figureꢀ3.ꢀProgram/Eraseꢀflowꢀwithꢀreadꢀarrayꢀdata ....................................................................................20
12. ELECTRICAL SPECIFICATIONS........................................................................................................................21
12-1. ABSOLUTE MAXIMUM RATINGS ..........................................................................................................21
Figure 4. Maximum Negative Overshoot Waveform...................................................................................21
12-2. CAPACITANCE TA = 25°C, f = 1.0 MHz..................................................................................................21
Figure 5. Maximum Positive Overshoot Waveform ....................................................................................21
Figure 6. Input Test Waveforms and Measurement Level ..........................................................................22
Figure 7. Output Loading............................................................................................................................22
Table 8. DC CHARACTERISTICS...........................................................................................................23
Table 9. AC CHARACTERISTICS ..........................................................................................................24
13. Timing Analysis..................................................................................................................................................25
Figure 8. Serial Input Timing.......................................................................................................................25
Figure 9. Output Timing..............................................................................................................................25
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1........................................26
Figure 11. Write Enable (WREN) Sequence (Command 06)......................................................................26
Figure 12. Write Disable (WRDI) Sequence (Command 04)......................................................................26
Figureꢀ13.ꢀReadꢀIdentificationꢀ(RDID)ꢀSequenceꢀ(Commandꢀ9F) ..............................................................27
Figure 14. Read Status Register (RDSR) Sequence (Command 05) ........................................................28
Figure 15. Write Status Register (WRSR) Sequence (Command 01).......................................................28
Figure 16. Read Data Bytes (READ) Sequence (Command 03)...............................................................28
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)...........................................29
Figure 18. Dual Read Mode Sequence (Command 3B).............................................................................29
Figure 19. 4 x I/O Read Mode Sequence (Command EB) .........................................................................30
Figure 20. Sector Erase (SE) Sequence (Command 20) ..........................................................................30
Figure 21. Block Erase (BE) Sequence (Command D8 or 52)..................................................................31
Figure 22. Chip Erase (CE) Sequence (Command 60 or C7) ...................................................................31
Figure 23. Page Program (PP) Sequence (Command 02)........................................................................31
Figure 24. Deep Power Down (DP) Sequence (Command B9) .................................................................32
Figure 25. Release from Deep Power Down (RDP) Sequence (Command AB) ........................................32
Figure 26. Power-Up Timing.......................................................................................................................33
Table 10. Power-Up Timing......................................................................................................................33
13-1. INITIAL DELIVERY STATE......................................................................................................................33
14. OPERATING CONDITIONS.................................................................................................................................34
Figure 27. AC Timing at Device Power-Up.................................................................................................34
Figure 28. Power-Down Sequence.............................................................................................................35
15. ERASE AND PROGRAMMING PERFORMANCE..............................................................................................36
17. DATA RETENTION .............................................................................................................................................36
16. LATCH-UP CHARACTERISTICS........................................................................................................................36
18. ORDERING INFORMATION................................................................................................................................37
19. PART NAME DESCRIPTION...............................................................................................................................38
20. PACKAGE INFORMATION..................................................................................................................................39
P/N: PM1980
REV. 0.00, OCT. 11, 2013
3
•ꢀꢀ
Performance
- Normal Read:
- 30MHz
•ꢀꢀ
•ꢀꢀ
InputꢀDataꢀFormat
•ꢀꢀ
•ꢀꢀ
•ꢀꢀ
SingleꢀPowerꢀSupplyꢀOperation
- 1.65 to 2.0 volt for read, erase, and program operations
Latch-upꢀprotectedꢀtoꢀ100mAꢀfromꢀ-1VꢀtoꢀVccꢀ+1V
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
512K-BIT [x 1/x 4] CMOS MXSMIO SERIAL FLASH MEMORY
1M-BIT [x 1/x 4] CMOS MXSMIO SERIAL FLASH MEMORY
1. FEATURES
GENERAL
•ꢀꢀSerialꢀPeripheralꢀInterfaceꢀcompatibleꢀ--ꢀModeꢀ0ꢀandꢀModeꢀ3
• 512Kb: 524,288 x 1 bit structure or 131,072 x 4 bit structure
1Mb: 1,048,576 x 1 bit structure or 262,144 x 4 bit structure
•ꢀꢀ16ꢀEqualꢀSectorsꢀwithꢀ4Kꢀbytesꢀeachꢀ(512Kb)ꢀ
32 Equal Sectors with 4K bytes each (1Mb)
- Any Sector can be erased individually
•ꢀ 1ꢀEqualꢀBlocksꢀwithꢀ64Kꢀbytesꢀeachꢀ(512Kb)
2 Equal Blocks with 64K bytes each (1Mb)
- Any Block can be erased individually
•ꢀꢀProgramꢀCapability
- Byte base
- Page base (32 bytes)
PERFORMANCE
- Fast Read:
- 1 I/O: 70MHz with 8 dummy cycles
- 2 I/O: 70MHz with 8 dummy cycles, equivalent to 140MHz
- 4 I/O: 60MHz with 6 dummy cycles, equivalent to 240MHz
- Fast program time: 360us(typ.) and 1.3ms(max.)/page
- Fast erase time: 120ms (typ.)/sector ; 1.3sec (typ.)/block
LowꢀPowerꢀConsumption
- Low active read current: 5mA(max.) at 30MHz, 10mA(max.) at 70MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 25uA (typ.)
- Deep power down current: 3uA (typ.)
•ꢀꢀꢀTypicalꢀ100,000ꢀerase/programꢀcycles
•ꢀꢀ20ꢀyearsꢀdataꢀretention
SOFTWARE FEATURES
- 1-byte Command code
BlockꢀLockꢀprotection
ꢀ -ꢀTheꢀ BP0~BP1ꢀ statusꢀ bitsꢀ definesꢀ theꢀ sizeꢀ ofꢀ theꢀ areaꢀ toꢀ beꢀ softwareꢀ protectedꢀ againstꢀ Programꢀ andꢀ Eraseꢀ
instructions
•ꢀꢀAutoꢀEraseꢀandꢀAutoꢀProgramꢀAlgorithm
ꢀꢀꢀꢀ-ꢀAutomaticallyꢀerasesꢀandꢀverifiesꢀdataꢀatꢀselectedꢀsector
ꢀꢀꢀꢀ-ꢀAutomaticallyꢀprogramsꢀandꢀverifiesꢀdataꢀatꢀselectedꢀpageꢀbyꢀanꢀinternalꢀalgorithmꢀthatꢀautomaticallyꢀtimesꢀtheꢀ
P/N: PM1980
REV. 0.00, OCT. 11, 2013
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
programꢀpulseꢀwidthsꢀ(Anyꢀpageꢀtoꢀbeꢀprogramedꢀshouldꢀhaveꢀpageꢀinꢀtheꢀerasedꢀstateꢀfirst)
• Status Register Feature
• ElectronicꢀIdentification
- JEDEC 1-byte manufacturer ID and 2-bytes device ID
HARDWARE FEATURES
• SCLK Input
Serial clock input
•ꢀꢀSI/SIO0
-
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
•ꢀꢀSO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
•ꢀꢀWP#/SIO2
- Hardware write protection or Serial Data Input/Output for 4 x I/O read mode
•ꢀꢀHOLD#/SIO3
- Pause the chip without diselecting the chip or Serial Data Input/Output for 4 x I/O read mode
•ꢀꢀꢀPACKAGE
- 8-pin SOP (150mil)
- 8-pin TSSOP (173mil)
- 8-USON (2x3mm)
- All devices are RoHS Compliant and Halogen-free
2. GENERAL DESCRIPTION
The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.
The device provides sequential read operation on the whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fiedꢀpageꢀorꢀsectorꢀlocationsꢀwillꢀbeꢀexecuted.ꢀProgramꢀcommandꢀisꢀexecutedꢀonꢀpageꢀ(32ꢀbytes)ꢀbasis,ꢀandꢀeraseꢀ
command is executes on sector, or block, or whole chip.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in Standby Mode and draws less than 35uA (typical:25uA)
DC current.
The device utilizes Macronix proprietary memory cell, which reliably stores memory contents even after typical
100,000 program and erase cycles.
P/N: PM1980
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5
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
3. PIN CONFIGURATIONS
8-PIN SOP (150mil)
4. PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
Chip Select
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
8
7
6
5
Serial Data Input or Serial Data
Input/Output for 2 x I/O read mode
and 4 x I/O read mode
Serial Data Output or Serial Data
Input/Output for 2 x I/O read mode
and 4 x I/O read mode
HOLD#/SIO3
SCLK
SI/SIO0
SI/SIO0
SO/SIO1
SCLK
8-PIN TSSOP (173mil)
Clock Input
Pause the chip without diselecting the
HOLD#/SIO3 chip or Serial Data Input/Output for
4 x I/O read mode
Hardware write protection or Serial
WP#/SIO2 Data Input/Output for 4 x I/O read
mode
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
8
HOLD#/SIO3
SCLK
7
6
5
SI/SIO0
VCC
GND
+1.8VꢀPowerꢀSupply
Ground
8-LAND USON (2x3mm)
1
2
3
4
VCC
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
HOLD#/SIO3
SCLK
SI/SIO0
P/N: PM1980
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
5. BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Data
Register
SI/SIO0
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
HOLD#/SIO3
Mode
Logic
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
SO/SIO1
P/N: PM1980
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
6. MEMORY ORGANIZATION
Table 1. Memory Organization (512Kb)
Table 2. Memory Organization (1Mb)
Block
Sector
Address Range
Block
Sector
Address Range
31
:
01F000h
01FFFFh
:
15
00F000h
00FFFFh
1
:
:
:
:
16
010000h
010FFFh
3
2
1
0
003000h
002000h
001000h
000000h
003FFFh
002FFFh
001FFFh
000FFFh
0
15
00F000h
00FFFFh
:
:
:
3
2
1
0
003000h
002000h
001000h
000000h
003FFFh
002FFFh
001FFFh
000FFFh
0
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
7. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes Standby Mode and keeps the Standby Mode
until next CS# falling edge. In Standby Mode, all SO pins of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".
5. For the following instructions: RDID, RDSR, READ, FAST_READ and 4READ the shifted-in instruction sequence
is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the follow-
ing instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, and DP the CS# must go high exactly at the byte
boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Program, Erase operation, to access the memory array is neglected and not affect the
current operation of Program and Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1980
REV. 0.00, OCT. 11, 2013
9
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
8. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while
Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Se-
rial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock (SCLK)
signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low),
see"Figure 2. Hold Condition Operation".
Figure 2. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Hold
Condition
(standard)
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
P/N: PM1980
REV. 0.00, OCT. 11, 2013
10
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
9. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architectureꢀ ofꢀ theꢀ deviceꢀ constrainsꢀ thatꢀ theꢀ memoryꢀ contentsꢀ canꢀ onlyꢀ beꢀ changedꢀ afterꢀ specificꢀ commandꢀ
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
powerup and power-down or from system noise.
•ꢀꢀꢀ Validꢀcommandꢀlengthꢀchecking:ꢀTheꢀcommandꢀlengthꢀwillꢀbeꢀcheckedꢀwhetherꢀitꢀisꢀatꢀbyteꢀbaseꢀandꢀcompletedꢀ
on byte boundary.
•ꢀꢀꢀ WriteꢀEnableꢀ(WREN)ꢀcommand:ꢀWRENꢀcommandꢀisꢀrequiredꢀtoꢀsetꢀtheꢀWriteꢀEnableꢀLatchꢀbitꢀ(WEL)ꢀbeforeꢀ
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•ꢀꢀ Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.
•ꢀꢀ Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data
change.
•ꢀꢀꢀ DeepꢀPowerꢀDownꢀMode:ꢀByꢀenteringꢀDeepꢀPowerꢀDownꢀMode,ꢀtheꢀflashꢀdeviceꢀalsoꢀisꢀunderꢀprotectedꢀfromꢀ
writing all commands except Release from Deep Power Down Mode command (RDP).
Table 3. Protected Area Sizes
Status bit
Protect level
BP1
BP0
MX25U5121E
0 (none)
1 (All)
MX25U1001E
0 (none)
1 (1 block)
2 (All)
0
0
1
1
0
1
0
1
2 (All)
3 (All)
3 (All)
P/N: PM1980
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
10. COMMAND DESCRIPTION
Table 4. Command Set
WRSR
RDID
RDSR
FAST READ
(fast read
data)
0B (hex)
AD1
Command WREN (write WRDI (write
READ (read
data)
(write status (readꢀidentific- (read status
register)
01 (hex)
(byte)
enable)
disable)
ation)
9F (hex)
register)
05 (hex)
1st byte
2nd byte
3rd byte
06 (hex)
04 (hex)
03 (hex)
AD1
AD2
AD2
4th byte
AD3
AD3
5th byte
Dummy
Data Cycles
sets the (WEL) resets the
write enable (WEL) write values of the
to write new
outputs
JEDEC
to read out n bytes read n bytes read
the values out until CS# out until CS#
latch bit
enable latch status register ID: 1-byte
of the status
register
goes high
goes high
Action
bit
Manufacturer
ID & 2-bytes
Device ID
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
DREAD
(1I/2O read) (4 I/O read)
3B (hex)
AD1
AD2
4READ
SE (sector
erase)
20 (hex)
AD1
BE (block
erase)
52 or D8 (hex) 60 or C7 (hex)
CE (chip
erase)
PP (page
program)
02 (hex)
AD1
DP (Deep
power down)
B9 (hex)
EB (hex)
AD1
AD2
AD3
Dummy
AD1
AD2
AD3
AD2
AD3
AD2
AD3
AD3
Dummy
1-32
n bytes read n bytes read to erase the to erase the
to erase
whole chip the selected Power Down
page Mode
to program enters Deep
out by 2 x I/ out by 4 x I/
O until CS# O until CS#
selected
sector
selected
block
Action
goes high
goes high
RDP (Release
from deep
power down)
Command
(byte)
1st byte
2nd byte
3rd byte
AB (hex)
4th byte
5th byte
Data Cycles
release from
Deep Power
Down Mode
Action
Noteꢀ1:ꢀꢀItꢀisꢀnotꢀrecommendedꢀtoꢀadoptꢀanyꢀotherꢀcodeꢀnotꢀinꢀtheꢀcommandꢀdefinitionꢀtable,ꢀwhichꢀwillꢀpotentiallyꢀ
enter the hidden mode.
Noteꢀ2:ꢀꢀValueꢀ"0"ꢀshouldꢀbeꢀinputꢀtoꢀtheꢀun-usedꢀsignificantꢀbitsꢀofꢀaddressꢀbitsꢀbyꢀuserꢀ(e.g.ꢀA17~A23(MSB)ꢀinꢀ
MX25U1001E ; A16-A23(MSB) in MX25U5121E)
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
10-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE and WRSR which are intended to change the device content, should be set every time after the WREN in-
struction setting the WEL bit.
TheꢀsequenceꢀofꢀissuingꢀWRENꢀinstructionꢀis:ꢀCS#ꢀgoesꢀlow→ꢀsendingꢀWRENꢀinstructionꢀcode→CS#ꢀgoesꢀhigh.ꢀ(Pleaseꢀ
refer to "Figure 11. Write Enable (WREN) Sequence (Command 06)")
10-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
TheꢀsequenceꢀofꢀissuingꢀWRDIꢀinstructionꢀis:ꢀCS#ꢀgoesꢀlow→sendingꢀWRDIꢀinstructionꢀcode→CS#ꢀgoesꢀhigh.ꢀ(Pleaseꢀ
refer to "Figure 12. Write Disable (WRDI) Sequence (Command 04)")
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
10-3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-bytes.
TheꢀMacronixꢀManufacturerꢀIDꢀisꢀC2(hex),ꢀtheꢀmemoryꢀtypeꢀIDꢀisꢀ25(hex)ꢀasꢀtheꢀfirst-byteꢀdeviceꢀID,ꢀandꢀtheꢀindi-
vidual device ID of second-byte ID are listed as "Table 5. ID Definitions".
TheꢀsequenceꢀofꢀissuingꢀRDIDꢀinstructionꢀis:ꢀCS#ꢀgoesꢀlow→sendingꢀRDIDꢀinstructionꢀcode→24-bitsꢀIDꢀdataꢀoutꢀ
onꢀSO→ꢀtoꢀendꢀRDIDꢀoperationꢀcanꢀuseꢀCS#ꢀtoꢀhighꢀatꢀanyꢀtimeꢀduringꢀdataꢀout.ꢀ(Pleaseꢀreferꢀtoꢀ"Figure 13. Read
Identification (RDID) Sequence (Command 9F)")
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at Standby Mode.
Table 5. ID Definitions
MX25U5121E
memory type
25
MX25U1001E
memory type
25
manufacturer
ID
memory
density
manufacturer
ID
memory
density
RDID Command
C2
30
C2
31
P/N: PM1980
REV. 0.00, OCT. 11, 2013
13
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
10-4. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program or erase operation is in progress.
Theꢀ sequenceꢀ ofꢀ issuingꢀ RDSRꢀ instructionꢀ is:ꢀ CS#ꢀ goesꢀ low→sendingꢀ RDSRꢀ instructionꢀ code→Statusꢀ Registerꢀ
data out on SO (Please refer to "Figure 14. Read Status Register (RDSR) Sequence (Command 05)")
Theꢀdefinitionꢀofꢀtheꢀstatusꢀregisterꢀbitsꢀisꢀasꢀbelow:ꢀ
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase
progress. When WIP bit sets to 1, which means the device is busy in program/erase progress. When WIP bit sets to 0,
which means the device is not in progress of program/erase register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept
program/erase instruction.
BP1, BP0 bits.ꢀTheꢀBlockꢀProtectꢀ(BP1,ꢀBP0)ꢀbits,ꢀvolatileꢀbits,ꢀindicateꢀtheꢀprotectedꢀarea(asꢀdefinedꢀinꢀ"Table 3.
Protected Area Sizes") of the device to against the program/erase instruction without hardware protection mode
being set. To write the Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be
executed.ꢀThoseꢀbitsꢀdefineꢀtheꢀprotectedꢀareaꢀofꢀtheꢀmemoryꢀtoꢀagainstꢀPageꢀProgramꢀ(PP),ꢀSectorꢀEraseꢀ(SE),ꢀ
Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed)
QE bit. The Quad Enable (QE) bit, volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is en-
able. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into four
I/O mode (QE=1), the features of HPM and HOLD will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, volatile bit, is operated together with Write Protection (WP#/
SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.
Table 6. Status Register
bit7
bit6
bit5
bit4
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
Reserved
Reserved
1=Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
enable operation
1=write
operation
1=status
register write
disable
0
0
(note 1)
(note 1)
Note: 1. See the "Table 3. Protected Area Sizes". The default BP0-BP1 values are "1" (protected).
2. The SRWD default value is "0"
P/N: PM1980
REV. 0.00, OCT. 11, 2013
14
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
10-5. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance.ꢀTheꢀWRSRꢀinstructionꢀcanꢀchangeꢀtheꢀvalueꢀofꢀBlockꢀProtectꢀ(BP1,ꢀBP0)ꢀbitsꢀtoꢀdefineꢀtheꢀprotectedꢀareaꢀofꢀ
memory (as shown in "Table 3. Protected Area Sizes"). The WRSR also can set or reset the Status Register Write
Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be execut-
ed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low sending WRSR instruction code Status Register
→
→
data on SI CS# goes high. (see "Figure 15. Write Status Register (WRSR) Sequence (Command 01)")
→
The WRSR instruction has no effect on b5, b4, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 7. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Software protection Status register can be written in (WEL WP#=1 and SRWD bit=0, or
The protected area cannot
be program or erase.
mode (SPM)
bit is set to "1") and the SRWD, WP#=0 and SRWD bit=0, or
BP0-BP1 bits can be changed
Hardware protection The SRWD, BP0-BP1 of status
mode (HPM) register bits cannot be changed
Note:
WP#=1 and SRWD=1
The protected area cannot
be program or erase.
WP#=0, SRWD bit=1
1.ꢀAsꢀ definedꢀ byꢀ theꢀ valuesꢀ inꢀ theꢀ Blockꢀ Protectꢀ (BP1,ꢀ BP0)ꢀ bitsꢀ ofꢀ theꢀ Statusꢀ Register,ꢀ asꢀ shownꢀ inꢀ "Table 3.
Protected Area Sizes".
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change
theꢀvaluesꢀofꢀSRWD,ꢀBP1,ꢀBP0.ꢀꢀTheꢀprotectedꢀarea,ꢀwhichꢀisꢀdefinedꢀbyꢀBP1,ꢀBP0,ꢀisꢀatꢀsoftwareꢀprotectedꢀ
mode (SPM).
- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of
SRWD,ꢀBP1,ꢀBP0.ꢀTheꢀprotectedꢀarea,ꢀwhichꢀisꢀdefinedꢀbyꢀBP1,ꢀBP0,ꢀisꢀatꢀsoftwareꢀprotectedꢀmodeꢀ(SPM)
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previ-
ously been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hard-
wareꢀprotectedꢀmodeꢀbyꢀtheꢀWP#ꢀtoꢀagainstꢀdataꢀmodification.
Note:
- To exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered.
If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can
use software protected mode via BP1, BP0.
- If the system had entered the Quad I/O (QE=1) mode, the feature of HPM will be disabled.
P/N: PM1980
REV. 0.00, OCT. 11, 2013
15
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
10-6. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
onꢀtheꢀfallingꢀedgeꢀofꢀSCLKꢀatꢀaꢀmaximumꢀfrequencyꢀfC.ꢀTheꢀfirstꢀaddressꢀcanꢀbeꢀatꢀanyꢀlocation.ꢀTheꢀaddressꢀisꢀ
automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be
read out at a single READ instruction.
This product does not provide the function of read around. After reading through density 512Kb or 1Mb, CS# must
go high. Otherwise, the data correctness will not be guaranteed. If the device needs to read data again, it must
issue read command once more.
TheꢀsequenceꢀofꢀissuingꢀREADꢀinstructionꢀis:ꢀCS#ꢀgoesꢀlow→ꢀsendingꢀREADꢀinstructionꢀcode→ꢀ3-bytesꢀaddressꢀ
onꢀSI→dataꢀoutꢀonꢀSO→toꢀendꢀREADꢀoperationꢀcanꢀuseꢀCS#ꢀtoꢀhighꢀatꢀanyꢀtimeꢀduringꢀdataꢀout.ꢀ(Pleaseꢀreferꢀtoꢀ
"Figure 16. Read Data Bytes (READ) Sequence (Command 03)")
10-7. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
dataꢀofꢀeachꢀbitꢀshiftsꢀoutꢀonꢀtheꢀfallingꢀedgeꢀofꢀSCLKꢀatꢀaꢀmaximumꢀfrequencyꢀfC.ꢀTheꢀfirstꢀaddressꢀbyteꢀcanꢀbeꢀatꢀ
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
Theꢀ sequenceꢀ ofꢀ issuingꢀ FAST_READꢀ instructionꢀ is:ꢀ CS#ꢀ goesꢀ low→ꢀ sendingꢀ FAST_READꢀ instructionꢀ code→ꢀ
3-byteꢀaddressꢀonꢀSI→ꢀ8ꢀdummyꢀcyclesꢀonꢀSI→dataꢀoutꢀonꢀSO→ꢀtoꢀendꢀFAST_READꢀoperationꢀcanꢀuseꢀCS#ꢀtoꢀ
high at any time during data out. (Please refer to "Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command
0B)")
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
10-8. Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mumꢀfrequencyꢀfT.ꢀTheꢀfirstꢀaddressꢀbyteꢀcanꢀbeꢀatꢀanyꢀlocation.ꢀTheꢀaddressꢀisꢀautomaticallyꢀincreasedꢀtoꢀtheꢀnextꢀ
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-
tion, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low
sending DREAD instruction
3-byte address on
→
→
SI
8-bit dummy cycle
data out interleave on SO1 & SO0
to end DREAD operation can use CS# to high at
→
→
→
any time during data out. (Please refer to "Figure 18. Dual Read Mode Sequence (Command 3B)")
10-9. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of Status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 x I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fC.ꢀTheꢀfirstꢀaddressꢀcanꢀbeꢀatꢀanyꢀlocation.ꢀTheꢀaddressꢀisꢀautomaticallyꢀincreasedꢀtoꢀtheꢀnextꢀhigherꢀaddressꢀaf-
ter each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
P/N: PM1980
REV. 0.00, OCT. 11, 2013
16
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
The sequence of issuing 4READ instruction is: CS# goes low sending 4READ instruction 24-bit address inter-
→
→
leave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles data out interleave on SIO3, SIO2, SIO1 & SIO0 to end
→
→
→
4READ operation can use CS# to high at any time during data out. (Please refer to "Figure 19. 4 x I/O Read Mode
Sequence (Command EB)")
10-10. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-bytes sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit be-
fore sending the Sector Erase (SE). Any address of the sector (Please refer to "Table 1. Memory Organization (512Kb)"
and "Table 2. Memory Organization (1Mb)") is a valid address for Sector Erase (SE) instruction. The CS# must go
high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the instruction will
be rejected and not executed.
Addressꢀbitsꢀ[Am-A12]ꢀ(Amꢀisꢀtheꢀmostꢀsignificantꢀaddress)ꢀselectꢀtheꢀsectorꢀaddress.
TheꢀsequenceꢀofꢀissuingꢀSEꢀinstructionꢀis:ꢀCS#ꢀgoesꢀlow→sendingꢀSEꢀinstructionꢀcode→3-bytesꢀaddressꢀonꢀSIꢀ
→CS#ꢀgoesꢀhigh.ꢀ(Pleaseꢀreferꢀtoꢀ"Figure 20. Sector Erase (SE) Sequence (Command 20)")
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-
gress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
10-11.Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see "Table 1. Memory Organization (512Kb)"
and "Table 2. Memory Organization (1Mb)") is a valid address for Block Erase (BE) instruction. The CS# must go
high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will
be rejected and not executed.
The sequence is shown as "Figure 21. Block Erase (BE) Sequence (Command D8 or 52)".
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-
gress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE
timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
10-12. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see "Table 1. Memory Organization (512Kb)" and "Table 2. Memory Organization (1Mb)") is a valid address
for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address
byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence is shown as "Figure 22. Chip Erase (CE) Sequence (Command 60 or C7)".
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-
gress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE tim-
ing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
P/N: PM1980
REV. 0.00, OCT. 11, 2013
17
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
10-13. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). After the instruction
and address input, data to be programmed is input sequentially. The internal sequence controller will sequentially
program the data from the initial address. If the transmitted data goes beyond the page boundary, the internal se-
quence controller may not function properly and the content of the device will not be guaranteed. Therefore, If the
initialꢀA4-A0ꢀ(Theꢀfiveꢀleastꢀsignificantꢀaddressꢀbits)ꢀareꢀsetꢀtoꢀallꢀ0,ꢀmaximumꢀ32ꢀbytesꢀofꢀdataꢀcanꢀbeꢀinputꢀsequen-
tially.ꢀIfꢀtheꢀinitialꢀaddressꢀA4-A0ꢀ(Theꢀfiveꢀleastꢀsignificantꢀaddressꢀbits)ꢀareꢀnotꢀsetꢀtoꢀallꢀ0,ꢀmaximumꢀbytesꢀofꢀdataꢀ
input will be the subtraction of the initial address A4-A0 from 32bytes. The data exceeding 32bytes data is not sent
to device. In this case, data is not guaranteed.
TheꢀsequenceꢀofꢀissuingꢀPPꢀinstructionꢀis:ꢀCS#ꢀgoesꢀlowꢀ→ꢀsendingꢀPPꢀinstructionꢀcodeꢀ→ꢀ3-bytesꢀaddressꢀonꢀSI→ꢀ
atꢀleastꢀ1-byteꢀonꢀdataꢀonꢀSIꢀ→ꢀCS#ꢀgoesꢀhigh.ꢀ(Pleaseꢀreferꢀtoꢀ"Figure 23. Page Program (PP) Sequence (Command
02)")
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
10-14. Deep Power-Down (DP)
The Deep Power Down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power Down Mode), the standby current is reduced from ISB1 to ISB2. The Deep Power Down Mode
requires the Deep Power Down (DP) instruction to enter, during the Deep Power Down Mode, the device is not ac-
tive and all Read/Write/Program/Erase instruction are ignored.
TheꢀsequenceꢀofꢀissuingꢀDPꢀinstructionꢀis:ꢀCS#ꢀgoesꢀlow→sendingꢀDPꢀinstructionꢀcode→ꢀCS#ꢀgoesꢀhigh.ꢀ(Pleaseꢀ
refer to "Figure 24. Deep Power Down (DP) Sequence (Command B9)")
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power Down Mode (RDP)
instruction. When Power-down, the Deep Power Down Mode automatically stops, and when power-up, the device
automatically is in Standby Mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest
eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#)
goes high, a delay of tDP is required before entering the Deep Power Down Mode.
10-15. Release from Deep Power-Down (RDP)
The Release from Deep Power Down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Standby Mode. If the device was not previously in the Deep
Power Down Mode, the transition to the Standby Mode is immediate. If the device was previously in the Deep Pow-
er Down Mode, though, the transition to the Standby Mode is delayed by tRES1, and Chip Select (CS#) must re-
mainꢀHighꢀforꢀatꢀleastꢀtRES1(max),ꢀasꢀspecifiedꢀinꢀ"Table 9. AC CHARACTERISTICS". Once in the Standby Mode,
the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only
for releasing from Deep Power Down Mode.
The sequence is shown as "Figure 25. Release from Deep Power Down (RDP) Sequence (Command AB)". Even
in Deep Power Down Mode, the RDP is also allowed to be executed, only except the device is in progress of pro-
gram/erase cycle; there's no effect on the current program/erase cycle in progress.
P/N: PM1980
REV. 0.00, OCT. 11, 2013
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
11. POWER-ON STATE
The device is at below states when power-up:
- Standby Mode ( please note it is not Deep Power Down Mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)
P/N: PM1980
REV. 0.00, OCT. 11, 2013
19
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 3. Program/Erase flow with read array data
start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
No
Program/erase completed
P/N: PM1980
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
12. ELECTRICAL SPECIFICATIONS
12-1. ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5VꢀtoꢀVCC+0.5V
ꢀ-0.5VꢀtoꢀVCC+0.5V
-0.5V to 2.5V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
toꢀtheꢀdevice.ꢀꢀThisꢀisꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀ
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2.ꢀ Specificationsꢀcontainedꢀwithinꢀtheꢀfollowingꢀtablesꢀareꢀsubjectꢀtoꢀchange.
3.ꢀ Duringꢀvoltageꢀtransitions,ꢀallꢀpinsꢀmayꢀovershootꢀtoꢀVCC+1.0Vꢀorꢀ-1.0Vꢀforꢀperiodꢀupꢀtoꢀ20ns.
Figure 5. Maximum Positive Overshoot Waveform
Figure 4. Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
2.0V
-1.0V
20ns
12-2. CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL PARAMETER
CIN Input Capacitance
COUT Output Capacitance
MIN.
TYP.
MAX.
UNIT
pF
CONDITIONS
VIN = 0V
6
8
pF
VOUT = 0V
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 6. Input Test Waveforms and Measurement Level
Input timing reference level
Output timing reference level
0.8VCC
0.7VCC
AC
Measurement
Level
0.5VCC
0.3VCC
0.2VCC
Note: Input pulse rise and fall time are <5ns
Figure 7. Output Loading
25K ohm
DEVICE UNDER
TEST
+1.8V
CL
25K ohm
CL=30pF Including jig capacitance
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Table 8. DC CHARACTERISTICS
Symbol Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
VCC = VCC Max,
uA
ILI
Input Load Current
1
± 2
± 2
35
VIN = VCC or GND
VCC = VCC Max,
uA
ILO
Output Leakage Current
1
1
VOUT = VCC or GND
VIN = VCC or GND,
CS# = VCC
ISB1 VCC Standby Current
25
3
uA
Deep Power Down
Current
VIN = VCC or GND,
CS# = VCC
ISB2
10
uA
f=70MHz,
10
5
mA SCLK=0.1VCC/0.9VCC,
SO=Open
f=30MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1 VCC Read
1
VCC Program Current
Program in Progress,
CS# = VCC
ICC2
(PP)
1
1
1
20
20
25
20
25
mA
VCC Write Register
ICC3
Program Status Register in
mA
(WRSR) Current
Progress, CS#=VCC
VCC Sector Erase
ICC4
Erase in Progress,
CS#=VCC
mA
Current (SE)
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.2VCC
VCC+0.4
0.2
V
V
0.8VCC
V
V
IOL = 100uA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
1.0
VWI
Command Inhibit Voltage
3
1.4
V
Notes :
1. Typical values at VCC = 1.8V, T = 25 C. These currents are valid for all product versions (package and speeds).
°
2. Typical value is calculated by simulation.
3. Not 100% tested.
P/N: PM1980
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Table 9. AC CHARACTERISTICS
Symbol Alt. Parameter
Min.
Typ.
Max. Unit
Clock Frequency for the following instructions: FAST_READ, PP,
SE, BE, CE, DP, RDP, WREN, WRDI, RDID, RDSR, WRSR
fR Clock Frequency for READ instruction
fT Clock Frequency for DREAD instruction
fQ Clock Frequency for 4READ instruction
fSCLK
fRSCLK
fTSCLK
fC
1KHz
70
MHz
1KHz
1KHz
1KHz
7
15
7
15
0.1
0.1
7
30
70
60
MHz
MHz
MHz
ns
ns
ns
Serial (fSCLK)
Normal Read (fRSCLK)
Serial (fSCLK)
tCH(1) tCLH Clock High Time
tCL(1)
tCLL Clock Low Time
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
Normal Read (fRSCLK)
ns
tCLCH(2)
tCHCL(2)
V/ns
V/ns
ns
ns
ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
5
2
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
5
5
7
12
30
ns
ns
ns
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
tSHSL(4) tCSH CS# Deselect Time
Write/Erase/Program
ns
tSHQZ(2) tDIS Output Disable Time
8
ns
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX
tHLQZ
HOLD# Active Setup Time (relative to SCLK)
HOLD# Active Hold Time (relative to SCLK)
HOLD# Not Active Setup Time (relative to SCLK)
HOLD# Not Active Hold Time (relative to SCLK)
tLZ HOLD# to Output Low-Z
tHZ HOLD# to Output High-Z
@ 30pF
tV Clock Low to Output Valid
@ 15pF
4
4
4
4
ns
ns
ns
ns
ns
ns
ns
ns
8
8
8
6
tCLQV
tCLQX
tWHSL(4)
tSHWL(4)
tDP(2)
tRES1(2)
tW
tHO Output Hold Time
1
20
100
ns
ns
ns
us
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power Down Mode
CS# High to Standby Mode without Electronic Signature Read
Write Status Register Cycle Time
Page Program Cycle Time (32 Bytes)
Sector Erase Cycle Time (4K Bytes)
Block Erase Cycle Time
10
10
15
1.3
400
3
us
5
ms
ms
ms
s
s
s
tPP
tSE
tBE
0.36
120
1.3
1.3
2.6
512Kb
3
6
tCE
Chip Erase Cycle Time
1Mb
Notes:
1.ꢀtCHꢀ+ꢀtCLꢀmustꢀbeꢀgreaterꢀthanꢀorꢀequalꢀtoꢀ1/ꢀfꢀ(fC).ꢀ
2. Value guaranteed by characterization, not 100% tested in production.
3. Test condition is shown as "Figure 6. Input Test Waveforms and Measurement Level" & "Figure 7. Output
Loading".
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
P/N: PM1980
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24
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
13. Timing Analysis
Figure 8. Serial Input Timing
tSHSL
tSHCH
CS#
tSLCH
tCHSH
tCHSL
SCLK
tCHCL
tDVCH
tCLCH
tCHDX
MSB
LSB
SI
High-Z
SO
Figure 9. Output Timing
CS#
tCH
SCLK
tCLQV
tSHQZ
tCLQV
tCL
tCLQX
SO
tCLQX
LSB
ADDR.LSB IN
SI
P/N: PM1980
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25
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
WP#
CS#
tSHWL
tWHSL
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06
SI
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04
SI
High-Z
SO
P/N: PM1980
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26
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 13. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9F
Manufacturer ID
Device ID
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
P/N: PM1980
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27
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 14. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 15. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCLK
command
01
Status
Register In
SI
7
6
5
4
3
2
0
1
MSB
High-Z
SO
Figure 16. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
P/N: PM1980
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0B
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Byte
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Figure 18. Dual Read Mode Sequence (Command 3B)
CS#
30 31 32
39 40 41 42 43 44 45
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Data Out
2
Data Out
1
8 dummy
cycle
Command
24 ADD Cycle
…
A23 A22
A1 A0
D4 D2
D6 D4
D0
3B
D6
D7
SI/SIO0
High Impedance
D7 D5
D1
D5 D3
SO/SIO1
P/N: PM1980
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29
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 19. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
6 dummy
cycles
8 Bit Instruction
EBh
6 Address cycles
Data Output
data
bit4, bit0, bit4....
address
bit20, bit16..bit0
SI/SIO0
High Impedance
High Impedance
High Impedance
address
data
SO/SIO1
bit21, bit17..bit1
bit5 bit1, bit5....
address
bit22, bit18..bit2
data
bit6 bit2, bit6....
WP#/SIO2
HOLD#/SIO3
address
bit23, bit19..bit3
data
bit7 bit3, bit7....
Note:
1. Hi-impedance is inhibited for the two clock cycles.
Figure 20. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20
24 Bit Address
2
SI
23 22
MSB
1
0
P/N: PM1980
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30
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 21. Block Erase (BE) Sequence (Command D8 or 52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
D8 or 52
24 Bit Address
SI
23 22
MSB
2
0
1
Note: BE command is D8(hex) or 52(hex).
Figure 22. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
60 or C7
SI
Note: CE command is 60(hex) or C7(hex).
Figure 23. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 32
Data Byte 2
Data Byte 3
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
P/N: PM1980
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31
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 24. Deep Power Down (DP) Sequence (Command B9)
CS#
t
DP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9
Standby Mode
Deep Power Down Mode
Figure 25. Release from Deep Power Down (RDP) Sequence (Command AB)
CS#
t
RES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
AB
High-Z
SO
Deep Power Down Mode Standby Mode
P/N: PM1980
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32
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 26. Power-Up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
tVSL
Device is fully
accessible
time
Note: VCC (max.) is 2.0V and VCC (min.) is 1.65V.
Table 10. Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
300
us
Note: 1. The parameter is characterized only.
13-1. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
P/N: PM1980
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33
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
14. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 27. AC Timing at Device Power-Up" and "Figure 28. Power-Down Sequence" are
forꢀtheꢀsupplyꢀvoltagesꢀandꢀtheꢀcontrolꢀsignalsꢀatꢀdeviceꢀpower-upꢀandꢀpower-down.ꢀIfꢀtheꢀtimingꢀinꢀtheꢀfiguresꢀisꢀig-
nored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 27. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
tVR
Parameter
VCC Rise Time
Notes
Min.
10
Max.
500000
Unit
us/V
1
Notes :
1. Sampled, not 100% tested.
2.ꢀForꢀACꢀspecꢀtCHSL,ꢀtSLCH,ꢀtDVCH,ꢀtCHDX,ꢀtSHSL,ꢀtCHSH,ꢀtSHCH,ꢀtCHCL,ꢀtCLCHꢀinꢀtheꢀfigure,ꢀpleaseꢀreferꢀtoꢀ
"Table 9. AC CHARACTERISTICS".
P/N: PM1980
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 28. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
P/N: PM1980
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35
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
15. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
120
Max. (2)
Unit
Sector Erase Time
Block Erase Time
400
3
ms
1.3
s
s
512Kb
1.3
3
Chip Erase Time
1Mb
2.6
6
s
Page Program Time (32 Bytes)
Erase/Program Cycle
0.36
100,000
1.3
ms
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25 C, 1.8V, and checkerboard pattern.
°
2. Under worst conditions of 85 C and 1.65V.
°
3.ꢀꢀSystem-levelꢀoverheadꢀisꢀtheꢀtimeꢀrequiredꢀtoꢀexecuteꢀtheꢀfirst-bus-cycleꢀsequenceꢀforꢀtheꢀprogrammingꢀcom-
mand.
4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.
17. DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
55˚C
20
years
16. LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
2 VCCmax
VCCꢀ+ꢀ1.0V
+100mA
-100mA
Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time.
P/N: PM1980
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
18. ORDERING INFORMATION
512Kb
CLOCK
(MHz)
PART NO.
TEMPERATURE
-40 C~85 C
PACKAGE
Remark
MX25U5121EMI-14G
MX25U5121EOI-14G
MX25U5121EZUI-14G
70
70
70
8-SOP (150mil)
8-TSSOP (173mil)
8-USON (2x3mm)
°
°
-40 C~85 C
°
°
-40 C~85 C
°
°
1Mb
CLOCK
(MHz)
PART NO.
TEMPERATURE
-40 C~85 C
PACKAGE
Remark
MX25U1001EMI-14G
MX25U1001EOI-14G
MX25U1001EZUI-14G
70
70
70
8-SOP (150mil)
8-TSSOP (173mil)
8-USON (2x3mm)
°
°
-40 C~85 C
°
°
-40 C~85 C
°
°
P/N: PM1980
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37
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
19. PART NAME DESCRIPTION
MX 25 U 1001E
M
I
14 G
OPTION:
G: RoHS Compliant and Halogen-free
SPEED:
14: 70MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M: 150mil 8-SOP
O: 173mil 8-TSSOP
ZU: 2x3mm 8-USON
DENSITY & MODE:
5121E: 512Kb
1001E: 1Mb
TYPE:
U: 1.8V
DEVICE:
25: Serial Flash
P/N: PM1980
REV. 0.00, OCT. 11, 2013
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ADVANCED INFORMATION
MX25U5121E
MX25U1001E
20. PACKAGE INFORMATION
P/N: PM1980
REV. 0.00, OCT. 11, 2013
39
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
P/N: PM1980
REV. 0.00, OCT. 11, 2013
40
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
P/N: PM1980
REV. 0.00, OCT. 11, 2013
41
MX25U5121E
MX25U1001E
Exceptꢀforꢀcustomizedꢀproductsꢀwhichꢀhasꢀbeenꢀexpresslyꢀidentifiedꢀinꢀtheꢀapplicableꢀagreement,ꢀMacronix'sꢀ
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
targetꢀusageꢀabove,ꢀtheꢀbuyerꢀshallꢀtakeꢀanyꢀandꢀallꢀactionsꢀtoꢀensureꢀsaidꢀMacronix'sꢀproductꢀqualifiedꢀforꢀitsꢀ
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2013. All rights reserved, including the trademarks and tradename
thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit,
Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names
andꢀbrandsꢀofꢀthirdꢀpartyꢀreferredꢀtheretoꢀ(ifꢀany)ꢀareꢀforꢀidentificationꢀpurposesꢀonly.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
42
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