UPD160061NL-XXX [NEC]
384-OUTPUT TFT-LCD SOURCE DRIVER; 384输出TFT -LCD源极驱动器
| 型号： | UPD160061NL-XXX |
| 厂家： | 
NEC |
| 描述： | 384-OUTPUT TFT-LCD SOURCE DRIVER |
| 文件： | 总18页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD160061
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µPD160061 is a source driver for TFT-LCD’s capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by
output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output
dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common electrode is
rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when
mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins
and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of
65 MHz when driving at 2.7 V, this driver is applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels.
FEATURES
• CMOS level input (2.3 to 3.6 V)
• 384 outputs
• Input of 6 bits (gray-scale data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)
• Logic power supply voltage (VDD1): 2.3 to 3.6 V
• Driver power supply voltage (VDD2): 7.5 to 9.5 V
• High-speed data transfer: fCLK = 65 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)
40 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.3 V)
• Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Input data inversion function (capable of controlling by each input port) (POL21, POL22)
• Apply for heavy load, light load
• Semi slim-chip shaped
ORDERING INFORMATION
Part Number
Package
µPD160061N-xxx
µPD160061NL-xxx
TCP (TAB package)
COF (COF package)
Remark The TCP’s/COF’s external shape are customized. To order the required shape, so please contact one of our
sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15843EJ3V0DS00 (3rd edition)
Date Published June 2004 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
2002
µPD160061
1. BLOCK DIAGRAM
STHR
STHL
64-bit bidirectional shift register
R,/L
CLK
STB
VDD1
VSS1
C
1
C
2
C
3
- - - - - - - - - - - - - - - - - - - - - - C63 C64
D00 toD05
D10 toD15
D20 toD25
D30 to
D35
D40 toD45
D50 to
POL21
POL22
SRC
D55
Data register
LPC
HPC
POL
Latch
VDD2
Level shifter
VSS2
V0
to V
9
D/A converter
Voltage follower output
--------------------------------
S1
S2
S3
S384
Remark /xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1
S2
S
383
S384
5
5
V0
:
V4
Multi-
Plexer
6-bit D/A converter
V5
:
V9
POL
2
Data Sheet S15843EJ3V0DS
µPD160061
3. PIN CONFIGURATION (Copper foil surface) (µPD160061N-xxx: TCP (TAB package): Face-up/
µPD160061NL-xxx: COF (COF package): Face-down)
384
383
382
381
S
S
S
S
STHL
55
D
54
D
53
D
52
D
51
D
50
D
45
D
44
D
43
D
42
D
41
D
40
D
35
D
34
D
33
D
32
D
31
D
30
D
DD1
V
LPC
R,/L
9
V
8
V
7
V
6
V
5
V
DD2
V
V
SS2
IC Pad Surface
4
V
3
V
2
V
1
V
0
V
HPC
SS1
V
SRC
CLK
STB
POL
POL21
POL22
25
D
24
D
23
D
22
D
21
D
20
D
15
D
14
D
13
D
12
D
11
D
10
D
05
D
04
D
03
D
4
S
02
D
3
S
2
1
01
D
S
S
00
D
STHR
Remark This figure does not specify the TCP or COF package.
3
Data Sheet S15843EJ3V0DS
µPD160061
4. PIN FUNCTIONS
(1/2)
Pin Symbol
S1 to S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L
Pin Name
I/O
Description
Driver output
Output The D/A converted 64-gray-scale analog voltage is output.
Display data input
Input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2
pixels).
DX0: LSB, DX5: MSB
Shift direction control
Input These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
R,/L = H (right shift): STHR input, S1→S384, STHL output
R,/L = L (left shift): STHL input, S384→S1, STHR output
STHR
STHL
Right shift start pulse
input/output
I/O
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
When right shift: STHR input, STHL output
When left shift: STHL input, STHR output
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is valid.
Left shift start pulse
input/output
CLK
Shift clock input
Input Refers to the shift register’s shift clock input. The display data is incorporated into the data
register at the rising edge. At the rising edge of the 64th after the start pulse input, the start
pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If
66th clock pulses are input after input of the start pulse, input of display data is halted
automatically. The contents of the shift register are cleared at the STB’s rising edge.
Input The contents of the data register are transferred to the latch circuit at the rising edge. And, at
the falling edge of the STB, the gray scale voltage is supplied to the driver. When STB = H
period, driver output level is Hi-Z (High impedance).
STB
POL
Latch input
It is necessary to ensure input of one pulse per horizontal period.
Polarity input
Input POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to
V9 as the reference supply.
POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to
V4 as the reference supply.
S2n-1 indicates the odd output, and S2n indicates the even output. Input of the POL signal is
allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
POL21,
POL22
Data inversion input
Input Data inversion can invert when display data is loaded.
POL21: D00 to D05, D10 to D15, D20 to D25, data inversion can invert display data
POL22: D30 to D35, D40 to D45, D50 to D55, data inversion can invert display data
POL21, POL22 = H: Data inversion loads display data after inverting it.
POL21, POL22 = L: Data inversion does not invert input data.
LPC,
HPC
Bias current control
input
Input Please refer to panel loads and driver power supply voltage (VDD2), when set up these pins.
Refer to 10. BIAS CURRENT CONTROL BY LPC AND HPC. LPC pin is pulled down to the
VSS1 inside the IC, HPC pin is pulled up to the VDD1 inside the IC.
4
Data Sheet S15843EJ3V0DS
µPD160061
(2/2)
Pin Symbol
SRC
Pin Name
I/O
Description
High driving time
control
Input This pin is set up to high drive time of the output amplifier. Please decide the pin setting refer
to panel loads and one horizontal period. SRC pin is pulled up to the VDD1 inside the IC.
SRC = H or open: High drive time 64 CLK (Normally period mode)
SRC = L: High drive time 128 CLK (Long time mode)
Refer to 9. SRC AND HIGH DRIVE TIME.
V0 to V9
γ -corrected power
−
Input the γ -corrected power supplies from outside by using operational amplifier.
supplies
Make sure to maintain the following relationships. During the gray scale voltage output, be
sure to keep the gray scale level power supply at a constant level.
VDD2 − 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2
VDD2 − 0.3 V ≥ > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V
VDD1
VDD2
VSS1
VSS2
Logic power supply
Driver power supply
Logic ground
−
−
−
−
2.3 to 3.6 V
7.5 to 9.5 V
Grounding
Grounding
Driver ground
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order.
Reverse this sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1 to VSS1 and VDD2 to VSS2. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power
supply terminals (V0, V1, V2,....., V9) and VSS.
5
Data Sheet S15843EJ3V0DS
µPD160061
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The µPD160061 incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray
scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. The D/A converter consists of
ladder resistors and switches.
The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ-compensated voltages to V0’ to V63’ and V0”
to V63” is almost equivalent, resistor ratio is shown in Figure 5−2. For the 2 sets of five γ-compensated power supplies, V0
to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When
fine-gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ-
compensated power supplies V1 to V3 and V6 to V8.
Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2,
common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage
relationships of below.
V
DD2 – 0.2 V ≥ V
0
> V
1
> V
2
> V
3
> V
4
≥ 0.5 VDD2
0.5 VDD2 – 0.3 V ≥ V
5
> V
6
> V
7
> V
8
> V
9
> VSS2 + 0.2 V
Figures 5–2 indicates γ -corrected voltages and ladder resistors ratio. Figures 5–3 indicates the relationship between the
input data and output voltage.
Figure 5–1. Relationship between Input Data and γ -corrected Power Supplies
V
DD2
0.2 V
V
0
16
V
1
16
16
15
V
V
2
3
V
4
0.5 VDD2
Split interval
15
0.3 V
V
5
V
6
7
16
16
V
V
8
16
V
9
0.2 V
V
SS2
00
10
20
30
3F
Input data (HEX.)
6
Data Sheet S15843EJ3V0DS
µPD160061
Figure 5–2. γ -corrected Voltages and Ladder Resistors Ratio
V
5
V
63’’
V
0
V
0
1
’
’
rn
Ratio Value (TYP.)
r
0
r
r
r
r
62
61
60
59
r0
8.5
7.5
7.0
6.5
6.0
5.5
5.5
5.0
5.0
4.0
4.0
3.5
3.5
3.5
3.0
3.0
3.0
2.5
2.5
2.5
2.0
2.0
2.0
1.5
1.5
1.5
1.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
2.0
2.0
2.5
2.5
3.0
5.0
8.0
800
750
700
650
600
550
550
500
500
400
400
350
350
350
300
300
300
250
250
250
200
200
200
150
150
150
150
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
150
150
150
200
200
250
250
300
500
800
r1
V
V62’’
V61’’
V60’’
r2
r1
r3
V
2
3
’
’
r4
r
2
3
r5
r6
V
r7
r
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
r
r
r
49
r
r
r
r
14
V15
V16
V17
’
’
’
V49’’
V48’’
V47’’
15
48
47
V1
V6
16
17
r46
r
r
r
r
46
47
48
49
r
r
r
r
17
V47
’
V
17’’
16’’
16
15
14
V48
’
V
V3
V8
V49
’
V15’’
r
r
r
2
1
0
r
60
V2
’’
’’
V
V
V
61
’
r
61
62
62
63
’
’
V1
r
V9
V4
V0’’
Cautions 1. There is no connection between V4 and V5 terminal in the IC.
2. The resistance ratio is a relative ratio in the case of setting the resistance minimum value to 1.
7
Data Sheet S15843EJ3V0DS
µPD160061
Figure 5–3. Relationship between Input Data and Output Voltage (POL21, POL22 = L)
Output Voltage 1: VDD2 – 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2
Output Voltage 2: 0.5 VDD2 – 0.3 V ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V
Input Data
00H
Output Voltage 1
Output Voltage 2
V0' V0
V0'' V9
01H
V1' V1+(V0-V1)×
V2' V1+(V0-V1)×
V3' V1+(V0-V1)×
V4' V1+(V0-V1)×
V5' V1+(V0-V1)×
V6' V1+(V0-V1)×
V7' V1+(V0-V1)×
V8' V1+(V0-V1)×
V9' V1+(V0-V1)×
V10' V1+(V0-V1)×
V11' V1+(V0-V1)×
V12' V1+(V0-V1)×
V13' V1+(V0-V1)×
V14' V1+(V0-V1)×
V15' V1+(V0-V1)×
V16' V1
7250 /
6500 /
5800 /
5150 /
4550 /
4000 /
3450 /
2950 /
2450 /
2050 /
1650 /
1300 /
950 /
8050 V1'' V9+(V8-V9)×
8050 V2'' V9+(V8-V9)×
8050 V3'' V9+(V8-V9)×
8050 V4'' V9+(V8-V9)×
8050 V5'' V9+(V8-V9)×
8050 V6'' V9+(V8-V9)×
8050 V7'' V9+(V8-V9)×
8050 V8'' V9+(V8-V9)×
8050 V9'' V9+(V8-V9)×
8050 V10'' V9+(V8-V9)×
8050 V11'' V9+(V8-V9)×
8050 V12'' V9+(V8-V9)×
8050 V13'' V9+(V8-V9)×
8050 V14'' V9+(V8-V9)×
8050 V15'' V9+(V8-V9)×
V16'' V8
800
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
8050
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
1550
2250
2900
3500
4050
4600
5100
5600
6000
6400
6750
7100
7450
7750
600 /
300 /
V17' V2+(V1-V2)×
V18' V2+(V1-V2)×
V19' V2+(V1-V2)×
V20' V2+(V1-V2)×
V21' V2+(V1-V2)×
V22' V2+(V1-V2)×
V23' V2+(V1-V2)×
V24' V2+(V1-V2)×
V25' V2+(V1-V2)×
V26' V2+(V1-V2)×
V27' V2+(V1-V2)×
V28' V2+(V1-V2)×
V29' V2+(V1-V2)×
V30' V2+(V1-V2)×
V31' V2+(V1-V2)×
V32' V2
2450 /
2200 /
1950 /
1700 /
1500 /
1300 /
1100 /
950 /
2750 V17'' V8+(V7-V8)×
2750 V18'' V8+(V7-V8)×
2750 V19'' V8+(V7-V8)×
2750 V20'' V8+(V7-V8)×
2750 V21'' V8+(V7-V8)×
2750 V22'' V8+(V7-V8)×
2750 V23'' V8+(V7-V8)×
2750 V24'' V8+(V7-V8)×
2750 V25'' V8+(V7-V8)×
2750 V26'' V8+(V7-V8)×
2750 V27'' V8+(V7-V8)×
2750 V28'' V8+(V7-V8)×
2750 V29'' V8+(V7-V8)×
2750 V30'' V8+(V7-V8)×
2750 V31'' V8+(V7-V8)×
V32'' V7
300
550
800
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
2750
1050
1250
1450
1650
1800
1950
2100
2250
2350
2450
2550
2650
800 /
650 /
500 /
400 /
300 /
200 /
100 /
V33' V3+(V2-V3)×
V34' V3+(V2-V3)×
V35' V3+(V2-V3)×
V36' V3+(V2-V3)×
V37' V3+(V2-V3)×
V38' V3+(V2-V3)×
V39' V3+(V2-V3)×
V40' V3+(V2-V3)×
V41' V3+(V2-V3)×
V42' V3+(V2-V3)×
V43' V3+(V2-V3)×
V44' V3+(V2-V3)×
V45' V3+(V2-V3)×
V46' V3+(V2-V3)×
V47' V3+(V2-V3)×
V48' V3
1500 /
1400 /
1300 /
1200 /
1100 /
1000 /
900 /
800 /
700 /
600 /
500 /
400 /
300 /
200 /
100 /
1600 V33'' V7+(V6-V7)×
1600 V34'' V7+(V6-V7)×
1600 V35'' V7+(V6-V7)×
1600 V36'' V7+(V6-V7)×
1600 V37'' V7+(V6-V7)×
1600 V38'' V7+(V6-V7)×
1600 V39'' V7+(V6-V7)×
1600 V40'' V7+(V6-V7)×
1600 V41'' V7+(V6-V7)×
1600 V42'' V7+(V6-V7)×
1600 V43'' V7+(V6-V7)×
1600 V44'' V7+(V6-V7)×
1600 V45'' V7+(V6-V7)×
1600 V46'' V7+(V6-V7)×
1600 V47'' V7+(V6-V7)×
V48'' V6
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
1600
V49' V4+(V3-V4)×
V50' V4+(V3-V4)×
V51' V4+(V3-V4)×
V52' V4+(V3-V4)×
V53' V4+(V3-V4)×
V54' V4+(V3-V4)×
V55' V4+(V3-V4)×
V56' V4+(V3-V4)×
V57' V4+(V3-V4)×
V58' V4+(V3-V4)×
V59' V4+(V3-V4)×
V60' V4+(V3-V4)×
V61' V4+(V3-V4)×
V62' V4+(V3-V4)×
3350 /
3250 /
3150 /
3050 /
2950 /
2800 /
2650 /
2500 /
2300 /
2100 /
1850 /
1600 /
1300 /
800 /
3450 V49'' V6+(V5-V6)×
3450 V50'' V6+(V5-V6)×
3450 V51'' V6+(V5-V6)×
3450 V52'' V6+(V5-V6)×
3450 V53'' V6+(V5-V6)×
3450 V54'' V6+(V5-V6)×
3450 V55'' V6+(V5-V6)×
3450 V56'' V6+(V5-V6)×
3450 V57'' V6+(V5-V6)×
3450 V58'' V6+(V5-V6)×
3450 V59'' V6+(V5-V6)×
3450 V60'' V6+(V5-V6)×
3450 V61'' V6+(V5-V6)×
100
200
300
400
500
650
800
950
1150
1350
1600
1850
2150
2650
/
/
/
/
/
/
/
/
/
/
/
/
/
/
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
3450
V62'' V6+(V5-V6)×
3450
V63' V4
V63'' V5
8
Data Sheet S15843EJ3V0DS
µPD160061
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format : 6 bits x 2 RGBs (6 dots)
Input width : 36 bits (2-pixel data)
(1) R,/L = H (Right shift)
Output
Data
S1
S2
S3
S4
...
S383
S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
...
D40 to D45
D50 to D55
(2) R,/L = L (Left shift)
Output
Data
S1
S2
S3
S4
...
...
S383
S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
S2n–1Note
S2nNote
POL
L
V0 to V4
V5 to V9
V5 to V9
V0 to V4
H
Note S2n–1 (Odd output), S2n (Even output)
9
Data Sheet S15843EJ3V0DS
µPD160061
7. RELATIONSHIP BETWEEN STB CLK AND OUTPUT WAVEFORM
Figure 7–1. Input Circuit Block Diagram
Output AMP.
-
+
DAC
SW1
Sn
(V
X
)
VAMP(IN)
Figure 7–2. Output Circuit Timing Waveform
[1]
[1']
CLK
STB
t
STB-CLK
SW1: OFF
V
AMP(IN)
Hi-Z
S
n
(VX)
STB = H is loaded with the rising edge of CLK[1]. However, when not satisfying the specification of fSTB-CLK, STB = H is
loaded with the rising edge of the next CLK[1′]. Latch operation of display data is completed with the falling edge of the
next CLK which loaded STB = H. Therefore, in order to complete latch operation of display data, it is necessary to input
at least 2 CLK in STB = H period. Besides, after loading STB=H to the timing of [1], it is necessary to continue inputting
CLK.
10
Data Sheet S15843EJ3V0DS
µPD160061
8. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM
When the STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in synchronization
with the falling edge of STB.
Therefore, high drive time of the output amplifier as below is determined by the CLK number of the required SRC pin
setting. Be sure to avoid using such as extremely changing the CLK frequency (ex. CLK stop).
STB
High drive time
High drive time
High drive time
Inside bias current
POL
V
0
- V
4
V
5
- V
9
V
5
- V
9
Vx (odd output)
Vx (even output)
V5
- V9
V0
- V4
V0
- V4
Hi-Z
Hi-Z
Hi-Z
9. SRC AND HIGH DRIVE TIME
The µPD160061 can control high drive time of the output amplifier by SRC pin logic (refer to below figure).
SRC = H or open (high drive time: standard mode): High drive time (PWhp) of the output amplifier is in 64 CLK
period from falling edge of the STB.
SRC = L (high drive time: long-term mode): High drive time (PWhp) of the output amplifier is in 128 CLK period
from falling edge of the STB.
STB
CLK
PWhp
Inside bias current
We recommend a thorough simulation of the output amplifier in advance when set the SRC pin.
11
Data Sheet S15843EJ3V0DS
µPD160061
10. BIAS CURRENT CONTROL BY LPC AND HPC
The µPD160061 can control the bias current of the output amplifier in high drive period and low drive period.
Bias Current
High
LPC
HPC
Panel Load
Heavy
H
L
★
Middle
Normal
Low
L or open
L or open
H
L
H or open
H or open
Light
We recommend a thorough simulation of the output amplifier in advance, when set the LPC and HPC pins.
Refer to the table below for the example of the combination of setting level and panel load, with driver part supply voltage.
Example of Condition
Load: RL = 5 kΩ, CL = 75 pF
LPC
L or open
Bias current mode: Middle
HPC
SRC
Example 1
Example 2
Example 3
L
H or open
H or open
L
Driver part supply voltage: VDD2 = 7.5 V
Load: RL = 5 kΩ, CL = 75 pF
L or open
H or open
Driver part supply voltage: VDD2 = 9.0 V
Load: RL = 40 kΩ, CL = 80 pF
Bias current mode: Normal
H
L
Driver part supply voltage: VDD2 = 9.0 V
Bias current mode: High
12
Data Sheet S15843EJ3V0DS
µPD160061
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Rating
Unit
V
Logic Part Supply Voltage
Driver Part Supply Voltage
Logic Part Input Voltage
Driver Part Input Voltage
Logic Part Output Voltage
Driver Part Output Voltage
VDD1
–0.5 to +4.0
VDD2
VI1
–0.5 to +10.0
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–10 to +75
V
V
VI2
V
VO1
VO2
V
V
Operating Ambient Temperature TA
°C
°C
Storage Temperature
Tstg
–55 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
2.3
TYP.
8.5
MAX.
3.6
Unit
V
Logic Part Supply Voltage
Driver Part Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
γ -Corrected Voltage
VDD1
VDD2
7.5
9.5
V
VIH
0.7 VDD1
0
VDD1
V
VIL
0.3 VDD1
VDD2 – 0.2
0.5 VDD2 – 0.3
0.5 VDD2
VDD2 – 0.2
40
V
V0 to V4
V5 to V9
7.5 V ≤ VDD1 ≤ 9.5 V
7.5 V ≤ VDD1 < 8.5 V
8.5 V ≤ VDD1 ≤ 9.5 V
0.5 VDD2
0.2
V
V
0.2
V
Driver Part Output Voltage
Clock Frequency
VO
0.2
V
fCLK
2.3 V ≤ VDD1 < 2.7 V
2.7 V ≤ VDD1 ≤ 3.6 V
MHz
MHz
65
13
Data Sheet S15843EJ3V0DS
µPD160061
Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 7.5 to 9.5 V, VSS1 = VSS2 = 0 V)
Parameter
Input Leak Current
Symbol
Condition
Except LPC, HPC, SRC
LPC, HPC, SRC
MIN.
TYP.
MAX.
1.0
150
Unit
µA
µA
V
IIL
High-Level Output Voltage
Low-Level Output Voltage
γ -Corrected Resistance
Driver Output Current
VOH
VOL
Rγ
IVOH
IVOL
∆VO
STHR (STHL), IOH = 0 mA
VDD1 – 0.1
7.9
STHR (STHL), IOL = 0 mA
0.1
23.7
– 20
V
V0 to V4 = V5 to V9 = 4.0 V, VDD2 = 8.5 V
VDD2 = 8.0 V, VX = 7.0 V, VOUT = 6.5 V Note1
VDD2 = 8.0 V, VX = 1.0 V, VOUT = 1.5 V Note1
TA = 25°C,
VDD1 = 3.3 V, VDD2 = 8.5 V,
VOUT = 2.0 V, 4.25 V, 6.5 V
15.8
kΩ
µA
µA
mV
20
Output Voltage Deviation
10
3
20
15
Output Swing Difference
Deviation
∆VP–P
mV
Logic Part Dynamic Current
IDD1
VDD1
4
12
8
mA
Consumption Note2, 3, 4
Driver Part Dynamic Current IDD22
Consumption Note2, 4
VDD2, with no load
3.5
mA
Notes 1. VX refers to the output voltage of analog output pins S1 to S384. VOUT refers to the voltage applied to analog
output pins S1 to S384.
2. Specified at fSTB = 65 kHz and fCLK = 54 MHz.
3. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in
the dot checkerboard input pattern.
4. Refers to the current consumption per driver when cascades are connected under the assumption of XGA
single-sided mounting (8 units).
Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 7.5 to 9.5 V, VSS1 = VSS2 = 0 V)
Parameter
Start Pulse Delay Time
Symbol
Condition
MIN.
TYP.
MAX.
20
10.5
20
10.5
5
Unit
ns
ns
ns
ns
µs
µs
µs
µs
pF
tPLH1
CL = 15 pF, 2.3 V ≤ VDD1 < 2.7 V
CL = 10 pF, 2.7 V ≤ VDD1 ≤ 3.6 V
CL = 10 pF, 2.3 V ≤ VDD1 < 2.7 V
CL = 10 pF, 2.7 V ≤ VDD1 ≤ 3.6 V
CL = 75 pF, RL = 5 kΩ,
tPLH1
Driver Output Delay Time
Input Capacitance
tPLH2
tPLH3
tPHL2
tPHL3
CI1
LPC = L or open,
8
★
HPC = H or open,
SRC = H or open
5
8
Logic input of exclude STHR (STHL),
TA = 25°C
10
CI2
STHR (STHL), TA = 25°C
5
pF
<Measurement condition>
RLn = 1 kΩ, CLn = 15 pF
The measurement point
RL1
RL2
RL3
RL4
RL5
Output
CL1
CL2
CL3
CL4
CL5
GND
14
Data Sheet S15843EJ3V0DS
µPD160061
Timing Requirements (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Clock Pulse Width
Symbol
Condition
2.3 V ≤ VDD1 < 2.7 V
2.7 V ≤ VDD1 ≤ 3.6 V
2.3 V ≤ VDD1 < 2.7 V
2.7 V ≤ VDD1 ≤ 3.6 V
2.3 V ≤ VDD1 < 2.7 V
2.7 V ≤ VDD1 ≤ 3.6 V
MIN.
25
15
6
TYP.
MAX.
Unit
ns
PWCLK
ns
Clock Pulse High Period
Clock Pulse Low Period
PWCLK(H)
PWCLK(L)
ns
4
ns
6
ns
4
ns
Data Setup Time
tSETUP1
tHOLD1
4
ns
Data Hold Time
0
ns
Start Pulse Setup Time
Start Pulse Hold Time
POL21, POL22 Setup Time
POL21, POL22 Hold Time
STB Pulse Width
tSETUP2
tHOLD2
4
ns
0
ns
tSETUP3
tHOLD3
4
ns
0
ns
PWSTB
tLDT
2
CLK
CLK
ns
Last Data Timing
2
STB-CLK Time
tSTB -CLK
tSTB-STH
tPOL-STB
tSTB-POL
STB ↑→ CLK ↑
9
Time Between STB and Start Pulse
POL-STB Time
STB ↑ → STHR(STHL) ↑
POL ↑ or ↓ → STB ↑
STB ↓ → POL ↓ or ↑
2
CLK
ns
–5
6
STB-POL Time
ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
15
Data Sheet S15843EJ3V0DS
CLK(H)
r
f
PWCLK(L) PWCLK
PW
3
t
t
1
2
V
V
DD1
SS1
90%
1
2
64
65
66
CLK
10%
STB-CLK
tSETUP2 tHOLD2
t
V
V
DD1
SS1
STHR
(1st Dr.)
tSETUP1 tHOLD1
t
STB-STH
V
V
DD1
SS1
D373 to
D378
D379 to
D385
D
390
Last
Data
to
n0
n5
D
to D
D1to D6
INVALID
INVALID
D
1
to D
6
D7toD12
INVALID
12
D7to D
384
D
tSETUP3 tHOLD3
V
V
DD1
SS1
POL21,
POL22
INVALID
tPLH1
V
V
DD1
SS1
STHL
(1st Dr.)
tLDT
PWSTB
V
V
DD1
SS1
STB
POL
tSTB-POL
tPOL-STB
V
V
DD1
SS1
tPLH3
Hi-Z
t
PLH2
+
Target Voltage:
10%
−
Sn
(VX)
+
Target Voltage:
2%
−
µ
PHL2
PHL3
t
t
µPD160061
12. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the µPD160061.
For more details, refer to the Semiconductor Device Mount Manual
(http://www.necel.com/pkg/en/mount/index.html).
Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under
different conditions.
µ PD160061N - ×××: TCP (TAB package)
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C, heating for 2 to 3 seconds, pressure 100 g (per
solder)
ACF
Temporary bonding 70 to 100°C, pressure 3 to 8 kg/cm2, time 3 to 5
(Adhesive Conductive
Film)
seconds.
Real bonding 165 to 180°C, pressure 25 to 45 kg/cm2, time 30 to 40
seconds. (When using the anisotropy conductive film SUMIZAC1003 of
Sumitomo Bakelite, Ltd.)
Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing
company. Be sure to avoid using two or more mounting methods at a time.
17
Data Sheet S15843EJ3V0DS
µPD160061
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
18
Data Sheet S15843EJ3V0DS
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