UPD16488AP [NEC]
1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM; 1/92 DUTY LCD控制器/驱动器，四级灰度，片上RAM
| 型号： | UPD16488AP |
| 厂家： | 
NEC |
| 描述： | 1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM |
| 文件： | 总91页 (文件大小：2618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
PD16488A
1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
DESCRIPTION
The µPD16488A is a controller/driver which includes display RAM for full-dot LCDs that can provide a four-level gray
scale display. This IC is able to drive full-dot LCDs that contain up to 128 x 92 dots.
FEATURES
• LCD controller/driver with on-chip display RAM
• Full dot outputs: 128 segment outputs and 92 common outputs
• Can operate using single power supply (logic system) in range from 1.7 to 3.6 V.
• Selection of four levels of gray scales from among 33 possible levels (four-frame rate control + 8 pulse width
modulation)
• Serial data input and 8-bit parallel data input (i80 series interface and M68 series interface)
• Dot display RAM: 128 x 128 x 2 bits
• On-chip booster: Switchable from x2 to x9 modes
• Selectable bias levels: 1/12 to 1/7 bias (normal display), 1/6 or 1/5 bias (partial display)
• Duty settings: 1/92 to 1/1 duty
• On-chip voltage divider resistor
• On-chip oscillator
ORDERING INFORMATION
Part Number
µPD16488AP
µPD16488AW
Package
Chip
Wafer
Remark Purchasing the chip/wafer entails the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representative.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15745EJ2V0DS00 (2nd Edition)
Date Published December 2001 NS CP(K)
2001
The mark shows major revised points.
µPD16488A
TABLE OF CONTENTS
1. BLOCK DIAGRAM....................................................................................................................................... 5
2. PIN CONFIGURATION (PAD LAYOUT) ..................................................................................................... 6
3. PIN FUNCTIONS.......................................................................................................................................... 9
3.1 Power Supply System Pins................................................................................................................................ 9
3.2 Logic System Pins............................................................................................................................................ 10
3.3 Driver-Related Pins........................................................................................................................................... 13
3.4 Test Pins........................................................................................................................................................... 13
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS...................................... 14
5. DESCRIPTION OF FUNCTIONS............................................................................................................... 15
5.1 CPU Interface.................................................................................................................................................... 15
5.1.1 Selection of interface type ...................................................................................................................... 15
5.1.2 Parallel interface..................................................................................................................................... 15
5.1.3 Serial interface........................................................................................................................................ 16
5.1.4 Chip select.............................................................................................................................................. 16
5.1.5 Display data RAM and on-chip register access ...................................................................................... 16
5.2 Display Data RAM............................................................................................................................................. 19
5.2.1 Display data RAM................................................................................................................................... 19
5.2.2 X address circuit..................................................................................................................................... 19
5.2.3 Column address circuit........................................................................................................................... 21
5.2.4 Y address circuit..................................................................................................................................... 21
5.2.5 Common scan circuit.............................................................................................................................. 21
5.2.6 Display start line set ............................................................................................................................... 21
5.2.7 Display data latch circuit......................................................................................................................... 21
5.3 Blink/Reverse Display Circuit.......................................................................................................................... 22
5.4 Oscillator........................................................................................................................................................... 24
5.5 Display Timing Generator................................................................................................................................ 28
5.6 Power Supply Circuit ....................................................................................................................................... 30
5.6.1 Booster ................................................................................................................................................... 30
5.6.2 Voltage regulator .................................................................................................................................... 32
5.6.3 Use of op amp for level power supply control......................................................................................... 35
5.6.4 Application examples of power supply circuits........................................................................................ 36
5.7 LCD Display Drivers......................................................................................................................................... 39
5.7.1 Full-dot pulse width modulation .............................................................................................................. 39
5.7.2 Full-dot frame rate control....................................................................................................................... 44
2
Data Sheet S15745EJ2V0DS
µPD16488A
5.7.3 Line shift driver ....................................................................................................................................... 45
5.7.4 Display size settings............................................................................................................................... 47
5.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position........................................ 47
5.8 Display Modes .................................................................................................................................................. 49
5.8.1 Partial display mode ............................................................................................................................... 49
5.8.2 Monochrome (black/white) display ......................................................................................................... 51
5.9 Reset.................................................................................................................................................................. 53
6. COMMAND REGISTERS........................................................................................................................... 54
6.1 Control Register 1 (R0)...................................................................................................................................... 55
6.2 Control Register 2 (R1)...................................................................................................................................... 56
6.3 Reset Command (R2)......................................................................................................................................... 57
6.4 X Address Register (R3).................................................................................................................................... 57
6.5 Y Address Register (R4).................................................................................................................................... 57
6.6 Duty Setting Register (R5) ................................................................................................................................ 58
6.7 AC Driver Inversion Cycle Register (R6).......................................................................................................... 59
6.8 AC Driver Inversion Position Shift Register (R7) ............................................................................................ 59
6.9 Partial AC Driver Inversion Cycle Register (R8).............................................................................................. 60
6.10 Partial AC Driver Inversion Position Shift Register (R9) .............................................................................. 60
6.11 Partial Display Mode Setting Register (R10) ................................................................................................. 61
6.12 Display Memory Access Register (R11)......................................................................................................... 61
6.13 Display Start Line Setting Register (R12) ...................................................................................................... 62
6.14 Blink X Address Register (R13) ...................................................................................................................... 62
6.15 Blink Start Line Address Register (R14)........................................................................................................ 62
6.16 Blink End Line Address Register (R15) ......................................................................................................... 62
6.17 Blink Data Memory Access Register (R16).................................................................................................... 63
6.18 Inverted X Address Register (R17)................................................................................................................. 63
6.19 Inversion Start Line Address Register (R18)................................................................................................. 63
6.20 Inversion End Line Address Register (R19) .................................................................................................. 64
6.21 Inverted Data Memory (R20)............................................................................................................................ 64
6.22 Partial Start Line Address Register (R21)...................................................................................................... 64
6.23 Gray Scale Data Registers 1 to 4 (R23 to R26).............................................................................................. 65
6.24 Partial Gray Scale Data Registers 1 to 4 (R27 to R30) .................................................................................. 65
6.25 Power System Control Register 1 (R32) ........................................................................................................ 66
6.26 Power System Control Register 2 (R33) ........................................................................................................ 67
6.27 Power System Control Register 3 (R34) ........................................................................................................ 68
6.28 Electronic Volume Register (R35) .................................................................................................................. 69
6.29 Partial Electronic Volume Register (R36) ...................................................................................................... 69
6.30 Boost Adjustment Register (R37)................................................................................................................... 69
6.31 RAM Test Mode Setting Register (R44).......................................................................................................... 70
6.32 Signature Read Register (R45) ....................................................................................................................... 70
3
Data Sheet S15745EJ2V0DS
µPD16488A
7. LIST OF µPD16488A REGISTERS ........................................................................................................... 71
8. POWER SUPPLY SEQUENCE ................................................................................................................. 72
8.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON ¡ Display ON) .................. 72
8.2 Power OFF Sequence (When Using On-Chip Power Supply) ........................................................................ 73
8.3 Power ON Sequence (When Using External Driver Power Supply, Power ON → Display ON) ................... 73
8.4 Power Supply OFF Sequence (When Using External Driver Power Supply) ................................................ 74
8.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF) ............................................................................... 75
9. USE OF RAM TEST MODE....................................................................................................................... 76
10. ELECTRICAL SPECIFICATIONS............................................................................................................ 77
11. CPU INTERFACE (REFERENCE EXAMPLE) ........................................................................................ 87
4
Data Sheet S15745EJ2V0DS
µPD16488A
1. BLOCK DIAGRAM
SEG128
SEG
1
COM
1
COM92
Common driver
Segment driver
Data
register
Segment
G/S and blink
control
/RES
/CS1
CS2
C86
Display data latch
PSX
/RD(E)
/WR(R,/W)
Common
timing
generator
D
6
7
(SI)
(SCL)
to D
Display data RAM
(128 x 128 x 2 bits)
D
D
I/O
buffer
5
0
RS
M/S
FR
FRSYNC
DOF
Address decoder
SIGIN1
SIGIN2
TSTIFS
TSTRTST
TSTVIHL
TESTOUT
Command decoder
Register
Segment
G/S and blink
timer
OSCIN1
OSCIN2
OSCOUT
OSCSYNC
CLS
Timing generator
Oscillator
circuit
D/A converter
-
+
C1 , C1
DC/DC
converter
Op amp
LCD voltage generator
+
-
C9
,
C9
C1A
V
OUT
V
RS
IRS
V
R
AMPOUTP AMPOUT
V
LCD
V
LC1
V
LC2
V
LC3
V
LC4
V
DD1
V
DD2
VSS
Remark /xxx indicates active low signals.
5
Data Sheet S15745EJ2V0DS
µPD16488A
2. PIN CONFIGURATION (PAD LAYOUT)
Chip size
Chip
: 3.0 x 11.4 mm2
: 485 µm TYP.
403
372
Pad type A : Pad size (AI) : 53 x 73 µm2
Bump size
: 45 x 60 µm2
A4
A1
1
Bump height : 17 µm TYP.
371
Pad type B : Pad size (AI) : 118 x 73 µm2
Bump size : 110 x 60 µm2
Bump height : 17 µm TYP.
Alignment Mark Coordinate
Mark Center Coordinate
X [µm]
−1200.00
−1200.00
1275.00
1275.00
Y [µm]
5300.00
−5300.00
−5475.00
5475.00
M1
M2
M3
M4
Shape of Alignment Mark (unit: µm)
Y
A1,A2
50 50
A3
A4
X
50
100
100
100
163
A1
197
A3
164
196
6
Data Sheet S15745EJ2V0DS
µPD16488A
•ꢀµPD16488A Pad Layout (1/2)
Pad
No.
1
Pin Name
Pad
Type
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Coordinate
Pad
No.
71 VDD1
72 VDD1
73 VSS
74 VSS
75 VSS
76 CLS
77 CLS
78 VDD1
79 M/S
80 M/S
81 VSS
82 C86
83 C86
84 PSX
85 PSX
86 VDD1
87 IRS
88 IRS
Pin Name
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Coordinate
Pad
No.
141 DUMMY
142 DUMMY
143 VSS
144 SIGIN1
145 SIGIN1
146 VDD1
147 SIGIN2
148 SIGIN2
149 VSS
150 TESTOUT
151 TESTOUT
152 TSTIFS
153 TSTIFS
154 TSTRTST
155 TSTRTST
156 TSTVIHL
157 TSTVIHL
158 VSS
Pin Name
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Coordinate
µ
µ
µ
µ
µ
µ
X [ m]
Y [ m]
X [ m]
Y [ m]
X [ m]
Y [ m]
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VSS
VRS
VRS
AMPOUTP
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
5284.00
5154.00
5024.00
4894.00
4796.50
4590.00
4530.00
4470.00
4410.00
4350.00
4290.00
4230.00
4170.00
4110.00
4050.00
3990.00
3930.00
3870.00
3810.00
3750.00
3690.00
3630.00
3570.00
3510.00
3450.00
3390.00
3330.00
3270.00
3210.00
3150.00
3090.00
3030.00
2970.00
2910.00
2850.00
2790.00
2730.00
2670.00
2610.00
2550.00
2490.00
2430.00
2370.00
2310.00
2250.00
2190.00
2130.00
2070.00
2010.00
1950.00
1890.00
1830.00
1770.00
1710.00
1650.00
1590.00
1530.00
1470.00
1410.00
1350.00
1290.00
1230.00
1170.00
1110.00
1050.00
990.00
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
690.00
630.00
570.00
510.00
450.00
390.00
330.00
270.00
210.00
150.00
90.00
30.00
-30.00
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1383.50
-1172.50
-1075.00
-965.00
-905.00
-845.00
-785.00
-725.00
-665.00
-605.00
-545.00
-485.00
-425.00
-365.00
-305.00
-245.00
-185.00
-125.00
-65.00
-3510.00
-3570.00
-3630.00
-3690.00
-3750.00
-3810.00
-3870.00
-3930.00
-3990.00
-4050.00
-4110.00
-4170.00
-4230.00
-4290.00
-4350.00
-4410.00
-4470.00
-4530.00
-4796.50
-4894.00
-5024.00
-5154.00
-5284.00
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5474.76
-5257.50
-5160.00
-5100.00
-5040.00
-4980.00
-4920.00
-4860.00
-4800.00
-4740.00
-4680.00
-4620.00
-4560.00
-4500.00
-4440.00
2
3
4
5
6
7
8
9
10 AMPOUTP
11 AMPOUT
12 AMPOUT
13 VR
14 VR
-90.00
15 VLC4
16 VLC4
17 VLC3
18 VLC3
19 VLC2
20 VLC2
21 VLC1
22 VLC1
23 VLCD
24 VLCD
25 VSS
26 VOUT
27 VOUT
28 VSS
29 C9-
-150.00
-210.00
-270.00
-330.00
-390.00
-450.00
-510.00
-570.00
-630.00
-690.00
-750.00
-810.00
-870.00
-930.00
-990.00
-1050.00
-1110.00
-1170.00
-1230.00
-1290.00
-1350.00
-1410.00
-1470.00
-1530.00
-1590.00
-1650.00
-1710.00
-1770.00
-1830.00
-1890.00
-1950.00
-2010.00
-2070.00
-2130.00
-2190.00
-2250.00
-2310.00
-2370.00
-2430.00
-2490.00
-2550.00
-2610.00
-2670.00
-2730.00
-2790.00
-2850.00
-2910.00
-2970.00
-3030.00
-3090.00
-3150.00
-3210.00
-3270.00
-3330.00
-3390.00
-3450.00
89 VSS
90 /CS1
91 /CS1
92 CS2
159 DUMMY
160 DUMMY
161 DUMMY
162 DUMMY
163 DUMMY
164 DUMMY
165 DUMMY
166 COM47
167 COM48
168 COM49
169 COM50
170 COM51
171 COM52
172 COM53
173 COM54
174 COM55
175 COM56
176 COM57
177 COM58
178 COM59
179 COM60
180 COM61
181 COM62
182 COM63
183 COM64
184 COM65
185 COM66
186 COM67
187 COM68
188 COM69
189 COM70
190 COM71
191 COM72
192 COM73
193 DUMMY
194 DUMMY
195 DUMMY
196 DUMMY
197 DUMMY
198 DUMMY
199 DUMMY
200 COM74
201 COM75
202 COM76
203 COM77
204 COM78
205 COM79
206 COM80
207 COM81
208 COM82
209 COM83
210 COM84
93 CS2
94 VDD1
95 /RES
96 /RES
97 RS
98 RS
99 VSS
100 /WR (R,/W)
101 /WR (R,/W)
102 /RD (E)
103 /RD (E)
104 VDD1
105 D7
106 D7
107 D6
108 D6
109 DUMMY
110 D5
111 D5
112 D4
113 D4
114 DUMMY
115 D3
116 D3
117 D2
118 D2
119 DUMMY
120 D1
121 D1
122 D0
123 D0
124 DUMMY
125 FRSYNC
126 FRSYNC
127 FR
30 C9-
31 C9+
32 C9+
33 C8-
34 C8-
35 C8+
36 C8+
37 C7-
38 C7-
39 C7+
40 C7+
41 C6-
42 C6-
-5.00
55.00
115.00
175.00
235.00
295.00
355.00
415.00
43 C6+
44 C6+
45 C5-
46 C5-
47 C5+
48 C5+
49 C4-
50 C4-
475.00
535.00
595.00
655.00
771.00
906.00
51 C4+
52 C4+
53 C3-
54 C3-
55 C3+
56 C3+
57 C2-
1041.00
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
58 C2-
128 FR
59 C2+
60 C2+
61 C1-
129 DUMMY
130 DOF
131 DOF
132 OSCIN1
133 OSCIN1
134 OSCIN2
135 OSCIN2
136 OSCOUT
137 OSCOUT
138 DUMMY
139 OSCSYNC
140 OSCSYNC
62 C1-
63 C1+
64 C1+
65 C1A
66 C1A
67 VDD2
68 VDD2
69 VDD2
70 VDD1
930.00
870.00
810.00
750.00
7
Data Sheet S15745EJ2V0DS
µPD16488A
•ꢀµPD16488A Pad Layout (2/2)
Pad
No.
Pin Name
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Coordinate
X [µ m] Y [µ m]
Pad
No.
Pin Name
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Coordinate
X [µ m] Y [µ m]
Pad
No.
Pin Name
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
Pad Coordinate
X [µ m]
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1041.00
906.00
Y [µ m]
211 COM85
212 COM86
213 COM87
214 COM88
215 COM89
216 COM90
217 COM91
218 COM92
219 DUMMY
220 SEG128
221 SEG127
222 SEG126
223 SEG125
224 SEG124
225 SEG123
226 SEG122
227 SEG121
228 SEG120
229 SEG119
230 SEG118
231 SEG117
232 SEG116
233 SEG115
234 SEG114
235 SEG113
236 SEG112
237 SEG111
238 SEG110
239 SEG109
240 SEG108
241 SEG107
242 SEG106
243 SEG105
244 SEG104
245 SEG103
246 SEG102
247 SEG101
248 SEG100
249 SEG99
250 SEG98
251 SEG97
252 SEG96
253 SEG95
254 SEG94
255 SEG93
256 SEG92
257 SEG91
258 SEG90
259 SEG89
260 SEG88
261 SEG87
262 SEG86
263 SEG85
264 SEG84
265 SEG83
266 SEG82
267 SEG81
268 SEG80
269 SEG79
270 SEG78
271 SEG77
272 SEG76
273 SEG75
274 SEG74
275 SEG73
276 SEG72
277 SEG71
278 SEG70
279 SEG69
280 SEG68
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
-4380.00
-4320.00
-4260.00
-4200.00
-4140.00
-4080.00
-4020.00
-3960.00
-3900.00
-3840.00
-3780.00
-3720.00
-3660.00
-3600.00
-3540.00
-3480.00
-3420.00
-3360.00
-3300.00
-3240.00
-3180.00
-3120.00
-3060.00
-3000.00
-2940.00
-2880.00
-2820.00
-2760.00
-2700.00
-2640.00
-2580.00
-2520.00
-2460.00
-2400.00
-2340.00
-2280.00
-2220.00
-2160.00
-2100.00
-2040.00
-1980.00
-1920.00
-1860.00
-1800.00
-1740.00
-1680.00
-1620.00
-1560.00
-1500.00
-1440.00
-1380.00
-1320.00
-1260.00
-1200.00
-1140.00
-1080.00
-1020.00
-960.00
281 SEG67
282 SEG66
283 SEG65
284 SEG64
285 SEG63
286 SEG62
287 SEG61
288 SEG60
289 SEG59
290 SEG58
291 SEG57
292 SEG56
293 SEG55
294 SEG54
295 SEG53
296 SEG52
297 SEG51
298 SEG50
299 SEG49
300 SEG48
301 SEG47
302 SEG46
303 SEG45
304 SEG44
305 SEG43
306 SEG42
307 SEG41
308 SEG40
309 SEG39
310 SEG38
311 SEG37
312 SEG36
313 SEG35
314 SEG34
315 SEG33
316 SEG32
317 SEG31
318 SEG30
319 SEG29
320 SEG28
321 SEG27
322 SEG26
323 SEG25
324 SEG24
325 SEG23
326 SEG22
327 SEG21
328 SEG20
329 SEG19
330 SEG18
331 SEG17
332 SEG16
333 SEG15
334 SEG14
335 SEG13
336 SEG12
337 SEG11
338 SEG10
339 SEG9
340 SEG8
341 SEG7
342 SEG6
343 SEG5
344 SEG4
345 SEG3
346 SEG2
347 SEG1
348 DUMMY
349 DUMMY
350 COM46
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
1274.76
-180.00
-120.00
-60.00
0.00
60.00
120.00
180.00
240.00
300.00
360.00
420.00
480.00
540.00
600.00
660.00
720.00
780.00
351 COM45
352 COM44
353 COM43
354 COM42
355 COM41
356 COM40
357 COM39
358 COM38
359 COM37
360 COM36
361 COM35
362 COM34
363 COM33
364 COM32
365 COM31
366 COM30
367 COM29
368 COM28
369 DUMMY
370 DUMMY
371 DUMMY
372 DUMMY
373 DUMMY
374 DUMMY
375 COM27
376 COM26
377 COM25
378 COM24
379 COM23
380 COM22
381 COM21
382 COM20
383 COM19
384 COM18
385 COM17
386 COM16
387 COM15
388 COM14
389 COM13
390 COM12
391 COM11
392 COM10
393 COM9
394 COM8
395 COM7
396 COM6
397 COM5
398 COM4
399 COM3
400 COM2
401 COM1
402 DUMMY
403 DUMMY
4020.00
4080.00
4140.00
4200.00
4260.00
4320.00
4380.00
4440.00
4500.00
4560.00
4620.00
4680.00
4740.00
4800.00
4860.00
4920.00
4980.00
5040.00
5100.00
5160.00
5257.50
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
5474.76
840.00
900.00
960.00
1020.00
1080.00
1140.00
1200.00
1260.00
1320.00
1380.00
1440.00
1500.00
1560.00
1620.00
1680.00
1740.00
1800.00
1860.00
1920.00
1980.00
2040.00
2100.00
2160.00
2220.00
2280.00
2340.00
2400.00
2460.00
2520.00
2580.00
2640.00
2700.00
2760.00
2820.00
2880.00
2940.00
3000.00
3060.00
3120.00
3180.00
3240.00
3300.00
3360.00
3420.00
3480.00
3540.00
3600.00
3660.00
3720.00
3780.00
3840.00
3900.00
3960.00
771.00
595.00
535.00
475.00
415.00
355.00
295.00
235.00
175.00
115.00
55.00
-5.00
-65.00
-125.00
-185.00
-245.00
-305.00
-365.00
-425.00
-485.00
-545.00
-605.00
-665.00
-725.00
-785.00
-845.00
-905.00
-965.00
-1075.00
-1172.50
-900.00
-840.00
-780.00
-720.00
-660.00
-600.00
-540.00
-480.00
-420.00
-360.00
-300.00
-240.00
8
Data Sheet S15745EJ2V0DS
µPD16488A
3. PIN FUNCTIONS
3.1 Power Supply System Pins
Symbol
Name
Pad No.
I/O
Description
Power supply pin for logic circuit
VDD1
VDD2
VSS
Logic power supply 70-72, 78, 86, 94,
−
pin
104, 146
67-69
Boost circuit
power supply pin
Logic and driver
ground pin
Driver power
supply pin
−
−
−
Power supply pin for booster
6, 25, 28, 73 to 75, 81,
89, 99, 143, 149, 158
26, 27
Ground pin for logic and driver circuits
VOUT
Power supply pin for driver. Output pin for on-chip booster.
Connect a 1 µF boost capacitor between this pin and the GND
pin.
If not using the on-chip booster, a direct driver power supply can
be input.
VLCD,
Reference power
24, 23,
22 to 15
−
−
These are reference power supply pins for the LCD driver.
Connect a capacitor between these pins and the GND pin if an
internal bias has been selected.
These are capacitor connection pins for the booster. When
using the on-chip booster, connect a 1 µF capacitor between
positive (+) and negative (-) pins.
VLC1 to VLC4 supply pins for
driver
C1+, C1−
C2+, C2−
C3+, C3−
C4+, C4−
C5+, C5−
C6+, C6−
C7+, C7−
C8+, C8−
C9+, C9−
C1A
Boost capacitor
connection pins (1)
64, 63, 62, 61
60, 59, 58, 57
56, 55, 54, 53
52, 51, 50, 49
48, 47, 46, 45
44, 43, 42, 41
40, 39, 38, 37
36, 35, 34, 33
32, 31, 30, 29
65, 66
Boost capacitor
connection pin (2)
−
This is a capacitor connection pin for boost adjustment. When
using the on-chip booster, connect a 1 µF capacitor between
this pin and the GND pin.
9
Data Sheet S15745EJ2V0DS
µPD16488A
3.2
Logic System Pins
(1/3)
Symbol
Name
Pad No.
84, 85
I/O
Description
PSX
Data transfer
selection
Input
This pin is used to select between parallel data input and serial
data input.
PSX = H: Parallel data input
PSX = L: Serial data input
/CS1,
CS2
Chip select
90, 91,
92, 93
Input
Input
These pins are used for chip select signals. When /CS1 = L
(CS2 = H), the chip is active and can perform data input/output
operations including command and data I/O.
When i80 series parallel data transfer (/RD) has been selected,
the signal at this pin is used to enable read operations. Data is
output to the data bus only when this pin is L.
When M68 series parallel data transfer (E) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the falling edge of this signal.
/RD
(E)
Read
(enable)
102, 103
/WR
(R,/W)
Write
(read/write)
100, 101
Input
When i80 series parallel data transfer (/WR) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the rising edge of this signal.
When 68 series parallel data transfer (R,/W) has been selected,
this pin is used to determine the direction of data transfer.
L: Write
H: Read
C86
Interface selection
82, 83
Input
I/O
This pin is used to switch between interface modes (i80 series
CPU or M68 series CPU).
L: Selects i80 series CPU mode
H: Selects M68 series CPU mode
D0 to D5,
D6 (SCL)
D7 (SI)
Data bus
(serial clock)
(serial input)
105 to 108, 110 to 113,
115 to 118,
These pins comprise an 8-bit bidirectional data bus that
connects to an 8-bit or 16-bit standard CPU bus.
When the serial interface has been selected (PSX = L), D6
functions as a serial clock input pin (SCL) and D7 functions as a
serial data input pin (SI). In either case, pins D0 to D5 are in
high impedance mode.
120 to 123
When the chip is not selected, D0 to D7 are in high impedance
mode.
RS
Index
97, 98
95, 96
Input
Input
Usually, this pin is connected to the LSB of the standard CPU
address bus and is used to distinguish between data from index
registers and data/commands.
RS = H: Indicates that data from D0 to D7 is data/command
RS = L : Indicates that data from D0 to D7 is index register
contents
register/data,
command
selection
/RES
Reset
When /RES is low, an internal reset is performed. The reset
operation is executed at the /RES signal level.
10
Data Sheet S15745EJ2V0DS
µPD16488A
(2/3)
Symbol
CLS
Name
Pad No.
76, 77
I/O
Description
Select clock
division
Input
This pin is used to select whether or not to use the divider within
the display clock oscillator.
CLS = H: Use divider
CLS = L: Do not use divider
When using an external clock, the CLS = L setting is input via
the OSCIN1 and OSCIN2 pins as normal and partial clocks
respectively.
When CLS = H, clock input is via the OSCIN1 pin only.
This pin is used as I/O pin for the LCD's AC conversion signal.
M/S = H: Output
FR
Frame signal
127, 128
125, 126
I/O
I/O
M/S = L: Input
When using the µPD16488A in master/slave mode, both FR
pins must be connected.
This pin is used as I/O pin for the LCD's AC conversion
synchronization signal.
FRSYNC
Frame
synchronization
signal
M/S = H: Output
M/S = L: Input
When the µPD16488A is used in master/slave mode, both
FRSYNC pins must be connected.
This pin is used to control the LCD's display blink function.
M/S = H: Output
M/S = L: Input
When the µPD16488A is used in master/slave mode, both DOF
pins must be connected.
This pin is used to select between master and slave operation
modes. In master operation mode, it outputs the timing signal
required by the LCD driver and in slave operation mode it inputs
this timing signal from an external source for use in LCD display
synchronization.
DOF
M/S
Display blink
Master/slave
I/O
130, 131
79, 80
Input
M/S = H: Master operation mode
M/S = L: Slave operation mode
Settings dependent on the M/S mode are listed in the following
chart.
Power
supply circuit
M/S
FR
FRSYNC
DOF
H
L
Valid
Invalid
Output
Input
Output
Input
Output
Input
IRS
VLCD regulation
Input
Input
This pin is used to select the resistor that is used for VLCD
voltage regulation.
IRS = H: Uses internal resistor
87, 88
IRS = L: Does not use internal resistor. The VLCD voltage level
is regulated using the external voltage division resistor that is
connected to the VR pin.
This pin is valid only in master operation mode. In slave
operation mode, this pin is fixed high or low level.
These pins can be used to set a unique signature for the IC. The
signal set via these pins can subsequently be read from the
signature read register (R45).
SIGIN1,
SIGIN2
Signature setting
pins
144, 145,
147, 148
11
Data Sheet S15745EJ2V0DS
µPD16488A
(3/3)
Symbol
OSCIN1
Name
Pad No.
132, 133
I/O
Description
Oscillation signal
pins
Input
A resistor can be inserted between OSCIN1-OSCOUT, and
OSCIN2-OSCOUT. When using an external oscillator, a clock
signal is input via the OSCIN pins according to the CLS pin's
status and the OSCOUT pin is left unconnected.
The wiring between OSCIN1-OSCOUT and OSCIN2-OSCOUT must
be as short as possible, and use after proper evaluation.
OSCIN2
Input
134, 135
136, 137
139, 140
OSCOUT
OSCSYNC
Output
Display clock
output
Output Display clock output pin.
See 5. 4 Oscillator concerning use or this pin when the
µPD16488A is in master or slave operation mode.
12
Data Sheet S15745EJ2V0DS
µPD16488A
3.3
Driver-Related Pins
Symbol
Name
Segment
Pad No.
347-220
I/O
Description
SEG1 to
SEG128
COM1 to
COM92
VRS
Output Segment output pins
Common
166 to 192, 200 to 218, Output Common output pins
350 to 368, 375 to 401
Op amp input pin
for regulating the
driving voltage of
the LCD
7, 8
Input
VRS is an op amp input pin for regulating the driving voltage of
the LCD. This is a reference voltage input for the LCD voltage
regulation amplifier.
When using the internal drive circuit (i.e., when OP1 = 1), we
recommend inserting a 0.1 to 1 µF capacitor between this pin
and GND.
VR
Input pin for the op
amp's feedback
connection
13, 14
Input
VR is an input for the op amp's feedback connection. Insert this
pin between GND and AMPOUT when using the feedback resistor
for this input.
This pin is valid only when not using an internal resistor for VLCD
voltage regulation (i.e., when IRS = L). This pin cannot be used
when using the internal resistor for VLCD voltage regulation (i.e.,
when IRS = H).
AMPOUT
AMPOUTP
DUMMY
Op amp output
9, 10
Output These are op amp output pins for regulating the driving voltage
of the LCD. When not using an internal resistor for VLCD voltage
regulation (i.e., when IRS = L), these outputs are connected to
the LCD drive voltage regulation resistor (see 5.6.2 Voltage
regulator).
11, 12
We recommend inserting a 0.01 to 0.1 µF capacitor between
these pins in order to stabilize the internal op amp's output.
Dummy pin
1 to 5, 109, 114, 119,
124, 129, 138, 141,
142, 159 to 165,
193 to 199, 219, 348,
349, 369 to 374, 402,
403
−
Dummy pin.
These pins are not connected inside IC. Usually, leave these
pins open.
3.4
Test Pins
Symbol
Name
Pad No.
I/O
Description
TSTIFS
Test input
152, 153,
154, 155,
156, 157
150, 151
Input
These pins are used to set a test mode for the IC.
Normally, connect these pins to VSS.
TSTRTST
TSTVIHL
TESTOUT
Test output
Output These pins are used when the IC is in test mode.
Usually, leave them open.
13
Data Sheet S15745EJ2V0DS
µPD16488A
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit type of each pin and recommended connection of unused pins are described below.
Pin Name
PSX
/CS1
CS2
Input Type
Schmitt trigger
Filter
Filter
Filter
Input/output
Input
Recommended Connection of Unused Pins
Mode setting pin.
Connect to VSS.
Notes
Note 1
Input
Input
Input
−
−
−
Connect to VDD1.
/RD(E)
Connect to VDD1 (i80 series interface), connect to VDD1
or VSS (serial interface).
Connect to VDD1 or VSS (serial interface).
Mode setting pin.
/WR(R,/W)
C86
D0 to D5
D6(SCL)
D7(SI)
Filter
Schmitt trigger
Filter
Filter
Filter
Input
Input
Input/output
Input/output
Input/output
Input
−
Note 1
−
Leave open
−
−
−
−
RS
Filter
Register setting pin.
Note 2
/RES
CLS
FR
FRSYNC
DOF
Schmitt trigger
Schmitt trigger
CMOS
CMOS
CMOS
Schmitt trigger
Schmitt trigger
Schmitt trigger
Schmitt trigger
Schmitt trigger
Schmitt trigger
−
Input
Input
Input/output
Input/output
Input/output
Input
Connect to VDD1.
Mode setting pin
Leave open (using master mode, M/S = H).
Leave open (using master mode, M/S = H).
Leave open (using master mode, M/S = H).
Mode setting pin.
−
Note 1
−
−
−
M/S
IRS
Note 1
Note 1
Input
Input
Input
Input
Mode setting pin.
SIGIN1
SIGIN2
OSCIN1
OSCIN2
OSCOUT
OSCSYNC
TSTIFS
TSTRTST
TSTVIHL
TESTOUT
Connect to VDD1 or VSS.
Connect to VDD1 or VSS.
−
−
−
−
−
−
−
−
−
−
Input
Connect to VDD1 or VSS (CLS = H)
Leave open (when using external clock)
Leave open
Connect to VSS (during normal use)
Connect to VSS (during normal use)
Connect to VSS (during normal use)
Leave open
Output
Output
Input
Input
Input
−
Schmitt trigger
Schmitt trigger
Schmitt trigger
－
Output
Notes 1. Connect to either VDD1 or VSS, depending on the mode setting.
2. Input either VDD1 or VSS output from CPU, depending on the mode setting.
14
Data Sheet S15745EJ2V0DS
µPD16488A
5. DESCRIPTION OF FUNCTIONS
5.1 CPU Interface
5.1.1 Selection of interface type
The µPD16488A chip transfers data using an 8-bit bidirectional data bus (D7 to D0) or a serial data input (SI). Setting the
polarity of the PSX pin as either H (high) or L (low) selects between 8-bit parallel or serial data input, as shown in the
following table.
PSX
CS
CS
CS
RS
RS
RS
/RD
/RD
/WR
/WR
C86
C86
D7
D7
SI
D6
D6
SCL
D5 to D0
H: Parallel input
L: Serial input
D5 to D0
Hi-Z Note2
Note1 Note1 Note1
Notes 1. Fixed as either High or Low.
2. Hi-Z: High impedance
5.1.2 Parallel interface
When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct connection
to an i80 series or M68 series CPU (see table below).
C86
/CS1
/CS1
/CS1
CS2
CS2
CS2
RS
RS
RS
/RD
E
/RD
/WR
R,/W
/WR
D7 to D0
D7 to D0
D7 to D0
H: M68 series CPU
L: i80 series CPU
The data bus signal is identified according to the combination of the RS, /RD(E), and /WR(R,/W) signals, as shown in the
following table.
Common
M68
i80
Function
RS
1
1
0
0
R,/W
/RD
0
1
0
1
/WR
1
0
1
0
1
0
1
0
Reads display data and registers
Writes display data and registers
Prohibited
Writes to index register
15
Data Sheet S15745EJ2V0DS
µPD16488A
5.1.3 Serial interface
When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI) and
serial clock input (SCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial
clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to
parallel data for processing. RS input is used to judge serial input data as display data or command data: when RS = H the
data is display/command data and when RS = L the data is index data. When the chip enters active mode, RS input is read
at the rising edge after every eighth serial clock and is then used to judge the serial input data. The serial interface signal
chart is shown below.
Figure 5-1. Serial Interface Signal Chart
CS2 = H
/CS1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
SI
SCL
RS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings.
2. The data read function is disabled during serial interface mode.
3. When using SCL wiring, take care concerning the possible effects of terminating reflection and
noise from external sources. We recommend checking operation with the actual device.
5.1.4 Chip select
The µPD16488A has two chip select pins (/CS1 and CS2). The CPU parallel interface or serial interface can be used only
when /CS1 = L and CS2 = H. When chip select is inactive, P0 to P7 are set to high impedance (invalid) and input of RS, /RD,
or /WR is not active. If serial interface mode has been set, the shift register and counter are both reset.
5.1.5 Display data RAM and on-chip register access
Because only the required cycle time (tcyc) is satisfied when accessing the µPD16488A from the CPU, high-speed data
transfer is possible. There is no need to consider any wait time. No dummy data is needed when writing data. Even when
data is read, there is no need for dummy data except in the display memory access register (R11).
In other words, dummy data is required only when reading data from the display memory access register (R11).
Figure 5-2 illustrates this relationship.
16
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-2. Write and Read (1/2)
Write
<CPU>
/WR
DATA
N
N + 1
N + 2
N + 3
<Internal timing>
Latch
BUS
holder
N
N + 1
N + 2
N + 3
Write
signal
Read (display memory access register (R11))
<CPU>
/WR
/RD
N
N
n
n + 1
DATA
<Internal timing>
Address
preset
Read
signal
Column
address
N + 2
Preset N
Increment N + 1
BUS
holder
N
n
n + 1
n + 2
Address set
#n
Dummy read
Data read
#n
Data read
#n + 1
17
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-2. Write and Read (2/2)
Read (other than display memory access register)
<CPU>
/WR
/RD
IRn + 1
Data
IRn
IRn data
IRn+1
DATA
IR address
set #n
IRn register
data read
IR address
set #n + 1
IRn + 1 register
data read
18
Data Sheet S15745EJ2V0DS
µPD16488A
5.2
Display Data RAM
5.2.1 Display data RAM
This is the RAM that is used to store the display's dot data. The RAM configuration is 256 bits (32 x 8 bits) x 128 bits. Any
specified bit can be accessed by selecting the corresponding X address and Y address. D0 to D7 are the display data sent
from the CPU, and correspond to SEGx on the LCD display (see Figure 5-3).
The CPU writes data to and reads data from the display RAM via the I/O buffer, and these read/write operations are
independent of the signal read operations for the LCD driver. Accordingly, there are no adverse effects (such as flicker) in
the LCD display when display data RAM is accessed asynchronously.
Figure 5-3. Display Data RAM
MSB
D7
LSB
D0
D6
D5
D4
D3
D2 D1
Pixel 1
Pixel 2
Pixel 3
Pixel 4
LCD panel
Pixel 1
Pixel 1
Pixel 2
Pixel 2
Pixel 3
Pixel 3
Pixel 4
Pixel 4
Pixel 1
Pixel 1
Pixel 2
Pixel 2
Pixel 3
Pixel 3
Pixel 4
Pixel 4
X address 00H
X address 01H
D7 D6 D5 D4
SEG1 SEG2
COM0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
COM1
COM2
COM3
COM4
Display data
LCD display
5.2.2 X address circuit
As shown in Figure 5-4, the display data RAM's X address is specified via the X address register (R3). When using X
address increment mode (INC = 0: control register 2 (R1)), the specified X address is incremented (by 1) each time a
display data read or write operation is executed. The CPU is able to continuously access the display data. The X address is
incremented to 1FH, after which the Y address is incremented after each read or write operation and the X address is set
back to 00H.
For monochrome (black-and-white) display, the X address is incremented to 0FH, after which the Y address is
incremented after each read or write operation and the X address is set back to 00H.
19
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-4. Configuration of X Address Register
D4
D3
D2
D1
0
0
0
1
1
1
1
1
0
0
0
0
0
COM output
COM1
D0
0
1
Yaddress
00H
01H
1FH
Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
Start
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
92-line
COM83
COM84
COM85
COM86
COM87
COM88
76H
77H
78H
79H
7AH
7BH
7CH
7DH
COM89
COM90
COM91
COM92
7EH
7FH
20
Data Sheet S15745EJ2V0DS
µPD16488A
5.2.3 Column address circuit
When displaying the contents of the display data RAM, the column address corresponds to the SEG output, as shown in
Figure 5-4.
As is shown in Table 5-1, the correspondence between the display RAM's column address and segment output can be
inverted using the ADC flag in control register 1 (R0) (segment driver direction selection flag). This reduces the constraints
on chip layout when assembling the LCD module.
Table 5-1. Relationship between Column Address and SEG Output
SEG Output
SEG1
00H
SEG128
7FH
0
1
→
←
Column address
Column address
→
←
ADC
(D1)
7FH
00H
5.2.4 Y address circuit
As is shown in Figure 5-4, the Y address register (R4) is used to specify the display data RAM's Y address. When using
Y address increment mode (INC = 1: control register 2 (R1)), the specified Y address is incremented (by 1) each time a
display data read or write operation is executed. The CPU is able to continuously access the display data. The Y address
is incremented to 7FH, after which the X address is incremented after each read or write operation and the Y address is set
back to 00H.
5.2.5 Common scan circuit
The common scan circuit sets the scan lines for common signals. The scan direction is set using the COMR flag in control
register 1 (R0), as shown in Table 5-2.
For example, when using 1/80 duty, when COMR = L the scan direction is COM1 → COM80 and when COMR = H,
the scan direction is COM80 → COM1 using the COM80 to COM1 pins.
Table 5-2. Relationship between Common Scan Circuit and Scan Direction
COMR
(D0)
0
1
COM1
COM92
→
→
COM92
COM1
5.2.6 Display start line set
As is shown in Figure 5-4, display start line set specifies the Y address that corresponds to the COM1 output for displaying
the contents of display data RAM. The display start line setting register (R12) is used to specify the top line in the display.
The screen can be scrolled, overwritten, etc. A 7-bit display start address is set to the display start line setting register.
5.2.7 Display data latch circuit
The display data latch circuit is used for temporary storage of data that is output to the LCD driver from the display data RAM.
The display scan command that sets normal or reverse display mode and the display ON/OFF command control latched
data so that there is no effect on the data in the display data RAM.
21
Data Sheet S15745EJ2V0DS
µPD16488A
5.3
Blink/Reverse Display Circuit
The µPD16488A enables blinking display and reverse display in designated parts of the full dot display. A blinking display
is achieved by cycling ON/OFF (level 0 when four-level gray scale mode has been selected) at approximately 1 Hz and
reverse display is achieved by inverting the display level value.
The area designated for blinking is specified via the blink start/end line address registers (R14 and R15), the blink X
address register (R13), and the blink data memory access register (R16).
First, the blinking display's start and end line addresses are selected via the blink start/end line address registers. Next,
the blink X address register (R13) and the blink data memory (R16) are used to select the column for the blinking display.
The inversion start/end line address registers (R18 and R19), the inverted X address register (R17), and the inverted data
memory access register (R20) are used to select the reverse display area.
First, the inversion start/end line address registers (R18 and R19) are set to select the line addresses where the reverse
display will start and end. Next, the inverted X address register (R17) and the inverted data memory access register (R20)
are used to select the column for the reverse display. The specified blink/inverted X address is incremented (by 1) with
each input of blink/reverse display data.
The blink RAM and inversion RAM, which have a 128 bit (16 x 8 bit) configuration, are used to store data for blinking
display and reverse display respectively. To access the desired bit, simply specify the corresponding X address. The
blink/reverse data (data bits D0 to D7 sent from the CPU) correspond to SEGx on the LCD display, as shown in Figure 5-5.
After the area and data settings are complete, the BLD bit and IVD bit in the control register 1 (R0) are set to H, at which
point the blinking and/or reverse display of data begins. Figure 5-6 illustrates the relationship between the start line address,
end line address, blink/reverse data, and LCD display.
Table 5-3. Inversion Manipulation and Display
Original Level
After Inversion
Four-level gray scale display mode
0, 0
0, 1
1, 0
1, 1
1, 1
1, 0
0, 1
0, 0
B/W display mode
1
0
0
1
Figure 5-5. Correspondence Between Blink/Reverse Data and Segments
D3
D2
D1
D0
0
0
0
0
0
0
1
1
1
0
1
1
00H
01H
0FH
Data
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
22
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-6. Setting Image of Blink/Reverse Display Area
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Blink/revese
data
0 0 1 1 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0
Start line
End line
Blinking or reverse display pixels.
Example of sequence for setting blink/reverse display
Start
Blink/inversion start line
address register
Blink/inversion end line
address register
Blink/inverted
X address register
Blink/inverted
data memory access register
Data
No
Write completed ?
Yes
Control register 1
(BLD, IVD = H)
End
23
Data Sheet S15745EJ2V0DS
µPD16488A
5.4
Oscillator
The µPD16488A include a CR-type oscillator (R external) for normal and partial display, which generates the display
clocks.
The clocks from this oscillator are controlled via the CLS pin and the DTY flag in the control register 2 (R1). The clock
configuration for the display can be set to suit the target system.
The functions of this circuit are described below.
•The oscillator for normal and partial display is enabled only when resistors RN and RP have been connected.
The DTY flag in the control register 2 (R1) and the CLS pin status are used to switch between the oscillation
clocks for normal display and partial display modes.
•The divider divides the external clock that has been input for the normal oscillator and the normal display into a
clock for partial display. The external clock that is input for the partial oscillator and partial display is also
divided for the partial display.
•The division level is automatically set for the divider based on the relationship between the ON/OFF status of
the divider setting pin (CLS pin) and the duty of the specified partial display, as shown in Table 5-4.
Figure 5-7. Oscillator Block
Selected via DTY/CLS
OSCIN1
OSCIN2
Normal display/
Signal to select division level
for partial display
partial display
oscillator
OSCOUT
MUX
To graphic driver
TOSCSYNC
Partial display
divider
Normal/partial signal
CLS
The relationship between the frame frequency (fFRAME), oscillation frequency (fOSCIN1), and setting duty (in normal display
mode) is described below.
fFRAME = fOSCIN1 ÷ 8 ÷ N (in four-level gray scale display mode)
fFRAME = fOSCIN1 ÷ 4 ÷ N (in B/W display mode)
N = 1/N duty (setting duty)
24
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-4. Setting of Division Level for Partial Display and Static Icon Display
In four-level gray scale display mode (GRAY = L, control register 2 (R1))
Division
Normal
Partial
Divider
ON/OFF
CLS
Partial
Division
Ratio
Display
Mode
Source
OSCIN1
/OSCIN2
Normal/Partial
Select DTY
Display
Display
Comments
Duty Ratio
Duty Ratio
1/38
1/25
1/12
1/38
1/25
1/12
L(OFF)
H(ON)
OSCIN1
L (Normal)
−
1/38
1/25
1/12
1/38
1/25
1/12
1/38
1/25
1/12
1/38
1/25
1/12
1/1
1/1
1/2
1/2
1/2
1/4
Partial frame frequency: fOSCIN2 /8 /38
Partial frame frequency: fOSCIN2 /8 /25
1/1 to 1/80
OSCIN2
OSCIN1
L(OFF)
H(ON)
Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12
Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38
Partial frame frequency: fOSCIN1 /2(division ratio) /8 /25
Partial frame frequency: fOSCIN1 /4(division ratio) /8 /12
H (Partial)
L (Normal)
H (Partial)
Four-level
gray scale
GRAY = L
L(OFF)
H(ON)
OSCIN1
−
1/38
1/25
1/12
1/38
1/25
1/12
1/1
1/1
1/2
1/2
1/4
1/8
Partial frame frequency: fOSCIN2 /8 /38
1/81 to 1/92
OSCIN2
OSCIN1
L(OFF)
H(ON)
Partial frame frequency: fOSCIN2 /8 /25
Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12
Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38
Partial frame frequency: fOSCIN1 /4(division ratio) /8 /25
Partial frame frequency: fOSCIN1 /8(division ratio) /8 /12
In black/white display mode (GRAY = H, control register 2 (R1))
Division
Source
OSCIN1
/OSCIN2
Normal
Display
Partial
Display
Divider
ON/OFF
CLS
Partial
Division
Ratio
Display
Mode
Normal/Partial
Select DTY
Comments
Duty Ratio
Duty Ratio
1/38
1/25
1/12
1/38
1/25
1/12
L(OFF)
H(ON)
OSCIN1
L (Normal)
H (Partial)
−
1/38
1/25
1/12
1/38
1/25
1/1
1/1
1/2
1/2
1/2
1/4
Partial frame frequency: fOSCIN2 /4 /38
1/1 to 1/80
OSCIN2
OSCIN1
L(OFF)
H(ON)
Partial frame frequency: fOSCIN2 /4 /25
Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12
Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38
Partial frame frequency: fOSCIN1 /2(division ratio) /4 /25
Partial frame frequency: fOSCIN1 /4(division ratio) /4 /12
B/W
1/12
1/38
1/25
1/12
1/38
1/25
1/12
GRAY = H
L(OFF)
H(ON)
OSCIN1
L (Normal)
H (Partial)
−
1/38
1/1
1/1
1/2
1/2
1/4
1/8
Partial frame frequency: fOSCIN2 /4 /38
1/81 to 1/92
OSCIN2
OSCIN1
L(OFF)
H(ON)
1/25
1/12
1/38
1/25
1/12
Partial frame frequency: fOSCIN2 /4 /25
Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12
Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38
Partial frame frequency: fOSCIN1 /4(division ratio) /4 /25
Partial frame frequency: fOSCIN1 /8(division ratio) /4 /12
25
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-5 shows the relationship between the CLS pin, resistors RN and RP, and the display clock circuit.
Table 5-5. Relationship between CLS Pin/Resistors and Display Clock Circuit
RN
Connection
RP
Connection
Use Example
(Figure 5-8)
CLS
Clock for Normal Display
Clock for Partial Display
Connected
Connected
Not connected
Not connected Not connected
Not connected Not connected
Connected
Not connected
Connected
L
H
L
L
H
Internal oscillator
Internal oscillator
External clock
External clock
External clock
Internal oscillator
Divided from oscillator clock
Internal oscillator
External clock
Divided from external clock
(A)
(B)
(C)
(D)
(E)
Figure 5-8. Clock Use Examples
(A)
(B)
OSCIN1
OSCIN2
OSCIN1
OSCIN2
RN
H or L
RN
RP
OSCOUT
OSCOUT
(C)
(D)
f
N
f
N
OSCIN1
OSCIN2
OSCIN1
OSCIN2
f
P
RP
Open
OSCOUT
OSCOUT
(E)
f
N
OSCIN1
OSCIN2
H or L
Open
OSCOUT
26
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-9. Master/Slave Connection Examples
(A)
Master
Slave
(M/S = H)
(M/S = L, CLS = L)
OSCSYNC
OSCIN1
OSCIN2
Open
OSCOUT
(B)
Master
Slave
(M/S = H)
(M/S = L, CLS = H)
OSCIN1
OSCIN2
OSCSYNC
H or L
Open
OSCOUT
27
Data Sheet S15745EJ2V0DS
µPD16488A
5.5
Display Timing Generator
The display clock generates timing signals for the line address circuit and the display data latch circuit.
Display data is latched into the display data latch circuit in synch with the display clock and is output via segment driver
output pins.
Reading of the display data is completely independent of the CPU's accessing of the display data RAM. Consequently,
there are no adverse effects (such as flicker) on the LCD panel even when the display data RAM is accessed
asynchronously in relation to the LCD contents.
The internal common timing is generated from the display clock. As shown in Figure 5-10, a driver waveform based on
the frame AC drive method is generated for the LCD driver.
If a multiple set of µPD16488A chips are used, the display timing signals (FR and FRSYNC) for the slave side must be
supplied from the master side.
Table 5-6. Relationship Between Operation Mode and FR, FRSYNC
Operation Mode
Master (M/S = H)
Slave (M/S = L)
FR
FRSYNC
Output
Input
Output
Input
28
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-10. Driver Waveform Based on Frame AC Drive Method
1frame
90 91 92
90 91 92
1
1 2 3 4 5 6 7 8
2 3 4 5 6 7 8
OSCSYNC
FRSYNC
FR
RAM
DATA
V
V
V
LCD
LC1
LC2
SEG
1
V
V
V
LC3
LC4
SS
V
V
V
LCD
LC1
LC2
COM
1
V
V
V
LC3
LC4
SS
V
V
V
LCD
LC1
LC2
COM
2
V
V
V
LC3
LC4
SS
V
V
V
LCD
LC1
LC2
COM92
V
V
V
LC3
LC4
SS
29
Data Sheet S15745EJ2V0DS
µPD16488A
5.6
Power Supply Circuit
The power supply circuit supplies the voltage needed to drive the LCD. It includes a booster, voltage regulator, and
voltage follower.
In the power supply circuit, the power system control register 1 (R32) is used to control the ON/OFF status of the power
supply circuit's booster, voltage regulator (also called V regulator), and voltage follower (V/F). This makes it possible to
jointly use an external power supply together with certain functions of the on-chip power supply. Table 5-7 shows the
function that controls the 3-bit data in the power system control register 1 (R32) and Table 5-8 shows a reference chart of
combinations.
Table 5-7. Control Values of Bits in Power System Control 1
Status
Item
1
0
OP2
OP1
OP0
Booster control bit
Voltage regulator (V regulator) control bit
Voltage follower (V/F) control bit
ON
ON
ON
OFF
OFF
OFF
Table 5-8. Reference Chart of Combinations
External
Power Supply
Input
Boost-Related Note
System Pins
Use Status
OP2 OP1 OP0 Booster V Regulator
V/F
<1> Use on-chip power supply
<2> Use V regulator and V/F only
<3> Use V/F only
1
0
0
0
1
1
0
0
1
1
1
0
enable
disable
disable
disable
enable
enable
disable
disable
enable
enable
enable
disable
VDD2
VOUT
VOUT, AMPOUT
VOUT,
Used
Not connected
Not connected
Not connected
<4> Use external power supply only
VLCD to VLC4
Note The boost-related system pins are indicated as pins C1+, C1− to C9+, C9−, and C1A.
5.6.1 Booster
A booster that boosts the LCD driving voltage by 2 to 9 times is incorporated in the power supply circuit.
Since the booster uses signals from the on-chip oscillator, either the oscillator must be operating or a display clock must be
input from an external source.
The booster uses pins C1+, C1− to C9+, C9− for normal boost and pins C1A and VDD2 for boost regulation. The wire
impedance should be kept as low as possible. The number of boost levels is set using the FBS2, FBS1, and FBS0 flags in
the power system control 3 (R34), as shown in Table 5-9.
Caution If a capacitor is connected to a boost-related system pin that is not for one of these set boost levels,
current consumption may increase. Therefore, do not connect any capacitors beyond the number of
set boost levels. This also applies for the CA1 pin, used to regulate the boost levels.
Figure 5-11 describes the connection method for boost levels and capacitors.
The partial booster is settings are made using the BST1 and BST0 flags in the power system control 3 (R34), as shown in
Table 5-10.
30
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-11. Connection Method for Boost Levels and Capacitors
9x boost mode
8x boost mode
7x boost mode
6x boost mode
5x boost mode
4x boost mode
Table 5-9. Boost Level Settings for Normal Display's Booster
FBS2
FBS1
FBS0
Boost Level
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4x
5x
6x
7x
8x
9x
Prohibited
Prohibited
Table 5-10. Boost Level Settings for Partial Display's Booster
BST1
BST0
Boost Level
0
0
1
1
0
1
0
1
2x
3x
4x
Prohibited
31
Data Sheet S15745EJ2V0DS
µPD16488A
5.6.2 Voltage regulator
The boost voltage from VOUT is supplied to the voltage regulator and output as the LCD drive voltage VLCD.
Since the µPD16488A has a 256-step electronic volume function and an on-chip resistor for VLCD voltage regulation, a
small number of components can be used to configure a highly accurate voltage regulator.
(1) When using an on-chip resistor for VLCD voltage regulation
The on-chip resistor for VLCD voltage regulation and the electronic volume function can be used to regulate the contrast of
the LCD contents by controlling the LCD drive voltage VLCD using commands only. In such cases, no external resistor is
needed.
If VLCD < VOUT, then the value for VLCD can be determined from the following equation.
Example Equation VLCD < VOUT
Rb
Ra
Rb
Ra
VLCD = (1 +
VLCD = (1 +
) VEV
α
384
) (1 −
) VREG
α
384
Remark VEV = (1 −
) VREG
Figure 5-12. When Using On-Chip Resistor for VLCD Voltage Regulation
+
V
EV (Constant voltage source +
electronic volume)
VLCD
-
Rb
Ra
VREG is the IC's on-chip constant voltage source, for which three types of temperature characteristic curves are available.
These temperature characteristic curves can be adjusted via settings in the power system control register 1 (R32) (TSC1,
TCS0), as shown in Table 5-11.
Table 5-11 shows the VREG voltage when TA = 25°C.
Table 5-11. VREG Voltage When TA = 25°C
Status
TCS1
TCS0
Temperature Curve (%/°C)
VREG (TYP.) (V)
Internal power supply
0
0
1
1
0
1
0
1
−0.06
−0.08
−0.09
−0.12
1.04
0.98
0.93
0.85
α is the electronic volume register (R35) value. Any of 256 statuses can be set as the fetched status for α corresponding
to the data set to the 8-bit electronic control register. α values based on settings in the electronic volume register (R35:
normal display mode) and the partial electronic volume register (R36: partial display mode) are listed in Table 5-12.
32
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-12. α Values Based on Settings in Electronic Volume Register
Register
EV7
EV6
EV5
EV4
EV3
EV2
EV1
EV0
α
PEV7
PEV6
PEV5
PEV4
PEV3
PEV2
PEV1
PEV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
384
254
253
252
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
2
1
0
Rb/Ra is an on-chip resistance factor used for the VLCD voltage regulator. This factor can be controlled at eight levels
based on settings in power control register 2 (R33) (VRR2, VRR1, VRR0: normal display mode and PVR2, PVR1, PVR0:
partial display mode). Reference voltage values (1 + Rb/Ra) are determined based on 4-bit data set to VLCD's on-chip
resistance factor register, as shown in Table 5-13.
Table 5-13. Determination of Reference Voltage Values Based on Settings of
On-Chip Resistor for VLCD Voltage Regulation
Register
VRR2
PVR2
VRR1
PVR1
VRR0
PVR0
1+Rb/Ra
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5
8
12
13
16
19
21
24
33
Data Sheet S15745EJ2V0DS
µPD16488A
(2) When using an external resistor (instead of using the on-chip resistor for VLCD voltage regulation)
Instead of using only the on-chip resistor setting for VLCD voltage regulation (IRS = L), resistors (Ra', Rb' and Rc') can be
added between VSS and VR, between AMPOUTP and AMPOUT, and between VR and AMPOUT to set the LCD drive voltage
VLCD. In such cases, the electronic volume function can be used to control the LCD drive voltage VLCD and to regulate the
contrast of the LCD contents via commands.
In addition, the µPD16488A enable selection between two display values (for normal display and partial display). The
value is set using an external division resistor and is automatically selected by the DTY flag in the control register 2 (R1).
The VLCD value can be determined using Example 1 (DTY = 0) and Example 2 (DTY = 1) if it is within the range of VLCD <
VOUT.
Example 1. DTY = 0, normal display mode
′
′
′
Rb
VLCD = (1 +
VLCD = (1 +
) VEV
Ra
Rb
Ra
α
384
) (1 −
) VREG
′
α
384
Remark VEV (1 −
) VREG
Example 2. DTY = 1, partial display mode
′
Rb ×Rc
VLCD = (1+
VLCD = (1+
) VEV
′
′
Ra (Rb + Rc)
′
α
384
Rb ×Rc
) (1 −
) VREG
′
(
′
Ra
Rb + Rc
)
α
384
Remark VEV = (1 −
) VREG
Figure 5-13. When Using External Resistor
+
VLCD
-
Normal/partial VLC1 regulation
select circuit
A
B
V
R
AMPOUT
AMPOUTP
Rb'
Rc
Ra'
Normal display mode
A
A
B
B
(DTY = 0)
Partial display mode
(DTY = 1)
34
Data Sheet S15745EJ2V0DS
µPD16488A
5.6.3 Use of op amp for level power supply control
Although the µPD16488A includes a circuit designed for low power consumption (HPM1, HPM0 = 0, 0), display quality
problems may occur when a large-load LCD panel is used. In such cases, the display quality and power consumption
level can be improved by setting. The HPM1 and HPM0 flags in the power system control register 1 (R32) to "0, 1" to
"1, 1" to switch to the op amp driver capacity for mode settings shown in Table 5-14. Check the actual display quality before
deciding which mode to set.
If setting high power mode still does not sufficiently improve the display quality, the LCD drive voltage must be provided
from an external power source.
Table 5-14. Op Amp Mode Setting
HPM1
HPM0
Mode Setting
Normal mode
Low power mode
High power mode
For power ON mode
0
0
1
1
0
1
0
1
35
Data Sheet S15745EJ2V0DS
µPD16488A
5.6.4 Application examples of power supply circuits
Figures 5-14 to 5-19 show application examples of power supply circuits.
Figure 5-14. IRS = H, [OP2, OP1, OP0] = [1, 1, 1]
9x boost mode
V
V
DD1
DD2
V
RS
V
R
V
OUT
Open
AMPOUTP
AMPOUT
+
C1
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
C4
+
C5
-
+
C5
C6
-
+
C6
C7
C9
+
-
C9
-
+
C7
C8
C1A
-
C8
V
SS
Figure 5-15. IRS = L, [OP2, OP1, OP0] = [1, 1, 1]
9x boost mode
V
RS
V
V
DD1
DD2
V
OUT
AMPOUTP
Rc
V
R
Rb'
Ra'
+
AMPOUT
C1
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
C4
+
C5
-
+
C5
C6
-
+
+
C6
C9
C7
-
C9
-
+
C7
C1A
C8
-
C8
V
SS
36
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-16. IRS = H, [OP2, OP1, OP0] = [0, 1, 1]
V
RS
V
V
DD1
DD2
V
R
Open
V
OUT
AMPOUTP
AMPOUT
+
C1
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
C4
Open
+
C5
-
+
C5
C6
-
+
C6
C7
C9
+
Open
-
C9
-
+
C7
C8
C1A
-
C8
V
SS
Figure 5-17. IRS = L, [OP2, OP1, OP0] = [0, 0, 1]
V
RS
Open
V
V
DD1
DD2
V
R
Open
V
OUT
+
C1
AMPOUTP
AMPOUT
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
+
C4
C5
Open
-
+
C5
C6
-
+
C6
C7
C9
+
Open
-
C9
-
+
C7
C8
C1A
-
C8
V
SS
37
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-18. IRS = L, [OP2, OP1, OP0] = [0, 0, 0]
V
RS
V
V
DD1
DD2
V
R
Open
V
OUT
AMPOUTP
AMPOUT
+
C1
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
C4
Open
+
C5
-
+
C5
C6
-
+
C6
C7
C9
+
Open
-
C9
-
+
C7
C8
C1A
-
C8
V
SS
Figure 5-19. Master/Slave Connection Example
V
DD1
DD2
V
RS
V
RS
V
V
DD1
DD2
V
V
R
V
R
Open
AMPOUTP
AMPOUT
V
OUT
+
V
OUT
AMPOUTP
AMPOUT
+
C1
C1
−
+
−
C1
C2
C1
C2
+
V
LCD
V
LCD
−
−
+
C2
C3
C2
C3
+
V
LC1
V
LC1
Master
Slave
−
−
+
V
V
V
LC2
LC3
C3
C4
V
V
V
LC2
LC3
C3
C4
+
−
+
−
C5+
C4
C4
C5
Open
Open
LC4
LC4
−
+
−
C5
C6
C5
C6+
+
−
+
+
−
+
C6
C7
C9
C9
C6
C7
Open
−
−
C9
C9
−
+
−
C7
C8
C1A
C7
C8
C1A
+
−
−
C8
V
C8
V
SS
SS
38
Data Sheet S15745EJ2V0DS
µPD16488A
5.7
LCD Display Drivers
µPD16488A includes a full dot driver. The full dot driver has a 33-level gray-scale palette (eight levels of pulse width
modulation plus four-frame rate control), from which four levels of gray scale can be selected and registered as the IC's
output gray-scale palette (refer to 6.23 Gary scale registers 1 to 4 (R23 to R26)).
5.7.1 Full-dot pulse width modulation
The µPD16488A's pulse width modulator divides the normal LCD display signal's segment pulse width by eight and
outputs in synch with the dot output timing based on the ratio (1/8 to 8/8 pulses) for the gray-scale palette that has been
selected via a command.
Figure 5-20. Full-Dot Pulse Width Modulation
1 frame
90 91 92
90 91 92
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
V
LCD
V
V
LC1
LC2
SEG
1
V
V
LC3
LC4
V
SS
V
LCD
V
V
LC1
LC2
COM
1
V
V
LC3
LC4
V
SS
Enlarged section
1
2
3
8/8
6/8
4/8
1/8
VLCD
VLC1
VLC2
Caution There is no pulse width modulation for common outputs.
39
Data Sheet S15745EJ2V0DS
µPD16488A
The output pulses are output as odd-numbered lines/even-numbered lines or as even-numbered lines/odd-numbered lines,
as shown in Figure 5-21. The pulse rising edge and falling edge combinations for each frame are listed in Table 5-15.
Figure 5-21. Example of Pulse Width Modulated Output
1 frame
90 91 92
1
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
6
7
8
V
LCD
V
V
LC1
LC2
V
V
LC3
LC4
V
SS
1
2
3
8/8
8/8
8/8
3/8
4/8
4/8
40
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-15. Example of Pulse Width Modulated Output (1/3)
1, 2 Frames 3, 4 Frames 5, 6 Frames
SEG Odd SEG Even SEG Odd SEG Even SEG Odd SEG Even
Gray-scale COM
level
7, 8 Frames
SEG Odd SEG Even
Numbered Numbered Numbered Numbered Numbered Numbered Numbered Numbered
0
1
2
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
0
0
0
0
↑1
0
0
0
↑1
0
0
0
0
↓1
0
0
0
↓1
0
0
0
0
0
0
0
↑1
0
0
0
0
0
0
0
0
↓1
0
0
0
0
0
0
↓1
0
0
0
0
0
0
0
↑1
0
0
0
0
0
0
0
0
↓1
0
0
0
0
0
0
0
↑1
0
↑1
↓1
0
0
4n+2
4n+3
4n+4
↓1
0
0
↑1
0
0
0
↓1
↑1
0
↑1
↓1
↓1
0
0
↑1
0
0
0
↓1
↑1
0
↑1
↓1
3
4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
↑1
↓1
↑1
0
↑1
↓1
↓1
↑1
↓1
0
↓1
↑1
↓1
0
↓1
↑1
↓1
↑1
↑1
0
↑1
↓1
↑1
↓1
↑1
↓1
0
↓1
↑1
↓1
↓1
↑1
0
↑1
↓1
↑1
0
0
↑1
↓1
↑1
↓1
↑1
↓1
↑1
↓1
↑1
↓1
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
↑1
↓1
↑2
↓1
↑1
↓1
↑2
↓1
↑1
↓2
↑1
↓1
↑1
↓2
↓1
↑1
↓1
↑1
↓1
↑2
↓1
↑1
↓1
↑1
↓1
↑1
↓2
↑1
↑1
↓1
↑1
↓2
↑1
↓1
↑2
↓1
↑1
↓1
↑2
↓1
↑1
↓2
↓1
↑1
↓1
↑1
↓2
↑1
↓1
↑1
↓1
↑1
↓1
↑2
↓1
↑1
5
6
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
↓2
↑1
↓1
↑2
↓2
↑2
↓1
↑2
↑2
↓1
↑1
↓2
↑2
↓2
↑1
↓2
↑1
↓2
↑2
↓2
↑1
↓2
↑2
↓2
↓1
↑2
↓2
↑2
↓1
↑2
↓2
↑2
↓2
↑1
↓1
↑2
↓2
↑1
↓2
↑2
↑2
↓1
↑1
↓2
↑2
↓1
↑2
↓2
↑1
↓2
↑2
↓1
↑2
↓2
↑2
↓2
↓1
↑2
↓2
↑1
↓2
↑2
↓2
↑2
7
8
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
↓2
↑2
↓2
↑3
↓2
↑2
↓2
↑3
↓3
↑2
↓2
↑2
↓2
↑2
↓3
↑2
↓2
↑2
↓3
↑3
↓2
↑2
↑2
↓2
↑2
↓2
↑2
↓2
↑3
↓2
↑2
↓3
↑3
↓2
↑2
↓2
↑2
↓2
↑2
↓3
↑2
↓2
↑3
↓3
↓2
↑2
↓2
↑2
↓3
↑2
↓2
↑3
↓3
↑2
↓2
↑2
↓2
↑2
↓2
↑3
↓2
↑2
↓3
↑3
↓2
↑2
↑2
↓2
↑2
↓2
↑2
↓3
↑2
↓2
↑2
↓3
↑3
↓2
↑2
↓2
↑2
↓2
↑3
↓2
↑2
↓2
↑3
↓3
9
10
Remarks 1. n: Integer from 0 to 31.
2. ↑A: Rising edge of pulse during line A output.
3. ↓A: Rising edge of pulse at start of line A output.
4. A: PWM pulse width (A/8)
41
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-15. Example of Pulse Width Modulated Output (2/3)
1, 2 Frames 3, 4 Frames 5, 6 Frames
SEG Odd SEG Even SEG Odd SEG Even SEG Odd SEG Even
Gray-scale COM
level
7, 8 Frames
SEG Odd SEG Even
Numbered Numbered Numbered Numbered Numbered Numbered Numbered Numbered
11
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
↑3
↓3
↑3
↓2
↑3
↓3
↑3
↓3
↑4
↓3
↑3
↓3
↑2
↓3
↑3
↓3
↑3
↓4
↓3
↑2
↓3
↑3
↓3
↑3
↓3
↑3
↓3
↑3
↓2
↑3
↓3
↑3
↓3
↑3
↓3
↑3
↑3
↓3
↑2
↓3
↑3
↓3
↑3
↓3
↑3
↓3
↑3
↓2
↑3
↓3
↑3
↓3
↑3
↓3
↓2
↑3
↓3
↑3
↓3
↑3
↓3
↑3
↓3
↑2
↓3
↑3
↓3
↑3
↓3
↑3
↓3
↑3
12
13
14
4n+2
↓3
↑3
↑3
↓3
↓4
↑4
↑3
↓3
4n+3
4n+4
4n+1
4n+2
↑3
↓3
↑4
↓4
↓3
↑3
↓4
↑4
↓3
↑4
↓3
↑3
↑3
↓4
↑3
↓3
↑3
↓3
↑4
↓4
↓3
↑3
↓4
↑4
↓4
↑3
↓3
↑3
↑4
↓3
↑3
↓3
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
↑3
↓3
↑4
↓4
↑4
↓3
↑4
↓4
↑4
↓4
↑5
↓4
↓3
↑3
↓4
↑4
↓4
↑3
↓4
↑4
↓4
↑4
↓5
↑4
↓4
↑4
↓4
↑3
↓4
↑4
↓4
↑4
↓4
↑4
↓4
↑4
↑4
↓4
↑4
↓3
↑4
↓4
↑4
↓4
↑4
↓4
↑4
↓4
↑3
↓3
↑4
↓4
↑3
↓4
↑4
↓4
↑4
↓4
↑4
↓5
↓3
↑3
↓4
↑4
↓3
↑4
↓4
↑4
↓4
↑4
↓4
↑5
↓4
↑4
↓3
↑4
↓4
↑4
↓4
↑4
↓4
↑4
↓4
↑4
↑4
↓4
↑3
↓4
↑4
↓4
↑4
↓4
↑4
↓4
↑4
↓4
15
16
17
18
4n+3
4n+4
4n+1
4n+2
↑4
↓4
↑5
↓5
↓4
↑4
↓5
↑5
↓4
↑5
↓4
↑4
↑4
↓5
↑4
↓4
↑4
↓4
↑5
↓5
↓4
↑4
↓5
↑5
↓5
↑4
↓4
↑4
↑5
↓4
↑4
↓4
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
↑4
↓4
↑5
↓5
↑5
↓4
↑5
↓5
↓4
↑4
↓5
↑5
↓5
↑4
↓5
↑5
↓5
↑5
↓5
↑4
↓5
↑5
↓5
↑5
↑5
↓5
↑5
↓4
↑5
↓5
↑5
↓5
↑4
↓4
↑5
↓5
↑4
↓5
↑5
↓5
↓4
↑4
↓5
↑5
↓4
↑5
↓5
↑5
↓5
↑5
↓4
↑5
↓5
↑5
↓5
↑5
↑5
↓5
↑4
↓5
↑5
↓5
↑5
↓5
19
20
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
↑5
↓5
↑6
↓5
↑5
↓5
↓5
↑5
↓6
↑5
↓5
↑5
↓5
↑5
↓5
↑5
↓5
↑6
↑5
↓5
↑5
↓5
↑5
↓6
↑5
↓5
↑5
↓6
↑5
↓5
↓5
↑5
↓5
↑6
↓5
↑5
↓5
↑5
↓5
↑5
↓6
↑5
↑5
↓5
↑5
↓5
↑6
↓5
21
Remarks 1. n: Integer from 0 to 31.
2. ↑A: Rising edge of pulse during line A output.
3. ↓A: Rising edge of pulse at start of line A output.
4. A: PWM pulse width (A/8)
42
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-15. Example of Pulse Width Modulated Output (3/3)
1, 2 Frames 3, 4 Frames 5, 6 Frames
SEG Odd SEG Even SEG Odd SEG Even SEG Odd SEG Even
Gray-scale COM
level
7, 8 Frames
SEG Odd SEG Even
Numbered Numbered Numbered Numbered Numbered Numbered Numbered Numbered
22
4n+1
↑6
↓6
↓5
↑5
↑6
↓6
↓5
↑5
4n+2
4n+3
↓6
↑5
↑6
↓5
↑5
↓6
↓5
↑6
↓6
↑5
↑6
↓5
↑5
↓6
↓5
↑6
4n+4
4n+1
↓5
↑6
↑5
↓6
↑6
↓6
↓6
↑6
↓5
↑6
↑5
↓6
↑6
↓5
↓6
↑5
23
24
25
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
↓6
↑6
↓5
↑6
↓6
↑6
↓6
↑7
↑6
↓6
↑5
↓6
↑6
↓6
↑6
↓7
↑5
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↓5
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑5
↓6
↑6
↓6
↑6
↓6
↑6
↑6
↓5
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑6
4n+2
4n+3
↓6
↑6
↑6
↓6
↑6
↓6
↓6
↑6
↓7
↑6
↑7
↓6
↑6
↓7
↓6
↑7
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
↓6
↑7
↓7
↑6
↓6
↑7
↓7
↑7
↓6
↑7
↓7
↑7
↑6
↓7
↑7
↓6
↑6
↓7
↑7
↓7
↑6
↓7
↑7
↓7
↑7
↓6
↑6
↓7
↑7
↓7
↑6
↓7
↑7
↓7
↑7
↓7
↓7
↑6
↓6
↑7
↓7
↑7
↓6
↑7
↓7
↑7
↓7
↑7
↓6
↑7
↓7
↑6
↓6
↑7
↓7
↑6
↓7
↑7
↓7
↑7
↑6
↓7
↑7
↓6
↑6
↓7
↑7
↓6
↑7
↓7
↑7
↓7
↑6
↓6
↑6
↓7
↑7
↓6
↑7
↓7
↑7
↓7
↑7
↓7
↓6
↑6
↓6
↑7
↓7
↑6
↓7
↑7
↓7
↑7
↓7
↑7
26
27
28
29
4n+4
4n+1
4n+2
↓7
8
↓7
↑7
8
↑7
↑7
↓7
↑7
↓7
↑7
↓7
↓7
↑7
8
↑7
↓7
8
↑7
↓7
↑7
↓7
↑7
↓7
4n+3
↑7
↓7
↓7
↑7
↑7
↓7
8
8
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
↓7
8
8
↑7
↓7
8
↑7
8
8
↓7
↑7
8
8
↓7
↑7
8
8
8
8
↑7
↓7
8
8
8
↓7
8
8
↑7
↓7
8
↑7
8
8
↓7
↑7
8
↑7
↓7
↑7
8
8
↓7
↓7
↑7
↓7
8
8
↑7
30
31
8
8
8
8
↑7
8
↓7
8
8
↑7
8
↓7
8
8
8
8
4n+4
4n+1
↓7
8
↑7
8
8
8
8
8
8
8
8
8
8
8
8
8
32
4n+2
4n+3
4n+4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Remarks 1. n: Integer from 0 to 31.
2. ↑A: Rising edge of pulse during line A output.
3. ↓A: Rising edge of pulse at start of line A output.
4. A: PWM pulse width (A/8)
43
Data Sheet S15745EJ2V0DS
µPD16488A
5.7.2 Full-dot frame rate control
When combined with pulse width modulation as described in Table 5-15, the µPD16488A's frame speed is based on 8-
frame cycles. The subsampling pattern is output based on the palette stored in the IC.
Full-Dot Gray-Scale Palette (Output Pulse Width: x/8 Pulses)
Frames
Gray Scale
Comments
1
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
2
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
3
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
4
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
5
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
6
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
7
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
Level 0
OFF data
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8
Level 9
Level 10
Level 11
Level 12
Level 13
Level 14
Level 15
Level 16
Level 17
Level 18
Level 19
Level 20
Level 21
Level 22
Level 23
Level 24
Level 25
Level 26
Level 27
Level 28
Level 29
Level 30
Level 31
Level 32
50%
100%
Remark The gradation in the Comments column are images of the gray-scale level.
44
Data Sheet S15745EJ2V0DS
µPD16488A
5.7.3 Line shift driver
If the frame rate control is performed with equal pulse widths and the same gray scale is displayed on the LCD's full
screen, problems such as flickering may occur on the LCD panel. The µPD16488A provides a line shift driver as a
countermeasure against such screen image problems.
Using 8 frames per cycle, the segment PWM output timing is shifted among the common outputs, as shown in Table 5-16
below.
Table 5-16. Line Shift Driver
Turn 1
Turn 2
Frame
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
•
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3
F7
F5
F1
F3
F7
F5
F1
F3
F7
•
F4
F8
F6
F2
F4
F8
F6
F2
F4
F8
•
F5 F6
F1 F2
F7 F8
F3 F4
F5 F6
F1 F2
F7 F8
F3 F4
F5 F6
F1 F2
F7
F3
F1
F5
F7
F3
F1
F5
F7
F3
•
F8
F4
F2
F6
F8
F4
F2
F6
F8
F4
•
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3
F7
F5
F1
F3
F7
F5
F1
F3
F7
•
F4
F8
F6
F2
F4
F8
F6
F2
F4
F8
•
F5 F6
F1 F2
F7 F8
F3 F4
F5 F6
F1 F2
F7 F8
F3 F4
F5 F6
F1 F2
F7
F3
F1
F5
F7
F3
F1
F5
F7
F3
•
F8
F4
F2
F6
F8
F4
F2
F6
F8
F4
•
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3
F7
F5
F1
F3
F7
F5
F1
F3
F7
•
F4
F8
F6
F2
F4
F8
F6
F2
F4
F8
•
•
•
•
•
•
•
•
•
•
•
Remark Fx: Pulse width modulated output frame (See 5.7.2 Full-dot frame rate control).
Figure 5-22. Full Dot Frame Rate Control
First frame
Second frame
1
2
3
4
5
1
2
91
92
ON
OFF
COM
COM
COM
1
2
3
ON
OFF
ON
OFF
ON
OFF
COM
4
5
ON
OFF
COM
ON
COM91
COM92
OFF
ON
OFF
SEG
SEG
1
8
8
1
1
5
5
3
3
7
7
1
1
5
5
3
3
7
7
2
2
6
6
2
3
4
5
8
8
1
1
5
5
3
3
7
7
1
1
5
5
3
3
7
7
2
2
6
6
SEG
SEG
SEG
8
1
5
3
7
1
5
3
7
2
6
Remark Numerical values in the segment data correspond to the gray-scale palette's frame numbers.
45
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-23. Line Shift Driver Image
Turn 1, first frame
SEG
1
SEG
3
SEG
5
SEG
7
SEG127
SEG
2
SEG
4
SEG
6
SEG
8
SEG126
SEG128
COM
1
2
F1
F5
F3
F7
F1
COM
COM
3
4
COM
COM
5
COM90
F5
F3
F7
COM91
COM92
Turn 1, second frame
SEG
SEG
1
SEG
3
SEG
5
7
SEG127
SEG
2
SEG
4
SEG
6
SEG
8
SEG126
SEG128
COM
1
2
F2
F6
F4
F8
F2
COM
COM
3
4
COM
COM
5
COM90
F6
F4
F8
COM91
COM92
46
Data Sheet S15745EJ2V0DS
µPD16488A
5.7.4 Display size settings
The µPD16488A can be set for any duty value from 1/1 to 1/92. This duty setting can be made via bits DT6 to DT0 in the
duty setting register (R5), as shown in Table 5-17.
Table 5-17. Duty Settings
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Duty
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
1/1
1/2
1/3
1/4
:
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
1/90
1/91
1/92
prohibited
Caution The duty setting can not be over 1/92 duty (5CH). If 1/92 duty is exceeded, operation is not guaranteed.
5.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position
The µPD16488A enable any setting to be made for the AC driver's inversion position and the inversion position shift
amount for each displayed frame via settings made in the AC driver inversion cycle register (R6) and the AC driver
inversion position shift register (R7) for normal display mode or via settings made in the partial AC driver inversion cycle
register (R8) and the partial AC driver inversion position shift register (R9) for partial display mode.
In normal display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed
in Table 5-18, based on the NID6 to NID0 bit settings in the AC driver inversion cycle register (R6).
If the screen display size has been changed via settings made in the duty setting register (R5), the NIDn values are
automatically overwritten by values from the corresponding DTYn bits.
The shift amount for each displayed frame can be set as shown in Table 5-19 via settings made to bits MSD6 to MSD0 in
the AC driver inversion position shift register (R7).
Table 5-18. Settings of AC Driver Inversion Cycle Register (R6)
NID6
NID5
NID4
NID3
NID2
NID1
NID0
Inverted Lines
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
2
3
4
:
90
91
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
92
prohibited
Caution The inversion line can not be over 92-inversion line (5CH). If 92-inversion line is exceeded, operation is
not guaranteed.
47
Data Sheet S15745EJ2V0DS
µPD16488A
Table 5-19. Settings of AC Driver Inversion Position Shift Register
MSD6
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
:
89
90
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
91
prohibited
Caution The inversion position shift amount can not be over 91 (5CH). If 91 is exceeded, operation is not guaranteed.
In partial display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed in
Table 5-20, based on the PID5 to PID0 bit settings in the partial AC driver inversion cycle register (R8).
The shift amount for each displayed frame can be set as shown in Table 5-21 via settings made to bits PSD5 to PSD0 in
the partial AC driver inversion position shift register (R9).
Table 5-20. Settings of Partial AC Driver Inversion Cycle Register (R8)
PID5
PID4
PID3
PID2
PID1
PID0
Inverted Lines
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
1
2
3
4
:
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
36
37
38
Table 5-21. Setting of Partial AC Driver Inversion Position Shift Register (R9)
PSD5
PSD4
PSD3
PSD2
PSD1
PSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
1
1
0
1
0
1
0
1
2
3
:
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
35
36
37
Be sure to maintain the following relationship among the display size, AC inversion cycle, and AC inversion position.
Display size (duty) ≥ AC inversion cycle ≥ AC inversion shift amount
Caution Setting a small inversion cycle will cause a reduction in the IC's display drive capacity and an increase
in the current consumption. We therefore recommend determining the inversion cycle after making a
thorough evaluation of the actual LCD panel.
48
Data Sheet S15745EJ2V0DS
µPD16488A
5.8
Display Modes
5.8.1 Partial display mode
The µPD16488A includes a function for outputting a display that uses only part of the LCD panel. The duty setting for
partial display mode can be selected as 1/12, 1/25, or 1/38. Parts of the LCD panel that are outside of the specified display
area are scanned with non-select waveforms. The partial start line address register (R21) is used to select which part of
the LCD panel to use for the partial display. The display area starts from the start line address and includes the number of
lines (12, 25, or 38 lines) that has been specified via the partial display mode setting (R10).
When entering this mode, the booster is set to the boost level number that has been set via the power system control
register 3 (partial display boost register) (R34) and the display start line is fixed as 00H. In addition, the bias level is
automatically changed to the value that has been set via the partial display mode setting (R10). The relationship between
the oscillator's frequency and the frame frequency in partial mode is also automatically changed.
Figure 5-24 shows the mutual relationship between the partial line start address and the LCD display.
When using the partial display mode, the blinking and reverse display functions can be used in the same way as during
full-dot display mode.
Caution The LCD driver voltage is lower in partial display mode, because the duty is lower than in normal display
mode. There may be restrictions on the usable duty depending on the LCD panel characteristics.
We recommend determining the partial duty after making a thorough evaluation of the actual LCD panel.
Figure 5-24. Relationship Between Partial Line Start Address and LCD Display
(in Partial Display Mode)
...
00H
01H
02H
03H
1DH
1EH
1FH
Display start line
(00H)
Partial display
start line
Non-display areas
Caution In partial display mode, the display start line setting register (R12) command is ignored.
When switching from normal display mode to partial display mode or from partial display mode to normal display mode, if
an electric charge remains in the smoothing capacitor that is connected between the LCD drive voltage pins (VLCD, VLC1 to
VLC4) and the VSS pin, troubles such as a brief all-black display may occur during the mode switching operation. To avoid
such troubles, we recommend using the following power-on sequence.
49
Data Sheet S15745EJ2V0DS
µPD16488A
(1) Normal display → partial display switch sequence
DISP = 0
R0
Display OFF
↓
HPM1 = 1, HPM0 = 0
R32
R1
High power mode settings
Control register 2: switch DTY flag
↓
Switch display mode
↓
700 ms (stabilization time for LCD drive voltage and
booster)Note
Wait time
↓
HPM1 = X, HPM0 = X
R32
R0
High power mode settings
(to mode used during normal display)
Display ON, internal operations status
↓
DISP = 1
Note This 700ms wait time indicates the time for the VLCD level to change from 15V to 6V and thus varies according to
the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend
determining the wait time after making a thorough evaluation of the actual device.
(2) Partial display → Normal display switch sequence
DISP = 0
R0
Display OFF
↓
HPM1 = 1, HPM0 = 1
R32
R1
Power ON mode settings
Control register 2: switch DTY flag
↓
Switch display mode
↓
400 ms (stabilization time for LCD drive voltage and
booster)Note
Wait time
↓
HPM1 = X, HPM0 = X
R32
R0
High power mode settings
(to mode used during normal display)
Display ON, internal operations status
↓
DISP = 1
Note This 400ms wait time indicates the time for the VLCD level to change from 6V to 15V and thus varies according to
the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend
determining the wait time after making a thorough evaluation of the actual device.
50
Data Sheet S15745EJ2V0DS
µPD16488A
5.8.2 Monochrome (black/white) display
The µPD16488A provides both a four-level gray scale display mode and a monochrome display mode.
To switch to the monochrome display mode, set GRAY = H. The display RAM for one screen of monochrome display
mode contents is configured as 128 bits x 128 bits (16 x 8 bits). When using these IC's in monochrome display mode, two
screens of data can be written to the display RAM and the two screens can be switched by setting the DSEL bit in the
control register 2 (R1). Screen 1 is displayed on the LCD panel when DSEL = L and screen 2 is displayed when DSEL = H.
When writing data, the display RAM uses the same X address (00H to 0FH) and Y address and the BWW bit value in the
control register 2 (R1) determines which of the two screens the data will be written to: when BWW = L, data is written to
screen 1 and when BWW = H, data is written to screen 2, as shown in Figure 5-25.
When accessing a specified bit, specify both the X address and Y address. The display data in D0 to D7 (sent from the
CPU) corresponds to the SEGx portions of the LCD display, as shown in Figure 5-26. Figure 5-27 shows the relationship
between the display data in monochrome display mode and the page/column addresses.
Figure 5-25. Display RAM Image in Monochrome (Black/White) Mode
00H
0FH
00H
0FH
Screen 1
Screen 2
DSEL = L (during display)
BWW = L (during write)
DSEL = H (during display)
BWW = H (during write)
Figure 5-26. Relationship Between Display Data and LCD Display
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 1 1 1 1 1 0 0 1 1
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0
0 1 0 1 0 1 0 1 1 1 1 1 0 1 0 0
0 1 0 0 1 1 0 1 0 0 0 0 0 1 0 0
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
0 1 0 0 0 1 0 1 1 1 1 1 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data
Display data
LCD display
51
Data Sheet S15745EJ2V0DS
µPD16488A
Figure 5-27. Relation Between the Display Data and X/Y Address
(in Monochrome Display Mode)
D4
D3
D2
D1
0
0
0
0
1
1
1
1
0
0
0
0
0
COM output
COM1
D0
0
1
Yaddress
00H
01H
0FH
Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
Start
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
92-line
COM83
COM84
COM85
COM86
COM87
COM88
76H
77H
78H
79H
7AH
7BH
7CH
7DH
COM89
COM90
COM91
COM92
7EH
7FH
52
Data Sheet S15745EJ2V0DS
µPD16488A
5.9
Reset
In the µPD16488A, a reset is executed when the /RES input is at low level or when a reset command is entered. The IC
is reset to its default settings. These default settings are listed in the table below.
Register
Number
R0
R1
/RES
Reset Command
Enabled
Control register 1
Control register 2
X address register
Y address register
Duty setting register
AC driver inversion cycle register
AC driver inversion position shift register
Partial AC driver inversion cycle register
Partial AC driver inversion position shift register
Partial display mode setting register
Display memory access registerNote1
Display start line setting register
Blink X address register
Enabled (DISP flag only)
Enabled (IDIS flag only)
Disabled
R3
R4
R5
R6
R7
R8
R9
EnabledNote2
Enabled
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R23
R24
R25
R26
R27
R28
R29
R30
R32
R33
R34
R35
R36
R37
R44
R45
Disabled
Enabled
Blink start line address register
Blink end line address register
Blink data memory access registerNote1
Inverted X address register
Disabled
Enabled
Inversion start line address register
Inversion end line address register
Inverted data memory access registerNote1
Partial start line address register
Gray scale data register 1 (0, 0)
Gray scale data register 2 (0, 1)
Gray scale data register 3 (1, 0)
Gray scale data register 4 (1, 1)
Partial gray scale data register 1 (0, 0)
Partial gray scale data register 2 (0, 1)
Partial gray scale data register 3 (1, 0)
Partial gray scale data register 4 (1, 1)
Power system control register 1
Power system control register 2
Power system control register 3
Electronic volume register
Disabled
Enabled
Partial electronic volume register
Boost adjustment register
RAM test mode setting register
Signature read register
Disabled
Enabled: Default value is input, Disabled: Default value is not input
Notes 1. When using the /RES pin to reset, the contents of memory are not retained. Use the reset command to reset
if the memory contents need to be retained.
2. Be sure to set this register again after input the reset command.
Cautions 1. Using the /RES pin to reset initializes the shift clock counter.
2. Always input the reset command as the first command after power ON.
53
Data Sheet S15745EJ2V0DS
µPD16488A
6. COMMAND REGISTERS
The µPD16488A uses a combination of RS, /RD (E), and /WR (R,/W) signals to identify data bus signals. Command
interpretation and execution is performed using internal timing that does not depend on any external clock. Therefore,
processing is very fast and there is usually no need to check for a busy status.
The i80 series CPU interface activates read commands using a low pulse input to the /RD pin and activates write
commands using a low pulse input to the /WR pin. The M68 series CPU interface sets read mode using a high level input
to the R,/W pin and sets write mode using a low level input to the same pin. It activates both read and write commands
using a high-level pulse input to the E pin.
Command descriptions using an i80 series CPU interface are shown as follows. The M68 series CPU interface differs
from the i80 series CPU interface in that /RD (E) is at high level during status read and display data read operations, as
shown in the following command descriptions and command table.
If the serial interface has been selected, data is input sequentially starting from D7.
Data Sheet S15745EJ2V0DS
54
µPD16488A
6.1 Control Register 1 (R0)
This command specifies the µPD16488A's general operation modes.
E
/RD
1
R,/W
/WR
0
RS
1
D7
RMW
D6
DISP
D5
STBY
D4
BLD
D3
IVD
D2
HALT
D1
ADC
D0
COMR
Flag
Function
RMW
0: Address is incremented after both write access and read access.
1: Read/modify/write mode
(Address is incremented only after write access)
DISP
STBY
BLD
0: Display OFF (All LCD output pins output the VSS level and oscillator and DC/DC converter are operating)
1: Display ON
0: Normal operation
1: Internal operation and oscillation are stopped. Display is OFF.
The blinking dots are specified via the blink start/end line address registers and data is set to blink data RAM.
0: Stop blinking
1: Start blinking
IVD
The number of inverted dots is specified via the inversion start/end line address registers and data is set to
inverted data RAM.
0: Stop inversion
1: Start inversion
HALT
0: Start internal operation
1: Stop internal operation (since different display modes are used, when switching between partial and normal
display modes, the LCD output pins all output the VSS level and the oscillator is operating, but the DC/DC
converter is stopped)
The column address corresponding to the SEG outputs (see Table 6-1) for displaying the contents of the display
data RAM.
ADC Note
COMR Note
This inverts (reverses) the scan direction for common outputs. (See Table 6-2)
Note The reset command must be executed before changing this flag's setting.
Table 6-1. Relationship between Display RAM Column Address and SEG Outputs
SEG Output
SEG1
00H
7FH
SEG128
7FH
00H
0
1
→
←
Column addresses
Column addresses
→
←
ADC
(D1)
Table 6-2. Relationship between Common Scan Circuit and Scan Direction
COM Output
Scan Direction
0
1
COM1
COM92
→
→
COM92
COM1
COMR
(D0)
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
55
µPD16488A
6.2 Control Register 2 (R1)
This command specifies the µPD16488A's general operation modes.
E
/RD
1
R,/W
/WR
0
RS
1
D7
FDM
D6
−
D5
−
D4
DSEL
D3
BWW
D2
GRAY
D1
DTY
D0
INC
Flag
Function
FDM
Settings for full screen display mode
0: Normal operation
1: Full screen display (set entire screen to ON) (When using four-level gray scale, gray-scale level 32 is output
for full screen display).
DSEL
BWW
Selects display screen during monochrome display mode.
0: Screen 1
1: Screen 2
Selects data write screen during monochrome display mode.
0: Screen 1
1: Screen 2
0: 4-level gray scale display mode
1: Monochrome display mode
0: Normal display mode (1/1 to 1/128 duty)
1: Partial display mode (1/12, 1/25, or 1/38 duty, 1/5 or 1/6 bias)
0: Increments X address at each access
1: Increments Y address at each access
GRAY Note
DTY Note
INC
Note The HALT command must be executed before changing this flag's setting.
Table 6-3. Relationship between IC's Functions and Display Modes
Item
Normal Display Mode (DTY = 0)
1/1 to 1/92 duty
×4, ×5, ×6, ×7, ×8, ×9
1/11, 1/12, 1/10, 1/9, 1/8, 1/7
Uses levels set to the gray scale data
registers (R23 to R26)
Uses values of VRR2 to VRR0 in the power
system control register 2 (R33)
Partial Display Mode (DTY = 1)
1/12, 1/25, or 1/38 duty
×2, ×3, ×4
Duty
Booster
Bias level
↔
↔
↔
↔
1/5, 1/6
Gray scale data
Uses levels set to the partial gray scale
data registers (R27 to R30)
Uses values of PVR2 to PVR0 in the power
system control register 2 (R33)
(1+Rb/Ra)
↔
↔
VLCD regulator resistance
factor
Electronic volume
Uses value from the electronic volume
register (R35)
Uses value from the partial electronic
volume register (R36)
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
56
µPD16488A
6.3 Reset Command (R2)
When this command is input, the IC's registers (R0 to R44) are reset to their initial values. However, the contents of
memory are retained.
Always input the reset command as the first command after power application.
RS
1
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
6.4 X Address Register (R3)
The X address register specifies the X address in the display RAM accessed by the CPU. This address is automatically
incremented each time the display RAM is accessed (INC = 0, RMW = 0).
RS
1
D7
−
D6
−
D5
−
D4
XA4
D3
XA3
D2
XA2
D1
XA1
D0
XA0
Default settings (initial values set by reset command)
D7
−
D6
−
D5
−
D4
0
D3
0
D2
0
D1
0
D0
0
6.5 Y Address Register (R4)
The Y address register specifies the Y address in the display RAM accessed by the CPU. This address is automatically
incremented each time the display RAM is accessed (INC = 1, RMW = 0).
RS
1
D7
−
D6
YA6
D5
YA5
D4
YA4
D3
YA3
D2
YA2
D1
YA1
D0
YA0
Default settings (initial values set by reset command)
D7
−
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
57
µPD16488A
6.6 Duty Setting Register (R5)
The display duty can be set to any duty ratio between 1/1 and 1/92, as is shown in Table 6-4.
Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations.
Also, be sure to set this register again after input the reset command.
RS
1
D7
−
D6
DT6
D5
DT5
D4
DT4
D3
DT3
D2
DT2
D1
DT1
D0
DT0
Table 6-4. Duty Setting Register (R5) Settings
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Duty
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
1/1
1/2
1/3
1/4
:
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1/90
1/91
1/92
inhibited
Caution The display size can not be over 1/92 duty ( 5CH). If 1/92 duty is exceeded, operation is not guaranteed.
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
Data Sheet S15745EJ2V0DS
58
µPD16488A
6.7 AC Driver Inversion Cycle Register (R6)
The AC driver's line position for normal display mode can be set as shown in Table 6-5.
When a DTYn value is changed in the duty setting register (R5), the NIDn value is automatically overwritten by the DTYn value.
Be sure to set this register again after input the reset command.
RS
1
D7
−
D6
NID6
D5
NID5
D4
NID4
D3
NID3
D2
NID2
D1
NID1
D0
NID0
Table 6-5. AC Driver Inversion Cycle Register (R6) Settings
NID6
NID5
NID4
NID3
NID2
NID1
NID0
Inversion Line
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
2
3
4
:
90
91
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
92
Inhibited
Caution The inversion line can not be over 92 (5CH). If 92-line is exceeded, operation is not guaranteed.
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
6.8 AC Driver Inversion Position Shift Register (R7)
This register shifts the inversion position for each frame in normal display mode by the shift amount shown in Table 6-6.
RS
1
D7
−
D6
MSD6
D5
MSD5
D4
MSD4
D3
MSD3
D2
MSD2
D1
MSD1
D0
MSD0
Table 6-6. AC Driver Inversion Position Shift Register (R7) Settings
MSD5
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
:
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
89
90
91
92
Caution The inversion position shift amount can not be over 91 (5CH). If 91 is exceeded, operation is not guaranteed.
Default settings (initial values set by reset command)
D7
−
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
59
µPD16488A
6.9 Partial AC Driver Inversion Cycle Register (R8)
The AC driver's line position can be set as shown in Table 6-7.
When a PDTn value is changed in the partial display mode setting register (R10), the PIDn value is automatically
overwritten by the PDTn value.
RS
1
D7
−
D6
−
D5
D4
D3
D2
D1
D0
PID5
PID4
PID3
PID2
PID1
PID0
Table 6-7. Partial AC Driver Inversion Cycle Register (R8) Settings
PID5
PID4
PID3
PID2
PID1
PID0
Inversion Line
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
1
1
0
1
0
1
1
2
3
4
:
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
36
37
38
Default settings (initial values set by reset command)
D7
−
D6
−
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
6.10 Partial AC Driver Inversion Position Shift Register (R9)
This register shifts the inversion position for each frame by the shift amount shown in Table 6-8.
RS
1
D7
−
D6
−
D5
PSD5
D4
PSD4
D3
PSD3
D2
PSD2
D1
PSD1
D0
PSD0
Table 6-8. Partial AC Driver Inversion Position Shift Register (R9) Settings
PSD5
PSD4
PSD3
PSD2
PSD1
PSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
:
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
35
36
37
Default settings (initial values set by reset command)
D7
−
D6
−
D5
−
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
60
µPD16488A
6.11 Partial Display Mode Setting Register (R10)
This command specifies the operation mode to be used in the µPD16488A's partial display mode.
Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations.
RS
1
D7
−
D6
−
D5
−
D4
−
D3
PBIS
D2
−
D1
PDT1
D0
PDT0
Flag
Function
PBIS
Sets bias level for partial display mode
0: 1/5 bias
1: 1/6 bias
PDT1, PDT0
PDT1
PDT0
Duty in partial display mode
1/38 duty
0
0
1
1
0
1
0
1
1/25 duty
1/12 duty
Prohibited
Caution With the setting of 1/12 duty, the level voltage (VLCn) for driving liquid crystal pannel may not reach the
set value depending on the panel used. Thoroughly evaluate the relationship between the duty and
driving voltage with the actual system.
Default settings (initial values set by reset command)
D7
−
D6
−
D5
−
D4
−
D3
0
D2
−
D1
0
D0
0
6.12 Display Memory Access Register (R11)
The display memory access register is used when accessing the display RAM. When this register is write-accessed, data
is written directly to the display RAM. When this register is read-accessed, data from the display RAM is first latched to this
register before being sent to the bus during the next read operation. Accordingly, one dummy read access is required after
display RAM access has been set.
When using reset command to reset, the contents of memory are retained.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
Data Sheet S15745EJ2V0DS
61
µPD16488A
6.13 Display Start Line Setting Register (R12)
Display start line set specifies the top line in the display.
RS
1
D7
−
D6
DSL6
D5
DSL5
D4
DSL4
D3
DSL3
D2
DSL2
D1
DSL1
D0
DSL0
Default settings (initial values set by reset command)
D7
−
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.14 Blink X Address Register (R13)
The blink X address register specifies the X address of the blink data RAM accessed by the CPU. This address is
automatically incremented each time the blink data RAM is accessed.
RS
1
D7
−
D6
−
D5
−
D4
−
D3
BXA3
D2
BXA2
D1
BXA1
D0
BXA0
Default settings (initial values set by reset command)
D7
−
D6
−
D5
−
D4
−
D3
0
D2
0
D1
0
D0
0
6.15 Blink Start Line Address Register (R14)
The blink start line address register specifies the start line address of the display RAM accessed when the CPU uses blink
display mode. The range of blinking lines is determined based on the contents of this register and the blink end line
address register.
RS
1
D7
−
D6
BSL6
D5
BSL5
D4
BSL4
D3
BSL3
D2
BSL2
D1
BSL1
D0
BSL0
Setting
−
Default settings (initial values set by reset command)
D7
−
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.16 Blink End Line Address Register (R15)
The blink end line address register specifies the end line address of the display RAM accessed when the CPU uses blink
display mode. The range of blinking lines is determined based on the contents of this register and the blink start line
address register.
RS
1
D7
−
D6
BEL6
D5
BEL5
D4
BEL4
D3
BEL3
D2
BEL2
D1
BEL1
D0
BEL0
Setting
−
Default settings (initial values set by reset command)
D7
−
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
62
µPD16488A
6.17 Blink Data Memory Access Register (R16)
The blink data memory access register is used to access the blink data RAM. When this register is write-accessed, data
is written directly to the blink data RAM.
When using reset command to reset, the contents of memory are retained.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Data
Status
0
1
Normal
Blink
Default settings (initial values set by reset command, all data)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.18 Inverted X Address Register (R17)
The inverted X address register specifies the X address in the inverted data RAM accessed by the CPU. This address is
incremented each time the inversion RAM is accessed.
RS
1
D7
−
D6
−
D5
−
D4
−
D3
IXA3
D2
IXA2
D1
IXA1
D0
IXA0
Default settings (initial values set by reset command)
D7
−
D6
−
D5
−
D4
−
D3
0
D2
0
D1
0
D0
0
6.19 Inversion Start Line Address Register (R18)
The inversion start line address register specifies the start line address in the display RAM accessed by the CPU when
using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and
the inversion end line address register.
RS
1
D7
−
D6
ISL6
D5
ISL5
D4
ISL4
D3
ISL3
D2
ISL2
D1
ISL1
D0
ISL0
Default settings (initial values set by reset command)
D7
−
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
63
µPD16488A
6.20 Inversion End Line Address Register (R19)
The inversion end line address register specifies the end line address in the display RAM accessed by the CPU when
using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and
the inversion start line address register.
RS
1
D7
−
D6
IEL6
D5
IEL5
D4
IEL4
D3
IEL3
D2
IEL2
D1
IEL1
D0
IEL0
Setting
−
Default settings (initial values set by reset command)
D7
−
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.21 Inverted Data Memory Access Register (R20)
The inverted data memory access register is used when accessing the inverted data RAM. When this register is
accessed, the data is written directly to the inverted data RAM.
When using reset command to reset, the contents of memory are retained.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Setting
−
Data
Status
0
1
Normal
Inverted
Default settings (initial values set by reset command, all data)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.22 Partial Start Line Address Register (R21)
The partial start line address register specifies the start line address in the display RAM accessed by the CPU when using
partial display mode. The partial display area is determined as the number of lines specified in the partial display mode
setting register (R10), starting from this start line address.
RS
1
D7
−
D6
PSL6
D5
PSL5
D4
PSL4
D3
PSL3
D2
PSL2
D1
PSL1
D0
PSL0
Setting
−
Default settings (initial values set by reset command)
D7
−
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
64
µPD16488A
6.23 Gray Scale Data Registers 1 to 4 (R23 to R26)
The gray scale data registers specify the gray scale level when using normal four-level gray scale display mode. Use of
this register optimizes the gray scale display.
Rx
Data
0, 0
0, 1
1, 0
1, 1
RS
1
1
1
1
D7
−
D6
−
D5
D4
D3
D2
D1
D0
Setting
−
−
−
−
R23
R24
R25
R26
GD5
GD5
GD5
GD5
GD4
GD4
GD4
GD4
GD3
GD3
GD3
GD3
GD2
GD2
GD2
GD2
GD1
GD1
GD1
GD1
GD0
GD0
GD0
GD0
−
−
−
−
−
−
D7
D6
D5
0
0
0
0
D4
0
0
0
0
:
D3
0
0
0
0
D2
0
0
0
0
D1
0
0
1
1
D0
0
1
0
1
Gray scale level
Level 0
Level 1
Level 2
Level 3
:
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
0
1
1
0
1
0
1
0
1
0
1
0
Level 31
Level 32
Default settings (initial values set by reset command, for all gray scale data registers)
D7
−
D6
−
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.24 Partial Gray Scale Data Registers 1 to 4 (R27 to R30)
The partial gray scale data registers specify the gray scale level when using partial four-level gray scale display mode.
Use of this register optimizes the gray scale display.
Rx
Data
0, 0
0, 1
1, 0
1, 1
RS
1
1
1
1
D7
−
D6
−
D5
D4
D3
D2
D1
D0
Setting
R27
R28
R29
R30
PGD5
PGD5
PGD5
PGD5
PGD4
PGD4
PGD4
PGD4
PGD3
PGD3
PGD3
PGD3
PGD2
PGD2
PGD2
PGD2
PGD1
PGD1
PGD1
PGD1
PGD0
PGD0
PGD0
PGD0
−
−
−
−
−
−
−
−
−
−
D7
D6
D5
0
0
0
0
D4
0
0
0
0
:
D3
0
0
0
0
D2
0
0
0
0
D1
0
0
1
1
D0
0
1
0
1
Gray scale level
Level 0
Level 1
Level 2
Level 3
:
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable Disable
Disable Disable
0
1
1
0
1
0
1
0
1
0
1
0
Level 31
Level 32
Default settings (initial values set by reset command, for all partial gray scale data registers)
D7
−
D6
−
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
65
µPD16488A
6.25 Power System Control Register 1 (R32)
This command sets the µPD16488A's power system mode.
E
/RD
1
R,/W
/WR
0
RS
1
D7
HPM1
D6
HPM0
D5
−
D4
TCS1
D3
TCS0
D2
OP2
D1
OP1
D0
OP0
Flag
Function
HPM1, HPM0
TCS1, TCS0
OP2 to OP0
These flags set the driver mode as shown in Table 6-9.
These flags set the value for selecting the VREG voltage's temperature curve, as shown in Table 6-10.
These flags control the booster's ON/OFF status, the voltage regulator (V regulator) and voltage follower (V/F).
The functions controlled via these three bits by the power control setting command are listed in Table 6-11.
Table 6-9. Driver Mode Setting
HPM1
HPM0
Mode Setting
Normal mode
Low-power mode
High-power mode
Power activation mode
0
0
1
1
0
1
0
1
Table 6-10. Selection VREG Voltage's Temperature Curve Value
TCS1
TCS0 Temperature gradient (%/°C)
VREG (TYP.) (V)
0
0
1
1
0
1
0
1
−0.06
−0.08
−0.09
−0.12
1.04
0.98
0.93
0.85
Table 6-11. Detailed Description of Functions Controlled by Flags of Power System Control 1
Status
Item
1
0
OP2
OP1
OP0
Booster control flag
V regulator control flag
Voltage follower control flag
ON
ON
ON
OFF
OFF
OFF
Default settings (initial values set by reset command)
D7
0
D6
0
D5
−
D4
0
D3
0
D2
1
D1
1
D0
1
Data Sheet S15745EJ2V0DS
66
µPD16488A
6.26 Power System Control Register 2 (R33)
This command is used to control the on-chip register for VLCD voltage regualation.
E
/RD
1
R,/W
/WR
0
RS
1
D7
−
D6
VRR2
D5
VRR1
D4
VRR0
D3
−
D2
PVR2
D1
PVR1
D0
PVR0
Setting
−
Flag
Function
VRR2 to VRR0
When using normal display mode, power system control 2 (VLCD regulator resistance factor setting command) can
be used to change the resistance factor at 8 levels. The three flags in power system control 2 set the values shown
in Table 6-12 as reference values for (1 + Rb/Ra).
PVR2 to PVR0
When using partial display mode, power system control 2 (VLCD regulator resistance factor setting command) can
be used to change the resistance factor at 8 levels. The three flags in power system control 2 set the values shown
in Table 6-12 as reference values for (1 + Rb/Ra).
Table 6-12. Reference Values for VLCD Internal Resistance Factor Regulator Register
Register
VRR2
PVR2
VRR1
PVR1
VRR0
PVR0
1+Rb/Ra
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5
8
12
13
16
19
21
24
Default settings (initial values set by reset command)
D7
−
D6
0
D5
0
D4
0
D3
−
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
67
µPD16488A
6.27 Power System Control Register 3 (R34)
This command sets the power system mode, including the bias setting for the µPD16488A's normal display mode and the
number of boost levels for partial display mode.
RS
1
D7
BIS2
D6
BIS1
D5
BIS0
D4
FBS2
D3
FBS1
D2
FBS0
D1
BST1
D0
BST0
Setting
−
Flag
Function
BIS2 to BIS0Note These three flags select the bias ratio as shown below.
BIS2
BIS1
BIS0
Bias ratio
1/12 bias
1/11 bias
1/10 bias
1/9 bias
1/8 bias
1/7 bias
Prohibited
Prohibited
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
When partial display mode is set, the bias ratio set by the partial mode setting register (R10) is automatically
selected.
FBS2 to FBS0Note The number of boost levels in booster for normal display mode is selected as shown below.
FBS2
FBS1
FBS0
Boost level
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x4
x5
x6
x7
x8
x9
Prohibited
Prohibited
BST1, BST0
The number of boost levels in the booster for partial display mode is selected as shown below.
BST1
BST0
Boost level
0
0
1
1
0
1
0
1
x2
x3
x4
Prohibited
Note Be sure to execute the HALT command before changing these flag settings.
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
68
µPD16488A
6.28 Electronic Volume Register (R35)
The electronic volume register specifies the electronic volume value for adjusting the contrast when using normal display
mode. Any value among 256 steps can be selected.
RS
1
D7
EV7
D6
EV6
D5
EV5
D4
EV4
D3
EV3
D2
EV2
D1
EV1
D0
EV0
Setting
−
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.29 Partial Electronic Volume Register (R36)
The partial electronic volume register specifies the electronic volume value for adjusting the contrast when using partial
display mode. Any value among 256 steps can be selected.
RS
1
D7
PEV7
D6
PEV6
D5
PEV5
D4
PEV4
D3
PEV3
D2
PEV2
D1
PEV1
D0
PEV0
Setting
−
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.30 Boost Adjustment Register (R37)
The voltage (range: 1/8 VDD2 to 7/8 VDD2) set to this register is applied to the boost level set for the booster.
RS
1
D7
−
D6
−
D5
−
D4
−
D3
−
D2
DDC2
D1
DDC1
D0
DDC0
Setting
−
Table 6-13. Boost Adjustment Register (R37) Settings
DDC2
DDC1
DDC0
Boost Adjustment Voltage
Regulator Circuit Stopped
1/8 VDD2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2/8 VDD2
3/8 VDD2
4/8 VDD2
5/8 VDD2
6/8 VDD2
7/8 VDD2
Default settings (initial values set by reset command)
D7
−
D6
−
D5
−
D4
−
D3
−
D2
0
D1
0
D0
0
Data Sheet S15745EJ2V0DS
69
µPD16488A
6.31 RAM Test Mode Setting Register (R44)
The RAM test mode setting register directly writes the data for each type of display mode to the display RAM, as shown in
Table 6-15.
RS
1
D7
−
D6
−
D5
−
D4
−
D3
RTS3
D2
RTS2
D1
RTS1
D0
RTS0
Table 6-15. RAM Test Mode Setting Register (R44) Setting
RTS3
RTS2
RTS1
RTS0
Write Data
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Normal operation
Displays list of gray scales
all 00/pixel
all 11/pixel
Checker pattern: 00/11
Checker pattern: 11/00
Checker pattern: 01/10
Checker pattern: 10/01
Vertical striped pattern: 00/11
Horizontal striped pattern: 00/11
Default settings (initial values set by reset command)
D7
−
D6
−
D5
−
D4
−
D3
0
D2
0
D1
0
D0
0
6.32 Signature Read Register (R45)
This command is used to read the IC signature set via the SIGIN1 and SIGIN2 pins. This is a read-only register.
RS
1
D7
−
D6
−
D5
−
D4
−
D3
−
D2
−
D1
SIGIN2
D0
SIGIN1
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
Data Sheet S15745EJ2V0DS
70
µPD16488A
7. LIST OF µPD16488A REGISTERS
Index Register
Data Bits
Register Name
R/W
W
CS RS
1
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IR5
IR4
IR3
IR2
IR1
IR0
IR
Index Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Control register 1
R/W RMW DISP STBY BLD IVD HALT ADC COMR
R0
R1
R2
R3
R4
R5
R6
R/W FDM
DSEL BWW GRAY DTY INC
CRES
XA4 XA3 XA2 XA1 XA0
Control register 2
Reset command
X address register
W
R/W
R/W
R/W
R/W
W
W
W
R/W
YA6 YA5 YA4 YA3 YA2 YA1 YA0
DT6 DT5 DT4 DT3 DT2 DT1 DT0
NID6 NID5 NID4 NID3 NID2 NID1 NID0
MSD6 MSD5 MSD4 MSD3 MSD2 MSD1 MSD0
PID4 PID3 PID2 PID1 PID0
Y address register
Duty setting register
AC driver inversion cycle register
AC driver inversion position shift register
Partial AC driver inversion cycle register
R7
R8
R9
PSD4 PSD3 PSD2 PSD1 PSD0
Partial AC driver inversion potision shift register
Partial display mode setting register
PBIS
PDT1 PDT0
R10
R/W
W
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
R11 Display memory access register
Display start line setting register
Blink X address register
DSL6 DSL5 DSL4 DSL3 DSL2 DSL1 DSL0
BXA3 BXA2 BXA1 BXA0
BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0
BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0
R12
R13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R14 Blink start line address register
R15
R16 Blink data memory access register
Blink end line address register
D
D
7
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
IXA3 IXA2 IXA1 IXA0
ISL6 ISL5 ISL4 ISL3 ISL2 ISL1 ISL0
IEL6 IEL5 IEL4 IEL3 IEL2 IEL1 IEL0
Inverted X address register
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
Inversion start line address register
Inversion end line address register
Inverted data memory access register
Partial start line address register
D
6
D
5
D
4
D
3
D
2
D
1
D0
PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0
Gray scale data register 1 (0, 0)
Gray scale data register 2 (0, 1)
Gray scale data register 3 (1, 0)
W
W
W
W
W
W
W
W
GD5 GD4 GD3 GD2 GD1 GD0
GD5 GD4 GD3 GD2 GD1 GD0
GD5 GD4 GD3 GD2 GD1 GD0
GD5 GD4 GD3 GD2 GD1 GD0
PGD5 PGD4 PGD3 PGD2 PGD1 PGD0
PGD5 PGD4 PGD3 PGD2 PGD1 PGD0
PGD5 PGD4 PGD3 PGD2 PGD1 PGD0
PGD5 PGD4 PGD3 PGD2 PGD1 PGD0
Gray scale data register 4 (1, 1)
Patial gray scale data register 1 (0, 0)
Patial gray scale data register 2 (0, 1)
Patial gray scale data register 3 (1, 0)
Patial gray scale data register 4 (1, 1)
R28
R29
R30
R31
R32
R33
R34
Power system control register 1
Power system control register 2
Power system control register 3
W
W
W
W
W
W
HPM1 HPM0
TCS1 TSC0 OP2 OP1 OP0
PVR2 PVR1 PVR0
BIS2 BIS1 BIS0 FBS2 FBS1 FBS0 BST1 BST0
EV7 EV6 EV5 EV4 EV3 EV2 EV1 EV0
PEV7 PEV6 PEV5 PEV4 PEV3 PEV2 PEV1 PEV0
DDC2 DDC1 DDC0
VRR2 VRR1 VRR0
R35 Electronic volume register
Partial electronic volume register
R36
R37 Boost adjustment register
R38
R39
R40
R41
R42
R43
W
R
RTS3 RTS2 RTS1 RTS0
SIG2 SIG1
R44 RAM test mode setting register
R45
Signature read register
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
Remark
: Not to use these registers.
Data Sheet S15745EJ2V0DS
71
µPD16488A
8. POWER SUPPLY SEQUENCE
The µPD16488A includes power supply circuitry, such as a booster and a voltage follower. When a reset is performed
using the /RES pin, the reset function is restricted so as to prevent operation faults that may occur due to noise effects, etc.
When electric charge remains in the smoothing capacitor that is connected between the VSS pin and the voltage pins
related to the LCD driver (VLCD, VLC1 to VLC4), troubles such as a brief all-black display screen may occur when the power is
switched ON or OFF. The following power-on sequence is recommended as a means to avoid such troubles when
switching the power ON or OFF.
8.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON ¡ Display ON)
Turn power ON when /RES pin = L
↓
Power supply stabilization
↓
/RES pin = H
↓
Wait at least 50 µs before command input
Command reset
R2
R0
Register reset
↓
Control register 1
DISP = 0, HALT = 1
↓
Display OFF, internal operations stopped
IC functions set via command input
• Control register 1
(DISP = 0, HALT = 1 status is retained)
• Control register 2
• Power control register 1
(HPM1, HPM0 = 1, 1)
Specification of power activation mode
• Power control registers 2, 3
• Electronic volume register
• Partial electronic volume register
• Boost adjustment register
↓
User-specified settings via command input
Duty setting register (R5)
Make sure to set the duty setting register (R5) and AC
driver inversion cycle register (R6)
AC driver inversion cycle register (R6)
Function settings for gray scale data, etc.
↓
Initialization complete
↓
Control register 1
DISP = 0, HALT = 0
↓
Display OFF, internal operations started
R0
R0
LCD display screen settings
• Display start line setting register
• Write screen data, etc. + wait time
↓
After internal operations are started, wait at least 400 ms
before turning on the LCD displayNote
.
Power system control register 1
Cancels V/F mode for power activation
(Mode except HPM1, HPM0 (1, 1))
↓
Control register 1
DISP = 1, HALT = 0
Display ON, internal operation start mode
Note This 400ms wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the
actual device (refer to 8.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF)).
Data Sheet S15745EJ2V0DS
72
µPD16488A
8.2 Power OFF Sequence (When Using On-Chip Power Supply)
Operation mode
↓
Display OFF, internal operation start mode
DISP = 0, HALT = 0
R0
↓
Sets high power mode
HPM1 = 1, HPM0 = 0
R32
↓
[EV7, EV6, EV5, EV4, EV3, EV2, EV1, EV0]
= [0, 0, 0, 0, 0, 0, 0, 0]
Set electronic volume register
R35
R36
↓
[PEV7, PEV6, PEV5, PEV4, PEV3, PEV2, PEV1, PEV0]
= [0, 0, 0, 0, 0, 0, 0, 0]
Set partial electronic volume register
Wait at least 1200ms before power OFFNote
.
↓
Power supply OFF
Note This 1200ms wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. NEC recommends determining the wait time after making a thorough evaluation of the
actual device (refer to 8.5 VOUT, VLCD Voltage Sequence (power ON → power OFF)).
8.3 Power ON Sequence (When Using External Driver Power Supply, Power ON → Display ON)
Logic power ON when /RES pin = L
VDD1, VDD2 power ON, VOUT = Hi-Z
↓
Power supply stabilization
↓
/RES pin = H
↓
Command reset
Wait at least 50 µs befor command input
R2
R0
Register reset
↓
Display OFF, internal operations stopped
DISP = 0, HALT = 1
↓
Initialization via command input (user-specified)
Selection of IC functions, etc.
Power system control register 1 (R32) :
[OP2, OP1, OP0] = [0 ,0 ,X]
↓
DISP = 0, HALT = 0
R0
R0
Display OFF, internal operations started
↓
VOUT power supply ON
External LCD driver power supply ON
↓
Stabilization of external LCD driver power supply
↓
Display ON, internal operations started
DISP = 1, HALT = 0
Data Sheet S15745EJ2V0DS
73
µPD16488A
8.4 Power Supply OFF Sequence (When Using External Driver Power Supply)
Operation mode
↓
DISP = 0, HALT = 0
Display OFF, internal operation start mode
VOUT = Hi-Z
R0
R0
↓
External driver power supply OFF
↓
DISP = 0, HALT = 1
↓
Display OFF, internal operations stopped
VDD1, VDD2, power supply OFF
Logic power supply OFF
Data Sheet S15745EJ2V0DS
74
µPD16488A
8.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF)
0 VDD
V
OUT
/RES pin = 0
Power ON
/RES pin = 1
DISP = 0, HALT = 1
Default settings
HPM = 3
HALT = 0
400 ms
Select HPM = 0 to 2
DISP = 1
Normal display
DISP = 0
HPM = 2
DTY = 1
700 ms
LCD = 15V 6V
V
Select HPM = 0 to 2
DISP = 1
Partial display
DISP = 0
HPM = 3
DTY = 0
400 ms
Select HPM = 0 to 2
DISP = 1
Normal display
DISP = 0
HPM = 2
EV = 0
1200 ms
Power OFF
Dotted line: VOUT
Solid line: VLCD
Conditions:
VDD: VDD1 = VDD2 = 3.0 V
Boost levels: x6 (in normal display mode), x3 (in partial display mode)
Capacitors: VLCn pin to Cn+/− pin = 1 µF,
AMPOUT pin, AMPOUTP pin, VRS pin = 0.1µF
Caution Connect a capacitor of less than 0.1µF to both AMPOUT and AMPOUTP pins.
Data Sheet S15745EJ2V0DS
75
µPD16488A
9. USE OF RAM TEST MODE
The µPD16488A has a test mode for writing nine types of screen data to display RAM. When using the test mode, be sure
to execute via the sequence shown below. If executing the test mode by some other sequence, troubles may appear in the
screen display.
Operation mode
↓
Control register 1
DISP = 0, STBY = 1
Display OFF, set to standby
R0
↓
Set RAM test mode
R44
R0
Select RAM write data
↓
Control register 1
Display OFF, cancel standby
DISP = 0, STBY = 0
↓
After internal operations are started, wait at least 1sec
Wait time
before turning on the LCD displayNote
.
↓
Control register 1
Display ON
R0
DISP = 1
↓
Settings complete
Note This 1sec wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the
actual device.
Data Sheet S15745EJ2V0DS
76
µPD16488A
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C, VSS = 0 V)
Parameter
Logic system supply voltage
Booster supply voltage
Symbol
Ratings
Unit
V
V
V
V
V
V
V
V
VDD1
VDD2
VOUT
−0.3 to +4.0
−0.3 to +4.0
Driver supply voltage
−0.3 to +20.0
−0.3 to VOUT+0.3
−0.3 to VDD1+0.3
−0.3 to VDD1+0.3
−0.3 to VDD1+0.3
−0.3 to VOUT+0.3
−0.3 to VOUT+0.3
−40 to +85
Driver reference supply input voltage
Logic system input voltage
Logic system output voltage
Logic system input/output voltage
Driver system input voltage
Driver system output voltage
Operating ambient temperature
Storage temperature
VLCD, VLC1 to VLC4
VIN1
VOUT1
VI/O1
VIN2
VOUT2
TA
V
°C
°C
Tstg
−55 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure
that the absolute maximum ratings are not exceeded.
Recommended Operating Range
Parameter
Logic system supply voltage
Booster supply voltage
Driver system supply voltage
Logic system input voltage
Driver system supply voltage
Symbol
MIN.
1.7
2.4
5.5
0
TYP.
MAX.
3.6
3.6
18.0
VDD1
Unit
V
V
V
V
VDD1
VDD2
VOUT
VIN
Note1
Note2
Note2
VLCD, VLC1 to VLC4
0
VOUT
VOUT −0.5
V
V
Note3
Maximum setting for LCD driver voltage VLCD
Notes 1. VDD1 must be less than or equal to VDD2
2. This item is the recommended parameter when the LCD has an external driver.
3. This item is the recommended parameter when an on-chip power supply circuit drives the LCD.
Cautions 1. When using an external LCD driver, be sure to maintain these relations:
VSS < VLC4 < VLC3 < VLC2 < VLC1 < VLCD ≤ VOUT.
2. Maintain the relations shown in 8. POWER SUPPLY SEQUENCE when turning the power ON or OFF.
3. When using an external resister (when not using an on-chip resister for VLCD adjustment), maintain
supply of a voltage between 1.0 V and the VDD1 voltage to the VR and VRS pins.
Data Sheet S15745EJ2V0DS
77
µPD16488A
Electrical Characteristics 1
(Unless Otherwise Specified, TA = −40 to +85°C, VDD1 = 1.7 to 3.6 V, VDD2 = 2.4 to 3.6 V)
Parameter
Symbol
Conditions
MIN.
TYP.Note1
MAX.
Unit
V
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
High-level leakage current
VIH
VIL
0.8 VDD1
0.2 VDD1
V
IIH1
IIL1
VOH
VOL
ILOH
Except for D7 (SI), D6 (SCL) and D5 to D0
Except for D7 (SI), D6 (SCL) and D5 to D0
IOUT = −1 mA except OSCOUT
IOUT = 1 mA except OSCOUT
D7 (SI), D6 (SCL) and D5 to D0,
VIN/OUT = VDD1
1
−1
µA
µA
V
V
µA
VDD1 −0.5
0.5
10
Low-level leakage current
ILOL
D7 (SI), D6 (SCL) and D5 to D0,
VIN/OUT = VSS
VLCn → COMn, VOUT = 15 V, VLCD = 12 V,
1/10 bias, |IO| = 50 µA
VLCn → SEGn, VOUT = 15 V, VLCD = 12 V,
1/10 bias, |IO| = 50 µA
In x5 boost mode, VDD = 3.0 V,
Checker pattern display
In x6 boost mode, VDD = 3.0 V,
Checker pattern display
VDD = 3.0 V, TA = 85°C, TSC1,TSC0 = 1,1
(temperature characteristic curves:−0.12%/°C)
VDD1 = 3.0 V, TA = 25°C, 1/92 duty,
in B/W mode, R = 1100 kΩ
−10
4
µA
kΩ
kΩ
V
Common output ON resistance RCOM
Segment output ON resistance RSEG
Driver voltage (boost voltage) VOUT
4
13.8
16.6
V
Note2
Reference voltage
VREG
0.720
0.790
26.9
10.6
0.860
V
Note3
Oscillation frequency
fOSC
kHz
kHz
VDD1 = 3.0 V, TA = 25°C, 1/38 duty,
in B/W mode, R = 3 MΩ
Notes 1. TYP. values are reference values when TA = 25°C (except VREG).
2. The reference voltage values when TA = 25°C are shown below:
MIN. = 0.775 V, TYP.= 0.850 V, MAX. = 0.925 V
3. The oscillation frequency varies according to the parasitic capacitance of the wiring capacitance. We therefore
recommend determining the oscillation resister’s value after making a thorough evaluation of the actual device.
Data Sheet S15745EJ2V0DS
78
µPD16488A
Electrical Characteristics 2
(Unless Otherwise Specified, TA = −40 to +85°C)
Parameter
Symbol
Conditions
MIN.
TYP.Note
160
MAX.
Unit
Current consumption
(normal mode)
IDD11
Frame frequency = 70 Hz,
220
310
390
480
155
230
140
160
10
µA
B/W all display OFF data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Frame frequency = 70 Hz,
210
270
325
115
165
95
µA
µA
µA
µA
µA
µA
µA
µA
B/W checker pattern display data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Frame frequency = 70 Hz,
B/W all display OFF data output,
1/92 duty, VDD1 = VDD2 =3.0 V,
in x5 boost mode, VLCD = 12 V
Frame frequency = 70 Hz,
B/W checker pattern display data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Frame frequency = 70 Hz,
B/W all display OFF data output,
1/92 duty, VDD1 = VDD2 =3.0 V,
in x5 boost mode, VLCD = 12 V
Frame frequency = 70 Hz,
B/W checker pattern display data output,
1/92 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 12 V
Frame frequency = 70 Hz,
B/W all display OFF data output,
1/38 duty, VDD1 = VDD2 =3.0 V,
in x3 boost mode, VLCD = 7.0 V, normal mode
Frame frequency = 70 Hz,
B/W checker pattern display data output,
1/38 duty, VDD1 = VDD2 = 3.0 V,
VLCD = 7.0 V, in x3 boost mode, normal mode
VDD1 = VDD2 = 3.0 V
Current consumption
(high-power mode)
IDD12
IDD13
IDD21
IDD22
Current consumption
(low-power mode)
Current consumption
(partial display mode)
105
Current consumption
(standby mode)
Note TYP. values are reference values when TA = 25°C.
Data Sheet S15745EJ2V0DS
79
µPD16488A
Required Timing Conditions (Unless Otherwise Specified, TA = −30 to +85°C)
(1) i80 CPU interface
RS
t
AH8
t
AS8
t
f
t
r
/CS1
(CS2 = H)
t
CYC8
t
CCLW, tCCLR
/WR, /RD
t
CCHR, tCCHW
t
DS8
t
DH8
D0
to D
7
(Write)
t
OH8
t
ACC8
D0 to D7
(Read)
When VDD1 = 1.7 V to 2.0 V
Parameter
Address hold time
Address setup time
System cycle time
Control low-level pulse width (/WR) tCCLW
Control low-level pulse width (/RD) tCCLR
Control high-level pulse width (/WR) tCCHW
Control high-level pulse width (/RD) tCCHR
Data setup time
Data hold time
/RD access time
Output disable time
Symbol
tAH8
tAS8
Conditions
MIN.
0
0
1000
160
430
160
160
160
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
tCYC8
/WR
/RD
/WR
/RD
D0 to D7
D0 to D7
tDS8
tDH8
tACC8
tOH8
D0 to D7, CL = 100 pF
D0 to D7, CL = 5 pF, R = 3 kΩ
0
0
470
170
Note TYP. values are reference values when TA = 25°C.
Data Sheet S15745EJ2V0DS
80
µPD16488A
When VDD1 = 2.0 to 2.5 V
Parameter
Symbol
tAH8
tAS8
Conditions
MIN.
0
0
600
120
240
120
120
120
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
Address setup time
System cycle time
Control low-level pulse width (/WR) tCCLW
Control low-level pulse width (/RD) tCCLR
Control high-level pulse width (/WR) tCCHW
Control high-level pulse width (/RD) tCCHR
Data setup time
Data hold time
/RD access time
Output disable time
RS
RS
tCYC8
/WR
/RD
/WR
/RD
D0 to D7
D0 to D7
tDS8
tDH8
tACC8
tOH8
D0 to D7, CL = 100 pF
D0 to D7, CL = 5 pF, R = 3 kΩ
0
0
280
170
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Address hold time
Address setup time
System cycle time
Control low-level pulse width (/WR) tCCLW
Control low-level pulse width (/RD) tCCLR
Control high-level pulse width (/WR) tCCHW
Control high-level pulse width (/RD) tCCHR
Data setup time
Data hold time
/RD access time
Output disable time
Symbol
tAH8
tAS8
Conditions
MIN.
0
0
250
60
120
60
60
60
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
tCYC8
/WR
/RD
/WR
/RD
D0 to D7
D0 to D7
tDS8
tDH8
tACC8
tOH8
D0 to D7, CL = 100 pF
D0 to D5, CL = 5 pF, R = 3 kΩ
0
0
140
70
Note TYP. values are reference values when TA = 25°C.
/CS1
(CS2 = H)
t
RD
/RD
(VDD1 = 1.8 to 3.6 V)
Parameter
Symbol
tRD
Conditions
MIN.
10
TYP.Note
MAX.
Unit
ns
Chip select disable time
/RD-CS
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15745EJ2V0DS
81
µPD16488A
(2) M68 CPU interface
RS
R,/W
t
AH6
t
AS6
t
f
tr
/CS1
(CS2 = H)
t
CYC6
t
EWHR, tEWHW
E
t
EWLR, tEWLW
t
DS6
t
DH6
D0
to D
7
(Write)
t
ACC6
t
OH6
D0 to D7
(Read)
When VDD1 = 1.7 to 2.0 V
Parameter
Address hold time
Address setup time
System cycle time
Data setup time
Symbol
tAH6
tAS6
tCYC6
tDS6
tDH6
Conditions
MIN.
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
0
0
1000
160
0
D0 to D7
D0 to D7
Data hold time
Access time
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
D0 to D7, CL = 100 pF
D0 to D7, CL = 5 pF, R = 3 kΩ
E
E
E
E
0
0
430
160
160
160
470
170
Output disable time
Enable high pulse width Read
Write
Enable low pulse width
Read
Write
Note TYP. values are reference values when TA = 25°C.
Data Sheet S15745EJ2V0DS
82
µPD16488A
When VDD1 = 2.0 to 2.5 V
Parameter
Symbol
tAH6
tAS6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
Conditions
MIN.
0
0
600
120
0
0
0
240
120
120
120
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable high pulse width Read
Write
RS
RS
D0 to D7
D0 to D7
D0 to D7, CL = 100 pF
D0 to D7, CL = 5 pF, R = 3 kΩ
280
170
E
E
E
E
Enable low pulse width
Read
Write
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Symbol
tAH6
tAS6
tCYC6
tDS6
tDH6
Conditions
MIN.
0
0
250
60
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
D0 to D7
D0 to D7
Access time
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
D0 to D7, CL = 100 pF
D0 to D7, CL = 5 pF, R = 3 kΩ
E
E
E
E
0
0
120
60
60
60
140
70
Output disable time
Enable high pulse width Read
Write
Enable low pulse width
Read
Write
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signals (tr and tf) are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) ≤ (tCYC6 − tEWLW − tEWHW) or (tr + tf) ≤ (tCYC6 − tEWLR −
tEWHR).
2. All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15745EJ2V0DS
83
µPD16488A
(3) Serial interface
t
CSS
t
CSH
/CS1
(CS2 = H)
t
SAS
t
SAH
RS
t
SCYC
t
SLW
SCL
t
f
t
SHW
t
r
t
SDS
tSDH
SI
When VDD1 = 1.7 to 2.5 V
Parameter
Symbol
tSCYC
Conditions
MIN.
250
100
100
150
150
100
100
150
150
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial clock cycle
SCL
SCL
SCL
RS
RS
SI
SI
CS
CS
SCL high-level pulse width
SCL low-level pulse width
Address hold time
Address setup time
Data setup time
tSHW
tSLW
tSAH
tSAS
tSDS
tSDH
tCSS
tCSH
Data hold time
CS-SCL time
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Symbol
tSCYC
Conditions
MIN.
TYP.Note
MAX.
Unit
Serial clock cycle
SCL
SCL
SCL
RS
RS
SI
SI
CS
CS
150
60
60
90
90
60
60
90
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL high-level pulse width
SCL low-level pulse width
Address hold time
Address setup time
Data setup time
tSHW
tSLW
tSAH
tSAS
tSDS
tSDH
tCSS
tCSH
Data hold time
CS-SCL time
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15745EJ2V0DS
84
µPD16488A
(4) Common
Parameter
Symbol
fN
Conditions
MIN.
TYP.Note
26.9
MAX.
150
Unit
kHz
Clock input 1
When using OSCIN1, external clock, and
on-chip divider, 1/92 duty, B/W mode
When using OSCIN1, external clock, and
on-chip divider, 1/92 duty,
53.8
150
kHz
four-level gray scale mode
Clock input 2
fP
When using OSCIN2, external clock for
partial display mode, but not using on-chip
divider, B/W mode
10.6
21.3
50
50
kHz
kHz
When using OSCIN2, external clock for
partial display mode, but not using on-chip
divider, four-level gray scale mode
Note TYP. values are reference values when frame frequency = 70 Hz.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD1.
(a) Display control output timing
OSCSYNC
t
DFR
FR
(VDD1 = 1.7 to 2.5 V)
Parameter
Symbol
tDFR
Conditions
MIN.
MIN.
TYP.Note
50
MAX.
200
Unit
ns
FR delay time
FR, CL = 50 pF
Note TYP. values are reference values when TA = 25°C.
(VDD1 = 2.5 to 3.6 V)
Parameter
Symbol
tDFR
Conditions
TYP.Note
20
MAX.
80
Unit
ns
FR delay time
FR, CL = 50 pF
Note TYP. values are reference values when TA = 25°C.
Caution All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15745EJ2V0DS
85
µPD16488A
(b) Reset timing
t
RW
/RES
t
R
Internal
status
During reset
Reset complete
When VDD1 = 1.7 to 2.5 V
Parameter
Reset time
Symbol
tR
tRW
Conditions
MIN.
50
TYP.Note
MAX.
50
Unit
µs
Reset low pulse width
/RES
µs
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Reset time
Reset low pulse width
Symbol
tR
tRW
Conditions
MIN.
50
TYP.Note
MAX.
50
Unit
µs
/RES
µs
Note TYP. values are reference values when TA = 25°C.
Caution All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15745EJ2V0DS
86
µPD16488A
11. CPU INTERFACE (REFERENCE EXAMPLE)
The µPD16488A can be connected to either an i80 series CPU or an M68 series CPU. Also, if a serial interface
connection is used, the number of signal lines can be reduced.
If several µPD16488A chip is used, the display area can be enlarged. When using this method, use the chip select signal
to select and access the ICs.
(1) M68 series CPU
V
CC
VDD1
A0
RS
A1 to A15
VIMA
C86
/CS1
Decoder
D0
to D
7
D0 to D7
CPU
E
E
R/W
R,/W
/RES
PSX
/RES
V
SS
GND
/RESET
(2) i80 series CPU
V
CC
VDD1
A0
RS
A1 to A7
/IORQ
C86
/CS1
Decoder
D0
to D
7
D0 to D7
CPU
/RD
/RD
/WR
/WR
PSX
/RES
/RES
V
SS
GND
/RESET
Data Sheet S15745EJ2V0DS
87
µPD16488A
(3) When using serial interface
V
CC
VDD1
A0
RS
C86
H or L
/CS1
Decoder
Open
A1 to A7
D0 to D5
CPU
Port1
SI(D7)
/Port2
SCL(D
6)
PSX
/RES
/RES
V
SS
GND
/RESET
Data Sheet S15745EJ2V0DS
88
µPD16488A
[MEMO]
Data Sheet S15745EJ2V0DS
89
µPD16488A
[MEMO]
Data Sheet S15745EJ2V0DS
90
µPD16488A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15745EJ2V0DS
91
相关型号：
UPD16510AGR-8JG-E1-A
SPECIALTY INTERFACE CIRCUIT, PDSO20, 5.72 MM, LEAD FREE, PLASTIC, SSOP-20
RENESAS
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