UPD16498 [NEC]
1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM; 1/128 DUTY LCD控制器/驱动器，四级灰度，片上RAM
| 型号： | UPD16498 |
| 厂家： | 
NEC |
| 描述： | 1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM |
| 文件： | 总95页 (文件大小：684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16498
1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
DESCRIPTION
The µPD16498 is a controller/driver which includes display RAM for full-dot LCDs that can provide a four-level gray scale
display. This IC is able to drive full-dot LCDs that contain up to 128 x 128 dots.
FEATURES
• LCD controller/driver with on-chip display RAM
• Full dot outputs: 128 segment outputs and 128 common outputs
• Static icon outputs: 20 segment outputs and 2 common outputs (same signal is output)
• Can operate using single power supply (logic system) in range from 1.7 to 3.6 V.
• Selection of four levels of gray scales from among 33 possible levels (four-frame rate control + 8 pulse width
modulation)
• Serial data input and 8-bit parallel data input (i80 series interface and M68 series interface)
• Dot display RAM: 128 x 128 x 2 bits
• On-chip booster: Switchable from x2 to x9 modes
• Selectable bias levels: 1/12 to 1/7 bias (normal display), 1/6 or 1/5 bias (partial display)
• Duty settings: 1/128 to 1/1 duty
• On-chip voltage divider resistor
• On-chip oscillator
ORDERING INFORMATION
Part Number
µPD16498P
µPD16498W
Package
Chip
Wafer
Remark Purchasing the chip/wafer entails the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representative.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15730EJ2V0DS00 (2nd Edition)
2001
Date Published June 2002 NS CP(K)
µPD16498
TABLE OF CONTENTS
1. BLOCK1. BLOCK DIAGRAM ................................................................................................................... 5
2. PIN CONFIGURATION (PAD LAYOUT) ................................................................................................... 6
3. PIN FUNCTIONS ...................................................................................................................................... 10
3.1 Power Supply System Pins ............................................................................................................................ 10
3.2 Logic System Pins .......................................................................................................................................... 11
3.3 Driver-Related Pins ......................................................................................................................................... 13
3.4 Test Pins ......................................................................................................................................................... 14
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS .................................... 15
5. DESCRIPTION OF FUNCTIONS ............................................................................................................. 16
5.1 CPU Interface ....................................................................................................................................... 16
5.1.1 Selection of interface type ............................................................................................................ 16
5.1.2 Parallel interface ........................................................................................................................... 16
5.1.3 Serial interface ............................................................................................................................ 18
5.1.4 Chip select ................................................................................................................................... 18
5.1.5 Display data RAM and on-chip register access ................................................................................ 18
5.2 Display Data RAM ................................................................................................................................ 21
5.2.1 Display data RAM .................................................................................................................................... 21
5.2.2 X address circuit ..................................................................................................................................... 21
5.2.3 Column address circuit ............................................................................................................................ 23
5.2.4 Y address circuit ...................................................................................................................................... 23
5.2.5 Common scan circuit ............................................................................................................................... 23
5.2.6 Display start line set ................................................................................................................................. 23
5.2.7 Display data latch circuit .......................................................................................................................... 23
5.3 Blink/Reverse Display Circuit ......................................................................................................................... 24
5.4 Oscillator .......................................................................................................................................................... 26
5.5 Display Timing Generator ............................................................................................................................... 30
5.6 Power Supply Circuit ....................................................................................................................................... 31
5.6.1 Booster .................................................................................................................................................... 31
5.6.2 Voltage regulator ..................................................................................................................................... 33
5.6.3 Use of op amp for level power supply control .......................................................................................... 36
5.6.4 Application examples of power supply circuits ......................................................................................... 37
5.7 LCD Display Drivers ........................................................................................................................................ 40
5.7.1 Full-dot pulse width modulation ............................................................................................................... 40
5.7.2 Full-dot frame rate control ........................................................................................................................ 45
5.7.3 Line shift driver ........................................................................................................................................ 46
5.7.4 Display size settings ................................................................................................................................ 48
5.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position ......................................... 48
2
Data Sheet S15730EJ2V0DS
µPD16498
5.8 Display Modes .................................................................................................................................................. 50
5.8.1 Partial display mode ................................................................................................................................ 50
5.8.2 Monochrome (black/white) display ........................................................................................................... 52
5.8.3 Icon display .............................................................................................................................................. 54
5.9 Reset ................................................................................................................................................................. 56
6. COMMAND REGISTERS .......................................................................................................................... 57
6.1 Control Register 1 (R0) .................................................................................................................................... 58
6.2 Control Register 2 (R1) .................................................................................................................................... 59
6.3 Reset Command (R2) ....................................................................................................................................... 60
6.4 X Address Register (R3) .................................................................................................................................. 60
6.5 Y Address Register (R4) .................................................................................................................................. 60
6.6 Duty Setting Register (R5) .............................................................................................................................. 61
6.7 AC Driver Inversion Cycle Register (R6) ........................................................................................................ 61
6.8 AC Driver Inversion Position Shift Register (R7) .......................................................................................... 62
6.9 Partial AC Driver Inversion Cycle Register (R8) ............................................................................................ 62
6.10 Partial AC Driver Inversion Position Shift Register (R9) ............................................................................ 63
6.11 Partial Display Mode Setting Register (R10) ................................................................................................ 63
6.12 Display Memory Access Register (R11)........................................................................................................ 64
6.13 Display Start Line Setting Register (R12) ..................................................................................................... 64
6.14 Blink X Address Register (R13) .................................................................................................................... 64
6.15 Blink Start Line Address Register (R14) ...................................................................................................... 65
6.16 Blink End Line Address Register (R15) ....................................................................................................... 65
6.17 Blink Data Memory Access Register (R16) .................................................................................................. 65
6.18 Inverted X Address Register (R17) ............................................................................................................... 66
6.19 Inversion Start Line Address Register (R18) ................................................................................................ 66
6.20 Inversion End Line Address Register (R19) ................................................................................................ 66
6.21 Inverted Data Memory (R20) .......................................................................................................................... 67
6.22 Partial Start Line Address Register (R21) .................................................................................................... 67
6.23 Gray Scale Data Registers 1 to 4 (R23 to R26) ............................................................................................ 68
6.24 Partial Gray Scale Data Registers 1 to 4 (R27 to R30) ................................................................................ 68
6.25 Power System Control Register 1 (R32) ...................................................................................................... 69
6.26 Power System Control Register 2 (R33) ...................................................................................................... 70
6.27 Power System Control Register 3 (R34) ...................................................................................................... 71
6.28 Electronic Volume Register (R35) ................................................................................................................ 72
6.29 Partial Electronic Volume Register (R36) .................................................................................................... 72
6.30 Boost Adjustment Register (R37) ................................................................................................................. 72
6.31 Static Icon Address Register (R40) ............................................................................................................. 73
6.32 Static Icon Data Register (R41) ..................................................................................................................... 73
6.33 Static Icon Contrast Register (R42) .............................................................................................................. 73
6.34 RAM Test Mode Setting Register (R44) ........................................................................................................ 74
6.35 Signature Read Register (R45) ..................................................................................................................... 74
7. LIST OF µPD16498 REGISTERS ............................................................................................................ 75
3
Data Sheet S15730EJ2V0DS
µPD16498
8. POWER SUPPLY SEQUENCE ................................................................................................................ 76
8.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON → Display ON) ................ 76
8.2 Power OFF Sequence (When Using On-Chip Power Supply) ...................................................................... 77
8.3 Power ON Sequence (When Using External Driver Power Supply, Power ON → Display ON) ................. 77
8.4 Power Supply OFF Sequence (When Using External Driver Power Supply) .............................................. 78
8.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF) .............................................................................. 79
9. USE OF RAM TEST MODE ..................................................................................................................... 80
10. USE OF STANDBY/HALT MODE ......................................................................................................... 81
11. ELECTRICAL SPECIFICATIONS .......................................................................................................... 82
12. CPU INTERFACE (REFERENCE EXAMPLE) ...................................................................................... 91
4
Data Sheet S15730EJ2V0DS
µPD16498
1. BLOCK DIAGRAM
SEG128
PCOM2
PCOM
1
SEG
1
COM
1
COM128
Data
register
Pictograph common driver
Common driver
Segment driver
/RES
/CS1
CS2
C86
PSX
Segment
G/S and blink
control
PSEG
1
Pictograph
segment
driver
PSEG20
RDS
/RD(E)
/WR(R,/W)
Display data latch
Pictograph
common
timing
Common
timing
generator
P
6
7
(SI)
(SCL)
to P
P
P
5
0
generator
Display data RAM
(128 x 128 x 2 bits)
Icon data RAM
(20 x 2 bits)
RS
IRS
I/O
buffer
TM/S
TFR
TFRSYNC
TDOF
Address decoder
TSISYNC
SIGIN1
SIGIN2
TSTIFS
TSTRTST
TSTVIHL
TESTOUT
Command decoder
Register
Segment
G/S and blink
timer
OSCIN1
OSCIN2
OSCOUT
TOSCSYNC
CLS
Timing generator
Oscillator
circuit
D/A converter
-
+
C1 , C1
DC/DC
converter
LCD voltage generator
Op amp
+
-
C9
,
C9
C1A
V
OUT
V
RS
IRS
V
R
AMPOUTP AMPOUT
V
LCD
V
LC1
V
LC2
V
LC3
V
LC4
V
DD1
V
DD2
VSS
Remark /xxx indicates active low signals.
5
Data Sheet S15730EJ2V0DS
µPD16498
2. PIN CONFIGURATION (PAD LAYOUT)
Chip size
Chip
：3.0 x 11.4 mm2
：485 µm TYP.
489
451
A1
1
A4
450
Y
X
211
A2
251
A3
212
6
Data Sheet S15730EJ2V0DS
µPD16498
•ꢀµPD16498 Pad Layout (1/3)
Pad
No.
Pin Name
Pad
Type
Pad Coordinate
Pad
No.
Pin Name
Pad
Type
Pad Coordinate
Pad
No.
Pin Name
Pad
Type
Pad Coordinate
µ
µ
µ
µ
µ
µ
X[ m]
Y[ m]
X[ m]
Y[ m]
X[ m]
Y[ m]
1
DUMMY
DUMMY
PSEG1
PSEG1
DUMMY
PSEG2
PSEG2
PSEG3
PSEG3
B
A
A
A
A
A
A
A
A
A
A
A
A
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
5341.000
5250.000
5150.000
5100.000
5050.000
5000.000
4950.000
4900.000
4850.000
4800.000
4750.000
4700.000
4650.000
71 C4-
A
A
A
A
A
A
A
A
A
A
A
A
A
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
1750.000
1700.000
1650.000
1600.000
1550.000
1500.000
1450.000
1400.000
1350.000
1300.000
1250.000
1200.000
1150.000
141 P3
142 P2
143 P2
144 DUMMY
145 P1
146 P1
147 P0
148 P0
149 DUMMY
150 TFRSYNC
151 TFRSYNC
152 TFR
153 TFR
A
A
A
A
A
A
A
A
A
A
A
A
A
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1750.000
-1800.000
-1850.000
-1900.000
-1950.000
-2000.000
-2050.000
-2100.000
-2150.000
-2200.000
-2250.000
-2300.000
-2350.000
2
3
4
5
6
7
8
9
72 C4-
73 C4+
74 C4+
75 C3-
76 C3-
77 C3+
78 C3+
79 C2-
80 C2-
81 C2+
82 C2+
83 C1-
10 DUMMY
11 PSEG4
12 PSEG4
13 PSEG5
14 PSEG5
15 DUMMY
A
A
-1383.500
-1383.500
4600.000
4550.000
84 C1-
85 C1+
A
A
-1383.500
-1383.500
1100.000
1050.000
154 DUMMY
155 TDOF
A
A
-1383.500
-1383.500
-2400.000
-2450.000
16 PSEG6
17 PSEG6
18 PSEG7
19 PSEG7
A
A
A
A
-1383.500
-1383.500
-1383.500
-1383.500
4500.000
4450.000
4400.000
4350.000
86 C1+
87 C1A
88 C1A
89 VDD2
A
A
A
A
-1383.500
-1383.500
-1383.500
-1383.500
1000.000
950.000
900.000
850.000
156 TDOF
A
A
A
A
-1383.500
-1383.500
-1383.500
-1383.500
-2500.000
-2550.000
-2600.000
-2650.000
157 OSCIN1
158 OSCIN1
159 OSCIN2
20 DUMMY
21 PSEG8
22 PSEG8
23 PSEG9
24 PSEG9
25 DUMMY
26 PSEG10
27 PSEG10
28 VSS
29 VRS
30 VRS
31 AMPOUTP
32 AMPOUTP
33 AMPOUT
34 AMPOUT
35 VR
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
4300.000
4250.000
4200.000
4150.000
4100.000
4050.000
4000.000
3950.000
3900.000
3850.000
3800.000
3750.000
3700.000
3650.000
3600.000
3550.000
3500.000
3450.000
3400.000
3350.000
3300.000
3250.000
3200.000
3150.000
3100.000
3050.000
3000.000
2950.000
2900.000
2850.000
2800.000
2750.000
2700.000
2650.000
2600.000
2550.000
2500.000
2450.000
2400.000
2350.000
2300.000
2250.000
2200.000
2150.000
2100.000
2050.000
2000.000
1950.000
1900.000
1850.000
1800.000
90 VDD2
91 VDD2
92 VDD1
93 VDD1
94 VDD1
95 VSS
96 VSS
97 VSS
98 CLS
99 CLS
100 VDD1
101 TM/S
102 TM/S
103 VSS
104 C86
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
800.000
750.000
700.000
650.000
600.000
550.000
500.000
450.000
400.000
350.000
300.000
250.000
200.000
150.000
100.000
50.000
0.000
-50.000
-100.000
-150.000
-200.000
-250.000
-300.000
-350.000
-400.000
-450.000
-500.000
-550.000
-600.000
-650.000
-700.000
-750.000
-800.000
-850.000
-900.000
-950.000
-1000.000
-1050.000
-1100.000
-1150.000
-1200.000
-1250.000
-1300.000
-1350.000
-1400.000
-1450.000
-1500.000
-1550.000
-1600.000
-1650.000
-1700.000
160 OSCIN2
161 OSCOUT
162 OSCOUT
163 DUMMY
164 TOSCSYNC
165 TOSCSYNC
166 TSISYNC
167 TSISYNC
168 VSS
169 SIGIN1
170 SIGIN1
171 VDD1
172 SIGIN2
173 SIGIN2
174 VSS
175 TESTOUT
176 TESTOUT
177 TSTIFS
178 TSTIFS
179 TSTRTST
180 TSTRTST
181 TSTVIHL
182 TSTVIHL
183 VSS
184 PSEG11
185 PSEG11
186 DUMMY
187 PSEG12
188 PSEG12
189 PSEG13
190 PSEG13
191 DUMMY
192 PSEG14
193 PSEG14
194 PSEG15
195 PSEG15
196 DUMMY
197 PSEG16
198 PSEG16
199 PSEG17
200 PSEG17
201 DUMMY
202 PSEG18
203 PSEG18
204 PSEG19
205 PSEG19
206 DUMMY
207 PSEG20
208 PSEG20
209 DUMMY
210 DUMMY
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-1383.500
-2700.000
-2750.000
-2800.000
-2850.000
-2900.000
-2950.000
-3000.000
-3050.000
-3100.000
-3150.000
-3200.000
-3250.000
-3300.000
-3350.000
-3400.000
-3450.000
-3500.000
-3550.000
-3600.000
-3650.000
-3700.000
-3750.000
-3800.000
-3850.000
-3900.000
-3950.000
-4000.000
-4050.000
-4100.000
-4150.000
-4200.000
-4250.000
-4300.000
-4350.000
-4400.000
-4450.000
-4500.000
-4550.000
-4600.000
-4650.000
-4700.000
-4750.000
-4800.000
-4850.000
-4900.000
-4950.000
-5000.000
-5050.000
-5100.000
-5200.000
-5250.000
105 C86
36 VR
106 /PSX
107 /PSX
108 VDD1
109 IRS
37 VLC4
38 VLC4
39 VLC3
40 VLC3
41 VLC2
42 VLC2
43 VLC1
44 VLC1
45 VLCD
46 VLCD
47 VSS
48 VOUT
49 VOUT
50 VSS
51 C9-
52 C9-
53 C9+
54 C9+
55 C8-
56 C8-
57 C8+
58 C8+
59 C7-
60 C7-
110 IRS
111 VSS
112 /CS1
113 /CS1
114 CS2
115 CS2
116 VDD1
117 /RES
118 /RES
119 RS
120 RS
121 VSS
122 WR (R,/W)
123 WR (R,/W)
124 /RD (E)
125 /RD (E)
126 VDD1
127 RDS
128 RDS
129 VSS
130 P7 (SI)
131 P7 (SI)
132 P6 (SCL)
133 P6 (SCL)
134 DUMMY
135 P5
61 C7+
62 C7+
63 C6-
64 C6-
65 C6+
66 C6+
67 C5-
68 C5-
136 P5
137 P4
138 P4
139 DUMMY
69 C5+
70 C5+
140 P3
7
Data Sheet S15730EJ2V0DS
µPD16498
•ꢀµPD16498 Pad Layout (2/3)
Pad
No.
Pin Name
Pad
Pad Coordinate
Pad
No.
Pin Name
Pad
Pad Coordinate
Pad
No.
Pin Name
Pad
Pad Coordinate
Type
X[µ m]
Y[µ m]
Type
X[µ m]
Y[µ m]
Type
X[µ m]
Y[µ m]
25.000
211 DUMMY
212 DUMMY
213 DUMMY
214 PCOM1
215 PCOM1
216 COM2
217 COM4
218 COM6
219 COM8
220 COM10
221 COM12
222 COM14
223 COM16
B
B
A
A
A
A
A
A
A
A
A
A
A
-1383.500
-1201.000
-1110.000
-1010.000
-960.000
-910.000
-860.000
-810.000
-760.000
-710.000
-660.000
-610.000
-560.000
-5341.000
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
281 COM122
282 COM124
283 COM126
284 COM128
285 DUMMY
286 DUMMY
287 SEG128
288 SEG127
289 SEG126
290 SEG125
291 SEG124
292 SEG123
293 SEG122
A
A
A
A
A
A
A
A
A
A
A
A
A
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
-3475.000
-3425.000
-3375.000
-3325.000
-3275.000
-3225.000
-3175.000
-3125.000
-3075.000
-3025.000
-2975.000
-2925.000
-2875.000
351 SEG64
352 SEG63
353 SEG62
354 SEG61
355 SEG60
356 SEG59
357 SEG58
358 SEG57
359 SEG56
360 SEG55
361 SEG54
362 SEG53
363 SEG52
A
A
A
A
A
A
A
A
A
A
A
A
A
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
75.000
125.000
175.000
225.000
275.000
325.000
375.000
425.000
475.000
525.000
575.000
625.000
224 COM18
225 COM20
A
A
-510.000
-460.000
-5482.760
-5482.760
294 SEG121
295 SEG120
A
A
1282.760
1282.760
-2825.000
-2775.000
364 SEG51
365 SEG50
A
A
1282.760
1282.760
675.000
725.000
226 COM22
227 COM24
228 COM26
229 COM28
A
A
A
A
-410.000
-360.000
-310.000
-260.000
-5482.760
-5482.760
-5482.760
-5482.760
296 SEG119
297 SEG118
298 SEG117
299 SEG116
A
A
A
A
1282.760
1282.760
1282.760
1282.760
-2725.000
-2675.000
-2625.000
-2575.000
366 SEG49
367 SEG48
368 SEG47
369 SEG46
A
A
A
A
1282.760
1282.760
1282.760
1282.760
775.000
825.000
875.000
925.000
230 COM30
231 COM32
232 COM34
233 COM36
234 COM38
235 COM40
236 COM42
237 COM44
238 COM46
239 COM48
240 COM50
241 COM52
242 COM54
243 COM56
244 COM58
245 COM60
246 COM62
247 COM64
248 DUMMY
249 DUMMY
250 DUMMY
251 DUMMY
252 DUMMY
253 COM66
254 COM68
255 COM70
256 COM72
257 COM74
258 COM76
259 COM78
260 COM80
261 COM82
262 COM84
263 COM86
264 COM88
265 COM90
266 COM92
267 COM94
268 COM96
269 COM98
270 COM100
271 COM102
272 COM104
273 COM106
274 COM108
275 COM110
276 COM112
277 COM114
278 COM116
279 COM118
280 COM120
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-210.000
-160.000
-110.000
-60.000
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5482.760
-5226.000
-5096.000
-4875.000
-4825.000
-4775.000
-4725.000
-4675.000
-4625.000
-4575.000
-4525.000
-4475.000
-4425.000
-4375.000
-4325.000
-4275.000
-4225.000
-4175.000
-4125.000
-4075.000
-4025.000
-3975.000
-3925.000
-3875.000
-3825.000
-3775.000
-3725.000
-3675.000
-3625.000
-3575.000
-3525.000
300 SEG115
301 SEG114
302 SEG113
303 SEG112
304 SEG111
305 SEG110
306 SEG109
307 SEG108
308 SEG107
309 SEG106
310 SEG105
311 SEG104
312 SEG103
313 SEG102
314 SEG101
315 SEG100
316 SEG99
317 SEG98
318 SEG97
319 SEG96
320 SEG95
321 SEG94
322 SEG93
323 SEG92
324 SEG91
325 SEG90
326 SEG89
327 SEG88
328 SEG87
329 SEG86
330 SEG85
331 SEG84
332 SEG83
333 SEG82
334 SEG81
335 SEG80
336 SEG79
337 SEG78
338 SEG77
339 SEG76
340 SEG75
341 SEG74
342 SEG73
343 SEG72
344 SEG71
345 SEG70
346 SEG69
347 SEG68
348 SEG67
349 SEG66
350 SEG65
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
-2525.000
-2475.000
-2425.000
-2375.000
-2325.000
-2275.000
-2225.000
-2175.000
-2125.000
-2075.000
-2025.000
-1975.000
-1925.000
-1875.000
-1825.000
-1775.000
-1725.000
-1675.000
-1625.000
-1575.000
-1525.000
-1475.000
-1425.000
-1375.000
-1325.000
-1275.000
-1225.000
-1175.000
-1125.000
-1075.000
-1025.000
-975.000
-925.000
-875.000
-825.000
-775.000
-725.000
-675.000
-625.000
-575.000
-525.000
-475.000
-425.000
-375.000
-325.000
-275.000
-225.000
-175.000
-125.000
-75.000
370 SEG45
371 SEG44
372 SEG43
373 SEG42
374 SEG41
375 SEG40
376 SEG39
377 SEG38
378 SEG37
379 SEG36
380 SEG35
381 SEG34
382 SEG33
383 SEG32
384 SEG31
385 SEG30
386 SEG29
387 SEG28
388 SEG27
389 SEG26
390 SEG25
391 SEG24
392 SEG23
393 SEG22
394 SEG21
395 SEG20
396 SEG19
397 SEG18
398 SEG17
399 SEG16
400 SEG15
401 SEG14
402 SEG13
403 SEG12
404 SEG11
405 SEG10
406 SEG9
407 SEG8
408 SEG7
409 SEG6
410 SEG5
411 SEG4
412 SEG3
413 SEG2
414 SEG1
415 DUMMY
416 DUMMY
417 COM127
418 COM125
419 COM123
420 COM121
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
975.000
1025.000
1075.000
1125.000
1175.000
1225.000
1275.000
1325.000
1375.000
1425.000
1475.000
1525.000
1575.000
1625.000
1675.000
1725.000
1775.000
1825.000
1875.000
1925.000
1975.000
2025.000
2075.000
2125.000
2175.000
2225.000
2275.000
2325.000
2375.000
2425.000
2475.000
2525.000
2575.000
2625.000
2675.000
2725.000
2775.000
2825.000
2875.000
2925.000
2975.000
3025.000
3075.000
3125.000
3175.000
3225.000
3275.000
3325.000
3375.000
3425.000
3475.000
-10.000
40.000
90.000
140.000
190.000
240.000
290.000
340.000
390.000
440.000
490.000
540.000
590.000
640.000
781.000
911.000
1041.000
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
-25.000
8
Data Sheet S15730EJ2V0DS
µPD16498
•ꢀµPD16498 Pad Layout (3/3)
Pad
No.
Pin Name
Pad
Pad Coordinate
Type
X[µ m]
Y[µ m]
421 COM119
422 COM117
423 COM115
424 COM113
425 COM111
426 COM109
427 COM107
428 COM105
429 COM103
430 COM101
431 COM99
432 COM97
433 COM95
A
A
A
A
A
A
A
A
A
A
A
A
A
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
3525.000
3575.000
3625.000
3675.000
3725.000
3775.000
3825.000
3875.000
3925.000
3975.000
4025.000
4075.000
4125.000
Pad type A:
Pad size (Al) : 43 x 73 µm2 TYP.
Bump size : 37 x 65 µm2 TYP.
Bump height : 17 µm TYP.
Pad type B:
Pad size (Al) : 118 x 73 µm2 TYP.
Bump size : 110 x 65 µm2 TYP.
Bump height : 17 µm TYP.
Alingment Mark
434 COM93
435 COM91
A
A
1282.760
1282.760
4175.000
4225.000
Mark Center Coordinate
X [µ m]
Y [µ m]
5193.00
436 COM89
437 COM87
438 COM85
439 COM83
A
A
A
A
1282.760
1282.760
1282.760
1282.760
4275.000
4325.000
4375.000
4425.000
A1
A2
A3
A4
-1103.92
-1130.20
1274.78
1274.78
-5217.10
-5474.78
5474.78
440 COM81
441 COM79
442 COM77
443 COM75
444 COM73
445 COM71
446 COM69
447 COM67
448 COM65
449 DUMMY
450 DUMMY
451 DUMMY
452 DUMMY
453 DUMMY
454 COM63
455 COM61
456 COM59
457 COM57
458 COM55
459 COM53
460 COM51
461 COM49
462 COM47
463 COM45
464 COM43
465 COM41
466 COM39
467 COM37
468 COM35
469 COM33
470 COM31
471 COM29
472 COM27
473 COM25
474 COM23
475 COM21
476 COM19
477 COM17
478 COM15
479 COM13
480 COM11
481 COM9
482 COM7
483 COM5
484 COM3
485 COM1
486 PCOM2
487 PCOM2
488 DUMMY
489 DUMMY
A
A
A
A
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1282.760
1041.000
911.000
781.000
665.000
615.000
565.000
515.000
465.000
415.000
365.000
315.000
265.000
215.000
165.000
115.000
65.000
4475.000
4525.000
4575.000
4625.000
4675.000
4725.000
4775.000
4825.000
4875.000
5081.000
5211.000
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
5482.760
Alingment Mark Form Coordinate (Unit : µ m)
40
100
15.000
-35.000
-85.000
-135.000
-185.000
-235.000
-285.000
-335.000
-385.000
-435.000
-485.000
-535.000
-585.000
-635.000
-685.000
-735.000
-785.000
-835.000
-885.000
-935.000
-985.000
-1085.000
-1176.000
9
Data Sheet S15730EJ2V0DS
µPD16498
3. PIN FUNCTIONS
3.1 Power Supply System Pins
Symbol
Name
Pad No.
I/O
Description
Power supply pin for logic circuit
VDD1
VDD2
VSS
Logic power supply 92 to 94, 100, 108,
−
pin
116, 126, 171
89 to 91,
Boost circuit
power supply pin
Logic and driver
ground pin
−
−
Power supply pin for booster
28, 47, 50, 95 to 97,
103, 111, 121, 129,
168, 174, 183,
48, 49
Ground pin for logic and driver circuits
VOUT
Driver power
supply pin
−
Power supply pin for driver. Output pin for on-chip booster.
Connect a 1 µF boost capacitor between this pin and the GND
pin.
If not using the on-chip booster, a direct driver power supply can
be input.
VLCD,
Reference power
46, 45,
−
−
These are reference power supply pins for the LCD driver.
Connect a capacitor between these pins and the GND pin if an
internal bias has been selected.
VLC1 to VLC4 supply pins for
driver
44 to 37
C1+, C1−
C2+, C2−
C3+, C3−
C4+, C4−
C5+, C5−
C6+, C6−
C7+, C7−
C8+, C8−
C9+, C9−
C1A
Boost capacitor
86, 85, 84, 83,
82, 81, 80, 79,
78, 77, 76, 75,
74, 73, 72, 71,
70, 69, 68, 67,
66, 65, 64, 63,
62, 61, 60, 59,
58, 57, 56, 55,
54, 53, 52, 51,
87, 88
These are capacitor connection pins for the booster. When using
the on-chip booster, connect a 1 µF capacitor between positive
(+) and negative (-) pins.
connection pins (1)
Boost capacitor
−
This is a capacitor connection pin for boost adjustment. When
using the on-chip booster, connect a 1 µF capacitor between this
pin and the GND pin.
connection pin (2)
10
Data Sheet S15730EJ2V0DS
µPD16498
3.2
Logic System Pins
(1/2)
Symbol
Name
Pad No.
106, 107
I/O
Description
PSX
Data transfer
selection
Input This pin is used to select between parallel data input and serial
data input.
PSX = H: Parallel data input
PSX = L: Serial data input
/CS1,
CS2
Chip select
Input These pins are used for chip select signals. When /CS1 = L (CS2
= H), the chip is active and can perform data input/output
operations including command and data I/O.
Input When i80 series parallel data transfer (/RD) has been selected,
the signal at this pin is used to enable read operations. Data is
output to the data bus only when this pin is L.
When M68 series parallel data transfer (E) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the falling edge of this signal.
112, 113,
114, 115
/RD
(E)
Read
124, 125
(enable)
/WR
Write
Input When i80 series parallel data transfer (/WR) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the rising edge of this signal.
122, 123
(R,/W)
(read/write)
When 68 series parallel data transfer (R,/W) has been selected,
this pin is used to determine the direction of data transfer.
L: Write
H: Read
C86
Interface selection
Data pin selection
Input This pin is used to switch between interface modes (i80 series
CPU or M68 series CPU).
104, 105
127,128
L: Selects i80 series CPU mode
H: Selects M68 series CPU mode
Input
RDS
This pin determines the direction of a data as follows. Fixed to
low level at the time serial data input (PSX = L).
RDS
Low
High
P7
D7
D0
P6
D6
D1
P5
D5
D2
P4
D4
D3
P3
D3
D4
P2
D2
D5
P1
D1
D6
P0
D0
D7
P0 to P5,
Data bus
I/O
These pins comprise an 8-bit bidirectional data bus that connects
to an 8-bit or 16-bit standard CPU bus.
148 to 145, 143 to 140,
138 to 135,
P6 (SCL)
P7 (SI)
(serial clock)
(serial input)
When the serial interface has been selected (PSX = L), P6
functions as a serial clock input pin (SCL) and P7 functions as a
serial data input pin (SI). In either case, pins P0 to P5 are in high
impedance mode.
133, 132,
131, 130
When the chip is not selected, P0 to P7 are in high impedance
mode.
RS
Index
Input Usually, this pin is connected to the LSB of the standard CPU
address bus and is used to distinguish between data from index
registers and data/commands.
119, 120
register/data,
command
selection
RS = H: Indicates that data from D0 to D7 is data/command
RS = L : Indicates that data from D0 to D7 is index register
contents
/RES
Reset
117, 118
Input When /RES is low, an internal reset is performed. The reset
operation is executed at the /RES signal level.
11
Data Sheet S15730EJ2V0DS
µPD16498
(2/2)
Symbol
CLS
Name
Pad No.
98, 99
I/O
Description
Select clock
division
Input This pin is used to select whether or not to use the divider within
the display clock oscillator.
CLS = H: Use divider
CLS = L: Do not use divider
When using an external clock, the CLS = L setting is input via the
OSCIN1 and OSCIN2 pins as normal and partial clocks
respectively.
When CLS = H, clock input is via the OSCIN1 pin only.
IRS
VLCD regulation
Input
This pin is used to select the resistor that is used for VLCD voltage
regulation.
109, 110
IRS = H: Uses internal resistor
IRS = L: Does not use internal resistor. The VLCD voltage level is
regulated using the external voltage division resistor that is
connected to the VR pin.
This pin is valid only in master operation mode. In slave
operation mode, this pin is fixed high or low level.
SIGIN1,
SIGIN2
Signature setting
pins
Input These pins can be used to set a unique signature for the IC. The
signal set via these pins can subsequently be read from the
signature read register (R45).
169, 170,
172, 173
OSCIN1
OSCIN2
OSCOUT
Oscillation signal
pins
Input A resistor can be inserted between OSCIN1- OSCOUT, and OSCIN2-
OSCOUT. When using an external oscillator, a clock signal is input
157, 158
159, 160
161, 162
via the OSCIN pins according to the CLS pin's status and the
OSCOUT pin is left unconnected.
Input
The wiring between OSCIN1-OSCOUT and OSCIN2-OSCOUT must
be as short as possible, and use after proper evaluation.
Output
12
Data Sheet S15730EJ2V0DS
µPD16498
3.3
Driver-Related Pins
Symbol
Name
Segment
Pad No.
I/O
Description
SEG1 to
SEG128
414 to 287
Output Segment output pins
COM1 to
COM128
PSEG1 to
PSEG20
Common
216 to 247, 253 to 284, Output Common output pins
417 to 448, 454 to 485
Static segment
3, 4, 6 to 9, 11 to 14, Output Segment output pins for static icon
16 to 19, 21 to 24, 26,
27, 184, 185,
187 to 190, 192 to 195,
197 to 200, 202 to 205,
207, 208
PCOM1,
PCOM2
VRS
Static common
214, 215,
486, 487
29, 30
Output Common output pins for static icon
(Same driver waveform is output from two pins.)
Op amp input pin
for regulating the
driving voltage of
the LCD
Input
VRS is an op amp input pin for regulating the driving voltage of the
LCD. This is a reference voltage input for the LCD voltage
regulation amplifier.
When using the internal drive circuit (i.e., when OP1 = 1), we
recommend inserting a 0.1 to 1 µF capacitor between this pin and
GND.
VR
Input pin for the op
amp's feedback
connection
35, 36
Input
VR is an input for the op amp's feedback connection. Insert this
pin between GND and AMPOUT when using the feedback resistor
for this input.
This pin is valid only when not using an internal resistor for VLCD
voltage regulation (i.e., when IRS = L). This pin cannot be used
when using the internal resistor for VLCD voltage regulation (i.e.,
when IRS = H).
AMPOUT
AMPOUTP
DUMMY
Op amp output
33, 34
31, 32
Output These are op amp output pins for regulating the driving voltage of
the LCD. When not using an internal resistor for VLCD voltage
regulation (i.e., when IRS = L), these outputs are connected to the
LCD drive voltage regulation resistor (see 5.6.2 Voltage regulator).
We recommend inserting a 0.01 to 0.1 µF capacitor between
these pins in order to stabilize the internal op amp's output.
Dummy pin
1, 2, 5, 10, 15, 20, 25,
134, 139, 144, 149,
154, 163, 186, 191,
196, 201, 206,
−
Dummy pin.
These pins are not connected inside IC. Usually, leave these pins
open.
209 to 213, 248 to 252,
415, 416, 449 to 453,
488, 489
13
Data Sheet S15730EJ2V0DS
µPD16498
3.4
Test Pins
Symbol
Name
Pad No.
152, 153
150, 151
155, 156
166, 167
164, 165
175, 176
101, 102
I/O
Description
TFR
Test output
Output These pins are used when the IC is in test mode.
Usually, leave them open.
TFRSYNC
TDOF
TSISYNC
TOSCSYNC
TESTOUT
TM/S
Test input
Test input
Input
Input
These pins are used to set a test mode for the IC.
Normally, connect these pins to VDD1.
TSTIFS
177, 178
179, 180
181, 182
These pins are used to set a test mode for the IC.
Normally, connect these pins to VSS.
TSTRTST
TSTVIHL
14
Data Sheet S15730EJ2V0DS
µPD16498
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit type of each pin and recommended connection of unused pins are described below.
Pin Name
PSX
Input Type
Schmitt trigger
Filter
Input/output
Input
Recommended Connection of Unused Pins
Mode setting pin.
Notes
Note 1
/CS1
CS2
Input
Connect to VSS.
−
−
−
Filter
Input
Connect to VDD1.
/RD(E)
Filter
Input
Connect to VDD1 (i80 series interface), connect to VDD1
or VSS (serial interface).
Connect to VDD1 or VSS (serial interface).
Mode setting pin.
/WR(R,/W)
C86
Filter
Input
Input
−
Schmitt trigger
Schmitt trigger
Filter
Note 1
RDS
Input
Mode setting pin.
Note 1
P0 to P5
P6(SCL)
P7(SI)
Input/output
Input/output
Input/output
Input
Leave open
−
Filter
−
−
Filter
−
−
RS
Filter
Register setting pin.
Connect to VDD1.
Note 2
/RES
Schmitt trigger
Schmitt trigger
Schmitt trigger
Schmitt trigger
Schmitt trigger
Schmitt trigger
Schmitt trigger
−
Input
−
CLS
Input
Mode setting pin
Note 1
IRS
Input
Mode setting pin.
Note 1
SIGIN1
SIGIN2
OSCIN1
OSCIN2
OSCOUT
TFR
Input
Connect to VDD1 or VSS.
Connect to VDD1 or VSS.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Input
Input
Input
Connect to VDD1 or VSS (CLS = H)
Leave open (when using external clock)
Leave open
Output
Output
Output
Output
Output
Input
CMOS
TFRSYNC
TDOF
CMOS
Leave open
CMOS
Leave open
TSISYNC
TM/S
CMOS
Leave open
Schmitt trigger
−
Connect to VDD1
TOSCSYNC
TSTIFS
TSTRTST
TSTVIHL
TESTOUT
Output
Input
Leave open
Schmitt trigger
Schmitt trigger
Schmitt trigger
－
Connect to VSS (during normal use)
Connect to VSS (during normal use)
Connect to VSS (during normal use)
Leave open
Input
Input
Output
Notes 1. Connect to either VDD1 or VSS, depending on the mode setting.
2. Input either VDD1 or VSS output from CPU, depending on the mode setting.
15
Data Sheet S15730EJ2V0DS
µPD16498
5. DESCRIPTION OF FUNCTIONS
5.1
CPU Interface
5.1.1 Selection of interface type
The µPD16498 chip transfers data using an 8-bit bidirectional data bus (P7 to P0) or a serial data input (SI). Setting the
polarity of the PSX pin as either H (high) or L (low) selects between 8-bit parallel or serial data input, as shown in the
following table.
PSX
CS
CS
RS
RS
/RD
/RD
/WR
/WR
C86
C86
RDS
L
P7
D7
D7
SI
P6
D6
P5
D5
D5
P4
D4
D4
P3
D3
D3
P2
D2
D2
P1
D1
D1
P0
D0
D0
H: Parallel input
H
LNote2
D6
Note1
Note1
Note1
Hi-ZNote3
L: Serial input
CS
RS
SCL
Notes 1. Fixed as either High or Low.
2. Fix the RDS pin to Low level when the serial interface has been selected (PSX = L).
3. Hi-Z: High impedance
5.1.2 Parallel interface
When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct connection
to an i80 series or M68 series CPU (see table below).
C86
/CS1
/CS1
/CS1
CS2
CS2
CS2
RS
RS
RS
/RD
E
/WR
R,/W
/WR
P7 to P0
D7 to D0
D7 to D0
H: M68 series CPU
L: i80 series CPU
/RD
The data bus signal is identified according to the combination of the RS, /RD(E), and /WR(R,/W) signals, as shown in the
following table.
Common
M68
i80
Function
RS
1
R,/W
/RD
0
/WR
1
0
1
0
1
0
1
0
Reads display data and registers
Writes display data and registers
Prohibited
1
1
0
0
0
1
Writes to index register
16
Data Sheet S15730EJ2V0DS
µPD16498
(1) i80 series parallel interface
When i80 series parallel data transfer has been selected, data is written to the µPD16498 at the rising edge of the /WR
signal. The data is output to the data bus when the /RD signal is L.
Figure 5-1. i80 Series Interface Data Bus Status
/CS1
(CS2=H)
/WR
/RD
Hi-Z
Hi-Z
DBn
Valid data
Data Read
Data write
(2) M68 series parallel interface
When M68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the R,/W
signal is L. During the data read operation, the data bus enters the output status when the R,/W signal is H, outputs valid
data at the rising edge of the E signal, and enters the high-impedance state at the falling edge of the R,/W signal (R,/W = L)
Figure 5-2. M68 Series Interface Data Bus Status
/CS1
(CS2=H)
R,/W
E
Hi-Z
Hi-Z
DBn
Invalid data
Valid data
17
Data Sheet S15730EJ2V0DS
µPD16498
5.1.3 Serial interface
When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI) and
serial clock input (SCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial
clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to
parallel data for processing. RS input is used to judge serial input data as display data or command data: when RS = H the
data is display/command data and when RS = L the data is index data. When the chip enters active mode, RS input is read
at the rising edge after every eighth serial clock and is then used to judge the serial input data. The serial interface signal
chart is shown below.
Figure 5-3. Serial Interface Signal Chart
CS2="H"
/CS1
SI
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
SCL
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
RS
Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings.
2. The data read function is disabled during serial interface mode.
3. When using SCL wiring, take care concerning the possible effects of terminating reflection and
noise from external sources. We recommend checking operation with the actual device.
5.1.4 Chip select
The µPD16498 has two chip select pins (/CS1 and CS2). The CPU parallel interface or serial interface can be used only
when /CS1 = L and CS2 = H. When chip select is inactive, P0 to P7 are set to high impedance (invalid) and input of RS, /RD,
or /WR is not active. If serial interface mode has been set, the shift register and counter are both reset.
5.1.5 Display data RAM and on-chip register access
Because only the required cycle time (tcyc) is satisfied when accessing the µPD16498 from the CPU, high-speed data
transfer is possible. There is no need to consider any wait time. No dummy data is needed when writing data. Even when
data is read, there is no need for dummy data except in the display memory access register (R11).
In other words, dummy data is required only when reading data from the display memory access register (R11).
Figure 5-4 illustrates this relationship.
18
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-4. Write and Read (1/2)
Write
<CPU>
/WR
DATA
N
N + 1
N + 2
N + 3
<Internal timing>
Latch
BUS
holder
N
N + 1
N + 2
N + 3
Write
signal
Read (display memory access register (R11))
<CPU>
/WR
/RD
N
N
n
n + 1
DATA
<Internal timing>
Address
preset
Read
signal
Column
address
N + 2
Preset N
Increment N + 1
BUS
holder
N
n
n + 1
n + 2
Address set
#n
Dummy read
Data read
#n
Data read
#n + 1
19
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-4. Write and Read (2/2)
Read (other than display memory access register)
<CPU>
/WR
/RD
IRn + 1
Data
IRn
IRn data
IRn+1
DATA
IR address
set #n
IRn register
data read
IR address
set #n + 1
IRn + 1 register
data read
20
Data Sheet S15730EJ2V0DS
µPD16498
5.2
Display Data RAM
5.2.1 Display data RAM
This is the RAM that is used to store the display's dot data. The RAM configuration is 256 bits (32 x 8 bits) x 128 bits. Any
specified bit can be accessed by selecting the corresponding X address and Y address. The display data D0 to D7 sent
from the CPU correspond to SEGx on the LCD display (see Figure 5-5).
The CPU writes data to and reads data from the display RAM via the I/O buffer, and these read/write operations are
independent of the signal read operations for the LCD driver. Accordingly, there are no adverse effects (such as flicker) in
the LCD display when display data RAM is accessed asynchronously.
Figure 5-5. Display Data RAM
MSB
D7
LSB
D0
D6
D5
D4
D3
D2 D1
Pixel 1
Pixel 2
Pixel 3
Pixel 4
LCD panel
Pixel 1
Pixel 1
Pixel 2
Pixel 2
Pixel 3
Pixel 3
Pixel 4
Pixel 4
Pixel 1
Pixel 1
Pixel 2
Pixel 2
Pixel 3
Pixel 3
Pixel 4
Pixel 4
X address 00H
X address 01H
D7 D6 D5 D4
SEG1 SEG2
COM0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
COM1
COM2
COM3
COM4
Display data
LCD display
5.2.2 X address circuit
As shown in Figure 5-6, the display data RAM's X address is specified via the X address register (R3). When using X
address increment mode (INC = 0: control register 2 (R1)), the specified X address is incremented (by 1) each time a
display data read or write operation is executed. The CPU is able to continuously access the display data. The X address is
incremented to 1FH, after which the Y address is incremented after each read or write operation and the X address is set
back to 00H.
For monochrome (black-and-white) display, the X address is incremented to 0FH, after which the Y address is
incremented after each read or write operation and the X address is set back to 00H.
21
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-6. Configuration of X Address Register
D4
D3
D2
D1
0
0
0
1
1
1
1
1
0
0
0
0
0
COM
output
D0
0
1
Y
address
00H
01H
1FH
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
COM1
Data
00H
01H
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
Start
COM119
COM120
COM121
COM122
COM123
COM124
COM125
COM126
COM127
COM128
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
22
Data Sheet S15730EJ2V0DS
µPD16498
5.2.3 Column address circuit
When displaying the contents of the display data RAM, the column address corresponds to the SEG output, as shown in
Figure 5-6. Similarly, the static icon address corresponds to the PSEG output.
As is shown in Tables 5-1 and 5-2, the correspondence between the display RAM's column address and segment output
can be inverted using the ADC flag in control register 1 (R0) (segment driver direction selection flag). This reduces the
constraints on chip layout when assembling the LCD module.
Table 5-1. Relationship between Column Address and SEG Output
SEG Output
SEG1
00H
SEG128
7FH
0
1
→
←
Column address
Column address
→
←
ADC
(D1)
7FH
00H
Table 5-2. Relationship between Column Address for Static Icon and PSEG Output
PSEG Output
PSEG1
00H
PSEG20
04H
0
1
→
←
Column address
Column address
→
←
ADC
(D1)
04H
00H
5.2.4 Y address circuit
As is shown in Figure 5-4, the Y address register (R4) is used to specify the display data RAM's Y address. When using
Y address increment mode (INC = 1: control register 2 (R1)), the specified Y address is incremented (by 1) each time a
display data read or write operation is executed. The CPU is able to continuously access the display data. The Y address
is incremented to 7FH, after which the X address is incremented after each read or write operation and the Y address is set
back to 00H.
5.2.5 Common scan circuit
The common scan circuit sets the scan lines for common signals. The scan direction is set using the COMR flag in control
register 1 (R0), as shown in Table 5-3.
For example, when using 1/80 duty, when COMR = 0 the scan direction is COM1 → COM80 and when COMR = 1,
the scan direction is COM80 → COM1 using the COM80 to COM1 pins.
Table 5-3. Relationship between Common Scan Circuit and Scan Direction
COMR
(D0)
0
1
COM1
→
→
COM128
COM1
COM128
5.2.6 Display start line set
As is shown in Figure 5-6, display start line set specifies the Y address that corresponds to the COM1 output for displaying
the contents of display data RAM. The display start line setting register (R12) is used to specify the top line in the display.
The screen can be scrolled, overwritten, etc. A 7-bit display start address is set to the display start line setting register.
5.2.7 Display data latch circuit
The display data latch circuit is used for temporary storage of data that is output to the LCD driver from the display data RAM.
The display scan command that sets normal or reverse display mode and the display ON/OFF command control latched
data so that there is no effect on the data in the display data RAM.
23
Data Sheet S15730EJ2V0DS
µPD16498
5.3
Blink/Reverse Display Circuit
The µPD16498 enables blinking display and reverse display in designated parts of the full dot display. A blinking display
is achieved by cycling ON/OFF (level 0 when four-level gray scale mode has been selected) at approximately 1 Hz and
reverse display is achieved by inverting the display level value.
The area designated for blinking is specified via the blink start/end line address registers (R14 and R15), the blink X
address register (R13), and the blink data memory access register (R16).
First, the blinking display's start and end line addresses are selected via the blink start/end line address registers. Next,
the blink X address register (R13) and the blink data memory (R16) are used to select the column for the blinking display.
The inversion start/end line address registers (R18 and R19), the inverted X address register (R17), and the inverted data
memory access register (R20) are used to select the reverse display area.
First, the inversion start/end line address registers (R18 and R19) are set to select the line addresses where the reverse
display will start and end. Next, the inverted X address register (R17) and the inverted data memory access register (R20)
are used to select the column for the reverse display. The specified blink/inverted X address is incremented (by 1) with
each input of blink/reverse display data.
The blink RAM and inversion RAM, which have a 128 bit (16 x 8 bit) configuration, are used to store data for blinking
display and reverse display respectively. To access the desired bit, simply specify the corresponding X address. The
blink/reverse data (data bits D0 to D7 sent from the CPU) correspond to SEGx on the LCD display, as shown in Figure 5-7.
After the area and data settings are complete, the BLD bit and IVD bit in the control register 1 (R0) are set to H, at which
point the blinking and/or reverse display of data begins. Figure 5-8 illustrates the relationship between the start line address,
end line address, blink/reverse data, and LCD display.
Table 5-4. Inversion Manipulation and Display
Original Level
After Inversion
Four-level gray scale display mode
0, 0
0, 1
1, 0
1, 1
1, 1
1, 0
0, 1
0, 0
B/W display mode
1
0
0
1
Figure 5-7. Correspondence between Blink/Reverse Data and Segments
D3
D2
D1
D0
0
0
0
0
0
0
1
1
1
0
1
1
00H
01H
0FH
Data
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
24
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-8. Setting Image of Blink/Reverse Display Area
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Blink/revese
data
0 0 1 1 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0
Start line
End line
Blinking or reverse display pixels.
Example of sequence for setting blink/reverse display
Start
Blink/inversion start line
address register
Blink/inversion end line
address register
Blink/inverted
X address register
Blink/inverted
data memory access register
Data
No
Write completed ?
Yes
Control register 1
(BLD, IVD = H)
End
25
Data Sheet S15730EJ2V0DS
µPD16498
5.4
Oscillator
The µPD16498 include a CR-type oscillator (R external) for normal and partial display, which generates the display
clocks.
The clocks from this oscillator are controlled via the CLS pin and the DTY flag in the control register 2 (R1). The clock
configuration for the display can be set to suit the target system.
The functions of this circuit are described below.
•The oscillator for normal and partial display is enabled only when resistors RN and RP have been connected.
The DTY flag in the control register 2 (R1) and the CLS pin status are used to switch between the oscillation
clocks for normal display and partial display modes.
•The divider divides the external clock that has been input for the normal oscillator and the normal display into a
clock for partial display. The external clock that is input for the partial oscillator and partial display is also
divided for the partial display.
•The division level is automatically set for the divider based on the relationship between the ON/OFF status of
the divider setting pin (CLS pin) and the duty of the specified partial display, as shown in Table 5-5.
Figure 5-9. Oscillator Block
Selected via DTY/CLS
OSCIN1
OSCIN2
Normal display/
Signal to select division level
for partial display
partial display
oscillator
OSCOUT
MUX
To graphic driver
TOSCSYNC
Partial display
divider
Normal/partial signal
CLS
Signal to select division level
for static icon display
Static icon
display divider
To static icon driver
The relationship between the frame frequency (fFRAME), oscillation frequency (fOSCIN1), and setting duty (in normal display
mode) is described below.
fFRAME = fOSCIN1 ÷ 8 ÷ N (in four-level gray scale display mode)
fFRAME = fOSCIN1 ÷ 4 ÷ N (in B/W display mode)
N = 1/N duty (setting duty)
26
Data Sheet S15730EJ2V0DS
µPD16498
Table 5-5. Setting of Division Level for Partial Display and Static Icon Display (1/2)
In four-level gray scale display mode (GRAY = L, control register 2 (R1))
Division
Normal
Display
Duty Ratio
Partial
Display
Duty Ratio
Divider
ON/OFF
CLS
Partial Static Icon
Division Division
Display
Mode
Source
OSCIN1
/OSCIN2
Normal/Partial
Select DTY
Comments
Ratio
Ratio
1/38
1/25
1/12
1/38
1/25
1/12
L(OFF)
H(ON)
Static icon frame frequency: fOSCIN1 /12(division ratio) /32
OSCIN1
L (Normal)
−
1/12
Partial frame frequency:
fOSCIN2 /8 /38
Partial frame frequency:
fOSCIN2 /8 /25
Partial frame frequency:
fOSCIN2 /2(division ratio) /8 /12
Partial frame frequency:
fOSCIN1 /2(division ratio) /8 /38
Partial frame frequency:
fOSCIN1 /2(division ratio) /8 /25
Partial frame frequency:
fOSCIN1 /4(division ratio) /8 /12
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN1 /12(division ratio) /32
Static icon frame frequency:
fOSCIN1 /12(division ratio) /32
Static icon frame frequency:
fOSCIN1 /12(division ratio) /32
1/38
1/25
1/12
1/38
1/25
1/12
1/1
1/1
1/2
1/2
1/2
1/4
1/1 to 1/80
OSCIN2
L(OFF)
H(ON)
1/4
H (Partial)
OSCIN1
1/12
1/38
1/25
1/12
1/38
1/25
1/12
L(OFF)
H(ON)
OSCIN1
L (Normal)
−
1/16
Static icon frame frequency: fOSCIN1 /16(division ratio) /32
Partial frame frequency:
fOSCIN2 /8 /38
Partial frame frequency:
fOSCIN2 /8 /25
Partial frame frequency:
fOSCIN2 /2(division ratio) /8 /12
Partial frame frequency:
fOSCIN1 /2(division ratio) /8 /38
Partial frame frequency:
fOSCIN1 /4(division ratio) /8 /25
Partial frame frequency:
fOSCIN1 /8(division ratio) /8 /12
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN1 /16(division ratio) /32
Static icon frame frequency:
fOSCIN1 /16(division ratio) /32
Static icon frame frequency:
fOSCIN1 /16(division ratio) /32
1/38
1/25
1/12
1/38
1/25
1/1
1/1
1/2
1/2
1/4
1/8
1/81 to 1/96
OSCIN2
L(OFF)
H(ON)
1/4
H (Partial)
OSCIN1
1/16
Four-level
gray scale
GRAY = L
1/12
1/38
1/25
1/12
1/38
1/25
1/12
L(OFF)
H(ON)
OSCIN1
L (Normal)
−
1/16
Static icon frame frequency: fOSCIN1 /16(division ratio) /32
1/97 to 1/112
Partial frame frequency:
fOSCIN2 /8 /38
Partial frame frequency:
fOSCIN2 /8 /25
Partial frame frequency:
fOSCIN2 /2(division ratio) /8 /12
Partial frame frequency:
fOSCIN1 /2(division ratio) /8 /38
Partial frame frequency:
fOSCIN1 /4(division ratio) /8 /25
Partial frame frequency:
fOSCIN1 /8(division ratio) /8 /12
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN1 /16(division ratio) /32
Static icon frame frequency:
fOSCIN1 /16(division ratio) /32
Static icon frame frequency:
fOSCIN1 /16(division ratio) /32
1/38
1/25
1/12
1/38
1/25
1/12
1/1
1/1
1/2
1/2
1/4
1/8
OSCIN2
L(OFF)
H(ON)
1/4
H (Partial)
L (Normal)
H (Partial)
1/16
OSCIN1
1/38
1/25
1/12
1/38
1/25
1/12
L(OFF)
H(ON)
OSCIN1
−
1/20
Static icon frame frequency: fOSCIN1 /20(division ratio) /32
1/113 to 1/128
Partial frame frequency:
fOSCIN2 /8 /38
Partial frame frequency:
fOSCIN2 /8 /25
Partial frame frequency:
fOSCIN2 /2(division ratio) /8 /12
Partial frame frequency:
fOSCIN1 /2(division ratio) /8 /38
Partial frame frequency:
fOSCIN1 /4(division ratio) /8 /25
Partial frame frequency:
fOSCIN1 /8(division ratio) /8 /12
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN2 /4(division ratio) /32
Static icon frame frequency:
fOSCIN1 /20(division ratio) /32
Static icon frame frequency:
fOSCIN1 /20(division ratio) /32
Static icon frame frequency:
fOSCIN1 /20(division ratio) /32
1/38
1/25
1/12
1/38
1/25
1/12
1/1
1/1
1/2
1/2
1/4
1/8
OSCIN2
L(OFF)
H(ON)
1/4
OSCIN1
1/20
27
Data Sheet S15730EJ2V0DS
µPD16498
Table 5-5. Setting of Division Level for Partial Display and Static Icon Display (2/2)
In black/white display mode (GRAY = H, control register 2 (R1))
Division
Normal
Display
Duty Ratio
Partial
Display
Duty Ratio
Divider
ON/OFF
CLS
Partial Static Icon
Division Division
Display
Mode
Normal/Partial
Select DTY
Source
OSCIN1
/OSCIN2
Comments
Ratio
Ratio
1/38
1/25
1/12
L(OFF)
H(ON)
OSCIN1
L (Normal)
−
1/6
Static icon frame frequency: fOSCIN1 /6(division ratio) /32
1/38
1/25
1/12
Partial frame frequency:
fOSCIN2 /4 /38
Partial frame frequency:
fOSCIN2 /4 /25
Partial frame frequency:
fOSCIN2 /2(division ratio) /4 /12
Partial frame frequency:
fOSCIN1 /2(division ratio) /4 /38
Partial frame frequency:
fOSCIN1 /2(division ratio) /4 /25
Partial frame frequency:
fOSCIN1 /4(division ratio) /4 /12
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN1 /6(division ratio) /32
Static icon frame frequency:
fOSCIN1 /6(division ratio) /32
Static icon frame frequency:
fOSCIN1 /6(division ratio) /32
1/38
1/25
1/12
1/38
1/25
1/12
1/1
1/1
1/2
1/2
1/2
1/4
1/1 to 1/80
OSCIN2
L(OFF)
H(ON)
1/2
1/6
H (Partial)
OSCIN1
1/38
1/25
1/12
1/38
1/25
1/12
L(OFF)
H(ON)
OSCIN1
L (Normal)
H (Partial)
L (Normal)
H (Partial)
L (Normal)
H (Partial)
−
1/8
Static icon frame frequency: fOSCIN1 /8(division ratio) /32
Partial frame frequency:
fOSCIN2 /4 /38
Partial frame frequency:
fOSCIN2 /4 /25
Partial frame frequency:
fOSCIN2 /2(division ratio) /4 /12
Partial frame frequency:
fOSCIN1 /2(division ratio) /4 /38
Partial frame frequency:
fOSCIN1 /4(division ratio) /4 /25
Partial frame frequency:
fOSCIN1 /8(division ratio) /4 /12
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN1 /8(division ratio) /32
Static icon frame frequency:
fOSCIN1 /8(division ratio) /32
Static icon frame frequency:
fOSCIN1 /8(division ratio) /32
1/38
1/1
1/1
1/2
1/2
1/4
1/8
1/81 to 1/96
OSCIN2
L(OFF)
H(ON)
1/2
1/8
1/25
1/12
1/38
1/25
1/12
OSCIN1
B/W
GRAY = H
1/38
1/25
1/12
1/38
1/25
1/12
L(OFF)
H(ON)
OSCIN1
−
1/8
Static icon frame frequency: fOSCIN1 /8(division ratio) /32
Partial frame frequency:
fOSCIN2 /4 /38
Partial frame frequency:
fOSCIN2 /4 /25
Partial frame frequency:
fOSCIN2 /2(division ratio) /4 /12
Partial frame frequency:
fOSCIN1 /2(division ratio) /4 /38
Partial frame frequency:
fOSCIN1 /4(division ratio) /4 /25
Partial frame frequency:
fOSCIN1 /8(division ratio) /4 /12
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN1 /8(division ratio) /32
Static icon frame frequency:
fOSCIN1 /8(division ratio) /32
Static icon frame frequency:
fOSCIN1 /8(division ratio) /32
1/38
1/25
1/12
1/38
1/25
1/12
1/1
1/1
1/2
1/2
1/4
1/8
1/97 to 1/112
OSCIN2
L(OFF)
H(ON)
1/2
1/8
OSCIN1
1/38
1/25
1/12
1/38
1/25
1/12
L(OFF)
H(ON)
OSCIN1
−
1/10
Static icon frame frequency: fOSCIN1 /10(division ratio) /32
Partial frame frequency:
fOSCIN2 /4 /38
Partial frame frequency:
fOSCIN2 /4 /25
Partial frame frequency:
fOSCIN2 /2(division ratio) /4 /12
Partial frame frequency:
fOSCIN1 /2(division ratio) /4 /38
Partial frame frequency:
fOSCIN1 /4(division ratio) /4 /25
Partial frame frequency:
fOSCIN1 /8(division ratio) /4 /12
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN2 /2(division ratio) /32
Static icon frame frequency:
fOSCIN1 /10(division ratio) /32
Static icon frame frequency:
fOSCIN1 /10(division ratio) /32
Static icon frame frequency:
fOSCIN1 /10(division ratio) /32
1/38
1/25
1/12
1/38
1/25
1/12
1/1
1/1
1/2
1/2
1/4
1/8
1/113 to 1/128
OSCIN2
L(OFF)
H(ON)
1/2
OSCIN1
1/10
28
Data Sheet S15730EJ2V0DS
µPD16498
Table 5-6 shows the relationship between the CLS pin, resistors RN and RP, and the display clock circuit.
Table 5-6. Relationship between CLS Pin/Resistors and Display Clock Circuit.
RN
RP
Use Example
(Figure 5-8)
CLS
Clock for Normal Display
Clock for Partial Display
Connection
Connection
Connected
Connected
Connected
Not connected
Connected
L
H
L
Internal oscillator
Internal oscillator
External clock
External clock
External clock
Internal oscillator
Divided from oscillator clock
Internal oscillator
(A)
(B)
(C)
(D)
(E)
Not connected
Not connected Not connected
Not connected Not connected
L
External clock
H
Divided from external clock
Figure 5-10. Clock Use Examples
(A)
(B)
OSCIN1
OSCIN2
OSCIN1
OSCIN2
RN
H or L
RN
RP
OSCOUT
OSCOUT
(C)
(D)
f
N
f
N
OSCIN1
OSCIN2
OSCIN1
OSCIN2
f
P
RP
Open
OSCOUT
OSCOUT
(E)
f
N
OSCIN1
OSCIN2
H or L
Open
OSCOUT
29
Data Sheet S15730EJ2V0DS
µPD16498
5.5
Display Timing Generator
The display clock generates timing signals for the line address circuit and the display data latch circuit.
Display data is latched into the display data latch circuit in synch with the display clock and is output via segment driver
output pins.
Reading of the display data is completely independent of the CPU's accessing of the display data RAM. Consequently,
there are no adverse effects (such as flicker) on the LCD panel even when the display data RAM is accessed
asynchronously in relation to the LCD contents.
The internal common timing is generated from the display clock. As shown in Figure 5-11, a driver waveform based on
the frame AC drive method is generated for the LCD driver.
Figure 5-11. Driver Waveform Based on Frame AC Drive Method
1 frame
126127128
126127128
1
1 2 3 4 5 6 7 8
2 3 4 5 6 7 8
RAM
DATA
VLCD
VLC1
VLC2
SEG
1
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM
1
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM
2
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM128
VLC3
VLC4
VSS
30
Data Sheet S15730EJ2V0DS
µPD16498
5.6
Power Supply Circuit
The power supply circuit supplies the voltage needed to drive the LCD. It includes a booster, voltage regulator, and
voltage follower.
In the power supply circuit, the power system control register 1 (R32) is used to control the ON/OFF status of the power
supply circuit's booster, voltage regulator (also called V regulator), and voltage follower (V/F). This makes it possible to
jointly use an external power supply together with certain functions of the on-chip power supply. Table 5-7 shows the
function that controls the 3-bit data in the power system control register 1 (R32) and Table 5-8 shows a reference chart of
combinations.
Table 5-7. Control Values of Bits in Power System Control 1
Status
Item
1
0
OP2
OP1
OP0
Booster control bit
ON
ON
ON
OFF
OFF
OFF
Voltage regulator (V regulator) control bit
Voltage follower (V/F) control bit
Table 5-8. Reference Chart of Combinations
External
Power Supply
Input
Boost-Related Note
System Pins
Use Status
OP2 OP1 OP0 Booster V Regulator
V/F
<1> Use on-chip power supply
<2> Use V regulator and V/F only
<3> Use V/F only
1
0
0
0
1
1
0
0
1
1
1
0
enable
disable
disable
disable
enable
enable
disable
disable
enable
enable
enable
disable
VDD2
Used
VOUT
Not connected
Not connected
Not connected
VOUT, AMPOUT
VOUT,
<4> Use external power supply only
VLCD to VLC4
Note The boost-related system pins are indicated as pins C1+, C1− to C9+, C9−, and C1A.
5.6.1 Booster
A booster that boosts the LCD driving voltage by 2 to 9 times is incorporated in the power supply circuit.
Since the booster uses signals from the on-chip oscillator, either the oscillator must be operating or a display clock must be
input from an external source.
The booster uses pins C1+, C1− to C9+, C9− for normal boost and pins C1A and VDD2 for boost regulation. The wire
impedance should be kept as low as possible. The number of boost levels is set using the FBS2, FBS1, and FBS0 flags in
power system control 3 (R34), as shown in Table 5-9.
Caution If a capacitor is connected to a boost-related system pin that is not for one of these set boost levels,
current consumption may increase. Therefore, do not connect any capacitors beyond the number of
set boost levels. This also applies for the C1A pin, used to regulate the boost levels.
Figure 5-12 describes the connection method for boost levels and capacitors.
The partial booster is settings are made using the BST1 and BST0 flags in the power system control 3 (R34), as shown in
Table 5-10.
31
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-12. Connection Method for Boost Levels and Capacitors
9x boost mode
8x boost mode
7x boost mode
6x boost mode
5x boost mode
4x boost mode
Table 5-9. Boost Level Settings for Normal Display's Booster
FBS2
FBS1
FBS0
Boost Level
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4x
5x
6x
7x
8x
9x
Prohibited
Prohibited
Table 5-10. Boost Level Settings for Partial Display's Booster
BST1
BST0
Boost Level
0
0
1
1
0
1
0
1
2x
3x
4x
Prohibited
32
Data Sheet S15730EJ2V0DS
µPD16498
5.6.2 Voltage regulator
The boost voltage from VOUT is supplied to the voltage regulator and output as the LCD drive voltage VLCD.
Since the µPD16498 has a 256-step electronic volume function and an on-chip resistor for VLCD voltage regulation, a small
number of components can be used to configure a highly accurate voltage regulator.
(1) When using an on-chip resistor for VLCD voltage regulation
The on-chip resistor for VLCD voltage regulation and the electronic volume function can be used to regulate the contrast of
the LCD contents by controlling the LCD drive voltage VLCD using commands only. In such cases, no external resistor is
needed.
If VLCD < VOUT, then the value for VLCD can be determined from the following equation.
Example Equation VLCD < VOUT
Rb
VLCD = (1 +
VLCD = (1 +
) VEV
Ra
Rb
Ra
α
) (1 −
) VREG
384
α
Remark VEV = (1 −
) VREG
384
Figure 5-13. When Using On-Chip Resistor for VLCD Voltage Regulation
+
V
EV (Constant voltage source +
electronic volume)
VLCD
-
Rb
Ra
VREG is the IC's on-chip constant voltage source, for which three types of temperature characteristic curves are available.
These temperature characteristic curves can be adjusted via settings in the power system control register 1 (R32) (TSC1,
TCS0), as shown in Table 5-11.
Table 5-11 shows the VREG voltage when TA = 25°C.
Table 5-11. VREG Voltage When TA = 25°C
Status
TCS1
TCS0
Temperature Curve (%/°C)
VREG (TYP.) (V)
Internal power supply
0
0
1
1
0
1
0
1
−0.06
−0.08
−0.09
−0.12
1.04
0.98
0.93
0.85
α is the electronic volume register (R35) value. Any of 256 statuses can be set as the fetched status for α corresponding
to the data set to the 8-bit electronic control register. α values based on settings in the electronic volume register (R35:
normal display mode) and the partial electronic volume register (R36: partial display mode) are listed in Table 5-12.
33
Data Sheet S15730EJ2V0DS
µPD16498
Table 5-12. α Values Based on Settings in Electronic Volume Register
Register
EV7
EV6
EV5
EV4
EV3
EV2
EV1
EV0
α
PEV7
PEV6
PEV5
PEV4
PEV3
PEV2
PEV1
PEV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
384
254
253
252
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
2
1
0
Rb/Ra is an on-chip resistance factor used for the VLCD voltage regulator. This factor can be controlled at eight levels
based on settings in power control register 2 (R33) (VRR2, VRR1, VRR0: normal display mode and PVR2, PVR1, PVR0:
partial display mode). Reference voltage values (1 + Rb/Ra) are determined based on 4-bit data set to VLCD's on-chip
resistance factor register, as shown in Table 5-13.
Table 5-13. Determination of Reference Voltage Values Based on Settings of
On-Chip Resistor for VLCD Voltage Regulation
Register
VRR2
PVR2
VRR1
PVR1
VRR0
PVR0
1+Rb/Ra
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5
8
12
13
16
19
21
24
34
Data Sheet S15730EJ2V0DS
µPD16498
(2) When using an external resistor (instead of using the on-chip resistor for VLCD voltage regulation)
Instead of using only the on-chip resistor setting for VLCD voltage regulation (IRS = L), resistors (Ra', Rb' and Rc') can be
added between VSS and VR, between AMPOUTP and AMPOUT, and between VR and AMPOUT to set the LCD drive voltage
VLCD. In such cases, the electronic volume function can be used to control the LCD drive voltage VLCD and to regulate the
contrast of the LCD contents via commands.
In addition, the µPD16498 enable selection between two display values (for normal display and partial display).
The value is set using an external division resistor and is automatically selected by the DTY flag in the control register 2
(R1).
The VLCD value can be determined using Example 1 (DTY = 0) and Example 2 (DTY = 1) if it is within the range of VLCD <
VOUT.
Example 1. DTY = 0, normal display mode
′
Rb
VLCD = (1 +
VLCD = (1 +
) VEV
′
′
Ra
Rb
α
) (1 −
) VREG
′
Ra
384
α
Remark VEV (1 −
) VREG
384
Example 2. DTY = 1, partial display mode
′
Rb ×Rc
VLCD = (1+
VLCD = (1+
) VEV
′
′
Ra (Rb + Rc)
′
α
Rb ×Rc
) (1 −
) VREG
′
′
384
Ra
(
Rb + Rc
)
α
Remark VEV = (1 −
) VREG
384
Figure 5-14. When Using External Resistor
+
V
LCD
-
Normal/partial VLC1 regulation
select circuit
A
B
V
R
AMPOUT
AMPOUTP
Rb'
Rc
Ra'
Normal display mode
A
A
B
B
(DTY = 0)
Partial display mode
(DTY = 1)
35
Data Sheet S15730EJ2V0DS
µPD16498
5.6.3 Use of op amp for level power supply control
Although the µPD16498 includes a circuit designed for low power consumption (HPM1, HPM0 = 0, 0), display quality
problems may occur when a large-load LCD panel is used. In such cases, the display quality and power consumption
level can be improved by setting. The HPM1 and HPM0 flags in the power system control register 1(R32) to "0, 1" to
"1, 1" to switch to the op amp driver capacity for mode settings shown in Table 5-14. Check the actual display quality before
deciding which mode to set.
If setting high power mode still does not sufficiently improve the display quality, the LCD drive voltage must be provided
from an external power source.
Table 5-14. Op Amp Mode Setting
HPM1
HPM0
Mode Setting
Normal mode
0
0
1
1
0
1
0
1
Low power mode
High power mode
For power ON mode
36
Data Sheet S15730EJ2V0DS
µPD16498
5.6.4 Application examples of power supply circuits
Figures 5-15 to 5-19 show application examples of power supply circuits.
Figure 5-15. IRS = H, [OP2, OP1, OP0] = [1, 1, 1]
9x boost mode
V
V
DD1
DD2
V
RS
V
R
V
OUT
Open
AMPOUTP
AMPOUT
+
C1
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
C4
+
C5
-
+
C5
C6
-
+
C6
C7
C9
+
-
C9
-
+
C7
C8
C1A
-
C8
V
SS
Figure 5-16. IRS = L, [OP2, OP1, OP0] = [1, 1, 1]
9x boost mode
V
RS
V
V
DD1
DD2
V
OUT
AMPOUTP
Rc
V
R
Rb'
Ra'
+
AMPOUT
C1
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
C4
+
C5
-
+
C5
C6
-
+
+
C6
C9
C7
-
C9
-
+
C7
C1A
C8
-
C8
V
SS
37
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-17. IRS = H, [OP2, OP1, OP0] = [0, 1, 1]
V
RS
V
V
DD1
DD2
V
R
Open
V
OUT
AMPOUTP
AMPOUT
+
C1
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
C4
Open
+
C5
-
+
C5
C6
-
+
C6
C7
C9
+
Open
-
C9
-
+
C7
C8
C1A
-
C8
V
SS
Figure 5-18. IRS = L, [OP2, OP1, OP0] = [0, 0, 1]
V
RS
Open
Open
V
V
DD1
DD2
V
R
V
OUT
+
C1
AMPOUTP
AMPOUT
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
+
C4
C5
Open
-
+
C5
C6
-
+
C6
C7
C9
+
Open
-
C9
-
+
C7
C8
C1A
-
C8
V
SS
38
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-19. IRS = L, [OP2, OP1, OP0] = [0, 0, 0]
V
RS
V
V
DD1
DD2
V
R
Open
V
OUT
AMPOUTP
AMPOUT
+
C1
-
+
C1
C2
V
LCD
-
C2
C3
+
V
V
LC1
LC2
-
+
C3
C4
V
V
LC3
LC4
-
C4
Open
+
C5
-
+
C5
C6
-
+
C6
C7
C9
+
Open
-
C9
-
+
C7
C8
C1A
-
C8
V
SS
39
Data Sheet S15730EJ2V0DS
µPD16498
5.7
LCD Display Drivers
µPD16498 includes both a full dot driver and a static driver icon driver. The full dot driver has a 33-level gray-scale palette
(eight levels of pulse width modulation plus four-frame rate control), from which four levels of gray scale can be selected
and registered as the IC's output gray-scale palette. The icon driver has a gray-scale palette with 32-level pulse width
modulation, from which four levels of gray scale can be selected and registered for use as the IC's output gray-scale palette
(refer to 6.23 Gary scale registers 1 to 4 (R23 to R26)).
5.7.1 Full-dot pulse width modulation
The µPD16498's pulse width modulator divides the normal LCD display signal's segment pulse width by eight and outputs
in synch with the dot output timing based on the ratio (1/8 to 8/8 pulses) for the gray-scale palette that has been selected via
a command.
Figure 5-20. Full-Dot Pulse Width Modulation
1 frame
126 127 128
126 127 128
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
V
LCD
V
V
LC1
LC2
SEG
1
V
V
LC3
LC4
V
SS
V
LCD
V
V
LC1
LC2
COM
1
V
V
LC3
LC4
V
SS
Enlarged section
1
2
3
8/8
6/8
4/8
1/8
VLCD
V
V
LC1
LC2
Caution There is no pulse width modulation for common outputs.
40
Data Sheet S15730EJ2V0DS
µPD16498
The output pulses are output as odd-numbered lines/even-numbered lines or as even-numbered lines/odd-numbered lines,
as shown in Figure 5-21. The pulse rising edge and falling edge combinations for each frame are listed in Table 5-15.
Figure 5-21. Example of Pulse Width Modulated Output
1 frame
126 127128
1
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
6
7
8
VLCD
VLC1
VLC2
VLC3
VLC4
VSS
1
2
3
8/8
8/8
8/8
4/8
3/8
4/8
41
Data Sheet S15730EJ2V0DS
µPD16498
Table 5-15. Example of Pulse Width Modulated Output (1/3)
Gray-scale COM
level
1, 2 Frames
SEG Odd SEG Even
Numbered Numbered Numbered Numbered Numbered Numbered Numbered Numbered
3, 4 Frames
5, 6 Frames
7, 8 Frames
SEG Odd SEG Even
SEG Odd SEG Even
SEG Odd SEG Even
0
1
2
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↑1
0
↓1
0
0
0
0
0
0
0
0
0
↓1
0
↑1
0
0
0
0
0
0
0
↓1
0
↑1
0
0
0
↑1
0
↓1
0
0
0
↑1
↓1
↑1
↓1
0
0
4n+2
4n+3
4n+4
↓1
0
↑1
0
0
0
↓1
0
↑1
0
0
0
↓1
↑1
↑1
↓1
↓1
↑1
↑1
↓1
0
0
0
0
3
4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
↑1
↓1
↑1
0
↓1
↑1
↓1
0
↓1
0
↑1
0
↑1
↓1
0
↓1
↑1
0
0
0
↑1
↓1
↑1
↓1
↑1
↓1
↑1
↓1
↑1
↓1
↓1
↑1
↓1
↑1
↑1
↓1
↑1
↓1
↓1
↑1
↓1
↑1
↓1
↑1
↑1
↓1
↓1
↑1
4n+3
4n+4
4n+1
4n+2
↑1
↓1
↑2
↓1
↓1
↑1
↓2
↑1
↓1
↑1
↓1
↑1
↑1
↓1
↑1
↓1
↑1
↓1
↑1
↓2
↓1
↑1
↓1
↑2
↓1
↑1
↓1
↑1
↑1
↓1
↑1
↓1
5
6
4n+3
4n+4
4n+1
↑1
↓1
↑2
↓1
↑1
↓2
↓1
↑2
↓1
↑1
↓2
↑1
↑1
↓1
↑2
↓1
↑1
↓2
↓2
↑1
↓1
↑2
↓1
↑1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
↓2
↑1
↓1
↑2
↓2
↑2
↓1
↑2
↑2
↓1
↑1
↓2
↑2
↓2
↑1
↓2
↑1
↓2
↑2
↓2
↑1
↓2
↑2
↓2
↓1
↑2
↓2
↑2
↓1
↑2
↓2
↑2
↓2
↑1
↓1
↑2
↓2
↑1
↓2
↑2
↑2
↓1
↑1
↓2
↑2
↓1
↑2
↓2
↑1
↓2
↑2
↓1
↑2
↓2
↑2
↓2
↓1
↑2
↓2
↑1
↓2
↑2
↓2
↑2
7
8
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
↓2
↑2
↓2
↑3
↓2
↑2
↓2
↑3
↓3
↑2
↓2
↑2
↓2
↑2
↓3
↑2
↓2
↑2
↓3
↑3
↓2
↑2
↑2
↓2
↑2
↓2
↑2
↓2
↑3
↓2
↑2
↓3
↑3
↓2
↑2
↓2
↑2
↓2
↑2
↓3
↑2
↓2
↑3
↓3
↓2
↑2
↓2
↑2
↓3
↑2
↓2
↑3
↓3
↑2
↓2
↑2
↓2
↑2
↓2
↑3
↓2
↑2
↓3
↑3
↓2
↑2
↑2
↓2
↑2
↓2
↑2
↓3
↑2
↓2
↑2
↓3
↑3
↓2
↑2
↓2
↑2
↓2
↑3
↓2
↑2
↓2
↑3
↓3
9
10
Remarks 1. n: Integer from 0 to 31.
2. ↑A: Rising edge of pulse during line A output.
3. ↓A: Rising edge of pulse at start of line A output.
4. A: PWM pulse width (A/8)
42
Data Sheet S15730EJ2V0DS
µPD16498
Table 5-15. Example of Pulse Width Modulated Output (2/3)
Gray-scale COM
level
1, 2 Frames
SEG Odd SEG Even
Numbered Numbered Numbered Numbered Numbered Numbered Numbered Numbered
3, 4 Frames
5, 6 Frames
7, 8 Frames
SEG Odd SEG Even
SEG Odd SEG Even
SEG Odd SEG Even
11
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
↑3
↓3
↑3
↓2
↑3
↓3
↓3
↑3
↓3
↑2
↓3
↑3
↓3
↑2
↓3
↑3
↓3
↑3
↑3
↓2
↑3
↓3
↑3
↓3
↑3
↓3
↑2
↓3
↑3
↓3
↓3
↑3
↓2
↑3
↓3
↑3
↓2
↑3
↓3
↑3
↓3
↑3
↑2
↓3
↑3
↓3
↑3
↓3
12
13
14
4n+3
4n+4
4n+1
↑3
↓3
↑4
↓3
↑3
↓4
↓3
↑3
↓3
↑3
↓3
↑3
↑3
↓3
↑3
↓3
↑3
↓3
↓3
↑3
↓3
↑3
↓3
↑3
4n+2
↓3
↑3
↑3
↓3
↓4
↑4
↑3
↓3
4n+3
4n+4
4n+1
4n+2
↑3
↓3
↑4
↓4
↓3
↑3
↓4
↑4
↓3
↑4
↓3
↑3
↑3
↓4
↑3
↓3
↑3
↓3
↑4
↓4
↓3
↑3
↓4
↑4
↓4
↑3
↓3
↑3
↑4
↓3
↑3
↓3
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
↑3
↓3
↑4
↓4
↑4
↓3
↑4
↓3
↑3
↓4
↑4
↓4
↑3
↓4
↓4
↑4
↓4
↑3
↓4
↑4
↓4
↑4
↓4
↑4
↓3
↑4
↓4
↑4
↑3
↓3
↑4
↓4
↑3
↓4
↑4
↓3
↑3
↓4
↑4
↓3
↑4
↓4
↓4
↑4
↓3
↑4
↓4
↑4
↓4
↑4
↓4
↑3
↓4
↑4
↓4
↑4
15
16
17
18
4n+2
4n+3
4n+4
4n+1
4n+2
↓4
↑4
↓4
↑5
↓4
↑4
↓4
↑4
↓5
↑4
↑4
↓4
↑4
↓4
↑4
↓4
↑4
↓4
↑4
↓4
↓4
↑4
↓4
↑4
↓5
↑4
↓4
↑4
↓4
↑5
↑4
↓4
↑4
↓4
↑4
↓4
↑4
↓4
↑4
↓4
4n+3
4n+4
4n+1
4n+2
↑4
↓4
↑5
↓5
↓4
↑4
↓5
↑5
↓4
↑5
↓4
↑4
↑4
↓5
↑4
↓4
↑4
↓4
↑5
↓5
↓4
↑4
↓5
↑5
↓5
↑4
↓4
↑4
↑5
↓4
↑4
↓4
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
↑4
↓4
↑5
↓5
↑5
↓4
↑5
↓5
↓4
↑4
↓5
↑5
↓5
↑4
↓5
↑5
↓5
↑5
↓5
↑4
↓5
↑5
↓5
↑5
↑5
↓5
↑5
↓4
↑5
↓5
↑5
↓5
↑4
↓4
↑5
↓5
↑4
↓5
↑5
↓5
↓4
↑4
↓5
↑5
↓4
↑5
↓5
↑5
↓5
↑5
↓4
↑5
↓5
↑5
↓5
↑5
↑5
↓5
↑4
↓5
↑5
↓5
↑5
↓5
19
20
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
↑5
↓5
↑6
↓5
↑5
↓5
↓5
↑5
↓6
↑5
↓5
↑5
↓5
↑5
↓5
↑5
↓5
↑6
↑5
↓5
↑5
↓5
↑5
↓6
↑5
↓5
↑5
↓6
↑5
↓5
↓5
↑5
↓5
↑6
↓5
↑5
↓5
↑5
↓5
↑5
↓6
↑5
↑5
↓5
↑5
↓5
↑6
↓5
21
Remarks 1. n: Integer from 0 to 31.
2. ↑A: Rising edge of pulse during line A output.
3. ↓A: Rising edge of pulse at start of line A output.
4. A: PWM pulse width (A/8)
43
Data Sheet S15730EJ2V0DS
µPD16498
Table 5-15. Example of Pulse Width Modulated Output (3/3)
Gray-scale COM
level
1, 2 Frames
SEG Odd SEG Even
Numbered Numbered Numbered Numbered Numbered Numbered Numbered Numbered
3, 4 Frames
5, 6 Frames
7, 8 Frames
SEG Odd SEG Even
SEG Odd SEG Even
SEG Odd SEG Even
22
4n+1
↑6
↓6
↓5
↑5
↑6
↓6
↓5
↑5
4n+2
4n+3
↓6
↑5
↑6
↓5
↑5
↓6
↓5
↑6
↓6
↑5
↑6
↓5
↑5
↓6
↓5
↑6
4n+4
4n+1
↓5
↑6
↑5
↓6
↑6
↓6
↓6
↑6
↓5
↑6
↑5
↓6
↑6
↓5
↓6
↑5
23
24
25
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
↓6
↑6
↓5
↑6
↓6
↑6
↓6
↑7
↑6
↓6
↑5
↓6
↑6
↓6
↑6
↓7
↑5
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↓5
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑5
↓6
↑6
↓6
↑6
↓6
↑6
↑6
↓5
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↓6
↑6
↓6
↑6
↓6
↑6
↓6
↑6
4n+2
4n+3
↓6
↑6
↑6
↓6
↑6
↓6
↓6
↑6
↓7
↑6
↑7
↓6
↑6
↓7
↓6
↑7
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
↓6
↑7
↓7
↑6
↓6
↑7
↓7
↑7
↓6
↑7
↓7
↑7
↑6
↓7
↑7
↓6
↑6
↓7
↑7
↓7
↑6
↓7
↑7
↓7
↑7
↓6
↑6
↓7
↑7
↓7
↑6
↓7
↑7
↓7
↑7
↓7
↓7
↑6
↓6
↑7
↓7
↑7
↓6
↑7
↓7
↑7
↓7
↑7
↓6
↑7
↓7
↑6
↓6
↑7
↓7
↑6
↓7
↑7
↓7
↑7
↑6
↓7
↑7
↓6
↑6
↓7
↑7
↓6
↑7
↓7
↑7
↓7
↑6
↓6
↑6
↓7
↑7
↓6
↑7
↓7
↑7
↓7
↑7
↓7
↓6
↑6
↓6
↑7
↓7
↑6
↓7
↑7
↓7
↑7
↓7
↑7
26
27
28
29
4n+4
4n+1
4n+2
↓7
8
↑7
8
↑7
↓7
↑7
↓7
↑7
↓7
↓7
↑7
8
↑7
↓7
8
↑7
↓7
↑7
↓7
↑7
↓7
↓7
↑7
4n+3
↑7
↓7
↓7
↑7
↑7
↓7
8
8
4n+4
4n+1
4n+2
4n+3
4n+4
4n+1
4n+2
4n+3
↓7
8
↑7
8
8
↓7
↑7
8
8
↑7
↓7
8
↓7
8
↑7
8
↑7
↓7
↑7
8
↓7
↑7
↓7
8
30
31
8
8
8
8
↑7
↓7
8
↓7
↑7
8
↑7
↓7
8
↓7
↑7
8
8
8
8
8
8
8
↓7
8
↑7
8
8
8
↑7
8
↓7
8
8
8
8
8
↑7
↓7
8
8
4n+4
4n+1
↓7
↑7
8
8
8
8
8
8
8
8
8
8
8
8
32
8
8
4n+2
4n+3
4n+4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Remarks 1. n: Integer from 0 to 31.
2. ↑A: Rising edge of pulse during line A output.
3. ↓A: Rising edge of pulse at start of line A output.
4. A: PWM pulse width (A/8)
44
Data Sheet S15730EJ2V0DS
µPD16498
5.7.2 Full-dot frame rate control
When combined with pulse width modulation as described in Table 5-15, the µPD16498's frame speed is based on 8-
frame cycles. The subsampling pattern is output based on the palette stored in the IC.
Full-Dot Gray-Scale Palette (Output Pulse Width: x/8 Pulses)
Frames
Gray scale level
Comments
1
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
2
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
3
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
4
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
5
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
6
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
7
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
0
OFF data
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
50%
100%
Remark The gradation in the Comments column are images of the gray-scale level.
45
Data Sheet S15730EJ2V0DS
µPD16498
5.7.3 Line shift driver
If the frame rate control is performed with equal pulse widths and the same gray scale is displayed on the LCD's full
screen, problems such as flickering may occur on the LCD panel. The µPD16498 provides a line shift driver as a
countermeasure against such screen image problems.
Using 8 frames per cycle, the segment PWM output timing is shifted among the common outputs, as shown in Table 5-16
below.
Table 5-16. Line Shift Driver
Turn 1
Turn 2
Frame
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
•
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3
F7
F5
F1
F3
F7
F5
F1
F3
F7
•
F4
F8
F6
F2
F4
F8
F6
F2
F4
F8
•
F5 F6
F1 F2
F7 F8
F3 F4
F5 F6
F1 F2
F7 F8
F3 F4
F5 F6
F1 F2
F7
F3
F1
F5
F7
F3
F1
F5
F7
F3
•
F8
F4
F2
F6
F8
F4
F2
F6
F8
F4
•
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3
F7
F5
F1
F3
F7
F5
F1
F3
F7
•
F4
F8
F6
F2
F4
F8
F6
F2
F4
F8
•
F5 F6
F1 F2
F7 F8
F3 F4
F5 F6
F1 F2
F7 F8
F3 F4
F5 F6
F1 F2
F7
F3
F1
F5
F7
F3
F1
F5
F7
F3
•
F8
F4
F2
F6
F8
F4
F2
F6
F8
F4
•
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3 F4
F7 F8
F1 F2
F5 F6
F3
F7
F5
F1
F3
F7
F5
F1
F3
F7
•
F4
F8
F6
F2
F4
F8
F6
F2
F4
F8
•
•
•
•
•
•
•
•
•
•
•
Remark Fx: Pulse width modulated output frame (See 5.7.2 Full-dot frame rate control).
Figure 5-22. Full Dot Frame Rate Control
First frame
Second frame
1
2
3
4
5
1
2
127
128
ON
OFF
COM
COM
COM
1
2
3
ON
OFF
ON
OFF
ON
OFF
COM
4
5
ON
OFF
COM
ON
COM127
COM128
OFF
ON
OFF
SEG
SEG
1
8
8
1
1
5
5
3
3
7
7
1
1
5
5
3
3
7
7
2
2
6
6
2
3
4
5
8
8
1
1
5
5
3
3
7
7
1
1
5
5
3
3
7
7
2
2
6
6
SEG
SEG
SEG
8
1
5
3
7
1
5
3
7
2
6
Remark Numerical values in the segment data correspond to the gray-scale palette's frame numbers.
46
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-23. Line Shift Driver Image
Turn 1, first frame
SEG
1
SEG
3
SEG
5
SEG
7
SEG127
SEG
2
SEG
4
SEG
6
SEG
8
SEG126
SEG128
COM
1
2
F1
F5
F3
F7
F1
COM
COM
3
4
COM
COM
5
COM126
F5
F3
F7
COM127
COM128
Turn 1, second frame
SEG
SEG
1
SEG
3
SEG
5
7
SEG127
SEG
2
SEG
4
SEG
6
SEG
8
SEG126
SEG128
COM
1
2
F2
F6
F4
F8
F2
COM
COM
3
4
COM
COM
5
COM126
F6
F4
F8
COM127
COM128
47
Data Sheet S15730EJ2V0DS
µPD16498
5.7.4 Display size settings
The µPD16498 can be set for any duty value from 1/1 to 1/128. This duty setting can be made via bits DT6 to DT0 in the
duty setting register (R5), as shown in Table 5-17.
Table 5-17. Duty Settings
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Duty
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
1/1
1/2
1/3
1/4
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1/126
1/127
1/128
5.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position
The µPD16498 enable any setting to be made for the AC driver's inversion position and the inversion position shift amount
for each displayed frame via settings made in the AC driver inversion cycle register (R6) and the AC driver inversion
position shift register (R7) for normal display mode or via settings made in the partial AC driver inversion cycle register (R8)
and the partial AC driver inversion position shift register (R9) for partial display mode.
In normal display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed
in Table 5-18, based on the NID6 to NID0 bit settings in the AC driver inversion cycle register (R6).
If the screen display size has been changed via settings made in the duty setting register (R5), the NIDn values are
automatically overwritten by values from the corresponding DTYn bits.
The shift amount for each displayed frame can be set as shown in Table 5-19 via settings made to bits MSD6 to MSD0 in
the AC driver inversion position shift register (R7).
Table 5-18. Settings of AC Driver Inversion Cycle Register (R6)
NID6
NID5
NID4
NID3
NID2
NID1
NID0
Inverted Lines
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
1
2
3
4
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
126
127
128
48
Data Sheet S15730EJ2V0DS
µPD16498
Table 5-19. Settings of AC Driver Inversion Position Shift Register
MSD6
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
125
126
127
In partial display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed in
Table 5-20, based on the PID5 to PID0 bit settings in the partial AC driver inversion cycle register (R8).
The shift amount for each displayed frame can be set as shown in Table 5-21 via settings made to bits PSD5 to PSD0 in
the partial AC driver inversion position shift register (R9).
Table 5-20. Settings of Partial AC Driver Inversion Cycle Register (R8)
PID5
PID4
PID3
PID2
PID1
PID0
Inverted Lines
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
1
2
3
4
:
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
36
37
38
Table 5-21. Setting of Partial AC Driver Inversion Position Shift Register (R9)
PSD5
PSD4
PSD3
PSD2
PSD1
PSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
1
1
0
1
0
1
0
1
2
3
:
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
35
36
37
Be sure to maintain the following relationship among the display size, AC inversion cycle, and AC inversion position.
Display size (duty) ≥ AC inversion cycle ≥ AC inversion shift amount
Caution Setting a small inversion cycle will cause a reduction in the IC's display drive capacity and an increase
in the current consumption.
We therefore recommend determining the inversion cycle after making a thorough evaluation of the
actual LCD panel.
49
Data Sheet S15730EJ2V0DS
µPD16498
5.8
Display Modes
5.8.1 Partial display mode
The µPD16498 include a function for outputting a display that uses only part of the LCD panel. The duty setting for partial
display mode can be selected as 1/12, 1/25, or 1/38. Parts of the LCD panel that are outside of the specified display area
are scanned with non-select waveforms. The partial start line address register (R21) is used to select which part of the
LCD panel to use for the partial display. The display area starts from the start line address and includes the number of lines
(12, 25, or 38 lines) that has been specified via the partial display mode setting (R10).
When entering this mode, the booster is set to the boost level number that has been set via the power system control
register 3 (partial display boost register) (R34) and the display start line is fixed as 00H. In addition, the bias level is
automatically changed to the value that has been set via the partial display mode setting (R10). The relationship between
the oscillator's frequency and the frame frequency in partial mode is also automatically changed.
Figure 5-24 shows the mutual relationship between the partial line start address and the LCD display.
When using the partial display mode, the blinking and reverse display functions can be used in the same way as during
full-dot display mode.
Caution The LCD driver voltage is lower in partial display mode, because the duty is lower than in normal display
mode. There may be restrictions on the usable duty depending on the LCD panel characteristics.
We recommend determining the partial duty after making a thorough evaluation of the actual LCD panel.
Figure 5-24. Relationship Between Partial Line Start Address and LCD Display
(in Partial Display Mode)
...
00H
01H
02H
03H
1DH
1EH
1FH
Display start line
(00H)
Partial display
start line
Non-display areas
Caution In partial display mode, the display start line setting register (R12) command is ignored.
When switching from normal display mode to partial display mode or from partial display mode to normal display mode, if
an electric charge remains in the smoothing capacitor that is connected between the LCD drive voltage pins (VLCD, VLC1 to
VLC4) and the VSS pin, troubles such as a brief all-black display may occur during the mode switching operation. To avoid
such troubles, we recommend using the following power-on sequence.
50
Data Sheet S15730EJ2V0DS
µPD16498
(1) Normal display → partial display switch sequence
DISP = 0
R0
Display OFF
↓
HPM1 = 1, HPM0 = 0
R32
R1
High power mode settings
Control register 2: switch DTY flag
↓
Switch display mode
↓
700 ms (stabilization time for LCD drive voltage and
booster)Note
Wait time
↓
HPM1 = X, HPM0 = X
R32
R0
High power mode settings
↓
(to mode used during normal display)
Display ON, internal operations status
DISP = 1
Note This 700ms wait time indicates the time for the VLCD level to change from 15V to 6V and thus varies according to
the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend
determining the wait time after making a thorough evaluation of the actual device.
(2) Partial display → Normal display switch sequence
DISP = 0
R0
Display OFF
↓
HPM1 = 1, HPM0 = 1
R32
R1
Power ON mode settings
Control register 2: switch DTY flag
↓
Switch display mode
↓
400 ms (stabilization time for LCD drive voltage and
booster)Note
Wait time
↓
HPM1 = X, HPM0 = X
R32
R0
High power mode settings
↓
(to mode used during normal display)
Display ON, internal operations status
DISP = 1
Note This 400ms wait time indicates the time for the VLCD level to change from 6V to 15V and thus varies according to
the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend
determining the wait time after making a thorough evaluation of the actual device.
51
Data Sheet S15730EJ2V0DS
µPD16498
5.8.2 Monochrome (black/white) display
The µPD16498 provides both a four-level gray scale display mode and a monochrome display mode.
To switch to the monochrome display mode, set GRAY = H. The display RAM for one screen of monochrome display
mode contents is configured as 128 bits x 128 bits (16 x 8 bits). When using these IC's in monochrome display mode, two
screens of data can be written to the display RAM and the two screens can be switched by setting the DSEL bit in the
control register 2 (R1). Screen 1 is displayed on the LCD panel when DSEL = L and screen 2 is displayed when DSEL = H.
When writing data, the display RAM uses the same X address (00H to 0FH) and Y address and the BWW bit value in the
control register 2 (R1) determines which of the two screens the data will be written to: when BWW = L, data is written to
screen 1 and when BWW = H, data is written to screen 2, as shown in Figure 5-25.
When accessing a specified bit, specify both the X address and Y address. The display data in D0 to D7 (sent from the
CPU) corresponds to the SEGx portions of the LCD display, as shown in Figure 5-26. Figure 5-27 shows the relationship
between the display data in monochrome display mode and the page/column addresses.
Figure 5-25. Display RAM Image in Monochrome (Black/White) Mode
00H
0FH
00H
0FH
Screen 1
Screen 2
DSEL = L (during display)
BWW = L (during write)
DSEL = H (during display)
BWW = H (during write)
Figure 5-26. Relationship Between Display Data and LCD Display
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 1 1 1 1 1 0 0 1 1
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0
0 1 0 1 0 1 0 1 1 1 1 1 0 1 0 0
0 1 0 0 1 1 0 1 0 0 0 0 0 1 0 0
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
0 1 0 0 0 1 0 1 1 1 1 1 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data
Display data
LCD display
52
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-27. Relation Between the Display Data and X/Y Address
(in Monochrome Display Mode)
D4
D3
D2
D1
0
0
0
0
0
1
0
0
1
0
0
1
COM
output
D0
0
1
1
0FH
Y
address
00H
01H
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Data
00H
COM1
COM2
COM3
COM4
COM5
01H
02H
03H
04H
05H
06H
07H
08H
09H
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
0A
H
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
COM29
COM30
COM31
COM32
COM33
COM34
COM35
Start
COM36
COM37
COM38
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
COM119
COM120
COM121
COM122
COM123
COM124
COM125
COM126
COM127
COM128
53
Data Sheet S15730EJ2V0DS
µPD16498
5.8.3 Icon display
The µPD16498 includes 20 segment pins and two common pins (both output the same signal) for displaying icons,
independent of the pins used to display graphics. Icons are static-driven and their contrast can be adjusted at 32 levels
using phase modulation.
The static icon data RAM that is used to record icon display data contains display data (DIS) and blink data (BRI) in a
20-bit x 2 configuration, as shown in Table 5-22 (where ADC = 0) and Table 5-23 (where ADC = 1).
Addresses in the static icon data RAM are specified via the static icon address register (R40) and then data is written to
memory.
The icon blink function operates only when the display data setting is 1, the blink data setting is 1, and the IBL setting is
also 1 (R1).
Table 5-22. Static Icon Data RAM (ADC = 0)
Static Icon Output Number (PSEGn)
Address
DIS
D7
BRI
D6
DIS
D5
BRI
D4
DIS
D3
BRI
D2
DIS
D1
BRI
D0
00H
01H
02H
03H
04H
1
5
2
3
4
6
7
8
9
10
14
18
11
15
19
12
16
20
13
17
Table 5-23. Static Icon Data RAM (ADC = 1)
Static Icon Output Number (PSEGn)
Address
DIS
D7
BRI
D6
DIS
D5
BRI
D4
DIS
D3
BRI
D2
DIS
D1
BRI
D0
00H
01H
02H
03H
04H
20
16
12
8
19
15
11
7
18
14
10
6
17
13
9
5
4
3
2
1
Adjustment of contrast is controlled by phase modulation set via the static icon contrast (R42). The pulse width of the ON
signal that is output in static drive mode is divided into 32 levels (1/32 to 32/32 pulse width) and the dot output's timing
changes during output according to the phase modulation ratio recorded in bits ICS4 to ICS0 of the static icon contrast
(R42), as shown in Table 5-24.
Table 5-24. Dot Output Timing Changes
ICS4
ICS3
ICS2
ICS1
ICS0
Phase Modulation Ratio
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
1
1
0
1
0
1
0/32
1/32
2/32
3/32
:
1
1
1
1
1
1
0
1
1
0
29/32
30/32
1
1
1
1
1
31/32
54
Data Sheet S15730EJ2V0DS
µPD16498
Figure 5-28. Phase Modulation Driver Waveforms
1 frame
31/32 to 0/32
V
DD1
PSEG
V
SS
V
DD1
PCOM
V
SS
Example of phase modulation amount for displaying 10H
1 frame
16/32
16/32
V
DD1
PSEG
PCOM
ON
ON
V
SS
V
DD1
VSS
55
Data Sheet S15730EJ2V0DS
µPD16498
5.9
Reset
In the µPD16498, a reset is executed when the /RES input is at low level or when a reset command is entered. The IC is
reset to its default settings. These default settings are listed in the table below.
Register
Number
R0
/RES
Reset Command
Enabled
Control register 1
Control register 2
X address register
Y address register
Duty setting register
Enabled (DISP flag only)
Enabled (IDIS flag only)
Disabled
R1
R3
R4
R5
AC driver inversion cycle register
AC driver inversion position shift register
Partial AC driver inversion cycle register
Partial AC driver inversion position shift register
Partial display mode setting register
Display memory access registerNote
Display start line set register
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R23
R24
R25
R26
R27
R28
R29
R30
R32
R33
R34
R35
R36
R37
R40
R41
R42
R44
R45
Disabled
Enabled
Blink X address register
Blink start line address register
Blink end line address register
Blink data memory access registerNote
Inverted X address register
Disabled
Enabled
Inversion start line address register
Inversion end line address register
Inverted data memory access registerNote
Partial start line address register
Gray scale data register 1 (0, 0)
Gray scale data register 2 (0, 1)
Gray scale data register 3 (1, 0)
Gray scale data register 4 (1, 1)
Partial gray scale data register 1 (0, 0)
Partial gray scale data register 2 (0, 1)
Partial gray scale data register 3 (1, 0)
Partial gray scale data register 4 (1, 1)
Power system control register 1
Power system control register 2
Power system control register 3
Electronic volume register
Disabled
Enabled
Partial electronic volume register
Boost adjustment register
Static icon address register
Static icon memory access registerNote
Disabled
Enabled
Static icon contrast register
RAM test mode setting register
Signature read register
Disabled
Enabled: Default value is input, Disabled: Default value is not input
Note When using the /RES pin to reset, the contents of memory are not retained. Use the reset command to reset if the
memory contents need to be retained.
Cautions 1. Using the /RES pin to reset initializes the shift clock counter.
2. Always input the reset command as the first command after power ON.
56
Data Sheet S15730EJ2V0DS
µPD16498
6. COMMAND REGISTERS
The µPD16498 chip uses a combination of RS, /RD (E), and /WR (R,/W) signals to identify data bus signals.
Command interpretation and execution is performed using internal timing that does not depend on any external clock.
Therefore, processing is very fast and there is usually no need to check for a busy status.
The i80 series CPU interface activates read commands using a low pulse input to the /RD pin and activates write
commands using a low pulse input to the /WR pin. The M68 series CPU interface sets read mode using a high level input
to the R,/W pin and sets write mode using a low level input to the same pin. It activates both read and write com mands
using a high-level pulse input to the E pin.
Command descriptions using an i80 series CPU interface are shown as follows. The M68 series CPU interface differs
from the i80 series CPU interface in that /RD (E) is at high level during status read and display data read operations, as
shown in the following command descriptions and command table.
If the serial interface has been selected, data is input sequentially starting from D7.
Data Sheet S15730EJ2V0DS
57
µPD16498
6.1 Control Register 1 (R0)
This command specifies the µPD16498's general operation modes.
E
/RD
1
R,/W
/WR
0
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
RMW
DISP
STBY
BLD
IVD
HALT
ADC
COMR
Flag
Function
RMW
0: Address is incremented after both write access and read access.
1: Read/modify/write mode
(Address is incremented only after write access)
DISP
STBY
BLD
0: Display OFF (All LCD output pins output the VSS level and oscillator and DC/DC converter are operating)
1: Display ON
0: Normal operation
1: Internal operation and oscillation are stopped. Display is OFF.
The blinking dots are specified via the blink start/end line address registers and data is set to blink data RAM.
0: Stop blinking
1: Start blinking
IVD
The number of inverted dots is specified via the inversion start/end line address registers and data is set to
inverted data RAM.
0: Stop inversion
1: Start inversion
HALT
0: Start internal operation
1: Stop internal operation (since different display modes are used, when switching between partial and normal
display modes, the LCD output pins all output the VSS level and the oscillator is operating, but the DC/DC
converter is stopped)
ADC Note
The column address corresponding to the SEG outputs (see Table 6-1) for displaying the contents of the display
data RAM.
COMR Note
This inverts (reverses) the scan direction for common outputs. (See Table 6-2)
Note The reset command must be executed before changing this flag's setting.
Table 6-1. Relationship between Display RAM Column Address and SEG Outputs
SEG Output
SEG1
00H
SEG128
7FH
0
1
→
←
Column addresses
Column addresses
→
←
ADC
(D1)
7FH
00H
Table 6-2. Relationship between Common Scan Circuit and Scan Direction
COM Output
Scan Direction
0
1
COM1
→
→
COM128
COM1
COMR
(D0)
COM128
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15730EJ2V0DS
58
µPD16498
6.2 Control Register 2 (R1)
This command specifies the µPD16498's general operation modes.
E
/RD
1
R,/W
/WR
0
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
FDM
IBL
IDIS
DSEL
BWW
GRAY
DTY
INC
Flag
Function
FDM
Settings for full screen display mode
0: Normal operation
1: Full screen display (set entire screen to ON) (When using four-level gray scale, gray-scale level 32 is output
for full screen display).
IBL
Static icon blink control, icons with "1" as blink data are blinking.
0: Static icon blink OFF
1: Static icon blink ON
IDIS
0: Static icon display OFF (All static LCD output pins output the VSS level and oscillator and DC/DC converter
are operating)
1: Static icon display ON
DSEL
BWW
Selects display screen during monochrome display mode.
0: Screen 1
1: Screen 2
Selects data write screen during monochrome display mode.
0: Screen 1
1: Screen 2
GRAY Note
DTY Note
INC
0: 4-level gray scale display mode
1: Monochrome display mode
0: Normal display mode (1/1 to 1/128 duty)
1: Partial display mode (1/12, 1/25, or 1/38 duty, 1/5 or 1/6 bias)
0: Increments X address at each access
1: Increments Y address at each access
Note The HALT command must be executed before changing this flag's setting.
Table 6-3. Relationship between IC's Functions and Display Modes
Item
Normal Display Mode (DTY = 0)
1/1 to 1/128 duty
Partial Display Mode (DTY = 1)
1/12, 1/25, or 1/38 duty
Duty
↔
↔
↔
↔
Booster
Bias level
×4, ×5, ×6, ×7, ×8, ×9
×2, ×3, ×4
1/11, 1/12, 1/10, 1/9, 1/8, 1/7
Uses levels set to the gray scale data
registers (R23 to R26)
1/5, 1/6
Gray scale data
Uses levels set to the partial gray scale
data registers (R27 to R30)
Uses values of PVR2 to PVR0 in the power
system control register 2 (R33)
(1+Rb/Ra)
Uses values of VRR2 to VRR0 in the power
system control register 2 (R33)
↔
↔
VLCD regulator resistance
factor
Electronic volume
Uses value from the electronic volume
register (R35)
Uses value from the partial electronic
volume register (R36)
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15730EJ2V0DS
59
µPD16498
6.3 Reset Command (R2)
When this command is input, the IC's registers (R0 to R44) are reset to their initial values. But the contents of memory are
retained.
Always input the reset command as the first command after power application.
RS
1
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
6.4 X Address Register (R3)
The X address register specifies the X address in the display RAM accessed by the CPU. This address is automatically
incremented each time the display RAM is accessed (INC = 0, RMW = 0).
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
XA4
XA3
XA2
XA1
XA0
Default settings (initial values set by reset command)
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
0
−
−
−
6.5 Y Address Register (R4)
The Y address register specifies the Y address in the display RAM accessed by the CPU. This address is automatically
incremented each time the display RAM is accessed (INC = 1, RMW = 0).
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
YA6
YA5
YA4
YA3
YA2
YA1
YA0
Default settings (initial values set by reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
−
Data Sheet S15730EJ2V0DS
60
µPD16498
6.6 Duty Setting Register (R5)
The display duty can be set to any duty ratio between 1/1 and 1/128, as is shown in Table 6-4.
Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Table 6-4. Duty Setting Register (R5) Settings
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Duty
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
1/1
1/2
1/3
1/4
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1/126
1/127
1/128
Default settings (initial values set by reset command)
D7
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
−
6.7 AC Driver Inversion Cycle Register (R6)
The AC driver's line position for normal display mode can be set as shown in Table 6-5.
When a DTYn value is changed in the duty setting register (R5), the NIDn value is automatically overwritten by the DTYn
value.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
NID6
NID5
NID4
NID3
NID2
NID1
NID0
Table 6-5. AC Driver Inversion Cycle Register (R6) Settings
NID6
NID5
NID4
NID3
NID2
NID1
NID0
Inversion Line
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
1
2
3
4
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
126
127
128
Default settings (initial values set by reset command)
D7
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
−
Data Sheet S15730EJ2V0DS
61
µPD16498
6.8 AC Driver Inversion Position Shift Register (R7)
This register shifts the inversion position for each frame in normal display mode by the shift amount shown in Table 6-6.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
MSD6
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Table 6-6. AC Driver Inversion Position Shift Register (R7) Settings
MSD5
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
125
126
127
Default settings (initial values set by reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
−
0
0
6.9 Partial AC Driver Inversion Cycle Register (R8)
The AC driver's line position can be set as shown in Table 6-7.
When a PDTn value is changed in the partial display mode setting register (R10), the PIDn value is automatically
overwritten by the PDTn value.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
−
PID5
PID4
PID3
PID2
PID1
PID0
Table 6-7. Partial AC Driver Inversion Cycle Register (R8) Settings
PID5
PID4
PID3
PID2
PID1
PID0
Inversion Line
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
1
1
0
1
0
1
1
2
3
4
:
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
36
37
38
Default settings (initial values set by reset command)
D7
D6
D5
1
D4
0
D3
0
D2
1
D1
D0
−
−
0
1
Data Sheet S15730EJ2V0DS
62
µPD16498
6.10 Partial AC Driver Inversion Position Shift Register (R9)
This register shifts the inversion position for each frame by the shift amount shown in Table 6-8.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
−
PSD5
PSD4
PSD3
PSD2
PSD1
PSD0
Table 6-8. Partial AC Driver Inversion Position Shift Register (R9) Settings
PSD5
PSD4
PSD3
PSD2
PSD1
PSD0
Inversion Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
:
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
35
36
37
Default settings (initial values set by reset command)
D7
D6
D5
D4
0
D3
0
D2
0
D1
D0
−
−
−
0
0
6.11 Partial Display Mode Setting Register (R10)
This command specifies the operation mode to be used in the µPD16498's partial display mode.
Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
PBIS
−
PDT1
PDT0
Flag
Function
PBIS
Sets bias level for partial display mode
0: 1/5 bias
1: 1/6 bias
PDT1, PDT0
PDT1
PDT0
Duty in partial display mode
1/38 duty
0
0
1
1
0
1
0
1
1/25 duty
1/12 duty
Prohibited
With the setting of 1/12 duty, the level voltage (VLCn) for driving the liquid crystal panel may not reach the set value.
Thoroughly evaluate the relationship between the duty and driving voltage with the actual system.
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
0
D2
D1
0
D0
0
−
−
−
−
−
Data Sheet S15730EJ2V0DS
63
µPD16498
6.12 Display Memory Access Register (R11)
The display memory access register is used when accessing the display RAM. When this register is write-accessed, data
is written directly to the display RAM. When this register is read-accessed, data from the display RAM is first latched to this
register before being sent to the bus during the next read operation. Accordingly, one dummy read access is required after
display RAM access has been set.
When using reset connand to reset, the contents of memory are retained.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
6.13 Display Start Line Setting Register (R12)
Display start line set specifies the top line in the display.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
DSL6
DSL5
DSL4
DSL3
DSL2
DSL1
DSL0
Default settings (initial values set by reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
−
6.14 Blink X Address Register (R13)
The blink X address register specifies the X address of the blink data RAM accessed by the CPU. This address is
automatically incremented each time the blink data RAM is accessed.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
BXA3
BXA2
BXA1
BXA0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
−
−
−
−
Data Sheet S15730EJ2V0DS
64
µPD16498
6.15 Blink Start Line Address Register (R14)
The blink start line address register specifies the start line address of the display RAM accessed when the CPU uses blink
display mode. The range of blinking lines is determined based on the contents of this register and the blink end line
address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
−
BSL6
BSL5
BSL4
BSL3
BSL2
BSL1
BSL0
−
Default settings (initial values set by reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
−
6.16 Blink End Line Address Register (R15)
The blink end line address register specifies the end line address of the display RAM accessed when the CPU uses blink
display mode. The range of blinking lines is determined based on the contents of this register and the blink start line
address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
−
BEL6
BEL5
BEL4
BEL3
BEL2
BEL1
BEL0
−
Default settings (initial values set by reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
−
6.17 Blink Data Memory Access Register (R16)
The blink data memory access register is used to access the blink data RAM. When this register is write-accessed, data
is written directly to the blink data RAM.
When using reset connand to reset, the contents of memory are retained.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Data
Status
0
1
Normal
Blink
Default settings (initial values set by reset command, all data)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15730EJ2V0DS
65
µPD16498
6.18 Inverted X Address Register (R17)
The inverted X address register specifies the X address in the inverted data RAM accessed by the CPU. This address is
incremented each time the inversion RAM is accessed.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
IXA3
IXA2
IXA1
IXA0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
−
−
−
−
6.19 Inversion Start Line Address Register (R18)
The inversion start line address register specifies the start line address in the display RAM accessed by the CPU when
using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and
the inversion end line address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
ISL6
ISL5
ISL4
ISL3
ISL2
ISL1
ISL0
Default settings (initial values set by reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
−
6.20 Inversion End Line Address Register (R19)
The inversion end line address register specifies the end line address in the display RAM accessed by the CPU when
using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and
the inversion start line address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
−
IEL6
IEL5
IEL4
IEL3
IEL2
IEL1
IEL0
−
Default settings (initial values set by reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
−
Data Sheet S15730EJ2V0DS
66
µPD16498
6.21 Inverted Data Memory Access Register (R20)
The inverted data memory access register is used when accessing the inverted data RAM. When this register is
accessed, the data is written directly to the inverted data RAM.
When using reset connand to reset, the contents of memory are retained.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Setting
−
Data
Status
0
1
Normal
Inverted
Default settings (initial values set by reset command, all data)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.22 Partial Start Line Address Register (R21)
The partial start line address register specifies the start line address in the display RAM accessed by the CPU when using
partial display mode. The partial display area is determined as the number of lines specified in the partial display mode
setting register (R10), starting from this start line address.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
−
PSL6
PSL5
PSL4
PSL3
PSL2
PSL1
PSL0
−
Default settings (initial values set by reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
−
Data Sheet S15730EJ2V0DS
67
µPD16498
6.23 Gray Scale Data Registers 1 to 4 (R23 to R26)
The gray scale data registers specify the gray scale level when using normal four-level gray scale display mode. Use of
this register optimizes the gray scale display.
Rx
Data
0, 0
0, 1
1, 0
1, 1
RS
1
D7
−
D6
−
D5
D4
D3
D2
D1
D0
Setting
−
−
−
−
R23
R24
R25
R26
GD5
GD5
GD5
GD5
GD4
GD4
GD4
GD4
GD3
GD3
GD3
GD3
GD2
GD2
GD2
GD2
GD1
GD1
GD1
GD1
GD0
GD0
GD0
GD0
−
−
1
−
−
1
−
−
1
D7
D6
D5
0
D4
0
0
0
0
:
D3
0
D2
0
D1
0
D0
0
Gray scale level
Level 0
Level 1
Level 2
Level 3
:
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
Disable
Disable
Disable
Disable
0
1
1
0
1
0
1
0
1
0
1
0
Level 31
Level 32
Default settings (initial values set by reset command, for all gray scale data registers)
D7
D6
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
−
−
6.24 Partial Gray Scale Data Registers 1 to 4 (R27 to R30)
The partial gray scale data registers specify the gray scale level when using partial four-level gray scale display mode.
Use of this register optimizes the gray scale display.
Rx
Data
0, 0
0, 1
1, 0
1, 1
RS
1
D7
−
D6
−
D5
D4
D3
D2
D1
D0
Setting
R27
R28
R29
R30
PGD5
PGD5
PGD5
PGD5
PGD4
PGD4
PGD4
PGD4
PGD3
PGD3
PGD3
PGD3
PGD2
PGD2
PGD2
PGD2
PGD1
PGD1
PGD1
PGD1
PGD0
PGD0
PGD0
PGD0
−
−
−
−
1
−
−
1
−
−
1
−
−
D7
D6
D5
0
D4
0
0
0
0
:
D3
0
D2
0
D1
0
D0
0
Gray scale level
Level 0
Level 1
Level 2
Level 3
:
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
Disable
Disable
Disable
Disable
0
1
1
0
1
0
1
0
1
0
1
0
Level 31
Level 32
Default settings (initial values set by reset command, for all partial gray scale data registers)
D7
D6
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
−
−
Data Sheet S15730EJ2V0DS
68
µPD16498
6.25 Power System Control Register 1 (R32)
This command sets the µPD16498's power system mode.
E
/RD
1
R,/W
/WR
0
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
HPM1
HPM0
−
TCS2
TCS1
OP2
OP1
OP0
Flag
Function
HPM1, HPM0
TCS1, TCS0
OP2 to OP0
These flags set the driver mode as shown in Table 6-9.
These flags set the value for selecting the VREG voltage's temperature curve, as shown in Table 6-10.
These flags control the booster's ON/OFF status, the voltage regulator (V regulator) and voltage follower (V/F).
The functions controlled via these three bits by the power control setting command are listed in Table 6-11.
Table 6-9. Driver Mode Setting
HPM1
HPM0
Mode Setting
Normal mode
0
0
1
1
0
1
0
1
Low-power mode
High-power mode
Power activation mode
Table 6-10. Selection VREG Voltage's Temperature Curve Value
TCS1
TCS0 Temperature gradient (%/°C)
VREG (TYP.) (V)
0
0
1
1
0
1
0
1
−0.06
−0.08
−0.09
−0.12
1.04
0.98
0.93
0.85
Table 6-11. Detailed Description of Functions Controlled by Flags of Power System Control 1
Status
Item
1
0
OP2
OP1
OP0
Booster control flag
ON
ON
ON
OFF
OFF
OFF
V regulator control flag
Voltage follower control flag
Default settings (initial values set by reset command)
D7
0
D6
0
D5
D4
0
D3
0
D2
1
D1
1
D0
1
−
Data Sheet S15730EJ2V0DS
69
µPD16498
6.26 Power System Control Register 2 (R33)
This command is used to control the on-chip register for VLCD voltage regualation.
E
/RD
1
R,/W
/WR
0
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
−
VRR2
VRR1
VRR0
−
PVR2
PVR1
PVR0
−
Flag
Function
VRR2 to VRR0
When using normal display mode, power system control 2 (VLCD regulator resistance factor setting command) can
be used to change the resistance factor at 8 levels. The three flags in power system control 2 set the values shown
in Table 6-12 as reference values for (1 + Rb/Ra).
PVR2 to PVR0
When using partial display mode, power system control 2 (VLCD regulator resistance factor setting command) can
be used to change the resistance factor at 8 levels. The three flags in power system control 2 set the values shown
in Table 6-12 as reference values for (1 + Rb/Ra).
Table 6-12. Reference Values for VLCD Internal Resistance Factor Regulator Register
Register
VRR2
PVR2
VRR1
PVR1
VRR0
PVR0
1+Rb/Ra
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5
8
12
13
16
19
21
24
Default settings (initial values set by reset command)
D7
D6
0
D5
0
D4
0
D3
D2
0
D1
0
D0
−
−
0
Data Sheet S15730EJ2V0DS
70
µPD16498
6.27 Power System Control Register 3 (R34)
This command sets the power system mode, including the bias setting for the µPD16498's normal display mode and the
number of boost levels for partial display mode.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
BIS2
BIS1
BIS0
FBS2
FBS1
FBS0
BST1
BST0
−
Flag
BIS2 to BIS0Note
Function
These three flags select the bias ratio as shown below.
BIS2
BIS1
BIS0
Bias ratio
1/12 bias
1/11 bias
1/10 bias
1/9 bias
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/8 bias
1/7 bias
Prohibited
Prohibited
When partial display mode is set, the bias ratio set by the partial mode setting is automatically selected.
FBS2 to FBS0Note The number of boost levels in booster for normal display mode is selected as shown below.
FBS2
FBS1
FBS0
Boost level
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x4
x5
x6
x7
x8
x9
Prohibited
Prohibited
BST1, BST0
The number of boost levels in the booster for partial display mode is selected as shown below.
BST1
BST0
Boost level
0
0
1
1
0
1
0
1
x2
x3
x4
Prohibited
Note Be sure to execute the HALT command before changing these flag settings.
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Data Sheet S15730EJ2V0DS
71
µPD16498
6.28 Electronic Volume Register (R35)
The electronic volume register specifies the electronic volume value for adjusting the contrast when using normal display
mode. Any value among 256 steps can be selected.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
EV7
EV6
EV5
EV4
EV3
EV2
EV1
EV0
−
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.29 Partial Electronic Volume Register (R36)
The partial electronic volume register specifies the electronic volume value for adjusting the contrast when using partial
display mode. Any value among 256 steps can be selected.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
PEV7
PEV6
PEV5
PEV4
PEV3
PEV2
PEV1
PEV0
−
Default settings (initial values set by reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.30 Boost Adjustment Register (R37)
The voltage (range: 1/8 VDD2 to 7/8 VDD2) set to this register is applied to the boost level set for the booster.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
−
−
−
−
−
DDC2
DDC1
DDC0
−
Table 6-13. Boost Adjustment Register (R37) Settings
DDC2
DDC1
DDC0
Boost Adjustment Voltage
Regulator Circuit Stopped
1/8 VDD2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2/8 VDD2
3/8 VDD2
4/8 VDD2
5/8 VDD2
6/8 VDD2
7/8 VDD2
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
0
D1
0
D0
0
−
−
−
−
−
Data Sheet S15730EJ2V0DS
72
µPD16498
6.31 Static Icon Address Register (R40)
The static icon address specifies the address in the static icon data RAM accessed by the CPU.
This address is automatically incremented each time the static icon data RAM is accessed.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
SIA2
SIA1
SIA0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
0
D1
0
D0
0
−
−
−
−
−
6.32 Static Icon Memory Access Register (R41)
The static icon memory access register is used when accessing the static icon data RAM. When this register is write-
accessed, the data is written directly to the static icon data RAM.
When using reset command to reset, the contents of this register are retained.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
6.33 Static Icon Contrast Register (R42)
The static icon contrast adjusts the contrast of static icons using phase modulation.
The pulse width of the ON signal that is output in static drive mode is divided into 32 levels (1/32 to 32/32 pulse width) and
the dot output's timing changes during output according to the phase modulation ratio recorded in bits ICS4 to ICS0 of the
static icon contrast (R42), as is shown in Table 6-14.
RS
1
D7
D6
D5
D4
0
D3
D2
D1
D0
−
−
−
ICS3
ICS2
ICS1
ICS0
Table 6-14. Static Icon Contrast Register (R42) Setting
ICS4
ICS3
ICS2
ICS1
ICS0
Phase Modulation Ratio
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
1
1
0
1
0
1
0/32
1/32
2/32
3/32
:
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
29/32
30/32
31/32
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
0
D2
0
D1
D0
−
−
−
−
0
0
Data Sheet S15730EJ2V0DS
73
µPD16498
6.34 RAM Test Mode Setting Register (R44)
The RAM test mode setting register directly writes the data for each type of display mode to the display RAM, as shown in
Table 6-15.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
RTS3
RTS2
RTS1
RTS0
Table 6-15. RAM Test Mode Setting Register (R44) Setting
RTS3
RTS2
RTS1
RTS0
Write Data
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Normal operation
Displays list of gray scales
all 00/pixel
all 11/pixel
Checker pattern: 00/11
Checker pattern: 11/00
Checker pattern: 01/10
Checker pattern: 10/01
Vertical striped pattern: 00/11
Horizontal striped pattern: 00/11
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
−
−
−
−
6.35 Signature Read Register (R45)
This commnad is used to read the IC signature set via the SIGIN1 and SIGIN2 pins. This is a read-only register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
SIGIN2
SIGIN1
Default settings (initial values set by reset command)
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
−
−
−
−
Data Sheet S15730EJ2V0DS
74
µPD16498
7. LIST OF µPD16498 REGISTERS
Index Register
Data Bits
Register Name
R/W
W
CS RS
1
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IR5
IR4
IR3
IR2
IR1
IR0
IR
Index Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Control register 1
R/W RMW DISP STBY BLD IVD HALT ADC COMR
R/W FDM IBL IDIS DSEL BWW GRAY DTY INC
R0
R1
R2
R3
R4
R5
R6
Control register 2
Reset command
X address register
CRES
XA4 XA3 XA2 XA1 XA0
W
R/W
R/W
R/W
R/W
W
W
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
YA6 YA5 YA4 YA3 YA2 YA1 YA0
DT6 DT5 DT4 DT3 DT2 DT1 DT0
NID6 NID5 NID4 NID3 NID2 NID1 NID0
MSD6 MSD5 MSD4 MSD3 MSD2 MSD1 MSD0
PID4 PID3 PID2 PID1 PID0
Y address register
Duty setting register
AC driver inversion cycle register
AC driver inversion position shift register
Partial AC driver inversion cycle register
R7
R8
R9
PSD4 PSD3 PSD2 PSD1 PSD0
Partial AC driver inversion potision shift register
Partial display mode setting register
PBIS
PDT1 PDT0
R10
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
R11 Display memory access register
Display start line setting register
Blink X address register
DSL6 DSL5 DSL4 DSL3 DSL2 DSL1 DSL0
BXA3 BXA2 BXA1 BXA0
BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0
BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0
R12
R13
R14 Blink start line address register
R15
R16 Blink data memory access register
Blink end line address register
D
D
7
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
IXA3 IXA2 IXA1 IXA0
ISL6 ISL5 ISL4 ISL3 ISL2 ISL1 ISL0
IEL6 IEL5 IEL4 IEL3 IEL2 IEL1 IEL0
Inverted X address register
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
Inversion start line address register
Inversion end line address register
Inverted data memory access register
Partial start line address register
D
6
D
5
D
4
D
3
D
2
D
1
D0
PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0
Gray scale data register 1 (0, 0)
Gray scale data register 2 (0, 1)
Gray scale data register 3 (1, 0)
W
W
W
W
W
W
W
W
GD5 GD4 GD3 GD2 GD1 GD0
GD5 GD4 GD3 GD2 GD1 GD0
GD5 GD4 GD3 GD2 GD1 GD0
GD5 GD4 GD3 GD2 GD1 GD0
PGD5 PGD4 PGD3 PGD2 PGD1 PGD0
PGD5 PGD4 PGD3 PGD2 PGD1 PGD0
PGD5 PGD4 PGD3 PGD2 PGD1 PGD0
PGD5 PGD4 PGD3 PGD2 PGD1 PGD0
Gray scale data register 4 (1, 1)
Patial gray scale data register 1 (0, 0)
Patial gray scale data register 2 (0, 1)
Patial gray scale data register 3 (1, 0)
Patial gray scale data register 4 (1, 1)
R28
R29
R30
R31
R32
R33
R34
Power system control register 1
Power system control register 2
Power system control register 3
W
W
W
W
W
W
HPM1 HPM0
TCS1 TSC0 OP2 OP1 OP0
PVR2 PVR1 PVR0
BIS2 BIS1 BIS0 FBS2 FBS1 FBS0 BST1 BST0
EV7 EV6 EV5 EV4 EV3 EV2 EV1 EV0
PEV7 PEV6 PEV5 PEV4 PEV3 PEV2 PEV1 PEV0
DDC2 DDC1 DDC0
VRR2 VRR1 VRR0
R35 Electronic volume register
Partial electronic volume register
R36
R37 Boost adjustment register
R38
R39
R40 Static icon address register
W
R/W
W
SIA2 SIA1 SIA0
Static icon memory access register
R41
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
Static icon contrast register
ICS4 ICS3 ICS2 ICS1 ICS0
R42
R43
W
R
RTS3 RTS2 RTS1 RTS0
SIG2 SIG1
R44 RAM test mode setting register
R45
Signature read register
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
Remark
: Not to use these registers.
Data Sheet S15730EJ2V0DS
75
µPD16498
8. POWER SUPPLY SEQUENCE
The µPD16498 includes power supply circuitry, such as a booster and a voltage follower. When a reset is performed using
the /RES pin, the reset function is restricted so as to prevent operation faults that may occur due to noise effects, etc.
When electric charge remains in the smoothing capacitor that is connected between the VSS pin and the voltage pins
related to the LCD driver (VLCD, VLC1 to VLC4), troubles such as a brief all-black display screen may occur when the power is
switched ON or OFF. The following power-on sequence is recommended as a means to avoid such troubles when
switching the power ON or OFF.
8.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON → Display ON)
Turn power ON when /RES pin = L
↓
Power supply stabilization
↓
/RES pin = H
↓
Wait at least 50 µs before command input
Command reset
R2
R0
Register reset
↓
Control register 1
DISP = 0, HALT = 1
↓
Display OFF, internal operations stopped
IC functions set via command input
• Control register 1
(DISP = 0, HALT = 1 status is retained)
• Control register 2
• Power control register 1
(HPM1, HPM0 = 1, 1)
Specification of power activation mode
• Power control registers 2, 3
• Electronic volume register
• Partial electronic volume register
• Boost adjustment register
↓
User-specified settings via command input
Function settings for gray scale data, etc.
↓
Initialization complete
↓
Control register 1
DISP = 0, HALT = 0
↓
Display OFF, internal operations started
R0
LCD display screen settings
• Display start line setting register
• Write screen data, etc. + wait time
↓
After internal operations are started, wait at least 400 ms
before turning on the LCD display.Note
Power system control register 1
(Mode except HPM1, HPM0 (1, 1))
↓
Cancels V/F mode for power activation
Control register 1
DISP = 1, HALT = 0
Display ON, internal operation start mode
R0
Note This 400ms wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the
actual device (refer to 8.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF)).
Data Sheet S15730EJ2V0DS
76
µPD16498
8.2 Power OFF Sequence (When Using On-Chip Power Supply)
Operation mode
↓
Display OFF, internal operation start mode
DISP = 0, HALT = 0
R0
↓
Sets high power mode
HPM1 = 1, HPM0 = 0
R32
↓
[EV7, EV6, EV5, EV4, EV3, EV2, EV1, EV0]
= [0, 0, 0, 0, 0, 0, 0, 0]
Set electronic volume register
R35
R36
↓
[PEV7, PEV6, PEV5, PEV4, PEV3, PEV2, PEV1, PEV0]
= [0, 0, 0, 0, 0, 0, 0, 0]
Set partial electronic volume register
Wait at least 1200ms before power OFF.Note
↓
Power supply OFF
Note This 1200ms wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. NEC recommends determining the wait time after making a thorough evaluation of the
actual device (refer to 8.5 VOUT, VLCD Voltage Sequence (power ON → power OFF)).
8.3 Power ON Sequence (When Using External Driver Power Supply, Power ON → Display ON)
Logic power ON when /RES pin = L
VDD1, VDD2 power ON, VOUT = Hi-Z
↓
Power supply stabilization
↓
/RES pin = H
↓
Wait at least 50 µs before command input
Command reset
R2
R0
Register reset
↓
Display OFF, internal operations stopped
DISP = 0, HALT = 1
↓
Initialization via command input (user-specified)
Selection of IC functions, etc.
Power system control register 1 (R32) :
[OP2, OP1, OP0] = [0 ,0 ,X]
↓
DISP = 0, HALT = 0
R0
R0
Display OFF, internal operations started
↓
VOUT power supply ON
External LCD driver power supply ON
↓
Stabilization of external LCD driver power supply
↓
Display ON, internal operations started
DISP = 1, HALT = 0
Data Sheet S15730EJ2V0DS
77
µPD16498
8.4 Power Supply OFF Sequence (When Using External Driver Power Supply)
Operation mode
↓
DISP = 0, HALT = 0
Display OFF, internal operation start mode
VOUT = Hi-Z
R0
R0
↓
External driver power supply OFF
↓
DISP = 0, HALT = 1
↓
Display OFF, internal operations stopped
VDD1, VDD2, power supply OFF
Logic power supply OFF
Data Sheet S15730EJ2V0DS
78
µPD16498
8.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF)
0 VDD
V
OUT
/RES pin = 0
Power ON
/RES pin = 1
DISP = 0, HALT = 1
Default settings
HPM = 3
HALT = 0
400 ms
Select HPM = 0 to 2
DISP = 1
Normal display
DISP = 0
HPM = 2
DTY = 1
700 ms
LCD = 15V 6V
V
Select HPM = 0 to 2
DISP = 1
Partial display
DISP = 0
HPM = 3
DTY = 0
400 ms
Select HPM = 0 to 2
DISP = 1
Normal display
DISP = 0
HPM = 2
EV = 0
1200 ms
Power OFF
Dotted line: VOUT
Solid line: VLCD
Conditions:
VDD: VDD1 = VDD2 = 3.0 V
Boost levels: x6 (in normal display mode), x3 (in partial display mode)
Capacitors: VLCn pin to Cn+/− pin = 1 µF,
AMPOUT pin, AMPOUTP pin, VRS pin = 0.1µF
Caution Connect a capacitor of less than 0.1µF to both AMPOUT and AMPOUTP pins.
Data Sheet S15730EJ2V0DS
79
µPD16498
9. USE OF RAM TEST MODE
The µPD16498 has a test mode for writing nine types of screen data to display RAM. When using the test mode, be sure
to execute via the sequence shown below. If executing the test mode by some other sequence,
troubles may appear in the screen display.
Operation mode
↓
Control register 1
Display OFF, set to standby
Select RAM write data
R0
DISP = 0, STBY = 1
↓
Set RAM test mode
R44
R0
↓
Control register 1
Display OFF, cancel standby
DISP = 0, STBY = 0
↓
After internal operations are started, wait at least 1sec
before turning on the LCD display.Note
Wait time
↓
Control register 1
Display ON
R0
DISP = 1
↓
Settings complete
Note
This 1sec wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the
actual device.
Data Sheet S15730EJ2V0DS
80
µPD16498
10. USE OF STANDBY/HALT MODE
The µPD16498 has a standby mode for reducing current consumption, and a HALT mode for switching display mode.
Electrical circuits as a DC/DC converter are stopped in standby/HALT mode.
When using the standby/HALT mode, be sure to execute via the sequence shown below. If executing the test mode by
some other sequence, troubles may appear in the screen display.
Operation mode
↓
Control register 1
Display OFF
R0
R0
DISP = 0, STBY = 0, HALT = 0
↓
Control register 1
Display OFF, set to standby (HALT)
DISP = 0, STBY = 1(or HALT = 1)
↓
Standby mode
↓
Power control register 1
(HPM1, HPM0 = 1, 1)
R32
R0
Reverse sequence to normal operation
↓
Control register 1
Display OFF, cancel standby (HALT)
DISP = 0, STBY = 0(or HALT = 0)
↓
After internal operations are started, wait at least 400ms
before turning on the LCD display.Note
Wait time
↓
Power control register 1
Set except HPM1, HPM0 = 1,1 (power activation) mode
R32
(Set except HPM1, HPM0 =1, 1)
↓
Control register 1
Display ON, internal operation start mode
DISP = 1, HALT = 0
Note This 400 ms wait time varies according to the panel characteristics and the capacitance value of the
boost/smoothing capacitor. We recommends determining the wait time after making a thorough evaluation of
the actual device.
Data Sheet S15730EJ2V0DS
81
µPD16498
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C, VSS = 0 V)
Parameter
Logic system supply voltage
Booster supply voltage
Symbol
Ratings
Unit
V
VDD1
VDD2
VOUT
−0.3 to +4.0
−0.3 to +4.0
V
Driver supply voltage
−0.3 to +20.0
−0.3 to VOUT+0.3
−0.3 to VDD1+0.3
−0.3 to VDD1+0.3
−0.3 to VDD1+0.3
−0.3 to VOUT+0.3
−0.3 to VOUT+0.3
−40 to +85
V
Driver reference supply input voltage
Logic system input voltage
Logic system output voltage
Logic system input/output voltage
Driver system input voltage
Driver system output voltage
Operating ambient temperature
Storage temperature
VLCD, VLC1 to VLC4
V
VIN1
VOUT1
VI/O1
VIN2
VOUT2
TA
V
V
V
V
V
°C
°C
Tstg
−55 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure
that the absolute maximum ratings are not exceeded.
Recommended Operating Range
Parameter
Logic system supply voltage
Booster supply voltage
Symbol
MIN.
1.7
2.4
5.5
0
TYP.
MAX.
3.6
Unit
V
VDD1
VDD2
VOUT
VIN
Note1
Note2
3.6
V
Driver system supply voltage
Logic system input voltage
Driver system supply voltage
18.0
V
VDD1
V
Note2
VLCD, VLC1 to VLC4
0
VOUT
VOUT −0.5
V
Note3
Maximum setting for LCD driver voltage VLCD
V
Notes 1. VDD1 must be less than or equal to VDD2
2. This item is the recommended parameter when the LCD has an external driver.
3. This item is the recommended parameter when an on-chip power supply circuit drives the LCD.
Cautions 1. When using an external LCD driver, be sure to maintain these relations:
VSS < VLC4 < VLC3 < VLC2 < VLC1 < VLCD ≤ VOUT.
2. Maintain the relations shown in 8. POWER SUPPLY SEQUENCE when turning the power ON or OFF.
3. When using an external resister (when not using an on-chip resister for VLCD adjustment), maintain
supply of a voltage between 1.0 V and the VDD1 voltage to the VR and VRS pins.
Data Sheet S15730EJ2V0DS
82
µPD16498
Electrical Characteristics 1
(Unless Otherwise Specified, TA = −40 to +85°C, VDD1 = 1.7 to 3.6 V, VDD2 = 2.4 to 3.6 V)
Parameter
Symbol
VIH
Conditions
MIN.
TYP.Note1
MAX.
Unit
V
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
High-level leakage current
0.8 VDD1
VIL
0.2 VDD1
V
IIH1
IIL1
Except for P7 (SI), P6 (SCL) and P5 to P0
Except for P7 (SI), P6 (SCL) and P5 to P0
IOUT = −1 mA except OSCOUT
IOUT = 1 mA except OSCOUT
P7 (SI), P6 (SCL) and P5 to P0,
VIN/OUT = VDD1
1
µA
µA
V
−1
VOH
VOL
ILOH
VDD1 −0.5
0.5
10
V
µA
Low-level leakage current
ILOL
P7 (SI), P6 (SCL) and P5 to P0,
VIN/OUT = VSS
−10
4
µA
kΩ
kΩ
V
Common output ON resistance RCOM
Segment output ON resistance RSEG
Driver voltage (boost voltage) VOUT
VLCn → COMn, VOUT = 15 V, VLCD = 13 V,
1/10 bias, |IO| = 50 µA
VLCn → SEGn, VOUT = 15 V, VLCD = 13 V,
1/10 bias, |IO| = 50 µA
4
In x5 boost mode, VDD = 3.0 V,
Checker pattern display
13.8
16.6
In x6 boost mode, VDD = 3.0 V,
Checker pattern display
V
Note2
Reference voltage
VREG
VDD = 3.0 V, TA = 85°C, TSC1,TSC0 = 1,1
(temperature characteristic curves:−0.12%/°C)
VDD1 = 3.0 V, TA = 25°C, 1/38 duty,
in B/W mode, R = 750 kΩ
0.715
0.775
36
0.835
V
Note3
Oscillation frequency
fOSC
kHz
kHz
VDD1 = 3.0 V, TA = 25°C, 1/38 duty,
in B/W mode, R = 3 MΩ
10.6
Notes 1. TYP. values are reference values when TA = 25°C (except VREG).
2. The reference voltage values (VREG) when TA = 25°C are shown below:
MIN. = 0.770 V, TYP.= 0.845 V, MAX. = 0.920 V
3. The oscillation frequency fluctuates depending on the wiring capacitance to the external resistor for oscillation.
Data Sheet S15730EJ2V0DS
83
µPD16498
Electrical Characteristics 2
(Unless Otherwise Specified, TA = −40 to +85°C)
Parameter
Symbol
IDD11
Conditions
MIN.
TYP.Note
180
MAX.
290
Unit
Current consumption
(normal mode)
Frame frequency = 70 Hz,
µA
B/W all display OFF data output,
1/128 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 13 V
Frame frequency = 70 Hz,
250
300
380
135
210
95
390
460
560
220
320
140
160
µA
µA
µA
µA
µA
µA
µA
B/W checker pattern display data output,
1/128 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 13 V
Frame frequency = 70 Hz,
Current consumption
(high-power mode)
IDD12
IDD13
IDD21
B/W all display OFF data output,
1/128 duty, VDD1 = VDD2 =3.0 V,
in x5 boost mode, VLCD = 13 V
Frame frequency = 70 Hz,
B/W checker pattern display data output,
1/128 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 13 V
Frame frequency = 70 Hz,
Current consumption
(low-power mode)
B/W all display OFF data output,
1/128 duty, VDD1 = VDD2 =3.0 V,
in x5 boost mode, VLCD = 13 V
Frame frequency = 70 Hz,
B/W checker pattern display data output,
1/128 duty, VDD1 = VDD2 = 3.0 V,
in x5 boost mode, VLCD = 13 V
Frame frequency = 70 Hz,
Current consumption
(partial display mode)
B/W all display OFF data output,
1/38 duty, VDD1 = VDD2 =3.0 V,
in x3 boost mode, VLCD = 7.0 V, normal mode
Frame frequency = 70 Hz,
105
B/W checker pattern display data output,
1/38 duty, VDD1 = VDD2 = 3.0 V,
VLCD = 7.0 V, in x3 boost mode, normal mode
VDD1 = VDD2 = 3.0 V
Current consumption
(standby mode)
IDD22
10
35
µA
µA
Current consumption
(display icon)
Icon frame frequency = 125 Hz,
B/W all display OFF data output,
VDD1 = 3.0 V
18
IDD23
Note TYP. values are reference values when TA = 25°C.
Data Sheet S15730EJ2V0DS
84
µPD16498
Required Timing Conditions (Unless Otherwise Specified, TA = −30 to +85°C)
(1) i80 CPU interface
RS
t
AH8
t
AS8
t
f
t
r
/CS1
(CS2 = H)
t
CYC8
t
CCLW, tCCLR
/WR, /RD
t
CCHR, tCCHW
t
DS8
t
DH8
D0
to D
7
(Write)
t
OH8
t
ACC8
D0 to D7
(Read)
When VDD1 = 1.7 V to 2.0 V
Parameter
Address hold time
Address setup time
System cycle time
Symbol
tAH8
Conditions
MIN.
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
tAS8
0
tCYC8
1000
160
430
160
160
160
0
Control low-level pulse width (/WR) tCCLW
Control low-level pulse width (/RD) tCCLR
Control high-level pulse width (/WR) tCCHW
Control high-level pulse width (/RD) tCCHR
/WR
/RD
/WR
/RD
Data setup time
Data hold time
tDS8
tDH8
tACC8
tOH8
D0 to D7
D0 to D7
/RD access time
Output disable time
D0 to D7, CL = 100 pF
D0 to D7, CL = 5 pF, R = 3 kΩ
0
470
170
0
Note TYP. values are reference values when TA = 25°C.
Data Sheet S15730EJ2V0DS
85
µPD16498
When VDD1 = 2.0 to 2.5 V
Parameter
Symbol
tAH8
Conditions
MIN.
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
Address setup time
System cycle time
RS
RS
tAS8
0
tCYC8
600
120
240
120
120
120
0
Control low-level pulse width (/WR) tCCLW
Control low-level pulse width (/RD) tCCLR
Control high-level pulse width (/WR) tCCHW
Control high-level pulse width (/RD) tCCHR
/WR
/RD
/WR
/RD
Data setup time
Data hold time
tDS8
tDH8
tACC8
tOH8
D0 to D7
D0 to D7
/RD access time
Output disable time
D0 to D7, CL = 100 pF
0
280
170
D0 to D7, CL = 5 pF, R = 3 kΩ
0
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Address hold time
Symbol
tAH8
Conditions
MIN.
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
Address setup time
System cycle time
tAS8
0
tCYC8
250
60
120
60
60
60
0
Control low-level pulse width (/WR) tCCLW
Control low-level pulse width (/RD) tCCLR
Control high-level pulse width (/WR) tCCHW
Control high-level pulse width (/RD) tCCHR
/WR
/RD
/WR
/RD
Data setup time
Data hold time
tDS8
tDH8
tACC8
tOH8
D0 to D7
D0 to D7
/RD access time
Output disable time
D0 to D7, CL = 100 pF
0
140
70
D0 to D5, CL = 5 pF, R = 3 kΩ
0
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15730EJ2V0DS
86
µPD16498
(2) M68 CPU interface
RS
R,/W
t
AH6
t
AS6
t
f
tr
/CS1
(CS2 = H)
t
CYC6
t
EWHR, tEWHW
E
t
EWLR, tEWLW
t
DS6
t
DH6
D0
to D
7
(Write)
t
ACC6
t
OH6
D0 to D7
(Read)
When VDD1 = 1.7 to 2.0 V
Parameter
Address hold time
Address setup time
System cycle time
Data setup time
Symbol
tAH6
Conditions
MIN.
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
0
0
tAS6
tCYC6
tDS6
1000
160
0
D0 to D7
D0 to D7
Data hold time
tDH6
Access time
tACC6
tOH6
D0 to D7, CL = 100 pF
0
470
170
Output disable time
Enable high pulse width Read
Write
D0 to D7, CL = 5 pF, R = 3 kΩ
0
tEWHR
tEWHW
tEWLR
tEWLW
E
E
E
E
430
160
160
160
Enable low pulse width
Read
Write
Note TYP. values are reference values when TA = 25°C.
Data Sheet S15730EJ2V0DS
87
µPD16498
When VDD1 = 2.0 to 2.5 V
Parameter
Symbol
tAH6
Conditions
MIN.
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
Address setup time
System cycle time
Data setup time
RS
RS
tAS6
0
tCYC6
tDS6
600
120
0
D0 to D7
D0 to D7
Data hold time
tDH6
Access time
tACC6
tOH6
D0 to D7, CL = 100 pF
0
280
170
Output disable time
Enable high pulse width Read
Write
D0 to D7, CL = 5 pF, R = 3 kΩ
0
tEWHR
tEWHW
tEWLR
tEWLW
E
E
E
E
240
120
120
120
Enable low pulse width
Read
Write
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Address hold time
Symbol
tAH6
Conditions
MIN.
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
Address setup time
System cycle time
Data setup time
Data hold time
tAS6
0
tCYC6
tDS6
250
60
0
D0 to D7
D0 to D7
tDH6
Access time
tACC6
tOH6
D0 to D7, CL = 100 pF
0
140
70
Output disable time
Enable high pulse width Read
Write
D0 to D7, CL = 5 pF, R = 3 kΩ
0
tEWHR
tEWHW
tEWLR
tEWLW
E
E
E
E
120
60
60
60
Enable low pulse width
Read
Write
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signals (tr and tf) are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) ≤ (tCYC6 − tEWLW − tEWHW) or (tr + tf) ≤ (tCYC6 − tEWLR −
tEWHR).
2. All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15730EJ2V0DS
88
µPD16498
(3) Serial interface
t
CSS
t
CSH
/CS1
(CS2 = H)
t
SAS
t
SAH
RS
t
SCYC
t
SLW
SCL
t
f
t
SHW
t
r
t
SDS
tSDH
SI
When VDD1 = 1.7 to 2.5 V
Parameter
Serial clock cycle
Symbol
tSCYC
Conditions
MIN.
250
100
100
150
150
100
100
150
150
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL
SCL
SCL
RS
RS
SI
SCL high-level pulse width
SCL low-level pulse width
Address hold time
Address setup time
Data setup time
tSHW
tSLW
tSAH
tSAS
tSDS
tSDH
tCSS
tCSH
Data hold time
SI
CS-SCL time
CS
CS
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
TYP.Note
Parameter
Serial clock cycle
Symbol
tSCYC
Conditions
MIN.
150
60
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL
SCL
SCL
RS
RS
SI
SCL high-level pulse width
SCL low-level pulse width
Address hold time
Address setup time
Data setup time
tSHW
tSLW
tSAH
tSAS
tSDS
tSDH
tCSS
tCSH
60
90
90
60
Data hold time
SI
60
CS-SCL time
CS
CS
90
90
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15730EJ2V0DS
89
µPD16498
(4) Common
Parameter
Symbol
fN
Conditions
MIN.
TYP.Note
36
MAX.
150
Unit
kHz
Clock input 1
When using OSCIN1, external clock, and
on-chip divider, 1/128 duty, B/W mode
When using OSCIN1, external clock, and
on-chip divider, 1/128 duty,
72
150
kHz
four-level gray scale mode
Clock input 2
fP
When using OSCIN2, external clock for
partial display mode, but not using on-chip
divider, B/W mode
10.6
21.3
50
50
kHz
kHz
When using OSCIN2, external clock for
partial display mode, but not using on-chip
divider, four-level gray scale mode
Note TYP. values are reference values when frame frequency = 70 Hz.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% or 80% of VDD1.
Reset timing
t
RW
/RES
t
R
Internal
status
During reset
Reset complete
When VDD1 = 1.7 to 2.5 V
Parameter
Reset time
Symbol
tR
tRW
Conditions
MIN.
50
TYP.Note
MAX.
50
Unit
µs
Reset low pulse width
/RES
µs
Note TYP. values are reference values when TA = 25°C.
When VDD1 = 2.5 to 3.6 V
Parameter
Reset time
Reset low pulse width
Symbol
tR
tRW
Conditions
MIN.
50
TYP.Note
MAX.
50
Unit
µs
/RES
µs
Note TYP. values are reference values when TA = 25°C.
Caution All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15730EJ2V0DS
90
µPD16498
12. CPU INTERFACE (REFERENCE EXAMPLE)
The µPD16498 can be connected to either an i80 series CPU or an M68 series CPU. Also, if a serial interface connection
is used, the number of signal lines can be reduced.
(1) M68 series CPU
VCC
VDD1
A0
RS
A1 to A15
VIMA
C86
/CS1
Decoder
P0 to P7
D0 to D7
CPU
E
E
R/W
R,/W
PSX
/RES
GND
/RES
VSS
/RESET
(2) i80 series CPU
V
CC
VDD1
A0
RS
A1 to A7
/IORQ
C86
/CS1
Decoder
P
0
to P
7
D0
to D
7
CPU
/RD
/RD
/WR
/WR
PSX
/RES
/RES
V
SS
GND
/RESET
Data Sheet S15730EJ2V0DS
91
µPD16498
(3) When using serial interface
V
CC
VDD1
A0
RS
C86
H or L
/CS1
Decoder
Open
A1 to A7
P
0
to P
5
CPU
Port1
SI(P )
7
/Port2
SCL(P
6)
PSX
/RES
/RES
V
SS
GND
/RESET
Data Sheet S15730EJ2V0DS
92
µPD16498
[MEMO]
Data Sheet S15730EJ2V0DS
93
µPD16498
[MEMO]
Data Sheet S15730EJ2V0DS
94
µPD16498
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15730EJ2V0DS
95
相关型号：
UPD16510AGR-8JG-E1-A
SPECIALTY INTERFACE CIRCUIT, PDSO20, 5.72 MM, LEAD FREE, PLASTIC, SSOP-20
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