UPD703003AGC(A)-33-XXX-8EU [NEC]
Microcontroller, 32-Bit, MROM, 33MHz, MOS, PQFP100, 14 X 14 MM, PLASTIC, QFP-100;
| 型号： | UPD703003AGC(A)-33-XXX-8EU |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 32-Bit, MROM, 33MHz, MOS, PQFP100, 14 X 14 MM, PLASTIC, QFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总43页 (文件大小：702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703003A,703004A,703025A,703003A(A),703025A(A)
V853
32-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703003A, 703004A, 703025A, 703003A(A), and 703025A(A) are members of the V850 Series of 32-bit
single-chip microcontrollers designed for real-time control operations. These microcontrollers provide on-chip
features including a 32-bit CPU core, ROM, RAM, an interrupt controller, a real-time pulse unit, a serial interface, an
A/D converter, a D/A converter, and PWM.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V853 Hardware User’s Manual:
U10913E
V850 Series Architecture User’s Manual: U10243E
FEATURES
•
•
Number of instructions: 74
•
•
•
Advanced internal interrupt controller
Minimum instruction execution time:
30 ns (@ 33 MHz operation)
Real-time pulse unit suitable for control operations
Powerful serial interface
•
•
•
General-purpose registers: 32 bits × 32 registers
Instruction set optimized for control applications
Internal memory
(With on-chip dedicated baud rate generator)
On-chip clock generator
•
•
•
•
•
10-bit resolution A/D converter: 8 channels
8-bit resolution D/A converter: 2 channels
8-/9-/10-/12-bit resolution PWM: 2 channels
Power saving functions
ROM: 256 KB (µPD703025A, 703025A(A))
128 KB (µPD703003A, 703003A(A))
96 KB (µPD703004A)
RAM: 8 KB (µPD703025A, 703025A(A))
4 KB (µPD703003A, 703004A, 703003A(A))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U13188EJ6V1DS00 (6th edition)
Date Published August 2005 N CP(K)
Printed in Japan
The mark
shows major revised points.
1998
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
ORDERING INFORMATION
Part Number
Package
Quality Grade
Standard
Standard
Standard
Standard
Standard
Special
µPD703003AGC-33-×××-8EU
µPD703003AGC-33-×××-8EU-A
µPD703004AGC-33-×××-8EU
µPD703025AGC-33-×××-8EU
µPD703025AGC-33-×××-8EU-A
µPD703003AGC(A)-33-×××-8EU
µPD703025AGC(A)-33-×××-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
Special
Remarks 1. ××× indicates ROM code suffix.
2. Products with -A at the end of the part number are lead-free products.
The µPD703003A, 703025A and µPD703003A(A), 703025A(A) differ in the quality grade only.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC
Electronics Corporation to know the specification of the quality grade on the devices and its recommended
applications.
APPLICATIONS
µPD703003A, 703004A, 703025A: Camcorders, VCRs, PPCs, LBPs, printers, motor controllers, NC machine
tools, mobile telephones, etc.
µPD703003A(A), 703025A(A):
Medical equipment, automotive appliances, etc.
2
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
PIN CONFIGURATION
•
100-pin plastic LQFP (fine pitch) (14 × 14)
µPD703003AGC-33-×××-8EU
µPD703003AGC-33-×××-8EU-A
µPD703004AGC-33-×××-8EU
µPD703025AGC-33-×××-8EU
µPD703025AGC-33-×××-8EU-A
µPD703003AGC(A)-33-×××-8EU
µPD703025AGC(A)-33-×××-8EU
P31/TO131
P32/TCLR13
P33/TI13
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P75/ANI5
2
P74/ANI4
3
P73/ANI3
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
P37/INTP133/SCK3
P63/A19
4
P72/ANI2
5
P71/ANI1
6
P70/ANI0
7
ANO0
8
ANO1
P62/A18
9
AVREF2
P61/A17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AVREF3
P60/A16
P07/INTP113/ADTRG
P06/INTP112
P05/INTP111
P04/INTP110
P03/TI11
VSS
VDD
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P02/TCLR11
P01/TO111
P00/TO110
P117/INTP143
P116/INTP142
P115/INTP141
P114/INTP140
P113/TI14
P50/AD8
P47/AD7
P46/AD6
P45/AD5
P112/TCLR14
P111/TO141
P44/AD4
Caution Connect the IC (Internally Connected) pin directly to VSS.
Data Sheet U13188EJ6V1DS
3
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
PIN NAMES
A16 to A19:
AD0 to AD15:
ADTRG:
Address bus
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P63:
P70 to P77:
P90 to P96:
P110 to P117:
PWM0, PWM1:
RESET:
Port 3
Address/data bus
A/D trigger input
Analog input
Port 4
Port 5
ANI0 to ANI7:
ANO0, ANO1:
ASTB:
Port 6
Analog output
Port 7
Address strobe
Port 9
AVDD:
Analog power supply
Analog reference voltage
Analog ground
Port 11
AVREF1 to AVREF3:
AVSS:
Pulse width modulation
Reset
CVDD:
Power supply for clock generator
Ground for clock generator
Clock select
R/W:
Read/write status
Receive data
Serial clock
Serial input
Serial output
CVSS:
RXD0, RXD1:
SCK0 to SCK3:
SI0 to SI3:
CKSEL:
CLKOUT:
Clock output
DSTB:
Data strobe
SO0 to SO3:
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141:
HLDAK:
Hold acknowledge
Hold request
HLDRQ:
IC:
Internally connected
INTP110 to INTP113,
INTP120 to INTP123,
INTP130 to INTP133,
Timer output
TCLR11 to TCLR14: Timer clear
TI11 to TI14:
TXD0, TXD1:
UBEN:
Timer input
Transmit data
Upper byte enable
Wait
INTP140 to INTP143: Interrupt request from peripherals
LBEN:
Lower byte enable
MODE:
Mode
WAIT:
NMI:
Non-maskable interrupt request
X1, X2:
VDD:
Crystal
P00 to P07:
P10 to P17:
P20 to P27:
Port 0
Port 1
Port 2
Power supply
Ground
VSS:
4
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
INTERNAL BLOCK DIAGRAM
Mask ROM
CPU
ASTB
DSTB
R/W
UBEN
LBEN
WAIT
A16 to A19
AD0 to AD15
NMI
Instruction
queue
PC
INTC
RPU
INTP110 to INTP113
INTP120 to INTP123
INTP130 to INTP133
INTP140 to INTP143
Note 1
32-bit
barrel shifter
Multiplier
16 × 16 → 32
BCU
System
registers
TO110, TO111
TO120, TO121
TO130, TO131
TO140, TO141
HLDRQ
HLDAK
RAM
General-
purpose
registers
ALU
TCLR11 to TCLR14
TI11 to TI14
32 bits × 32
Note 2
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
BRG0
UART1/CSI1
BRG1
SO1/TXD1
SI1/RXD1
SCK1
CKSEL
CLKOUT
X1
Port
A/D
D/A
CG
converter converter
X2
SO2
SI2
SCK2
MODE
RESET
CSI2
BRG2
V
DD
SS
V
SO3
SI3
SCK3
CVDD
CVSS
CSI3
PWM0, PWM1
PWM
Notes 1. µPD703003A, 703003A(A):
µPD703004A:
128 KB
96 KB
µPD703025A, 703025A(A):
256 KB
2. µPD703003A, 703004A, 703003A (A): 4 KB
µPD703025A, 703025A(A): 8 KB
Data Sheet U13188EJ6V1DS
5
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
CONTENTS
1. DIFFERENCES BETWEEN PRODUCTS ........................................................................................
2. PIN FUNCTIONS..............................................................................................................................
7
8
8
2.1
2.2
2.3
Port Pins ................................................................................................................................................
Non-Port Pins ........................................................................................................................................ 10
Pin I/O Circuits and Recommended Connection of Unused Pins .................................................... 12
3. ELECTRICAL SPECIFICATIONS.................................................................................................... 15
4. PACKAGE DRAWING ..................................................................................................................... 36
5. RECOMMENDED SOLDERING CONDITIONS............................................................................... 37
APPENDIX NOTES ON TARGET SYSTEM DESIGN........................................................................... 39
6
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
1. DIFFERENCES BETWEEN PRODUCTS
Item
µPD703003A µPD703004A µPD703025A µPD703003A(A)µPD703025A(A) µPD70F3003A µPD70F3025A µPD70F3003A(A)
Internal ROM
Mask ROM
128 KB
4 KB
Flash memory
96 KB
256 KB
8 KB
128 KB
4 KB
256 KB
8 KB
128 KB
4 KB
256 KB
8 KB
128 KB
4 KB
Internal RAM
Flash memory
None
Provided
programming mode
VPP pin
None
Provided
Standard
Quality grade
Standard
Special
Special
Electrical specifications Current consumption, etc. differs. (Refer to each product data sheets.)
Others Noise immunity and noise radiation differ because circuit scale and mask layout differ.
Caution There are differences in noise immunity and noise radiation between the flash memory version and
mask ROM version. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation for
commercial samples (not engineering samples) of the mask ROM version.
Data Sheet U13188EJ6V1DS
7
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name
P00
I/O
I/O
Function
Alternate Function
TO110
Port 0
8-bit I/O port
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40 to P47
TO111
Input/output can be specified in 1-bit units.
TCLR11
TI11
INTP110
INTP111
INTP112
INTP113/ADTRG
TO120
I/O
I/O
I/O
Port 1
8-bit I/O port
TO121
Input/output can be specified in 1-bit units.
TCLR12
TI12
INTP120
INTP121/SO2
INTP122/SI2
INTP123/SCK2
PWM0
Port 2
8-bit I/O port
PWM1
Input/output can be specified in 1-bit units.
TXD0/SO0
RXD0/SI0
SCK0
TXD1/SO1
RXD1/SI1
SCK1
Port 3
TO130
8-bit I/O port
TO131
Input/output can be specified in 1-bit units.
TCLR13
TI13
INTP130
INTP131/SO3
INTP132/SI3
INTP133/SCK3
AD0 to AD7
I/O
I/O
Port 4
8-bit I/O port
Input/output can be specified in 1-bit units.
P50 to P57
Port 5
AD8 to AD15
8-bit I/O port
Input/output can be specified in 1-bit units.
8
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(2/2)
Pin Name
I/O
I/O
Function
Alternate Function
A16 to A19
P60 to P63
Port 6
4-bit I/O port
Input/output can be specified in 1-bit units.
P70 to P77
Input
I/O
Port 7
ANI0 to ANI7
8-bit input port
P90
Port 9
LBEN
7-bit I/O port
P91
UBEN
Input/output can be specified in 1-bit units.
P92
R/W
P93
DSTB
P94
ASTB
P95
HLDAK
HLDRQ
TO140
TO141
TCLR14
TI14
P96
P110
P111
P112
P113
P114
P115
P116
P117
I/O
Port 11
8-bit I/O port
Input/output can be specified in 1-bit units.
INTP140
INTP141
INTP142
INTP143
Data Sheet U13188EJ6V1DS
9
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
2.2 Non-Port Pins
(1/2)
Pin Name
TO110
I/O
Function
Alternate Function
P00
Output Pulse signal output from timers 11 to 14
TO111
TO120
TO121
TO130
TO131
TO140
TO141
TCLR11
TCLR12
TCLR13
TCLR14
TI11
P01
P10
P11
P30
P31
P110
P111
Input
Input
Input
Input
Input
Input
External clear signal input for timers 11 to 14
External count clock input for timers 11 to 14
P02
P12
P32
P112
P03
TI12
P13
TI13
P33
TI14
P113
INTP110
INTP111
INTP112
INTP113
INTP120
INTP121
INTP122
INTP123
INTP130
INTP131
INTP132
INTP133
INTP140
INTP141
INTP142
INTP143
SO0
External maskable interrupt request input, also used as external capture
trigger input for timer 11
P04
P05
P06
P07/ADTRG
P14
External maskable interrupt request input, also used as external capture
trigger input for timer 12
P15/SO2
P16/SI2
P17/SCK2
P34
External maskable interrupt request input, also used as external capture
trigger input for timer 13
P35/SO3
P36/SI3
P37/SCK3
P114
External maskable interrupt request input, also used as external capture
trigger input for timer 14
P115
P116
P117
Output Serial transmit data output for CSI0 to CSI3 (3-wire)
P22/TXD0
P25/TXD1
P15/INTP121
P35/INTP131
P23/RXD0
P26/RXD1
P16/INTP122
P36/INTP132
SO1
SO2
SO3
SI0
Input
Serial receive data input for CSI0 to CSI3 (3-wire)
SI1
SI2
SI3
10
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(2/2)
Pin Name
SCK0
I/O
I/O
Function
Alternate Function
Serial clock I/O for CSI0 to CSI3 (3-wire)
P24
SCK1
P27
SCK2
P17/INTP123
SCK3
P37/INTP133
TXD0
Output
Input
Serial transmit data output for UART0 and UART1
Serial receive data input for UART0 and UART1
P22/SO0
TXD1
P25/SO1
RXD0
P23/SI0
RXD1
P26/SI1
PWM0
PWM1
AD0 to AD7
AD8 to AD15
A16 to A19
LBEN
Output PWM pulse signal output
P20
P21
I/O
16-bit multiplexed address/data bus for external memory expansion
P40 to P47
P50 to P57
Output Higher address bus used for external memory expansion
Output External data bus’s lower byte enable signal output
External data bus’s higher byte enable signal output
P60 to P63
P90
UBEN
R/W
P91
Output
External read/write status output
External data strobe signal output
External address strobe signal output
Bus hold acknowledge output
Bus hold request input
P92
DSTB
P93
ASTB
P94
HLDAK
HLDRQ
ANI0 to ANI7
ANO0, ANO1
NMI
Output
Input
P95
P96
Input
Analog input to A/D converter
P70 to P77
Output Analog output from D/A converter
Input Non-maskable interrupt request input
Output System clock output
—
—
CLKOUT
CKSEL
WAIT
—
Input
Input
Input
Input
Input
—
Input for specifying clock generator’s operation mode
CVDD
Control signal input for inserting wait in bus cycle
Operation mode specification
—
MODE
RESET
X1
—
System reset input
—
Resonator connection for system clock. Input is via X1 when using an
external clock.
—
X2
—
ADTRG
AVREF1
AVREF2
AVREF3
AVDD
Input
Input
Input
A/D converter external trigger input
P07/INTP113
Reference voltage input for A/D converter
Reference voltage input for D/A converter
—
—
—
—
—
—
—
—
—
—
Positive power supply for A/D converter
Ground potential for A/D converter
Positive power supply for on-chip clock generator
Ground potential for on-chip clock generator
Positive power supply
—
AVSS
—
CVDD
CKSEL
—
CVSS
VDD
—
VSS
Ground potential
—
IC
Internally connected pin (Connect directly to VSS)
—
Data Sheet U13188EJ6V1DS
11
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. Figure 2-
1 illustrates the various circuit types using partially abridged diagrams.
It is recommended that 1 to 10 kΩ resistors be used when connecting to VDD or VSS via a resistor.
Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)
Pin Name
I/O Circuit Type
Recommended Connection of Unused Pins
P00/TO110, P01/TO111
5
8
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P02/TCLR11, P03/TI11,
P04/INTP110 to P07/INTP113/ADTRG
P10/TO120, P11/TO121
5
8
P12/TCLR12, P13/TI12
P14/INTP120
P15/INTP121/SO2
P16/INTP122/SI2
P17/INTP123/SCK2
P20/PWM0, P21/PWM1
P22/TXD0/SO0
5
P23/RXD0/SI0, P24/SCK0
P25/TXD1/SO1
8
5
8
5
8
P26/RXD1/SI1, P27/SCK1
P30/TO130, P31/TO131
P32/TCLR13, P33/TI13
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
P37/INTP133/SCK3
10-A
5
P40/AD0 to P47/AD7
P50/AD8 to P57/AD15
P60/A16 to P63/A19
P70/ANI0 to P77/ANI7
P90/LBEN
9
5
Connect directly to VSS.
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
P110/TO140, P111/TO141
P112/TCLR14, P113/TI14
8
P114/INTP140 to P117/INTP143
ANO0, ANO1
NMI
12
2
Leave open.
Connect directly to VSS.
12
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
Pin Name
I/O Circuit Type
Recommended Connection of Unused Pins
Leave open.
CLKOUT
WAIT
3
1
2
Connect directly to VDD.
MODE
—
RESET
CVDD/CKSEL
AVREF1 to AVREF3, AVSS
—
—
—
Connect directly to VSS.
Connect directly to VDD.
Connect directly to VSS.
AVDD
IC
Data Sheet U13188EJ6V1DS
13
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
Figure 2-1. Pin I/O Circuits
Type 1
Type 8
VDD
VDD
data
P-ch
N-ch
IN/OUT
P-ch
output
disable
IN
N-ch
Type 2
Type 9
P-ch
N-ch
Comparator
+
–
IN
IN
VREF (Threshold voltage)
input enable
Schmitt-triggered input with hysteresis characteristics
Type 3
Type10-A
VDD
VDD
pullup
enable
P-ch
VDD
P-ch
OUT
data
P-ch
IN/OUT
N-ch
open drain
N-ch
output disable
Type 5
Type 12
VDD
P-ch
data
IN/OUT
P-ch
N-ch
output
disable
Analog output voltage
OUT
N-ch
input
enable
14
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
–0.5 to +7.0
Unit
V
VDD pin
CVDD
CVSS
AVDD
AVSS
VI1
CVDD pin
CVSS pin
AVDD pin
AVSS pin
–0.5 to VDD + 0.3Note 1
V
–0.5 to +0.5
V
–0.5 to VDD + 0.3Note 1
–0.5 to +0.5
–0.5 to VDD + 0.3Note 1
–0.5 to VDD + 1.0Note 1
4.0
V
V
Input voltage
Note 2, VDD = 5.0 V 10%
X1 pin, VDD = 5.0 V 10%
Per pin
V
Clock input voltage
Output current, low
VK
V
IOL
mA
mA
mA
mA
V
Total for all pins
Per pin
100
Output current, high
IOH
–4.0
Total for all pins
VDD = 5.0 V 10%
P70/ANI0 to P77/ANI7
–100
Output voltage
VO
–0.5 to VDD + 0.3Note 1
–0.5 to VDD + 0.3Note 1
–0.5 to AVDD + 0.3Note 1
–0.5 to VDD + 0.3Note 1
–0.5 to AVDD + 0.3Note 1
–40 to +85
Analog input voltage
VIAN
AVDD > VDD
VDD ≥ AVDD
AVDD > VDD
VDD ≥ AVDD
V
V
Analog reference input voltage
AVREF
AVREF1 to AVREF3
V
V
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–65 to +150
Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
2. X1, P70 to P77, AVREF1 to AVREF3, and their alternate-function pins are excluded.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC
and GND. However, direct connections among open-drain and open-collector pins are
possible, as are direct connections to external circuits that have timing designed to prevent
output conflict with pins that become high-impedance.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Condition
MIN.
TYP. MAX.
Unit
pF
fC = 1 MHz
Unmeasured pins returned to 0 V.
15
15
15
I/O capacitance
CIO
pF
Output capacitance
CO
pF
Data Sheet U13188EJ6V1DS
15
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
Operating Conditions
Operation Mode
Internal System Clock Frequency (φ)
Operating Ambient
Temperature (TA)
Power Supply
Voltage (VDD)
Note 1
Direct mode, PLL mode
2 to 33 MHz
–40 to +85°C
–40 to +85°C
5.0 V 10%
5.0 V 10%
Note 2
5 to 33 MHz
Notes 1. When not using A/D converter
2. When using A/D converter
Recommended Oscillator
Caution For the resonator selection and oscillator constant of the µPD703003A(A) and 703025A(A),
customers are requested to apply to the resonator manufacturer for evaluation.
(1) Ceramic resonator connection (TA = –40 to +85°C)
(a) µPD703003A, 703004A
X1
X2
Rd
C2
C1
Manufacturer
Part Number
Oscillation
Frequency
fXX (MHz)
Recommended
Circuit Constant
Oscillation
Oscillation
Voltage Range
Stabilization Time
(MAX.) TOST (ms)
C1 (pF) C2 (pF)
On-chip On-chip
On-chip On-chip
On-chip On-chip
On-chip On-chip
On-chip On-chip
Rd (Ω) MIN. (V) MAX. (V)
Kyocera
Corporation
TDK
PBRC5.00B
5.0
6.6
5.0
5.0
6.6
5.0
5.0
6.6
6.6
680
—
—
—
—
—
—
—
—
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
0.14
0.08
0.19
0.16
0.17
0.32
0.32
0.72
0.72
PBRC6.60B
CCR5.0MC3
FCR5.0MC5
CCR6.6MC3
Murata Mfg.
Co., Ltd
CSA5.00MG040
CST5.00MGW040
CSA6.60MTZ040
CST6.60MTW040
100
On-chip On-chip
100 100
On-chip On-chip
100
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the µPD703003A or 703004A and the resonator.
16
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(b) µPD703025A
X1
X2
Rd
C2
C1
Manufacturer
Part Number
Oscillation
Frequency
fXX (MHz)
Recommended
Circuit Constant
Oscillation
Oscillation
Voltage Range
Stabilization Time
(MAX.) TOST (ms)
C1 (pF) C2 (pF)
On-chip On-chip
On-chip On-chip
On-chip On-chip
On-chip On-chip
Rd (Ω) MIN. (V) MAX. (V)
Kyocera
PBRC4.00HR
PBRC5.00HR
PBRC6.00HR
PBRC6.60HR
4.0
5.0
6.0
6.6
—
—
—
—
4.5
4.5
4.5
4.5
5.5
5.5
5.5
5.5
0.08
0.06
0.08
0.08
Corporation
TDK
CCR4.0MC3
CCR5.0MC3
4.0
5.0
On-chip On-chip
On-chip On-chip
—
—
4.5
4.5
5.5
5.5
0.22
0.28
Murata Mfg.
Co., Ltd
CSA4.00MG040
CST4.00MGW040
CSTS0400MG06
CSA6.60MTZ040
CST6.60MTW040
CSTS0660MG06
4.0
4.0
4.0
6.6
6.6
6.6
100
100
—
—
—
—
—
—
4.5
4.5
4.5
4.5
4.5
4.5
5.5
5.5
5.5
5.5
5.5
5.5
0.40
0.40
0.16
0.50
0.50
0.20
On-chip On-chip
On-chip On-chip
100
100
On-chip On-chip
On-chip On-chip
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the µPD703025A and the resonator.
(2) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Cautions 1. Put the high-speed CMOS inverter as close to the X1 pins as possible.
2.SufficientlyevaluatethematchingbetweentheµPD703003A,703004A,703025A,703003A(A),
or 703025A(A) and the high-speed CMOS inverter.
Data Sheet U13188EJ6V1DS
17
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V 10%, VSS = 0 V)
Parameter
Input voltage, high
Symbol
Conditions
MIN.
2.2
TYP.
MAX.
VDD + 0.3
VDD + 0.3
+0.8
Unit
V
VIH
Except for X1 and pins listed in Note1
Note 1
0.8VDD
–0.5
V
Input voltage, low
VIL
Except for X1 and pins listed in Note1
V
Note 1
–0.5
0.2VDD
VDD + 0.5
+0.6
V
Clock input voltage, high
Clock input voltage, low
VXH
VXL
X1
0.8VDD
–0.5
V
X1
V
+
Schmitt-triggered input
Threshold voltage
VT
Note 1, rising edge
Note 1, falling edge
Note 1
3.0
2.0
V
–
VT
V
+
–
Schmitt-triggered input hysteresis width VT – VT
0.5
V
Output voltage, high
VOH
IOH = –2.5 mA
IOH = –100 µA
IOL = 2.5 mA
VI = VDD
0.7VDD
V
VDD – 0.4
V
Output voltage, low
VOL
ILIH
ILIL
0.45
10
V
Input leakage current, high
Input leakage current, low
Output leakage current, high
Output leakage current, low
Software pull-up resistor
µA
µA
µA
µA
kΩ
VI = 0 V
–10
10
ILOH
ILOL
R
VO = VDD
VO = 0 V
–10
90
P35 to P37 and their
alternate-function pins
15
40
Power µPD703003A, When
IDD1
IDD2
IDD3
IDD4
IDD1
IDD2
IDD3
IDD4
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Note 2
1.9 × φ + 5 2.1 × φ + 17 mA
2.0 × φ + 7 2.2 × φ + 20 mA
1.2 × φ + 5 1.3 × φ + 13 mA
1.3 × φ + 7 1.4 × φ + 15 mA
8 × φ + 300 10 × φ + 500 µA
703004A,
operating
supply
current
703003A(A)
In
HALT mode
In
IDLE mode
0.1 × φ + 2 0.2 × φ + 3
mA
µA
µA
In
2
2
50
STOP mode
Note 3
200
µPD703025A, When
703025A(A) operating
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Note 2
2.5 × φ + 2 2.8 × φ + 16.5 mA
2.6 × φ + 4 2.9 × φ +19.5 mA
1.3 × φ + 5 1.4 × φ + 13 mA
1.3 × φ + 10 1.4 × φ + 18 mA
8 × φ + 300 10 × φ + 500 µA
In
HALT mode
In
IDLE mode
0.1 × φ + 2 0.2 × φ + 3
mA
µA
µA
In
2
2
50
STOP mode
Note 3
200
Notes 1. P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, and
their alternate-function pins.
2. –40°C ≤ TA ≤ +50°C
3. 50°C < TA ≤ 85°C
Remarks 1. TYP. values are reference values for when TA = 25°C (except for the conditions in Note 3) and VDD
= 5.0 V. The power supply current does not include AVREF1 to AVREF3 or the current that flows through
software pull-up resistors.
2. φ = Internal system clock frequency
18
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
Data Retention Characteristics (TA = –40 to +85°C, VDD = VDDDR)
Parameter
Data retention voltage
Data retention current
Symbol
VDDDR
IDDDR
Conditions
MIN.
1.5
TYP.
MAX.
5.5
Unit
V
STOP mode
Note 1
0.4VDDDR
0.4VDDDR
50
µA
µA
µs
Note 2
200
Power supply voltage rise time
Power supply voltage fall time
tRVD
tFVD
tHVD
200
200
0
µs
Power supply voltage hold time
(vs. STOP mode setting)
ms
STOP mode release signal input time tDREL
Data retention high-level input voltage
Note 3
Note 3
0
0.9VDDDR
0
ns
V
VIHDR
VDDDR
Data retention low-level input voltage VILDR
0.1VDDDR
V
Notes 1. –40°C ≤ TA ≤ +50°C
2. 50°C <TA ≤ 85°C
3. P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, X1, and
their alternate-function pins.
Remark TYP. values are reference values for when TA = 25°C (except for the conditions in Note 2) and VDD =
5.0 V.
STOP mode setting (fifth clock after PSC register is set)
VDD
VDD
VDD
VDDDR
tDREL
tHVD
tFVD
tRVD
RESET (input)
VIHDR
NMI (input)
(Released at falling edge)
VIHDR
NMI (input)
(Released at rising edge)
VILDR
Data Sheet U13188EJ6V1DS
19
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
AC Characteristics (TA = –40 to +85°C, VDD = 5.0 V 10%, VSS = 0 V)
AC test input test points
(a) P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, X1, and their
alternate-function pins
V
DD
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Test points
Test points
0 V
(b) Pins other than those listed in (a) above
2.4 V
2.2 V
2.2 V
0.8 V
0.8 V
0.4 V
AC test output test points
2.2 V
0.8 V
2.2 V
0.8 V
Load condition
DUT
(Device under testing)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert
a buffer or other element to reduce the device’s load capacitance to below 50 pF.
20
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(1) Clock timing
Parameter
X1 input cycle
Symbol
Conditions
Direct mode
MIN.
MAX.
Note 1
Note 3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
<1> tCYX
15
151Note 2
PLL mode (PLL locked)
Direct mode
PLL mode
X1 input high-level width
X1 input low-level width
X1 input rise time
<2> tWXH
<3> tWXL
<4> tXR
<5> tXF
6
60
6
Direct mode
PLL mode
60
Direct mode
PLL mode
7
10
X1 input fall time
Direct mode
PLL mode
7
10
CPU operating frequency
CLKOUT output cycle
—
φ
Note 4
30
33
<6> tCYK
<7> tWKH
<8> tWKL
<9> tKR
Note 5
CLKOUT input high-level width
CLKOUT input low-level width
CLKOUT input rise time
CLKOUT input fall time
0.5T – 5
0.5T – 5
5
5
<10> tKF
Delay time from X1↓ to CLKOUT <11> tDXK
Direct mode
3
17
Notes 1. When using A/D converter: 100 ns
When not using A/D converter: 250 ns
2. When using A/D converter: The value when φ = 5 × fXX and φ = fXX are set. Setting φ = 1/2 × fXX is
prohibited.
When not using A/D converter: The value when φ = 5 × fXX, φ = fXX, and φ = 1/2 × fXX are set.
3. When using A/D converter: 250 ns (when φ = 5 × fXX is set) and 200 ns (when φ = fXX is set). Setting
φ = 1/2 × fXX is prohibited.
When not using A/D converter: 250 ns (when φ = 5 × fXX, φ = fXX, and φ = 1/2 × fXX are set).
4. When using A/D converter: 5 MHz
When not using A/D converter: 2 MHz
5. When using A/D converter: 200 ns
When not using A/D converter: 500 ns
Remark T = tCYK
<1>
<2>
<3>
X1 (input)
<4>
<11>
<5>
<6>
<11>
<7>
<8>
CLKOUT (output)
<9>
<10>
Data Sheet U13188EJ6V1DS
21
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(2) Input waveform
(a) P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, and their
alternate-function pins
Parameter
Input rise time
Input fall time
Symbol
<12> tIR2
<13> tIF2
Conditions
MIN.
MIN.
MIN.
MAX.
20
Unit
ns
20
ns
V
DD
0.8VDD
0.8VDD
<12>
Input signal
0.2VDD
<13>
0.2VDD
0 V
(b) Pins other than those listed in (a) above
Parameter
Input rise time
Input fall time
Symbol
<14> tIR1
<15> tIF1
Conditions
MAX.
10
Unit
ns
10
ns
2.4 V
0.4 V
2.2 V
2.2 V
<14>
Input signal
0.8 V
<15>
0.8 V
(3) Output waveform (other than CLKOUT)
Parameter
Output rise time
Output fall time
Symbol
<16> tOR
<17> tOF
Conditions
MAX.
10
Unit
ns
10
ns
2.2 V
2.2 V
Output signal
0.8 V
0.8 V
<17>
<16>
22
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(4) Reset timing
Parameter
RESET high-level width
RESET low-level width
Symbol
<18> tWRSH
<19> tWRSL
Conditions
MIN.
500
MAX.
Unit
ns
When power supply is ON
and STOP mode has been
released
500 + TOST
ns
Other than when power
supply is ON and STOP
mode has been released
500
ns
Remark TOST: Oscillation stabilization time
<18>
<19>
RESET (input)
Data Sheet U13188EJ6V1DS
23
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(5) Read timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay time from CLKOUT↑ to address
<20> tDKA
3
Delay time from CLKOUT↑ to R/W, UBEN, LBEN <78> tDKA2
Delay time from CLKOUT↑ to address float <21> tFKA
Delay time from CLKOUT↓ to ASTB <22> tDKST
Delay time from CLKOUT↑ to DSTB <23> tDKD
Data input setup time (to CLKOUT↑) <24> tSIDK
Data input hold time (from CLKOUT↑) <25> tHKID
WAIT setup time (to CLKOUT↓) <26> tSWTK
WAIT hold time (from CLKOUT↓) <27> tHKWT
Address hold time (from CLKOUT↑) <28> tHKA
Address setup time (to ASTB↓) <29> tSAST
–2
+13
15
3
3
15
3
15
5
5
5
5
0
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
0.5T – 10
0.5T – 12
0.5T – 10
Address hold time (from ASTB↓) <30> tHSTA
Delay time from DSTB↓ to address float <31> tFDA
Data input setup time (to address) <32> tSAID
0
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
(2 + n)T – 22
(2 + n)T – 25
(1 + n)T – 20
(1 + n)T – 24
Data input setup time (to DSTB↓) <33> tSDID
Delay time from ASTB↓ to DSTB↓ <34> tDSTD
Data input hold time (from DSTB↑) <35> tHDID
Delay time from DSTB↑ to address output <36> tDDA
Delay time from DSTB↑ to ASTB↑ <37> tDDSTH
Delay time from DSTB↑ to ASTB↓ <38> tDDSTL
0.5T – 10
0
(1 + i)T
0.5T – 10
(1.5 + i)T – 10
(1 + n)T – 10
(1 + n)T – 13
T – 10
DSTB low-level width
<39> tWDL
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
ASTB high-level width
<40> tWSTH
<41> tSAWT1
WAIT setup time (to address)
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1
1.5T – 20
1.5T – 24
<42> tSAWT2
(1.5 + n)T – 20
(1.5 + n)T – 24
WAIT hold time (from address) <43> tHAWT1
<44> tHAWT2
(0.5 + n)T
(1.5 + n)T
n ≥ 1
WAIT setup time (to ASTB↓)
<45> tSSTWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1
T – 18
T – 20
<46> tSSTWT2
<47> tHSTWT1
<48> tHSTWT2
(1 + n)T – 15
WAIT hold time (from ASTB↓)
Remarks 1. T = tCYK
n ≥ 1
nT
n ≥ 1
(1 + n)T
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle.
4. Maintain at least one of the two data input hold times, either tHKID (<25>) or tHDID (<35>).
24
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(5) Read timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
<20>
<28>
A16 to A19 (output)
<78>
R/W (output)
UBEN (output)
LBEN (output)
<32>
<21>
<24>
<25>
AD0 to AD15 (I/O)
A0 to A15 (output)
D0 to D15 (input)
<35>
<22>
<29>
<30>
<22>
ASTB (output)
<37>
<36>
<40>
<31>
<23>
<34>
<23>
<33>
DSTB (output)
<38>
<39>
<45> <26>
<47>
<46>
<48>
<27>
<26>
<27>
WAIT (input)
<41>
<43>
<42>
<44>
Remark Broken lines indicate high impedance.
Data Sheet U13188EJ6V1DS
25
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(6) Write timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay time from CLKOUT↑ to address <20> tDKA
Delay time from CLKOUT↑ to R/W, UBEN, LBEN <78> tDKA2
Delay time from CLKOUT↓ to ASTB <22> tDKST
Delay time from CLKOUT↑ to DSTB <23> tDKD
WAIT setup time (to CLKOUT↓) <26> tSWTK
WAIT hold time (from CLKOUT↓) <27> tHKWT
Address hold time (from CLKOUT↑) <28> tHKA
Address setup time (to ASTB↓) <29> tSAST
3
–2
+13
15
3
3
15
5
5
0
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
0.5T – 10
0.5T – 12
0.5T – 10
0.5T – 10
0.5T – 10
(1 + n)T – 10
(1 + n)T – 13
T – 10
Address hold time (from ASTB↓) <30> tHSTA
Delay time from ASTB
↓ to DSTB↓ <34> tDSTD
Delay time from DSTB
↓
to ASTB
↓
<37> tDDSTH
<39> tWDL
DSTB low-level width
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
ASTB high-level width
<40> tWSTH
<41> tSAWT1
WAIT setup time (to address)
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1
1.5T – 20
1.5T – 24
<42> tSAWT2
(1.5 + n)T – 20
(1.5 + n)T – 24
WAIT hold time (from address) <43> tHAWT1
<44> tHAWT2
(0.5 + n)T
(1.5 + n)T
n ≥ 1
WAIT setup time (to ASTB↓)
<45> tSSTWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1
T – 18
T – 20
<46> tSSTWT2
<47> tHSTWT1
<48> tHSTWT2
(1 + n)T – 15
WAIT hold time (from ASTB↓)
n ≥ 1
nT
n ≥ 1
(1 + n)T
Address hold time (from CLKOUT↑) <49> tDKOD
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
20
23
10
Delay time from DSTB↓ to data output <50> tDDOD
Data output hold time (from CLKOUT↑) <51> tHKOD
Data output setup time (to DSTB↑) <52> tSODD
Data output hold time (from DSTB↑) <53> tHDOD
0
(1 + n)T – 15
T – 10
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
26
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(6) Write timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
<20>
<78>
<28>
A16 to A19 (output)
R/W (output)
UBEN (output)
LBEN (output)
<49>
<51>
AD0 to AD15 (I/O)
A0 to A15 (output)
D0 to D15 (output)
<22>
<29>
<30>
<22>
ASTB (output)
DSTB (output)
<23>
<37>
<53>
<23>
<50>
<40>
<34>
<52>
<39>
<45> <26>
<47>
<46>
<48>
<27>
<26>
<27>
WAIT (input)
<41>
<43>
<42>
<44>
Remark Broken lines indicate high impedance.
Data Sheet U13188EJ6V1DS
27
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(7) Bus hold timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
20
Units
ns
HLDRQ setup time (to CLKOUT↓) <54> tSHQK
HLDRQ hold time (from CLKOUT↓) <55> tHKHQ
HLDAK delay time from CLKOUT↑ <56> tDKHA
5
5
ns
ns
HLDRQ high-level width
HLDAK low-level width
<57> tWHQH
<58> tWHAL
T + 10
T – 10
T – 12
ns
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
ns
ns
Delay time from CLKOUT↑ to bus float <59> tDKF
Delay time from HLDAK↑ to bus output <60> tDHAC
Delay time from HLDRQ↓ to HLDAK↓ <61> tDHQHA1
Delay time from HLDRQ↑ to HLDAK↑ <62> tDHQHA2
20
ns
–3
ns
(2n + 7.5)T + 20
1.5T + 20
ns
0.5T
ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
28
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(7) Bus hold timing (2/2)
TH
TH
TH
TH
TI
CLKOUT (output)
<54>
<54><55>
<57>
HLDRQ (input)
HLDAK (output)
<56>
<56>
<61>
<62>
<58>
<60>
<59>
A16 to A19 (output),
Note
D0 to D15
(input or output)
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output)
R/W (output)
Note UBEN (output), LBEN (output)
Remark Broken lines indicate high impedance.
Data Sheet U13188EJ6V1DS
29
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(8) Interrupt timing
Parameter
NMI high-level width
NMI low-level width
INTPn high-level width
Symbol
<63> tWNIH
<64> tWNIL
<65> tWITH
Conditions
MIN.
500
MAX.
Unit
ns
500
ns
n = 110 to 113, 120 to 123,
130 to 133, 140 to 143
3T + 10
ns
INTPn low-level width
<66> tWITL
n = 110 to 113, 120 to 123,
130 to 133, 140 to 143
3T + 10
ns
Remark T = tCYK
<63>
<64>
NMI (input)
<65>
<66>
INTPn (input)
Remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
30
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(9) CSI timing (1/2)
(a) Master mode
(i) Timing of CSI0 to CSI2
Parameter
SCKn cycle
Symbol
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
<67> tCYSK1
<68> tWSKH1
<69> tWSKL1
<70> tSSISK1
<71> tHSKSI1
Output
Output
Output
120
SCKn high-level width
0.5tCYSK1 – 20
SCKn low-level width
0.5tCYSK1 – 20
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
30
0
SOn output delay time (from SCKn↓) <72> tDSKSO1
SOn output hold time (from SCKn↑) <73> tHSKSO1
18
0.5tCYSK1 – 5
Remark n = 0 to 2
(ii) Timing of CSI3
Parameter
SCK3 cycle
Symbol
Conditions
RL = 1.5 kΩ
CL = 50 pF
MIN.
500
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
<67> tCYSK3
<68> tWSKH3
<69> tWSKL3
<70> tSSISK3
<71> tHSKSI3
Output
Output
Output
SCK3 high-level width
0.5tCYSK3 – 70
0.5tCYSK3 – 70
100
SCK3 low-level width
SI3 setup time (to SCK3↑)
SI3 hold time (from SCK3↑)
50
SO3 output delay time (from SCK3↓) <72> tDSKSO3
SO3 output hold time (from SCK3↑) <73> tHSKSO3
RL = 1.5 kΩ
CL = 50 pF
150
0.5tCYSK3 – 5
Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines.
(b) Slave mode
(i) Timing of CSI0 to CSI2
Parameter
SCKn cycle
Symbol
Conditions
MIN.
120
30
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
<67> tCYSK2
<68> tWSKH2
<69> tWSKL2
<70> tSSISK2
<71> tHSKSI2
Input
Input
Input
SCKn high-level width
SCKn low-level width
30
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
10
10
SOn output delay time (from SCKn↓) <72> tDSKSO2
SOn output hold time (from SCKn↑) <73> tHSKSO2
30
tWSKH2
Remark n = 0 to 2
Data Sheet U13188EJ6V1DS
31
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(9) CSI timing (2/2)
(ii) Timing of CSI3
Parameter
SCK3 cycle
Symbol
Conditions
MIN.
500
180
180
100
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
<67> tCYSK4
<68> tWSKH4
<69> tWSKL4
<70> tSSISK4
<71> tHSKSI4
Input
Input
Input
SCK3 high-level width
SCK3 low-level width
SI3 setup time (to SCK3↑)
SI3 hold time (from SCK3↑)
SO3 output delay time (from SCK3↓) <72> tDSKSO4
SO3 output hold time (from SCK3↑) <73> tHSKSO4
RL = 1.5 kΩ
CL = 50 pF
150
tWSKH4
Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines.
<67>
<69>
<68>
SCKn (I/O)
<70>
<71>
SIn (Input)
Input data
<72>
<73>
SOn (output)
Output data
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 3
32
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
(10) RPU timing
Parameter
TI1n high-level width
TI1n low-level width
Symbol
<74> tWTIH
<75> tWTIL
<76> tWTCH
<77> tWTCL
Conditions
MIN.
MAX.
Unit
ns
3T + 10
3T + 10
3T + 10
3T + 10
ns
TCLR1n high-level width
TCLR1n low-level width
ns
ns
Remark T = tCYK
<74>
<75>
TI1n (input)
<76>
<77>
TCLR1n (input)
Remark n = 1 to 4
Data Sheet U13188EJ6V1DS
33
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V 10%, VSS = AVSS = 0 V)
Parameter
Resolution
Overall error
Symbol
—
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Note 1
—
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
0.4
%FSR
%FSR
LSB
tCYK
—
0.7
Quantization error
Conversion time
—
1/2
tCONV
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
60
60
10
10
tCYK
Sampling time
tSAMP
tCYK
tCYK
Note 1
Zero-scale error
—
—
1.5
1.5
1.5
1.5
1.5
1.5
3.5
4.5
LSB
LSB
LSB
LSB
LSB
LSB
V
Note 1
Full-scale error
Non-linearity error
Analog input
—
2.5
—
4.5
Note 1
—
2.5
—
4.5
VIAN
–0.3
3.5
AVDD + 0.3
Note 2
voltage
Reference voltage
AVREF1 current
AVREF1
AIREF1
AIDD
AVDD
3.0
V
1.2
2.3
mA
mA
AVDD supply current
6.0
Notes 1. Excludes quantization error.
2. When VIAN = 0, the conversion result becomes 000H.
When 0 < VIAN < AVREF1, conversion has 10-bit resolution.
When AVREF1 ≤ VIAN ≤ AVDD, the conversion result becomes 3FFH.
34
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V 10%, VSS = AVSS = 0 V)
Parameter
Resolution
Symbol
—
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
bit
Overall error
—
Load condition: 2 MΩ, 30 pF
AVREF2 = VDD
0.8
%
AVREF3 = 0
—
—
—
Load condition: 2 MΩ, 30 pF
AVREF2 = 0.75VDD
1.0
0.6
0.8
10
%
%
%
AVREF3 = 0.25VDD
Load condition: 4 MΩ, 30 pF
AVREF2 = VDD
AVREF3 = 0
Load condition: 4 MΩ, 30 pF
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD
Settling time
—
Load condition: 2 MΩ, 30 pF
µs
kΩ
V
Output resistance
AVREF2 input voltage
AVREF3 input voltage
RO
8
4
AVREF2
AVREF3
0.75VDD
VDD
0
2
0.25VDD
V
Resistance between
RAIREF DACS0, DACS1 = 55H
kΩ
AVREF2 and AVREF3
Data Sheet U13188EJ6V1DS
35
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
4. PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
16.00 0.20
14.00 0.20
14.00 0.20
16.00 0.20
1.00
G
1.00
+0.05
0.22
H
−0.04
I
J
0.08
0.50 (T.P.)
1.00 0.20
0.50 0.20
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.40 0.05
0.10 0.05
+7°
3°
R
−3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
36
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
5. RECOMMENDED SOLDERING CONDITIONS
The µPD703003A, 703004A, 703025A, 703003A(A), and 703025A(A) should be soldered and mounted under the
following recommended conditions.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 5-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD703003AGC-33-×××-8EU:
µPD703004AGC-33-×××-8EU:
µPD703025AGC-33-×××-8EU:
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
µPD703003AGC(A)-33-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
µPD703025AGC(A)-33-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Method
Infrared reflow
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or
higher), Count: Two times or less, Exposure limit: 7 days
IR35-107-2
VP15-107-2
—
Note
(after that,
prebake at 125°C for 10 to 72 hours)
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or
higher), Count: Two times or less, Exposure limit: 7 days
VPS
Note
(after that,
prebake at 125°C for 10 to 72 hours)
Partial heating
Pin temperature: 300°C max., Time 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark For soldering methods and conditions other than those recommended above, consult an NEC Electronics
sales representative.
Data Sheet U13188EJ6V1DS
37
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
Table 5-1. Surface Mounting Type Soldering Conditions (2/2)
(2) µPD703003AGC-33-xxx-8EU-A: 100-pin plastic LQFP (fine pitch) (14 × 14)
µPD703025AGC-33-xxx-8EU-A: 100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Method
Infrared reflow
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or
higher), Count: Three times or less, Exposure limit: 7 days
IR60-207-3
Note
(after that,
prebake at 125°C for 20 to 72 hours)
Wave soldering
Partial heating
For details, consult an NEC Electronics sales representative.
—
—
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remarks 1. Products with -A at the end of the part number are lead-free products.
2. For soldering methods and conditions other than those recommended above, consult an NEC
Electronics sales representative.
38
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
APPENDIX NOTES ON TARGET SYSTEM DESIGN
The following shows a diagram of the connection conditions between the in-circuit emulator option board and
conversion connector. Design your system making allowances for conditions such as the form of parts mounted on
the target system as shown below.
Side view
In-circuit emulator
IE-703002-MC
In-circuit emulator option board
IE-703003-MC-EM1
Conversion connector
132.24 mm
YQGUIDE
YQPACK100SD
Note
NQPACK100SD
Target system
Note YQSOCKET100SDN (included with IE-703002-MC) can be inserted here to adjust the height (height: 3.2 mm).
Top view
IE-703002-MC
Target system
Pin 1 position
IE-703003-MC-EM1
YQPACK100SD, NQPACK100SD,
YQGUIDE
Connection
condition diagram
IE-703003-MC-EM1
Connect to
IE-703002-MC.
Pin 1 position
75 mm
YQGUIDE
YQPACK100SD
NQPACK100SD
13.3 mm
31.84 mm
15.24 mm
Target system
21.58 mm
24 mm
Data Sheet U13188EJ6V1DS
39
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
40
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
RELATED DOCUMENTS µPD70F3003A, 70F3025A, 70F3003A(A) Data Sheet (U13189E)
Reference Materials Electrical Characteristics for Microcomputer (U15170JNote
Note This document number is that of Japanese version.
)
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Data Sheet U13188EJ6V1DS
41
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
•
•
•
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Tel: 02-558-3737
Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
•
Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-2654010
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
•
•
Tyskland Filial
Taeby, Sweden
Tel: 08-63 87 200
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J05.6
42
Data Sheet U13188EJ6V1DS
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of July, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
UPD703003AGC-25
V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703003AGC-25-8EU
32-Bit MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
UPD703003AGC-25-XXX-8E
32-Bit MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
UPD703003AGC-25-XXX-8EU
32-BIT, MROM, 25MHz, RISC MICROCONTROLLER, PQFP100, 14 X 14 MM, FINE PITCH, PLASTIC, LQFP-100Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
RENESAS
UPD703003AGC-33
V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703003AGC-33-XXX-8E
32-Bit MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
UPD703003AGC-33-XXX-8EU
MICROCONTROLLER|32-BIT|V850 CPU|CMOS|QFP|100PIN|PLASTICWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
UPD703003AGC-33-XXX-8EU-A
Microcontroller, 32-Bit, MROM, 33MHz, MOS, PQFP100, 14 X 14 MM, LEAD FREE, PLASTIC, QFP-100Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703003AGC-33-XXX-8EU-A
UPD703003AGC-33-XXX-8EU-AWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
RENESAS
UPD703003GC
V853TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703003GC-25
V853TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703003GC-25-XXX-7EA
RISC Microcontroller, 32-Bit, MROM, MOS, PQFP100, 14 X 14 MM, FINE PITCH, PLASTIC, QFP-100Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
©2020 ICPDF网 联系我们和版权申明