UPD789026_技术文档

User’s Manual

µPD789026 Subseries

8-Bit Single-Chip Microcontrollers

µPD789022

µPD789024

µPD789025

µPD789026

µPD78F9026A

Document No. U11919EJ3V0UMJ1 (3rd edition)

Date Published October 2000 N CP(K)

1998

1996, 1999

©

Printed in Japan

[MEMO]

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User's Manual U11919EJ3V0UM00

SUMMARY OF CONTENTS

CHAPTER 1 GENERAL....................................................................................................................................23

CHAPTER 2 PIN FUNCTIONS..........................................................................................................................33

CHAPTER 3 CPU ARCHITECTURE.................................................................................................................41

CHAPTER 4 PORT FUNCTIONS......................................................................................................................69

CHAPTER 5 CLOCK GENERATION CIRCUIT ................................................................................................85

CHAPTER 6 16-BIT TIMER ..............................................................................................................................93

CHAPTER 7 8-BIT TIMER/EVENT COUNTER..............................................................................................105

CHAPTER 8 WATCHDOG TIMER..................................................................................................................115

CHAPTER 9 SERIAL INTERFACE 00............................................................................................................121

CHAPTER 10 INTERRUPT FUNCTIONS .........................................................................................................149

CHAPTER 11 STANDBY FUNCTION..............................................................................................................167

CHAPTER 12 RESET FUNCTION....................................................................................................................175

CHAPTER 13 µPD78F9026A............................................................................................................................179

CHAPTER 14 INSTRUCTION SET...................................................................................................................185

APPENDIX A DEVELOPMENT TOOLS...........................................................................................................195

APPENDIX B EMBEDDED SOFTWARE..........................................................................................................205

APPENDIX C REGISTER INDEX .....................................................................................................................207

APPENDIX D REVISION HISTORY .................................................................................................................211

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User's Manual U11919EJ3V0UM00

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

EEPROM is a trademark of NEC Corporation.

MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft

Corporation in the United States and/or other countries.

IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

OSF/Motif is a trademark of Open Software Foundation, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

TRON is an abbreviation of The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

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User's Manual U11919EJ3V0UM00

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these

products may be prohibited without governmental license. To export or re-export some or all of these products from a

country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

License not needed: µPD78F9026A

The customer must judge the need for license: µPD789022, µPD789024, µPD789025, µPD789026

•

The information in this document is current as of October, 1999. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or

data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all

products and/or types are available in every country. Please check with an NEC sales representative

for availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

liability arising from the use of such products. No license, express, implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third

parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not

intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness

to support a given application.

(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4

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User's Manual U11919EJ3V0UM00

Major Revision in This Edition

Page

Description

Completion of development of µPD789022 and µPD789024

Change of part number from µPD78F9026 to µPD78F9026A

Throughout

Deletion of following products:

µPD789022CU-×××, 789024CU-×××

Addition of GB-8ES type package to all models

p.39

Change of circuit type and recommended connection of unused pins in Table 2-1

Addition of cautions on rewriting CR20 to Section 6.4.1

Addition of cautions on rewriting CR00 to Section 7.2 (1)

Addition of description of operation to Section 7.4.1

Addition of description of operation to Section 7.4.2

Addition of description of operation to Section 7.4.3

Change of flash writer from Flashpro II to Flashpro III

Addition of setting example to Section 13.1.4

p.99

p.106

p.109

p.111

p.112

pp.180 to 183

p.183

p.205

Addition of part number of MX78K0S to Appendix B

The mark shows the major revised points.

6

User's Manual U11919EJ3V0UM00

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, pIease contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

•

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.

Benelux Office

Hong Kong

Eindhoven, The Netherlands

Tel: 040-2445845

Tel: 2886-9318

Fax: 2886-9022/9044

Fax: 408-588-6130

800-729-9288

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 01-30-67 58 99

Fax: 0211-65 03 490

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore

Tel: 65-253-8311

NEC Electronics (France) S.A.

Madrid Office

Madrid, Spain

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 65-250-3583

Tel: 91-504-2787

Fax: 01908-670-290

Fax: 91-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

NEC Electronics Italiana s.r.l.

Milano, Italy

Tel: 02-66 75 41

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Fax: 02-2719-5951

Fax: 02-66 75 42 99

Tel: 08-63 80 820

NEC do Brasil S.A.

Electron Devices Division

Guarulhos-SP Brasil

Tel: 55-11-6462-6810

Fax: 55-11-6462-6829

Fax: 08-63 80 388

J00.7

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User's Manual U11919EJ3V0UM00

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User's Manual U11919EJ3V0UM00

INTRODUCTION

Readers

This manual is intended for user engineers who understand the functions of the

µPD789026 Subseries to design and develop its application systems and programs.

The target subseries is the µPD789026 Subseries, which consists of the

µPD789022, µPD789024, µPD789025, µPD789026, and µPD78F9026A.

Purpose

This manual is designed to deepen your understanding of the following functions

described in the following organization.

Organization

Two manuals are available for the µPD789026 Subseries: this manual and

Instruction Manual (common to the 78K/0S Series).

µPD789026 Subseries

78K/0S Series

User's Manual

Instruction

User's Manual

• Pin functions

• CPU function

• Internal block functions

• Interrupt

• Instruction set

• Instruction description

• Other internal peripheral functions

How to Read This Manual

It is assumed that the readers of this manual have general knowledge on electric

engineering, logic circuits, and microcontrollers.

◊ To understand the overall functions of the µPD789026 Subseries

→ Read this manual in the order of the TABLE OF CONTENTS.

◊ How to read register formats

→ The name of a bit whose number is encircled is reserved for the assembler and

is defined for the C compiler by the header file sfrbit.h.

◊ To learn the detailed functions of a register whose register name is known

→ See APPENDEX C.

◊ To learn the details of the instruction functions of the 78K/0S Series

→ Refer to 78K/0S Series User's Manual

Instruction (U11047E) separately

available.

Legend

Data significance

Active low

Note

:

Left: higher digit, right: lower digit

××× (top bar over pin or signal name)

Description of text marked Note

Important information

Caution

Remark

Supplement

Numerical representation : Binary ... ×××× or ××××B

Decimal ... ××××

Hexadecimal ... ××××H

9

User's Manual U11919EJ3V0UM00

Other Related Documents

Document Name

Document No.

English Japanese

X13769X

SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)

Semiconductor Device Mounting Technology Manual

C10535E

C11531E

C10983E

C11892E

−

C10535J

Quality Grades on NEC Semiconductor Device

C11531J

C10983J

C11892J

C12769J

U11416J

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

Semiconductor Device Quality Control/Reliability Handbook

Guide for products Related to Microcomputer: Other Companies

−

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

documents for designing, etc.

11

User's Manual U11919EJ3V0UM00

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User's Manual U11919EJ3V0UM00

TABLE OF CONTENTS

CHAPTER 1 GENERAL.............................................................................................................................23

1.1 Features ......................................................................................................................................23

1.2 Applications................................................................................................................................23

1.3 Ordering Information .................................................................................................................24

1.4 Pin Configuration (Top View)....................................................................................................25

1.5 Development of 78K/0S Series..................................................................................................28

1.6 Block Diagram ............................................................................................................................30

1.7 Outline of Functions ..................................................................................................................31

CHAPTER 2 PIN FUNCTIONS ..................................................................................................................33

2.1 List of Pin Functions..................................................................................................................33

2.2 Description of Pin Functions ....................................................................................................35

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

2.2.10

2.2.11

2.2.12

2.2.13

P00 to P07 (Port 0)......................................................................................................................35

P10 to P17 (Port 1)......................................................................................................................35

P20 to P22 (Port 2)......................................................................................................................35

P30 to P32 (Port 3)......................................................................................................................36

P40 to P47 (Port 4)......................................................................................................................36

P50 to P53 (Port 5)......................................................................................................................37

RESET.........................................................................................................................................37

X1, X2..........................................................................................................................................37

NC ...............................................................................................................................................37

V^DD...............................................................................................................................................37

V^SS...............................................................................................................................................37

V^PP(µPD78F9026A only) ............................................................................................................37

IC (mask ROM model only) .........................................................................................................38

2.3 Pin Input/Output Circuits and Connection of Unused Pins...................................................39

CHAPTER 3 CPU ARCHITECTURE .........................................................................................................41

3.1 Memory Space............................................................................................................................41

3.1.1

3.1.2

3.1.3

3.1.4

Internal program memory space..................................................................................................46

Internal data memory (internal high-speed RAM) space.............................................................47

Special function register (SFR) area ...........................................................................................47

Data memory addressing ............................................................................................................48

3.2 Processor Registers ..................................................................................................................53

3.2.1

3.2.2

3.2.3

Control registers ..........................................................................................................................53

General-purpose registers...........................................................................................................56

Special function register (SFR)....................................................................................................57

3.3 Instruction Address Addressing ..............................................................................................60

3.3.1

Relative addressing.....................................................................................................................60

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User's Manual U11919EJ3V0UM00

3.3.2

3.3.3

3.3.4

Immediate addressing.................................................................................................................61

Table indirect addressing ............................................................................................................62

Register addressing ....................................................................................................................62

3.4 Operand Address Addressing ..................................................................................................63

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

Direct addressing ........................................................................................................................63

Short direct addressing ...............................................................................................................64

Special function register (SFR) addressing.................................................................................65

Register addressing ....................................................................................................................66

Register indirect addressing........................................................................................................67

Based addressing........................................................................................................................68

Stack addressing.........................................................................................................................68

CHAPTER 4 PORT FUNCTIONS ..............................................................................................................69

4.1 Functions of Ports .....................................................................................................................69

4.2 Port Configuration .....................................................................................................................71

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

Port 0...........................................................................................................................................71

Port 1...........................................................................................................................................72

Port 2...........................................................................................................................................73

Port 3...........................................................................................................................................76

Port 4...........................................................................................................................................77

Port 5...........................................................................................................................................78

4.3 Port Function Control Registers ..............................................................................................81

4.4 Operation of Port Functions .....................................................................................................83

4.4.1

4.4.2

4.4.3

Writing to I/O port ........................................................................................................................83

Reading from I/O port..................................................................................................................83

Arithmetic operation of I/O port....................................................................................................83

CHAPTER 5 CLOCK GENERATION CIRCUIT.........................................................................................85

5.1 Function of Clock Generation Circuit ...................................................................................... 85

5.2 Configuration of Clock Generation Circuit..............................................................................85

5.3 Register Controlling Clock Generation Circuit .......................................................................86

5.4 System Clock Oscillation Circuits............................................................................................87

5.4.1

5.4.2

System clock oscillation circuit....................................................................................................87

Divider circuit...............................................................................................................................89

5.5 Operation of Clock Generation Circuit ....................................................................................90

5.6 Changing Setting of System Clock and CPU Clock ...............................................................91

5.6.1

5.6.2

Time required for switching between system clock and CPU clock ............................................91

Switching CPU clock ...................................................................................................................91

CHAPTER 6 16-BIT TIMER.......................................................................................................................93

6.1 16-Bit Timer Functions ..............................................................................................................93

6.2 16-Bit Timer Configuration........................................................................................................94

6.3 Registers Controlling 16-Bit Timer...........................................................................................96

6.4 16-Bit Timer Operation ..............................................................................................................99

6.4.1

Operation as timer interrupt.........................................................................................................99

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User's Manual U11919EJ3V0UM00

6.4.2

6.4.3

6.4.4

Operation as timer output..........................................................................................................101

Capture operation......................................................................................................................102

16-bit timer counter 20 readout .................................................................................................103

CHAPTER 7 8-BIT TIMER/EVENT COUNTER .......................................................................................105

7.1 8-Bit Timer/Event Counter Functions.....................................................................................105

7.2 8-Bit Timer/Event Counter Configuration ..............................................................................106

7.3 8-Bit Timer/Event Counter Control Registers........................................................................107

7.4 8-Bit Timer/Event Counter Operation.....................................................................................109

7.4.1

7.4.2

7.4.3

Operation as interval timer ........................................................................................................109

Operation as external event counter .........................................................................................111

Operation as square wave output..............................................................................................112

7.5 Notes on Using 8-Bit Timer/Event Counters .........................................................................114

CHAPTER 8 WATCHDOG TIMER...........................................................................................................115

8.1 Watchdog Timer Functions.....................................................................................................115

8.2 Watchdog Timer Configuration ..............................................................................................116

8.3 Watchdog Timer Control Registers........................................................................................117

8.4 Operation of Watchdog Timer.................................................................................................119

8.4.1

8.4.2

Operation as watchdog timer.....................................................................................................119

Operation as interval timer ........................................................................................................120

CHAPTER 9 SERIAL INTERFACE 00.....................................................................................................121

9.1 Serial Interface 00 Functions ..................................................................................................121

9.2 Serial Interface 00 Configuration............................................................................................121

9.3 Serial Interface 00 Control Register .......................................................................................125

9.4 Serial Interface 00 Operation...................................................................................................132

9.4.1

9.4.2

9.4.3

Operation stop mode.................................................................................................................132

Asynchronous serial interface (UART) mode ............................................................................134

3-wire serial I/O mode ...............................................................................................................145

CHAPTER 10 INTERRUPT FUNCTIONS................................................................................................149

10.1 Interrupt Function Types.........................................................................................................149

10.2 Interrupt Sources and Configuration .....................................................................................149

10.3 Interrupt Function Control Registers.....................................................................................152

10.4 Interrupt Processing Operation..............................................................................................158

10.4.1

10.4.2

10.4.3

10.4.4

Non-maskable interrupt request acceptance operation.............................................................158

Maskable interrupt request acceptance operation.....................................................................161

Nesting processing....................................................................................................................163

Interrupt request reserve ...........................................................................................................165

CHAPTER 11 STANDBY FUNCTION .....................................................................................................167

11.1 Standby Function and Configuration.....................................................................................167

11.1.1

Standby function........................................................................................................................167

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User's Manual U11919EJ3V0UM00

11.1.2

Standby function control register...............................................................................................168

11.2 Operation of Standby Function ..............................................................................................169

11.2.1

11.2.2

HALT mode ...............................................................................................................................169

STOP mode...............................................................................................................................172

CHAPTER 12 RESET FUNCTION...........................................................................................................175

CHAPTER 13 µPD78F9026A ..................................................................................................................179

13.1 Flash Memory Programming...................................................................................................180

13.1.1

13.1.2

13.1.3

13.1.4

Selecting communication mode.................................................................................................180

Flash memory programming function........................................................................................181

Connection Example of Flashpro III ..........................................................................................181

Setting example when using Flashpro III (PG-FP3) ..................................................................183

CHAPTER 14 INSTRUCTION SET..........................................................................................................185

14.1 Operation ..................................................................................................................................185

14.1.1

14.1.2

14.1.3

Operand identifiers and writing methods...................................................................................185

Description of "Operation" column.............................................................................................186

Description of "Flag" column .....................................................................................................186

14.2 Operation List...........................................................................................................................187

14.3 Instructions Listed by Addressing Type ...............................................................................192

APPENDIX A DEVELOPMENT TOOLS..................................................................................................195

A.1 Language Processing Software.............................................................................................. 197

A.2 Flash Memory Writing Tools...................................................................................................198

A.3 Debugging Tools......................................................................................................................199

A.3.1

A.3.2

Hardware...................................................................................................................................199

Software ....................................................................................................................................200

A.4 Conversion Socket (EV-9200G-44) Drawing and Recommended Footprint.......................201

A.5 Conversion Adapter (TGB-044SAP) Drawing........................................................................203

APPENDIX B EMBEDDED SOFTWARE ................................................................................................205

APPENDIX C REGISTER INDEX ............................................................................................................207

C.1 Register Name Index................................................................................................................207

C.2 Register Symbol Index ............................................................................................................209

APPENDIX D REVISION HISTORY ........................................................................................................211

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User's Manual U11919EJ3V0UM00

LIST OF FIGURES (1/3)

Figure No.

2-1

Title

Page

List of Pin Input/Output Circuits................................................................................................................. 40

3-1

Memory Map (µPD789022)....................................................................................................................... 41

Memory Map (µPD789024)....................................................................................................................... 42

Memory Map (µPD789025)....................................................................................................................... 43

Memory Map (µPD789026)....................................................................................................................... 44

Memory Map (µPD78F9026A) .................................................................................................................. 45

Data Memory Addressing (µPD789022) ................................................................................................... 48

Data Memory Addressing (µPD789024) ................................................................................................... 49

Data Memory Addressing (µPD789025) ................................................................................................... 50

Data Memory Addressing (µPD789026) ................................................................................................... 51

Data Memory Addressing (µPD78F9026A)............................................................................................... 52

Program Counter Configuration ................................................................................................................ 53

Program Status Word Configuration ......................................................................................................... 53

Stack Pointer Configuration ...................................................................................................................... 55

Data to be Saved to Stack Memory .......................................................................................................... 55

Data to be Restored from Stack Memory.................................................................................................. 55

General-Purpose Register Configuration.................................................................................................. 56

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

3-10

3-11

3-12

3-13

3-14

3-15

3-16

4-1

Port Types................................................................................................................................................. 69

Block Diagram of P00 to P07.................................................................................................................... 71

Block Diagram of P10 to P17.................................................................................................................... 72

Block Diagram of P20 ............................................................................................................................... 73

Block Diagram of P21 ............................................................................................................................... 74

Block Diagram of P22 ............................................................................................................................... 75

Block Diagram of P30 to P32.................................................................................................................... 76

Block Diagram of P40 to P47.................................................................................................................... 77

Block Diagram of P50 ............................................................................................................................... 78

Block Diagram of P51 ............................................................................................................................... 79

Block Diagram of P52 and P53................................................................................................................. 80

Port Mode Register Format....................................................................................................................... 82

Pull-Up Resistor Option Register Format.................................................................................................. 82

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

4-10

4-11

4-12

4-13

5-1

5-2

5-3

5-4

5-5

Block Diagram of Clock Generation Circuit............................................................................................... 85

Processor Clock Control Register Format................................................................................................. 86

External Circuit of System Clock Oscillation Circuit.................................................................................. 87

Incorrect Examples of Resonator Connection........................................................................................... 88

Switching CPU Clock ................................................................................................................................ 91

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User's Manual U11919EJ3V0UM00

LIST OF FIGURES (2/3)

Figure No.

Title

Page

6-1

6-2

6-3

6-4

6-5

6-6

6-7

6-8

6-9

6-10

Block Diagram of 16-Bit Timer 20 ..............................................................................................................94

16-Bit Timer Mode Control Register 20 Format .........................................................................................97

Port Mode Register 5 Format.....................................................................................................................98

Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation ......................................99

Timer Interrupt Operation Timing.............................................................................................................100

Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation.......................................101

Timer Output Timing ................................................................................................................................101

Setting Contents of 16-Bit Timer Mode Control Register 20 during Capture Operation...........................102

Capture Operation Timing (Both Edges of CPT2 Pin are Specified) .......................................................102

16-Bit Timer Counter 20 Readout Timing ................................................................................................103

7-1

7-2

7-3

7-4

7-5

7-6

7-7

7-8

Block Diagram of 8-Bit Timer/Event Counter 00 ......................................................................................106

8-Bit Timer Mode Control Register 00 Format .........................................................................................107

Port Mode Register 5 Format...................................................................................................................108

Interval Timer Operation Timing...............................................................................................................110

External Event Counter Operation Timing (with Rising Edge Specified) .................................................111

Square Wave Output Timing....................................................................................................................113

8-Bit Timer Counter 00 Start Timing ........................................................................................................114

External Event Counter Operation Timing ...............................................................................................114

8-1

8-2

8-3

Block Diagram of Watchdog Timer ..........................................................................................................116

Timer Clock Select Register 2 Format .....................................................................................................117

Watchdog Timer Mode Register Format..................................................................................................118

9-1

9-2

9-3

9-4

9-5

9-6

9-7

9-8

9-9

9-10

9-11

Block Diagram of Serial Interface 00........................................................................................................122

Block Diagram of Baud Rate Generator...................................................................................................123

Serial Operation Mode Register 00 Format .............................................................................................125

Asynchronous Serial Interface Mode Register 00 Format .......................................................................126

Asynchronous Serial Interface Status Register 00 Format ......................................................................128

Baud Rate Generator Control Register 00 Format...................................................................................129

Asynchronous Serial Interface Transmit/Receive Data Format ...............................................................139

Asynchronous Serial Interface Transmission Completion Interrupt Timing .............................................141

Asynchronous Serial Interface Reception Completion Interrupt Timing...................................................142

Receive Error Timing ...............................................................................................................................143

3-Wire Serial I/O Mode Timing.................................................................................................................148

10-1

10-2

10-3

Basic Configuration of Interrupt Function.................................................................................................151

Interrupt Request Flag Register Format...................................................................................................153

Interrupt Mask Flag Register Format .......................................................................................................154

18

User's Manual U11919EJ3V0UM00

LIST OF FIGURES (3/3)

Figure No.

Title

Page

10-4

External Interrupt Mode Register 0 Format............................................................................................. 155

Program Status Word Configuration ....................................................................................................... 156

Key Return Mode Register 00 Format..................................................................................................... 157

Falling Edge Detection Circuit................................................................................................................. 157

Flowchart from Non-Maskable Interrupt Request Generation to Acceptance......................................... 159

Non-Maskable Interrupt Request Acceptance Timing............................................................................. 159

Accepting Non-Maskable Interrupt Request ........................................................................................... 160

Interrupt Request Acceptance Program Algorithm.................................................................................. 162

Interrupt Request Acceptance Timing (Example of MOV A,r)................................................................. 163

Interrupt Request Acceptance Timing

10-5

10-6

10-7

10-8

10-9

10-10

10-11

10-12

10-13

(When Interrupt Request Flag Generates at the Last Clock during Instruction Execution)..................... 163

Example of Nesting................................................................................................................................. 164

10-14

11-1

11-2

11-3

11-4

11-5

Oscillation Settling Time Select Register Format.................................................................................... 168

Releasing HALT Mode by Interrupt......................................................................................................... 170

Releasing HALT Mode by RESET Input ................................................................................................. 171

Releasing STOP Mode by Interrupt ........................................................................................................ 173

Releasing STOP Mode by RESET Input................................................................................................. 174

12-1

12-2

12-3

12-4

Block Diagram of Reset Function............................................................................................................ 175

Reset Timing by RESET Input ................................................................................................................ 176

Reset Timing by Overflow in Watchdog Timer........................................................................................ 176

Reset Timing by RESET Input in STOP Mode........................................................................................ 176

13-1

13-2

13-3

13-4

Communication Mode Selection Format ................................................................................................. 180

Connection Example of Flashpro III in 3-Wire Serial I/O Mode............................................................... 181

Connection Example of Flashpro III in UART Mode................................................................................ 182

Connection Example of Flashpro III in Pseudo 3-Wire Mode (When using P0)...................................... 182

A-1

A-2

A-3

A-4

Development Tools ................................................................................................................................. 196

EV-9200G-44 Package Drawing (Reference) ......................................................................................... 201

EV-9200G-44 Recommended Footprint (Reference).............................................................................. 202

TGB-044SAP Package Drawing (Reference) ......................................................................................... 203

19

User's Manual U11919EJ3V0UM00

LIST OF TABLES (1/2)

Table No.

2-1

Title

Page

Type of Input/Output Circuit of Each Pin and Handling of Unused Pins ....................................................39

3-1

3-2

3-3

3-4

Internal ROM Capacity...............................................................................................................................46

Vector Table...............................................................................................................................................46

Internal High-Speed RAM Capacity ...........................................................................................................47

Special Function Registers ........................................................................................................................58

4-1

4-2

4-3

Port Functions............................................................................................................................................70

Port Configuration......................................................................................................................................71

Port Mode Register and Output Latch Settings when Using Alternate Functions......................................81

5-1

5-2

Configuration of Clock Generation Circuit..................................................................................................85

Maximum Time Required for Switching CPU Clock...................................................................................91

6-1

6-2

6-3

Configuration of 16-Bit Timer 20 ................................................................................................................94

Interval Time of 16-Bit Timer 20.................................................................................................................99

Setting Contents of Capture Edge ...........................................................................................................102

7-1

7-2

7-3

7-4

7-5

Interval Time of 8-Bit Timer/Event Counter 00.........................................................................................105

Square Wave Output Range of 8-Bit Timer/Event Counter 00 ................................................................105

Configuration of 8-Bit Timer/Event Counter 00 ........................................................................................106

Interval Time of 8-Bit Timer/Event Counter 00.........................................................................................109

Square Wave Output Range of 8-Bit Timer/Event Counter 00 ................................................................112

8-1

8-2

8-3

8-4

8-5

Inadvertent Loop Detection Time of Watchdog Timer..............................................................................115

Interval Time ............................................................................................................................................115

Configuration of Watchdog Timer ............................................................................................................116

Inadvertent Loop Detection Time of Watchdog Timer..............................................................................119

Interval Time of Interval Timer .................................................................................................................120

9-1

9-2

9-3

9-4

9-5

9-6

9-7

Configuration of Serial Interface 00 .........................................................................................................121

Serial Interface 00 Operating Mode Settings ...........................................................................................127

Example of Relationship between System Clock and Baud Rate............................................................130

Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC00 is Set to 80H) ........131

Example of Relationship between System Clock and Baud Rate............................................................138

Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC00 is Set to 80H) .......138

Receive Error Causes..............................................................................................................................143

10-1

Interrupt Source List.................................................................................................................................150

20

User's Manual U11919EJ3V0UM00

LIST OF TABLES (2/2)

Table No.

Title

Page

10-2

10-3

Flags Corresponding to Interrupt Request Signal Name ........................................................................ 152

Time from Generation of Maskable Interrupt Request to Processing ..................................................... 161

11-1

11-2

11-3

11-4

HALT Mode Operating Status ................................................................................................................. 169

Operation after Release of HALT Mode.................................................................................................. 171

STOP Mode Operating Status................................................................................................................. 172

Operation after Release of STOP Mode ................................................................................................. 174

12-1

Hardware Status after Reset................................................................................................................... 177

13-1

13-2

13-3

13-4

Differences between µPD78F9026A and Mask ROM Models ................................................................ 179

Communication Modes ........................................................................................................................... 180

Major Flash Memory Programming Functions ........................................................................................ 181

Setting Example When Using PG-FP3.................................................................................................... 183

14-1

Operand Identifiers and Writing Methods................................................................................................ 185

21

User's Manual U11919EJ3V0UM00

[MEMO]

22

User's Manual U11919EJ3V0UM00

CHAPTER 1 GENERAL

1.1 Features

• ROM and RAM capacity

Item

Program Memory

Data Memory

Part Number

µPD789022

µPD789024

µPD789025

µPD789026

µPD78F9026A

ROM

4 Kbytes

8 Kbytes

12 Kbytes

16 Kbytes

256 bytes

512 bytes

Flash memory

16 Kbytes

•

Variable minimum instruction execution time - from high speed (0.4 µs: with 5.0-MHz system clock) to slow

(1.6 µs: with 5.0-MHz system clock)

I/O port: 34 lines

•

Serial interface: 1 channel

3-wire serial I/O mode/UART mode selection

Timer: 3 channels

•

16-bit timer

8-bit timer/event counter : 1 channel

Watchdog timer : 1 channel

: 1 channel

•

Vectored interrupt: 10

Supply voltage: V^DD= 1.8 to 5.5 V

Operating ambient temperature: T^A= -40°C to +85°C

1.2 Applications

Home appliances, car accessories, air conditioners, game machines, etc.

23

User's Manual U11919EJ3V0UM00

CHAPTER 1 GENERAL

1.3 Ordering Information

Part Number

Package

Internal ROM

Mask ROM

Flash memory

µPD789022GB-×××-3BS-MTX

µPD789022GB-×××-8ES

µPD789024GB-×××-3BS-MTX

µPD789024GB-×××-8ES

µPD789025CU-×××

44-pin plastic QFP (10 × 10 mm, resin thickness 2.7 mm)

44-pin plastic LQFP (10 × 10 mm, resin thickness 1.4 mm)

44-pin plastic QFP (10 × 10 mm, resin thickness 2.7 mm)

44-pin plastic LQFP (10 × 10 mm, resin thickness 1.4 mm)

42-pin plastic shrink DIP (600 mil)

µPD789025GB-×××-3BS-MTX

µPD789025GB-×××-8ES

µPD789026CU-×××

44-pin plastic QFP (10 × 10 mm, resin thickness 2.7 mm)

44-pin plastic LQFP (10 × 10 mm, resin thickness 1.4 mm)

42-pin plastic shrink DIP (600 mil)

µPD789026GB-×××-3BS-MTX

µPD789026GB-×××-8ES

µPD78F9026ACU

44-pin plastic QFP (10 × 10 mm, resin thickness 2.7 mm)

44-pin plastic LQFP (10 × 10 mm, resin thickness 1.4 mm)

42-pin plastic shrink DIP (600 mil)

µPD78F9026AGB-3BS-MTX

µPD78F9026AGB-8ES

44-pin plastic QFP (10 × 10 mm, resin thickness 2.7 mm)

44-pin plastic LQFP (10 × 10 mm, resin thickness 1.4 mm)

Remark ××× indicates ROM code suffix.

24

User's Manual U11919EJ3V0UM00

CHAPTER 1 GENERAL

1.4 Pin Configuration (Top View)

•

42-pin plastic shrink DIP (600 mil)

µPD789025CU-×××

µPD789026CU-×××

µPD78F9026ACU

V

DD0

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

V

SS0

RESET

P53

2

X1

3

X2

P52

4

IC (V^PP)

P51/TO2

P50/TI0/TO0

P32/INTP2/CPT2

P31/INTP1

P30/INTP0

P22/RxD/SI0

P21/TxD/SO0

P20/ASCK/SCK0

P07

5

P40/KR0

P41/KR1

P42/KR2

P43/KR3

P44/KR4

P45/KR5

P46/KR6

P47/KR7

P10

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

P06

P11

P05

P12

P04

P13

P03

P14

P02

P15

P01

P16

P00

P17

V

DD1

V

SS1

Caution Connect the IC pin directly to V^SS0or V^SS1.

Remark An item in parentheses applies to the µPD78F9026A only.

25

User's Manual U11919EJ3V0UM00

CHAPTER 1 GENERAL

•

44-pin plastic QFP (10 × 10 mm, resin thickness 2.7 mm)

µPD789022GB-×××-3BS-MTX

µPD789024GB-×××-3BS-MTX

µPD789025GB-×××-3BS-MTX

µPD789026GB-×××-3BS-MTX

µPD78F9026AGB-3BS-MTX

•

44-pin plastic LQFP (10 × 10 mm, resin thickness 1.4 mm)

µPD789022GB-×××-8ES

µPD789024GB-×××-8ES

µPD789025GB-×××-8ES

µPD789026GB-×××-8ES

µPD78F9026AGB-8ES

44 43 42 41 40 39 38 37 36 35 34

P12

P11

1

33

32

31

30

29

28

27

26

25

24

23

P03

2

P04

P10

3

P05

P47/KR7

P46/KR6

P45/KR5

P44/KR4

P43/KR3

P42/KR2

P41/KR1

P40/KR0

4

P06

5

P07

6

P20/ASCK/SCK0

P21/TxD/SO0

P22/RxD/SI0

P30/INTP0

P31/INTP1

P32/INTP2/CPT2

7

8

9

10

11

12 13 14 15 16 17 18 19 20 21 22

Caution Connect the IC pin directly to V^SS0or V^SS1.

Remark An item in parentheses applies to the µPD78F9026A only.

26

User's Manual U11919EJ3V0UM00

CHAPTER 1 GENERAL

ASCK

CPT2

IC

: Asynchronous Serial Clock

RESET

RxD

: Reset

: Capture Trigger Input

: Internally Connected

: Receive Data

: Serial Clock

: Serial Input

: Serial Output

: Timer Input

: Timer Output

: Transmit Data

: Power Supply

: Programming Power Supply

: Ground

SCK0

SI0

INTP0 to INTP2 : Interrupt from Peripherals

KR0 to KR7

NC

: Key Return

: Non-connection

: Port 0

SO0

TI0

P00 to P07

P10 to P17

P20 to P22

P30 to P32

P40 to P47

P50 to P53

TO0, TO2

TxD

: Port 1

: Port 2

V^DD0, V^DD1

V^PP

: Port 3

: Port 4

V^SS0, V^SS1

X1, X2

: Port 5

: Crystal

27

User's Manual U11919EJ3V0UM00

CHAPTER 1 GENERAL

1.5 Development of 78K/0S Series

The following shows the history of 78K/0S Series product development. Subseries names are shown inside

frames.

In production

Under development

For small-scale, general-

purpose applicationns

µ

Device developed by adding the subsystem clock to the PD789026

44-pin

PD789046

µ

Device developed by enhancing the timers of the

µ

PD789014 and

42/44-pin

28-pin

PD789026

PD789014

expanding ROM and RAM

With built-in UART bus and capable of low-voltage (1.8 V) operation

For small-scale, general-purpose

applications and A/D function

µ

PD789217AY

PD789197AY

44/48-pin

44-pin

RC oscillation of the

With built-in EEPROM^TMand SMB in the

Device developed by enhancing the A/D function of the

Device developed by enhancing the timers of the PD789104A

µPD789197AY

µ

PD789177

µ

PD789167

PD789177

PD789167

PD789156

PD789146

µ

44-pin

µ

30-pin

Device developed by enhancing the A/D function of the

µ

PD789146

With built-in EEPROM in the PD789104A

µ

30-pin

µ

PD789134A

µ

PD789124A

µ

PD789114A

µ

PD789104A

Device developed by enhancing the A/D function of the

µ

PD789124A

µ

RC oscillation of the PD789104A

30-pin

Device developed by enhancing the A/D function of the PD789104A

µ

30-pin

Device developed by adding the A/D function and multiplier to the

µ

PD789026

For inverter control

PD789842

µ

44-pin

With built-in inverter control circuit and UART bus

78K/0S

Series

For LCD driving

PD789830

µ

With built-in UART bus and dot LCD

88-pin

80-pin

µ

Device developed by enhancing the A/D function of the PD789407A

µ

PD789417A

PD789407A

µ

Device developed by enhancing the I/O of the PD789457

Device developed by enhancing the A/D function of the PD789447

RC oscillation of the PD789427

Device developed by enhancing the A/D funciton of the PD789427

80-pin

64-pin

µ

PD789457

PD789447

PD789437

PD789427

PD789316

PD789306

µ

Device developed by adding the A/D function of the PD789306

µ

RC oscillation of the PD789306

64-pin

Basic subseries for LCD driving

For ASSP

Device for a PC keyboard, with a built-in USB function

Device for a keypad, with a built-in POC

44-pin

20-pin

µ

PD789800

PD789840

PD789861

PD789860

RC oscillation of the PD789860

µ

Device for a keyless entry, with built-in POC and key return circuit

For IC card

PD789810

µ

5-pin

With built-in EEPROM and security circuit

28

User's Manual U11919EJ3V0UM00

CHAPTER 1 GENERAL

The following lists the main functional differences between subseries products.

Function

ROM

Timer

8-Bit 10-Bit

Serial Interface

I/O

V^DD

MIN.

Value

Remark

Capacity

A/D

8-Bit 16-Bit Watch WDT

Subseries Name

−

General µPD789046

16 K

1 ch

1 ch 1 ch 1 ch

1 ch (UART: 1 ch)

34 1.8 V

compact

−

µPD789026

4 K to 16 K

2 K to 4 K

−

µPD789014

2 ch

22

−

General µPD789217AY 16 K to 24 K 3 ch

1 ch 1 ch 1 ch

8 ch 2 ch UART: 1 ch

SMB : 1 ch

31 1.8 V RC oscillation,

compact

+ A/D

EEPROM on

chip

µPD789197AY

EEPROM on

chip

−

µPD789177

µPD789167

1 ch (UART: 1 ch)

−

4 ch

−

8 ch

−

µPD789156

µPD789146

8 K to 16 K

1 ch

20

EEPROM on

chip

4 ch

−

µPD789134A 2 K to 8 K

µPD789124A

4 ch

−

RC oscillation

4 ch

−

µPD789114A

4 ch

−

µPD789104A

4 ch

−

Inverter µPD789842

8 K to 16 K

24 K

3 ch Note 1 ch 1 ch 8 ch

1 ch (UART: 1 ch)

30

4.0 V

2.7 V

control

−

7 ch

−

LCD

drive

µPD789830

1 ch

1 ch 1 ch 1 ch

µPD789417A 12 K to 24 K 3 ch

µPD789407A

43 1.8 V

25

7 ch

−

µPD789457

µPD789447

µPD789437

µPD789427

µPD789316

µPD789306

µPD789800

µPD789840

µPD789861

µPD789860

16 K to 24 K 2 ch

4 ch 2 ch (UART: 1 ch)

RC oscillation

−

4 ch

−

4 ch

−

4 ch

−

8 K to 16 K

23

RC oscillation

−

4 ch

−

ASSP

8 K

4 K

6 K

2 ch

1 ch

−

1 ch

2 ch (USB: 1 ch)

31 4.0 V

29 2.8 V

1 ch

−

14 1.8 V RC oscillation

−

IC card µPD789810

1 ch

1

2.7 V EEPROM on

chip

29

User's Manual U11919EJ3V0UM00

CHAPTER 1 GENERAL

1.6 Block Diagram

8-bit TIMER

EVENT/COUNTER 00

TI0/TO0/P50

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

P00 to P07

P10 to P17

P20 to P22

P30 to P32

P40 to P47

P50 to P53

TO2/P51

16-bit TIMER 20

CPT2/INTP2/P32

78K/0S

ROM

CPU CORE

WATCHDOG TIMER

SCK0/ASCK/P20

SO0/TxD/P21

SI0/RxD/P22

SERIAL

INTERFACE 00

RAM

RESET

X1

INTP0/P30 to INTP2/

CPT2/P32

INTERRUPT

CONTROL

SYSTEM

CONTROL

V

DD0

DD1

V

SS0

SS1

IC

(V^PP

KR0/P40 to KR7/P47

X2

)

Remarks 1. The internal ROM and internal high-speed RAM capacities differ depending on the product.

2. An item in parentheses applies to the µPD78F9026A only.

30

User's Manual U11919EJ3V0UM00

CHAPTER 1 GENERAL

1.7 Outline of Functions

Part Number

µPD789022

µPD789024

µPD789025

µPD789026

µPD78F9026A

Item

Internal memory

ROM

Mask ROM

4 Kbytes

Flash Memory

16 Kbytes

8 Kbytes

12 Kbytes

512 bytes

16 Kbytes

High-speed RAM

256 bytes

Minimum instruction execution time

Instruction set

0.4/1.6 µs (when operated at 5.0 MHz with system clock)

• 16-bit operations

• Bit manipulations (set, reset, test), etc.

I/O port

Total

: 34

• CMOS input/output : 34

Serial interface

Timer

• 3-wire serial I/O mode/UART mode selectable: 1 channel

• 16-bit timer

: 1 channel

• 8-bit timer/event counter : 1 channel

• Watchdog timer

2

: 1 channel

Timer output

Vectored interrupt

source

Maskable

Internal: 5, External: 4

Internal: 1

Non-maskable

Power supply voltage

V^DD= 1.8 to 5.5 V

T^A= −40°C to +85°C

Operating ambient temperature

Package

• 44-pin plastic QFP (10 × 10

mm, resin thickness 2.7 mm)

• 44-pin plastic LQFP (10 × 10

mm, resin thickness 1.4 mm)

• 42-pin plastic shrink DIP (600 mil)

• 44-pin plastic QFP (10 × 10 mm, resin

thickness 2.7 mm)

• 44-pin plastic LQFP (10 × 10 mm, resin

thickness 1.4 mm)

The outline of the timer is as follows.

16-Bit Timer 20

8-Bit Timer/Event

Counter 00

Watchdog Timer

Operating

mode

Interval timer

−

1 channel

1 channel^Note

External event counter

Timer output

1 channel

−

1

Function

1 output

1 input

1

1 output

Capture

−

Interrupt source

1

Note Watchdog timer has a watchdog timer and interval timer functions. Select one of them.

31

User's Manual U11919EJ3V0UM00

[MEMO]

32

User's Manual U11919EJ3V0UM00

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

(1) Port pins

Pin Name Input/Output

Function

After Reset Alternate Function

P00 to P07 Input/output Port 0

Input

−

8-bit I/O port

I/O specifiable in 1-bit units

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P10 to P17 Input/output Port 1

−

8-bit I/O port

I/O specifiable in 1-bit units

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P20

P21

P22

Input/output Port 2

SCK0/ASCK

SO0/TxD

SI0/RxD

3-bit I/O port

I/O specifiable in 1-bit units

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P30

P31

P32

Input/output Port 3

INTP0

3-bit I/O port

INTP1

I/O specifiable in 1-bit units

INTP2/CPT2

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P40 to P47 Input/output Port 4

8-bit I/O port

KR0 to KR7

I/O specifiable in 1-bit units

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P50

Input/output Port 5

TI0/TO0

TO2

−

4-bit I/O port

P51

I/O specifiable in 1-bit units

P52, P53

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

33

User's Manual U11919EJ3V0UM00

CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins

Pin Name

INTP0

Input/Output

Input

Function

After Reset Alternate Function

External interrupt request input for which the active edge (rising

edge, falling edge, or both) can be specified

Input

P30

INTP1

P31

INTP2

P32/CPT2

P40 to P47

P22/RxD

P21/TxD

P20/ASCK

P20/SCK0

P22/SI0

P21/SO0

P51

KR0 to KR7 Input

Key return signal detection

Input

SI0

Input

3-wire serial interface serial data input

3-wire serial interface serial data output

SO0

SCK0

ASCK

RxD

TxD

TO2

CPT2

TI0

Output

Input/output 3-wire serial interface serial clock input/output

Input

Output

Input

Asynchronous serial interface serial clock input

Asynchronous serial interface serial data input

Asynchronous serial interface serial data output

16-bit timer (TM20) output

16-bit timer capture edge input

P32/INTP2

P50/TO0

P50/TI0

−

Input

External count clock input to 8-bit timer (TM00)

8-bit timer (TM00) output

TO0

X1

Output

Input

System clock oscillation crystal connection

−

X2

−

RESET

NC

Input

System reset input

Input

−

Not connected internally. Connect this pin directly to the V^SSpin

(it can also be left open).

−

V^DD0

V^DD1

V^SS0

V^SS1

IC

−

Positive power supply for ports

Positive power supply (except for ports)

Ground potential for ports

−

Ground potential (except for ports)

Internally connected. Connect this pin directly to the V^SS0or V^SS1

pin.

V^PP

−

Flash memory programming mode setting.

−

Apply high voltage during program write/verify. Connect this pin

directly to the V^SSpin in normal operating mode.

34

User's Manual U11919EJ3V0UM00

CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions

2.2.1 P00 to P07 (Port 0)

These pins constitute an 8-bit I/O port and can be set in the input or output port mode in 1-bit units by using port

mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used in the

pull-up resistor option register (PUO).

This port can drive LEDs directly.

2.2.2 P10 to P17 (Port 1)

These pins constitute an 8-bit I/O port. Can be set in the input or output port mode in 1-bit units by using port

mode register 1 (PM1). When these pins are used as an input port, an on-chip pull-up resistor can be used in the

pull-up resistor option register (PUO).

This port can drive LEDs directly.

2.2.3 P20 to P22 (Port 2)

These pins constitute a 3-bit I/O port. In addition, these pins provide the function to input/output the data and

clock of the serial interface.

This port can drive LEDs directly.

Port 2 can be specified in the following operation modes in bit-wise.

(1) Port mode

In this mode, port 2 functions as a 3-bit I/O port. Port 2 can be set in the input or output mode in 1-bit units

by using the port mode register 2 (PM2). When the port is used as an input port, an on-chip pull-up resistor

can be used in the pull-up resistor option register (PUO).

(2) Control mode

In this mode, port 2 functions as the data input/output and the clock input/output of the serial interface.

(a) SI0, SO0

These are the serial data I/O pins of the serial interface.

(b) SCK0

This is the serial clock I/O pin of the serial interface.

(c) RxD, TxD

These are the serial data I/O pins of asynchronous serial interface.

(d) ASCK

This is the serial clock input pin of asynchronous serial interface.

Caution When using port 2 as serial interface pins, the input/output mode and output latch must

be set according to the functions to be used. For details of the setting, see Table 9-2.

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CHAPTER 2 PIN FUNCTIONS

2.2.4 P30 to P32 (Port 3)

These pins constitute a 3-bit I/O port. In addition, they also function as external interrupt input and capture edge

input.

This port can drive LEDs directly.

Port 3 can be specified in the following operation modes in bit-wise.

(1) Port mode

In this mode, port 3 functions as a 3-bit I/O port. Port 3 can be set in the input or output mode in 1-bit units

by using the port mode register 3 (PM3). When the port is used as an input port, an on-chip pull-up resistor

can be used in the pull-up resistor option register (PUO).

(2) Control mode

In this mode, port 3 functions as the external interrupt input.

(a) INTP0 to INTP2

These pins input external interrupt for which effective edges (rising edge, falling edge, and both the rising

and falling edges) can be specified.

(b) CPT2

This is a capture edge input pin.

2.2.5 P40 to P47 (Port 4)

These pins constitute an 8-bit I/O port. In addition, they also function as key return signal detection.

This port can drive LEDs directly.

Port 4 can be set in the following operation modes in bit-wise.

(1) Port mode

In this mode, port 4 functions as an 8-bit I/O port which can be set in the input or output mode in 1-bit units

by using the port mode register 4 (PM4). When used as an input port, an on-chip pull-up resistor can be

used in the pull-up resistor option register (PUO).

(2) Control mode

In this mode, the pins of port 4 can be used as key return signal detection pin (KR0 to KR7).

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CHAPTER 2 PIN FUNCTIONS

2.2.6 P50 to P53 (Port 5)

These pins constitute a 4-bit I/O port. In addition, these pins provide the function for performing input/output

to/from the timer.

This port can drive LEDs directly.

Port 5 can be specified in the following operation modes in bit-wise.

(1) Port mode

In this mode, port 5 functions as a 4-bit I/O port. Port 5 can be set in the input or output mode in 1-bit units

by using the port mode register 5 (PM5). When the port is used as an input port, an on-chip pull-up resistor

can be used in the pull-up resistor option register (PUO).

(2) Control mode

In this mode, port 5 functions as the timer input/output.

(a) TI0

This is the external clock input pin for 8-bit timer/event counter.

(b) TO0

This is an 8-bit timer output pin.

(C) TO2

This is a 16-bit timer output pin.

2.2.7 RESET

This pin inputs an active-low system reset signal.

2.2.8 X1, X2

These pins are used to connect a crystal resonator for system clock oscillation.

To supply an external clock, input the clock to X1 and input the inverted signal to X2.

2.2.9 NC

The NC (Non-connection) pin is not connected internally. Connect this pin directly to the V^SSpin (it can also be

left open).

2.2.10 V^DD

Positive power supply pins

2.2.11 V^SS

Ground potential pins

2.2.12 V^PP(µPD78F9026A only)

A high voltage should be applied to this pin when the flash memory programming mode is set and when the

program is written or verified.

Directly connect this pin to the V^SS0or V^SS1pin in the normal operating mode.

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CHAPTER 2 PIN FUNCTIONS

2.2.13 IC (mask ROM model only)

The IC (Internally Connected) pin is used to set the µPD789026 Subseries in the test mode in testing before

shipment. In the normal operating mode, directly connect the IC pin to the V^SS0or V^SS1pin with as short a wire as

possible.

If a potential difference is generated between the IC pin and V^SS0or V^SS1pin due to a long wiring length between

these pins, or external noise is superimposed on the IC pin, the user program may not run correctly.

• Connect the IC pin directly to the V^SS0or V^SS1pin.

V

SS0 or VSS1 IC

Keep short

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CHAPTER 2 PIN FUNCTIONS

2.3 Pin Input/Output Circuits and Connection of Unused Pins

Types of input/output circuits for pins and recommended connection of unused pins are shown in Table 2-1.

For the configuration of each type of input/output circuit, see Figure 2-1.

Table 2-1. Type of Input/Output Circuit of Each Pin and Handling of Unused Pins

Pin Name

P00 to P07

I/O Circuit Type

5-X

Input/Output

Input/output

Recommended Connection for Unused Pins

Input: Connect these pins to the V^DD0, V^DD1, V^SS0, or V^SS1

pin via respective resistors.

P10 to P17

P20/ASCK/SCK0

P21/TxD/SO0

P22/RxD/SI0

P30/INTP0

Output: Leave these pins open.

8-J

5-X

8-J

P31/INTP1

P32/INTP2/CPT2

P40/KR0 to P47/KR7

P50/TI0/TO0

P51/TO2

5-X

P52, P53

RESET

2

Input

−

NC

−

Connect this pin directly to the V^SS0or V^SS1pin (possible

to leave open).

IC (mask ROM model)

Connect these pins directly to the V^SS0or V^SS1pin.

V^PP(µPD78F9026A)

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CHAPTER 2 PIN FUNCTIONS

Figure 2-1. List of Pin Input/Output Circuits

Type 8-J

Type 2

V

DD

Pullup

enable

P-ch

IN

V

DD0

Output

data

P-ch

IN/OUT

Schmitt-triggered input with hysteresis characteristics

Output

disable

N-ch

VSS0

VDD0

Type 5-X

Pullup

enable

P-ch

V

DD0

Output

data

P-ch

IN/OUT

Output

disable

N-ch

Port

read

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CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

The µPD789026 Subseries can access 64 Kbytes of memory space. Figures 3-1 through 3-5 show the memory

maps.

Figure 3-1. Memory Map (µPD789022)

FFFFH

Special Function Registers

256 × 8 bits

FF00H

FEFFH

Internal High-Speed RAM

256 × 8 bits

FE00H

FDFFH

Reserved

Data

Memory Space

0FFFH

1000H

0FFFH

Program Area

0080H

007FH

Program

Memory Space

Internal ROM

4,096 × 8 bits

CALLT Table Area

Program Area

0040H

003FH

002CH

002BH

Vector Table Area

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-2. Memory Map (µPD789024)

FFFFH

Special Function Registers

256 × 8 bits

FF00H

FEFFH

Internal High-Speed RAM

256 × 8 bits

FE00H

FDFFH

Reserved

Data

Memory Space

1FFFH

2000H

1FFFH

Program Area

0080H

007FH

Program

Memory Space

Internal ROM

8,192 × 8 bits

CALLT Table Area

Program Area

0040H

003FH

002CH

002BH

Vector Table Area

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-3. Memory Map (µPD789025)

FFFFH

Special Function Registers

256 × 8 bits

FF00H

FEFFH

Internal High-Speed RAM

512 × 8 bits

FD00H

FCFFH

Reserved

Data

Memory Space

2FFFH

3000H

2FFFH

Program Area

0080H

007FH

Program

Memory Space

Internal ROM

12,288 × 8 bits

CALLT Table Area

Program Area

0040H

003FH

002CH

002BH

Vector Table Area

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-4. Memory Map (µPD789026)

FFFFH

Special Function Registers

256 × 8 bits

FF00H

FEFFH

Internal High-Speed RAM

512 × 8 bits

FD00H

FCFFH

Reserved

Data

Memory Space

3FFFH

4000H

3FFFH

Program Area

0080H

007FH

Program

Memory Space

Internal ROM

16,384 × 8 bits

CALLT Table Area

Program Area

0040H

003FH

002CH

002BH

Vector Table Area

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-5. Memory Map (µPD78F9026A)

FFFFH

Special Function Registers

256 × 8 bits

FF00H

FEFFH

Internal High-Speed RAM

512 × 8 bits

FD00H

FCFFH

Reserved

Data

Memory Space

3FFFH

4000H

3FFFH

Program Area

0080H

007FH

Program

Memory Space

Internal Flash Memory

16,384 × 8 bits

CALLT Table Area

Program Area

0040H

003FH

002CH

002BH

Vector Table Area

0000H

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CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the

program counter (PC).

The µPD789026 Subseries provides the internal ROMs (or flash memory) containing the following capacities on

each product.

Table 3-1. Internal ROM Capacity

Part Number

Internal ROM

Structure

Mask ROM

Capacity

µPD789022

4,096 × 8 bits

8,192 × 8 bits

12,288 × 8 bits

16,384 × 8 bits

µPD789024

µPD789025

µPD789026

µPD78F9026A

Flash memory

The following areas are allocated to the internal program memory space:

(1) Vector table area

A 44-byte area of addresses 0000H to 002BH is reserved as a vector table area. This area stores program

start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16-

bit program address, the low-order 8 bits are stored in an even address, and the high-order 8 bits are stored

in an odd address.

Table 3-2. Vector Table

Vector Table Address

0000H

Interrupt Request

RESET input

Vector Table Address

000CH

Interrupt Request

INTSR/INTCSI0

0004H

0006H

0008H

000AH

INTWDT

INTP0

INTP1

INTP2

000EH

0010H

0014H

002AH

INTST

INTTM0

INTTM2

INTKR

(2) CALLT instruction table area

In a 64-byte area of addresses 0040H to 007FH, the subroutine entry address of a 1-byte call instruction

(CALLT) can be stored.

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CHAPTER 3 CPU ARCHITECTURE

3.1.2 Internal data memory (internal high-speed RAM) space

The µPD789026 Subseries provides internal high-speed RAM containing the following capacity on each product.

The internal high-speed RAM can also be used as a stack memory.

Table 3-3. Internal High-Speed RAM Capacity

Part Number

µPD789022

Capacity

256 × 8 bits

µPD789024

µPD789025

µPD789026

µPD78F9026A

512 × 8 bits

3.1.3 Special function register (SFR) area

Special function registers (SFRs) of on-chip peripheral hardware are allocated to an area of FF00H to FFFFH

(see Table 3-4).

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CHAPTER 3 CPU ARCHITECTURE

3.1.4 Data memory addressing

The µPD789026 Subseries provides a variety of addressing modes which take account of memory

manipulability, etc. Especially at address corresponding to data memory area (FE00H to FFFFH^{Note 1}, FD00H to

FFFFH^{Note 2}), particular addressing modes are possible to meet the functions of the special function registers (SFR)

and other registers. Figures 3-6 through 3-10 show the data memory addressing modes.

Notes 1. With µPD789022 or µPD789024

2. With µPD789025, µPD789026, or µPD78F9026A

Figure 3-6. Data Memory Addressing (µPD789022)

FFFFH

Special Function Registers (SFR)

SFR Addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

Short Direct

Addressing

Internal High-Speed RAM

256 × 8 bits

FE20H

FE1FH

FE00H

FDFFH

Direct Addressing

Register Indirect

Addressing

Based Addressing

Reserved

1000H

0FFFH

Internal ROM

4,096 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-7. Data Memory Addressing (µPD789024)

FFFFH

Special Function Registers (SFR)

SFR Addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

Short Direct

Addressing

Internal High-Speed RAM

256 × 8 bits

FE20H

FE1FH

FE00H

FDFFH

Direct Addressing

Register Indirect

Addressing

Based Addressing

Reserved

2000H

1FFFH

Internal ROM

8,192 × 8 bits

0000H

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Figure 3-8. Data Memory Addressing (µPD789025)

FFFFH

Special Function Registers (SFR)

SFR Addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

Short Direct

Addressing

Internal High-Speed RAM

512 × 8 bits

FE20H

FE1FH

FD00H

FCFFH

Direct Addressing

Register Indirect

Addressing

Based Addressing

Reserved

3000H

2FFFH

Internal ROM

12,288 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-9. Data Memory Addressing (µPD789026)

FFFFH

Special Function Registers (SFR)

SFR Addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

Short Direct

Addressing

Internal High-Speed RAM

512 × 8 bits

FE20H

FE1FH

FD00H

FCFFH

Direct Addressing

Register Indirect

Addressing

Based Addressing

Reserved

4000H

3FFFH

Internal ROM

16,384 × 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-10. Data Memory Addressing (µPD78F9026A)

FFFFH

Special Function Registers (SFR)

SFR Addressing

256 × 8 bits

FF20H

FF1FH

FF00H

FEFFH

Short Direct

Addressing

Internal High-Speed RAM

512 × 8 bits

FE20H

FE1FH

FD00H

FCFFH

Direct Addressing

Register Indirect

Addressing

Based Addressing

Reserved

4000H

3FFFH

Internal Flash Memory

16,384 × 8 bits

0000H

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3.2 Processor Registers

The µPD789026 Subseries provides the following on-chip processor registers:

3.2.1 Control registers

The control registers contains special functions to control the program sequence statuses and stack memory. A

program counter, a program status word, and a stack pointer are control registers.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be

executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction

to be fetched. When a branch instruction is executed, immediate data or register contents is set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-11. Program Counter Configuration

15

0

PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction

execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are automatically restored upon execution of the RETI and POP PSW

instructions.

RESET input sets PSW to 02H.

Figure 3-12. Program Status Word Configuration

7

0

IE

Z

0

AC

0

1

CY

PSW

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(a) Interrupt enable flag (IE)

This flag controls interrupt request acknowledge operations of the CPU.

When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable

interrupt are disabled.

When IE = 1, the interrupt enabled (EI) status is set and interrupt request acknowledgement is controlled

with an interrupt mask flag for each interrupt source.

This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI

instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.

(c) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all

other cases.

(d) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out

value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction

execution.

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(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed

RAM area can be set as the stack area.

Figure 3-13. Stack Pointer Configuration

15

0

SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)

from the stack memory.

Each stack operation saves/restores data as shown in Figures 3-14 and 3-15.

Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before

instruction execution.

Figure 3-14. Data to be Saved to Stack Memory

Interrupt

PUSH rp

Instruction

CALL, CALLT

Instructions

_

SP SP

SP

3

2

1

_

SP SP

SP

2

1

SP SP

SP

2

1

PC7 to PC0

PC15 to PC8

PSW

Lower Half

Register Pairs

SP

PC7 to PC0

Upper Half

Register Pairs

SP

PC15 to PC8

SP

Figure 3-15. Data to be Restored from Stack Memory

POP rp

RET Instruction

RETI Instruction

Instruction

Lower Half

Register Pairs

SP

SP + 1

PC7 to PC0

SP

PC7 to PC0

PC15 to PC8

PSW

Upper Half

Register Pairs

PC15 to PC8

SP + 1

SP + 2

SP SP + 2

SP SP + 3

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3.2.2 General-purpose registers

A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).

In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit

register (AX, BC, DE, and HL).

They can be written in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute

names (R0 to R7 and RP0 to RP3).

Figure 3-16. General-Purpose Register Configuration

(a) Absolute Names

16-Bit Processing

RP3

8-Bit Processing

R7

R6

R5

R4

RP2

RP1

RP0

R3

R2

R1

R0

15

0

7

0

(b) Functional Names

16-Bit Processing

HL

8-Bit Processing

H

L

D

E

DE

BC

AX

B

C

A

X

15

0

7

0

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3.2.3 Special function register (SFR)

Unlike a general-purpose register, each special function register has a special function.

It is allocated in the 256-byte area FF00H to FFFFH.

The special function register can be manipulated, like the general-purpose register, with the operation, transfer,

and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function

register type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation

Writes a symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). This

manipulation can also be specified with an address.

• 8-bit manipulation

Writes a symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). This manipulation

can also be specified with an address.

• 16-bit manipulation

Writes a symbol reserved with assembler for the 16-bit manipulation instruction operand. When specifying an

address, write an even address.

Table 3-4 lists the special function register. The meanings of the symbols in this table are as follows:

• Symbol

Indicates the addresses of the incorporated special function registers. The symbols shown in this column are

the reserved words of the assembler, and have already been defined in the header file called "sfrbit.h" of C

compiler. Therefore, these symbols can be used as instruction operands if assembler or integrated debugger

is used.

• R/W

Indicates whether the special function register can be read or written.

R/W

R

: Read/write

: Read only

: Write only

W

• Bit units for manipulation

Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.

• After reset

Indicates the status of the special function register when the RESET signal is input.

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Table 3-4. Special Function Registers (1/2)

Address Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

After Reset

00H

1 Bit

8 Bits

Ο

16 Bits

FF00H Port 0

P0

P1

P2

P3

P4

P5

R/W

Ο

−

FF01H Port 1

Ο

FF02H Port 2

Ο

FF03H Port 3

Ο

FF04H Port 4

Ο

FF05H Port 5

Ο

SIO00

FF10H Transmit shift register 00

Receive buffer register 00

FF16H 16-bit compare register 20

FF17H

TXS00

RXB00

CR20

W

R

Ο

FFH

−

Ο

Undefined

FFFFH

Ο^{Note 1}

Ο^{Note 2}

W

−

FF18H 16-bit timer counter 20

FF19H

TM20

R

−

0000H

Undefined

FFH

TCP20

FF1AH 16-bit capture register 20

FF1BH

FF20H Port mode register 0

FF21H Port mode register 1

FF22H Port mode register 2

FF23H Port mode register 3

FF24H Port mode register 4

FF25H Port mode register 5

FF42H Timer clock select register 2

FF50H 8-bit compare register 00

FF51H 8-bit timer counter 00

FF53H 8-bit timer mode control register 00

FF5BH 16-bit timer mode control register 20

PM0

R/W

Ο

−

Ο

−

PM1

PM2

PM3

PM4

PM5

TCL2

CR00

TM00

TMC00

TMC20

ASIM00

00H

W

R

−

Undefined

00H

−

R/W

Ο

FF70H Asynchronous serial interface mode

register 00

FF71H Asynchronous serial interface status

register 00

ASIS00

CSIM00

R

Ο

−

FF72H Serial operation mode register 00

R/W

Ο

−

Ο

−

FF73H Baud rate generator control register 00

BRGC00

Notes 1. CR20, TM20, and TCP20 are designed for 16-bit access. They can also be accessed in 8-bit mode,

however. In 8-bit access mode, use direct addressing.

2. 16-bit access is allowed only with short direct addressing.

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Table 3-4. Special Function Registers (2/2)

Address Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

After Reset

00H

1 Bit

8 Bits

Ο

16 Bits

FFE0H Interrupt request flag register 0

FFE1H Interrupt request flag register 1

FFE4H Interrupt mask flag register 0

FFE5H Interrupt mask flag register 1

FFECH External interrupt mode register 0

FFF5H Key return mode register 00

FFF7H Pull-up resistor option register

FFF9H Watchdog timer mode register

FFFAH Oscillation settling time select register

FFFBH Processor clock control register

IF0

IF1

R/W

Ο

−

Ο

MK0

Ο

FFH

MK1

Ο

INTM0

KRM00

PUO

Ο

00H

Ο

−

Ο

WDTM

OSTS

PCC

Ο

04H

02H

Ο

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3.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents. PC contents are normally incremented

(+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another

instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC

and branched by the following addressing (For details of each instruction, refer to 78K/0S Series User's Manual

Instruction (U11047E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The

displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In

other words, the range of branch in relative addressing is between -128 and +127 of the start address of the

following instruction.

This function is carried out when the "BR $addr16" instruction or a conditional branch instruction is executed.

[Illustration]

15

0

...

PC is the start address of

the next instruction of

a BR instruction.

PC

+

8

7

6

α

S

jdisp8

15

0

PC

When S = 0, α indicates all bits "0".

When S = 1, α indicates all bits "1".

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3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.

CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces.

[Illustration]

In case of CALL !addr16 or BR !addr16 instruction

7

0

CALL or BR

Low Addr.

High Addr.

15

8 7

0

PC

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3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by the low-order-5-bit

immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and

branched.

Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can

refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces.

[Illustration]

7

6

1

5

1

0

Instruction Code

Effective Address

0

ta4-0

15

8

0

7

0

6

1

5

1

0

7

Memory (Table)

Low Addr.

0

High Addr.

Effective Address + 1

15

8

7

0

PC

3.3.4 Register addressing

[Function]

Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)

and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

7

0

8

7

0

rp

A

X

15

PC

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CHAPTER 3 CPU ARCHITECTURE

3.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) which undergo

manipulation during instruction execution.

3.4.1 Direct addressing

[Function]

The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier

addr16

Description

Label or 16-bit immediate data

[Example]

MOV A, !FE00H; When setting !addr16 to FE00H

Instruction Code

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OP Code

00H

FEH

[Illustration]

7

0

OP Code

addr16 (Low)

addr16 (High)

Memory

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3.4.2 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal high-

speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH,

respectively.

The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of all SFR areas. In this

area, ports which are frequently accessed in a program and a compare register of the timer/event counter are

mapped, and these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,

bit 8 is set to 1. See [Illustration].

[Operand format]

Identifier

saddr

Description

Label or FE20H to FF1FH immediate data

Label or FE20H to FF1FH immediate data (even address only)

saddrp

[Example]

MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H

Instruction Code

1

0

1

0

1

0

1

0

1

0

1

0

OP Code

30H (saddr-offset)

50H (immediate data)

[Illustration]

7

0

OP Code

saddr-offset

Short Direct Memory

15

8

0

Effective

Address

1

α

When 8-bit immediate data is 20H to FFH, α = 0.

When 8-bit immediate data is 00H to 1FH, α = 1.

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3.4.3 Special function register (SFR) addressing

[Function]

The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction

word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR

mapped at FF00H to FF1FH can also be accessed with short direct addressing.

[Operand format]

Identifier

sfr

Description

Special function register name

[Example]

MOV PM0, A; When selecting PM0 for sfr

Instruction Code

1

0

1

0

1

0

1

0

1

0

1

0

[Illustration]

7

0

OP Code

sfr-offset

SFR

15

1

8 7

0

Effective

Address

1

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CHAPTER 3 CPU ARCHITECTURE

3.4.4 Register addressing

[Function]

The general-purpose register is accessed as an operand. The general-purpose register to be accessed is

specified with register specification code and functional name in the instruction code.

Register addressing is carried out when an instruction with the following operand format is executed. When an

8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

[Operand format]

Identifier

Description

r

X, A, C, B, E, D, L, H

AX, BC, DE, HL

rp

'r' and 'rp' can be written with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,

B, E, D, L, H, AX, BC, DE, and HL).

[Example]

MOV A, C; When selecting the C register for r

Instruction Code

0

1

0

1

0

1

0

1

Register Specification Code

INCW DE; When selecting the DE register pair for rp

Instruction Code

1

0

1

0

Register Specification Code

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3.4.5 Register indirect addressing

[Function]

The memory is addressed with the contents of the register pair specified as an operand. The register pair to be

accessed is specified with the register pair specification code in the instruction code. This addressing can be

carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[DE], [HL]

[Example]

MOV A, [DE]; When selecting register pair [DE]

Instruction Code

0

1

0

1

0

1

[Illustration]

15

8

7

0

DE

D

E

Memory address specified

by register pair DE

The contents of addressed

memory are transferred

7

0

A

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3.4.6 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is

used to address the memory. Addition is performed by expanding the offset data as a positive number to 16

bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[HL+byte]

[Example]

MOV A, [HL+10H]; When setting byte to 10H

Instruction Code

0

1

0

1

0

1

0

1

0

3.4.7 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN

instructions are executed or the register is saved/restored upon generation of an interrupt request.

Stack addressing enables to access the internal high-speed RAM area only.

[Example]

In the case of PUSH DE

Instruction Code

1

0

1

0

1

0

1

0

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CHAPTER 4 PORT FUNCTIONS

4.1 Functions of Ports

The µPD789026 Subseries provides the ports shown in Figure 4-1, enabling various methods of control.

Alternate functions are provided in addition to the digital I/O port function. For more information on these

alternate functions, see Chapter 2.

Figure 4-1. Port Types

P20

P22

P00

Port 2

Port 3

Port 0

P30

P32

P07

P10

P40

Port 4

Port 5

Port 1

P47

P50

P53

P17

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Table 4-1. Port Functions

Pin Name

Input/Output

Function

After Reset Alternate Function

P00 to P07

Input/output Port 0

Input

−

8-bit I/O port

I/O specifiable in 1-bit units

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P10 to P17

Input/output Port 1

−

8-bit I/O port

I/O specifiable in 1-bit units

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P20

P21

P22

Input/output Port 2

SCK0/ASCK

SO0/TxD

SI0/RxD

3-bit I/O port

I/O specifiable in 1-bit units

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P30

P31

P32

Input/output Port 3

INTP0

3-bit I/O port

INTP1

I/O specifiable in 1-bit units

INTP2/CPT2

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P40 to P47

Input/output Port 4

KR0 to KR7

8-bit I/O port

I/O specifiable in 1-bit units

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

P50

Input/output Port 5

TI0/TO0

TO2

−

4-bit I/O port

P51

I/O specifiable in 1-bit units

P52, P53

When used as input port, on-chip pull-up resistor can be

connected by setting of the pull-up resistor option register (PUO).

LEDs can be driven directly.

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CHAPTER 4 PORT FUNCTIONS

4.2 Port Configuration

Ports have the following hardware configuration.

Table 4-2. Port Configuration

Configuration

Parameter

Control register

Port mode register (PMm: m = 0 to 5)

Pull-up resistor option register (PUO)

Port

Total: 34 (input/output: 34)

Pull-up resistor

Total: 34 (on-chip pull-up resistor can be connected by software)

4.2.1 Port 0

This is an 8-bit I/O port with output latch. Port 0 can be specified in the input or output mode in 1-bit units by

using the port mode register 0 (PM0). When using P00 to P07 pins as input port pins, on-chip pull-up resistors can

be connected in 8-bit units by using the pull-up resistor option register (PUO).

RESET input sets port 0 to input mode.

Figure 4-2 shows the block diagram of port 0.

Figure 4-2. Block Diagram of P00 to P07

VDD0

WRPUO

PUO0

P-ch

RD

WR^PORT

Output Latch

(P00 to P07)

P00 to P07

WRPM

PM00 to PM07

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 0 read signal

WR : Port 0 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.2 Port 1

This is an 8-bit I/O port with output latch. Port 1 can be specified in the input or output mode in 1-bit units by

using the port mode register 1 (PM1). When using P10 to P17 pins as input port pins, on-chip pull-up resistors can

be connected in 8-bit units by using the pull-up resistor option register (PUO).

RESET input sets port 1 to input mode.

Figure 4-3 shows the block diagram of port 1.

Figure 4-3. Block Diagram of P10 to P17

VDD0

WRPUO

PUO1

P-ch

RD

WR^PORT

Output Latch

(P10 to P17)

P10 to P17

WRPM

PM10 to PM17

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 1 read signal

WR : Port 1 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.3 Port 2

This is a 3-bit I/O port with output latch. Port 2 can be specified in the input or output mode in 1-bit units by using

the port mode register 2 (PM2). When using P20 to P22 pins as input port pins, on-chip pull-up resistors can be

connected in 3-bit units by using the pull-up resistor option register (PUO).

The pins of this port are also used as the data I/O and clock I/O pins of the serial interface.

RESET input sets port 2 to input mode.

Figures 4-4 through 4-6 show the block diagrams of port 2.

Caution When using the pins of port 2 as the serial interface, the I/O mode and output latch must be set

according to the function to be used. For details of the settings, see Table 9-2.

Figure 4-4. Block Diagram of P20

V

DD0

WR^PUO

PUO2

P-ch

Alternate

Function

RD

WR^PORT

Output Latch

(P20)

P20/ASCK/SCK0

WRPM

PM20

Alternate

Function

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 2 read signal

WR : Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-5. Block Diagram of P21

VDD0

WRPUO

PUO2

P-ch

RD

WR^PORT

Output Latch

(P21)

P21/TxD/SO0

WRPM

PM21

Alternate

Function

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 2 read signal

WR : Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-6. Block Diagram of P22

V

DD0

WRPUO

PUO2

P-ch

Alternate

Function

RD

WR^PORT

Output Latch

(P22)

P22/RxD/SI0

WRPM

PM22

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 2 read signal

WR : Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.4 Port 3

This is a 3-bit I/O port with output latch. It can be specified in input or output mode in 1-bit units by using the port

mode register 3 (PM3). When using P30 to P32 pins as input port pins, on-chip pull-up resistors can be connected

in 3-bit units by using the pull-up resistor option register (PUO).

The pins of this port are also used as the external interrupt input and capture edge input.

RESET input sets port 3 to input mode.

Figure 4-7 shows the block diagram of port 3.

Figure 4-7. Block Diagram of P30 to P32

VDD0

WRPUO

PUO3

P-ch

Alternate

Function

RD

WR^PORT

Output Latch

(P30 to P32)

P30/INTP0

P31/INTP1

P32/INTP2/

CPT2

WRPM

PM30 to PM32

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 3 read signal

WR : Port 3 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.5 Port 4

This is an 8-bit I/O port with output latch. Port 4 can be specified in the input or output mode in 1-bit units by

using port mode register 4 (PM4). When using P40 to P47 pins as input port pins, on-chip pull-up resistors can be

connected in 8-bit units by using the pull-up resistor option register (PUO).

The pins of this port are also used as the key return input.

RESET input sets port 4 to input mode.

Figure 4-8 shows the block diagram of port 4.

Caution When using port 4 for the key return function, it is necessary to set key return mode register 00.

For details of the settings, see Section 10.3 (5).

Figure 4-8. Block Diagram of P40 to P47

VDD0

WR^PUO

PUO4

P-ch

RD

WRKRM00

WR^PORT

WRPM

KRM000 to KRM007

Output Latch

(P40 to P47)

P40/KR0 to

P47/KR7

PM40 to PM47

Alternate

Function

KRM00 : Key return mode register 00

PUO : Pull-up resistor option register

PM

RD

WR

: Port mode register

: Port 4 read signal

: Port 4 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.6 Port 5

This is a 4-bit I/O port with output latch. Port 5 can be specified in the input or output mode in 1-bit units by using

the port mode register 5 (PM5). When using P50 to P53 pins as input port pins, on-chip pull-up resistors can be

connected in 4-bit units by using the pull-up resistor option register (PUO).

The pins of this port are also used as the data I/O pins of the timer.

RESET input sets port 5 to input mode.

Figures 4-9 through 4-11 show the block diagrams of port 5.

Figure 4-9. Block Diagram of P50

VDD0

WR^PUO

PUO5

P-ch

Alternate

Function

RD

WR^PORT

Output Latch

(P50)

P50/TI0/TO0

WRPM

PM50

Alternate

Function

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 5 read signal

WR : Port 5 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-10. Block Diagram of P51

VDD0

WR^PUO

PUO5

P-ch

RD

WR^PORT

Output Latch

(P51)

P51/TO2

WRPM

PM51

Alternate

Function

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 5 read signal

WR : Port 5 write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-11. Block Diagram of P52 and P53

V

DD0

WRPUO

PUO5

P-ch

RD

WR^PORT

Ouput Latch

(P52, P53)

P52, P53

WRPM

PM52, PM53

PUO : Pull-up resistor option register

PM : Port mode register

RD : Port 5 read signal

WR : Port 5 write signal

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CHAPTER 4 PORT FUNCTIONS

4.3 Port Function Control Registers

The following two types of registers control the ports.

• Port mode registers (PM0 to PM5)

• Pull-up resistor option register (PUO)

(1) Port mode registers (PM0 to PM5)

These registers are used to set port input/output in 1-bit units.

Port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to FFH.

When port pins are used as alternate-function pins, set the port mode register and output latch according to

Table 4-3.

Caution As port 3 has an alternate function as external interrupt input, when the port function

output mode is specified and the output level is changed, the interrupt request flag is set.

When the output mode is used, therefore, the interrupt mask flag should be set to 1

beforehand.

Table 4-3. Port Mode Register and Output Latch Settings when Using Alternate Functions

Pin Name

Alternate Function

Name

PM××

P××

Input/Output

Input

P30

P31

P32

INTP0

INTP1

INTP2

CPT2

KR0 to KR7

TI0

1

0

×

0

Input

P40 to P47^Note

P50

Input

Output

TO0

P51

TO2

Note When an alternate function is used, set the key return mode register 00 (KRM00) to 1 (see Section

10.3 (5)).

Caution When Port 2 is used for serial interface pin, the I/O mode and output latch must be set

according to its function. For details of the settings, see Table 9-2.

Remark

×

: Don't care

PM×× : Port mode register

P×× : Output latch of port

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CHAPTER 4 PORT FUNCTIONS

Figure 4-12. Port Mode Register Format

Symbol

PM0

7

6

5

4

3

2

1

0

Address

FF20H

After Reset

FFH

R/W

PM07

PM06

PM05

PM04

PM03

PM02

PM01

PM00

PM1

PM2

PM3

PM4

PM5

PM17

PM16

PM15

PM14

PM13

1

PM12

PM22

PM32

PM42

PM52

PM11

PM21

PM31

PM41

PM51

PM10

PM20

PM30

PM40

PM50

FF21H

FF22H

FF23H

FF24H

FF25H

FFH

R/W

1

PM47

1

PM46

1

PM45

1

PM44

1

PM43

PM53

Pmn Pin Input/Output Mode Selection

m = 0, 1, 4 : n = 0 to 7

PMmn

m = 2, 3

m = 5

: n = 0 to 2

: n = 0 to 3

0

1

Output mode (output buffer ON)

Input mode (output buffer OFF)

(2) Pull-up resistor option register (PUO)

The pull-up resistor option register (PUO) sets whether an on-chip pull-up resistor on each port is used or

not.

On the port which is specified to use the on-chip pull-up resistor in the PUO, the pull-up resistor can be

internally used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits

set in the output mode in spite of setting the PUO. On-chip pull-up resistors cannot be used either when the

pins are used as the alternate-function output pins.

PUO is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PUO to 00H.

Figure 4-13. Pull-Up Resistor Option Register Format

Symbol

PUO

7

0

6

0

<5>

<4>

<3>

<2>

<1>

<0>

Address

FFF7H

After Reset

00H

R/W

PUO5

PUO4

PUO3

PUO2

PUO1

PUO0

PUOm

Port m On-Chip Pull-Up Resistor Selection

(m = 0 to 5)

On-chip pull-up resistor not used

On-chip pull-up resistor used

0

1

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CHAPTER 4 PORT FUNCTIONS

4.4 Operation of Port Functions

The operation of a port differs depending on whether the port is set in the input or output mode, as described

below.

4.4.1 Writing to I/O port

(1) In output mode

A value can be written to the output latch of a port by using a transfer instruction. The contents of the

output latch can be output from the pins of the port.

The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

A value can be written to the output latch by using a transfer instruction. However, the status of the port pin

is not changed because the output buffer is OFF.

The data once written to the output latch is retained until new data is written to the output latch.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.

However, this instruction accesses the port in 8-bit units. When this instruction is

executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the

contents of the output latch of the pin that is set in the input mode and not subject to

manipulation become undefined.

4.4.2 Reading from I/O port

(1) In output mode

The contents of an output latch can be read by using a transfer instruction. The contents of the output latch

are not changed.

(2) In input mode

The status of a pin can be read by using a transfer instruction. The contents of the output latch are not

changed.

4.4.3 Arithmetic operation of I/O port

(1) In output mode

An arithmetic operation can be performed with the contents of an output latch. The result of the operation is

written to the output latch. The contents of the output latch are output from the port pins.

The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

The contents of the output latch become undefined. However, the status of the pin is not changed because

the output buffer is OFF.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.

However, this instruction accesses the port in 8-bit units. When this instruction is

executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the

contents of the output latch of the pin that is set in the input mode and not subject to

manipulation become undefined.

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[MEMO]

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CHAPTER 5 CLOCK GENERATION CIRCUIT

5.1 Function of Clock Generation Circuit

The clock generation circuit generates the clock to be supplied to the CPU and peripheral hardware. The system

clock oscillator consists of the following type.

• System clock oscillator

This circuit oscillates at frequencies of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP

instruction.

5.2 Configuration of Clock Generation Circuit

The clock generation circuit consists of the following hardware.

Table 5-1. Configuration of Clock Generation Circuit

Item

Control register

Oscillator

Configuration

Processor clock control register (PCC)

System clock oscillator

Figure 5-1. Block Diagram of Clock Generation Circuit

Prescaler

Clock to Peripheral

Hardware

X1

X2

System Clock

Oscillator

Prescaler

f

X

f

X

2²

Standby

Control

Circuit

STOP

Wait Control

Circuit

CPU Clock (fCPU

)

PCC1

Processor Clock Control Register (PCC)

Internal Bus

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CHAPTER 5 CLOCK GENERATION CIRCUIT

5.3 Register Controlling Clock Generation Circuit

The clock generation circuit is controlled by the following register:

• Processor clock control register (PCC)

(1) Processor clock control register (PCC)

PCC sets CPU clock selection and the ratio of division.

PCC is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PCC to 02H.

Figure 5-2. Processor Clock Control Register Format

Symbol

PCC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Address

FFFBH

After Reset

02H

R/W

PCC1

CPU Clock (fCPU) Selection

0

1

f

X

(0.2 µs)

/2²(0.8 µs)

Caution Be sure to set bit 0 and bits 2 to 7 to 0.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to opration at f^X= 5.0 MHz.

3. Minimum instruction execution time: 2 f^CPU

• When f^CPU= 0.2 µs : 0.4 µs

• When f^CPU= 0.8 µs : 1.6 µs

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5.4 System Clock Oscillation Circuits

5.4.1 System clock oscillation circuit

The system clock oscillation circuit is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected

across the X1 and X2 pins.

An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the

reversed signal to the X2 pin.

Figure 5-3 shows the external circuit of the system clock oscillation circuit.

Figure 5-3. External Circuit of System Clock Oscillation Circuit

(a) Crystal or ceramic oscillation

(b) External clock

V

X1

SS0, VSS1

External

Clock

X1

X2

Crystal

or

Ceramic Resonator

Caution When using the system clock oscillator circuit, to avoid influence of wiring capacity, etc., wire

the portion enclosed by the broken line in Figure 5-3 as follows:

• Keep the wiring length as short as possible.

• Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a

line through which a high alternating current flows.

• Always keep the ground of the capacitor of the oscillation circuit at the same potential as V^SS.

Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not extract signals from the oscillation circuit.

Figure 5-4 shows incorrect examples of resonator connection.

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Figure 5-4. Incorrect Examples of Resonator Connection (1/2)

(a) Too long wiring

(b) Crossed signal line

PORTn

(n = 0 to 5)

VSS0, VSS1

X1

X2

VSS0, VSS1

X1

X2

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Figure 5-4. Incorrect Examples of Resonator Connection (2/2)

(c) Wiring near high alternating current

(d) Current flowing through ground line of oscillation

circuit (potential at points A, B, and C fluctuates)

V

DD

P

mn

V

SS0, VSS1

X1

X2

V

SS0, VSS1 X1

X2

A

B

C

High Current

(e) Signal is extracted

V

SS0, VSS1

X1

X2

5.4.2 Divider circuit

The divider circuit divides the output of the system clock oscillation circuit (f^X) to generate various clocks.

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5.5 Operation of Clock Generation Circuit

The clock generation circuit generates the following clocks and controls operation modes of the CPU, such as

the standby mode:

• System clock

• CPU clock

f^X

f^CPU

• Clock to peripheral hardware

The operation of the clock generation circuit is determined by the processor clock control register (PCC), as

follows:

(a) The slow mode 2 f^CPU(1.6 µs: at 5.0-MHz operation) of the system clock is selected when the RESET signal

is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is

stopped .

(b) Two types of CPU clocks f^CPU(0.2 µs and 0.8 µs: at 5.0-MHz operation) can be selected by the PCC

setting.

(c) Two standby modes, STOP and HALT, can be used.

(d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral

hardware is stopped when the system clock is stopped (except, however, the external clock input

operation).

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5.6 Changing Setting of System Clock and CPU Clock

5.6.1 Time required for switching between system clock and CPU clock

The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC).

Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old

clock is used for the duration of several instructions after that (see Table 5-2).

Table 5-2. Maximum Time Required for Switching CPU Clock

Set Value before Switching

PCC1

Set Value after Switching

PCC1

0

PCC1

1

0

1

4 clocks

2 clocks

Remark Two clocks are the minimum instruction execution

time of the CPU clock before switching.

5.6.2 Switching CPU clock

The following figure illustrates how the CPU clock switches.

Figure 5-5. Switching CPU Clock

VDD

RESET

CPU Clock

Slow

Operation

High-Speed

Operation

Wait (6.55 ms: at 5.0-MHz operation)

Internal Reset Operation

<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is

released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the

time during which oscillation settles (2¹⁵/f^X) is automatically secured.

After that, the CPU starts instruction execution at the slow speed of the system clock (1.6 µs: at 5.0-MHz

operation).

<2> After the time during which the V^DDvoltage rises to the level at which the CPU can operate at the high

speed has elapsed, the processor clock control register (PCC) is rewritten so that the high speed can be

selected.

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6.1 16-Bit Timer Functions

16-bit timer 20 has the following functions.

• Timer interrupt

• Timer output

• Count value capture

(1) Timer interrupt

An interrupt is generated when a count value and compare value matches.

(2) Timer output

Timer output control is possible when a count value and compare value matches.

(3) Count value capture

A TM20 count value is latched synchronizing with the capture trigger and retained.

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6.2 16-Bit Timer Configuration

16-bit timer 20 is configured in the following hardware.

Table 6-1. Configuration of 16-Bit Timer 20

Configuration

Item

Timer counter

16 bits × 1 (TM20)

Register

Compare register : 16 bits × 1 (CR20)

Capture register : 16 bits × 1 (TCP20)

Timer output

1 (TO20)

Control register

16-bit timer mode control register 20 (TMC20)

Port mode register 5 (PM5)

Figure 6-1. Block Diagram of 16-Bit Timer 20

Internal Bus

16-Bit Timer Mode

Control Register 20

(TMC20)

P51

Output Latch

PM51

TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20

TO2/P51

INTTM2

F/F

TOD20

16-Bit Timer Mode

Control Register 20

16-Bit Compare Register 20 (CR20)

Match

f

X

/2²

/2⁶

OVF

16-Bit Timer Counter 20 (TM20)

CPT2/P32/

INTP2

Edge Detection

Circuit

16-Bit Capture

Register 20 (TCP20)

16-Bit Counter

Read Buffer

Internal Bus

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(1) 16-bit compare register 20 (CR20)

This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and

when they match, generates an interrupt request (INTTM2).

CR20 is set with a 16-bit memory manipulation instruction. The 0000H to FFFFH values can be set.

RESET input sets this register to FFFFH.

Cautions 1. This register is manipulated with a 16-bit memory manipulation instruction, however

an 8-bit memory manipulation instruction can be used. When manipulated with an 8-

bit memory manipulation instruction, accessing method should be direct addressing.

This register can be accessed only in short direct addressing mode when a 16-bit

memory manipulation instruction is used.

2. When rewriting CR20 during count operation, set CR20 to interrupt disable from

interrupt mask flag register 0 (MK0) beforehand. Beside, set the timer output data to

inversion disable by 16-bit timer mode control register 20 (TMC20).

If CR20 is rewritten with the interrupt enabled, an interrupt request may be issued

immediately.

(2) 16-bit timer counter 20 (TM20)

This is a 16-bit register that counts count pulses.

TM20 is read with a 16-bit memory manipulation instruction.

This register is in free running during count clock input.

RESET input clears this register to 0000H and after that to be in free running.

Cautions 1. The count value after releasing stop becomes undefined because the count operation

is executed during the oscillation settling time.

2. This register is manipulated with a 16-bit memory manipulation instruction, however

an 8-bit memory manipulation instruction can be used. When manipulated with an 8-

bit memory manipulation instruction, accessing method should be direct addressing.

This register can be accessed only in short direct addressing mode when a 16-bit

memory manipulation instruction is used.

3. When manipulated with an 8-bit memory manipulation instruction, readout should be

performed in the order from low-order byte to high-order byte and must be in pairs.

(3) 16-bit capture register 20 (TCP20)

This is a 16-bit register that captures the contents of 16-bit timer counter 20 (TM20).

TCP20 is set with a 16-bit memory manipulation instruction.

RESET input makes this register undefined.

Caution This register is manipulated with a 16-bit memory manipulation instruction, however an 8-

bit memory manipulation instruction can be used. When manipulated with an 8-bit

memory manipulation instruction, accessing method should be direct addressing. This

register can be accessed only in short direct addressing mode when a 16-bit memory

manipulation instruction is used.

(4) 16-bit counter read buffer

This buffer latches a counter value and retains a count value of 16-bit timer counter 20 (TM20).

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6.3 Registers Controlling 16-Bit Timer

The following two types of registers control 16-bit timer 20.

• 16-bit timer mode control register 20 (TMC20)

• Port mode register 5 (PM5)

(1) 16-bit timer mode control register 20 (TMC20)

16-bit timer mode control register 20 (TMC20) controls the setting of a count clock, capture edge, etc.

TMC20 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC20 to 00H.

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Figure 6-2. 16-Bit Timer Mode Control Register 20 Format

7

<6>

5

4

3

2

1

<0>

Symbol

TMC20

Address After Reset

FF5BH 00H

R/W

TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20

R/W^Note

TOD20

Timer Output Data

Overflow Flag Set

0

1

Timer output data is 0.

Timer output data is 1.

TOF20

0

1

Clear by reset and software

Set by overflow of 16-bit timer

CPT201 CPT200

Capture Edge Selection

0

1

0

1

0

1

Capture operation disabled

Rising edge of CPT2

Falling edge of CPT2

Both edges of CPT2

TOC20

Timer Output Data Inverse Control

0

1

Inverse disabled

Inverse enabled

TCL201 TCL200

16-bit Timer Counter 20 Count Clock Selection

/2²(1.25 MHz)

/2⁶(78.1 kHz)

0

1

f

X

f

Other than above

Setting prohibited

16-bit Timer 20 Output Control

TOE20

0

1

Output disabled (port mode)

Output enabled

Note Bit 7 is read-only.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

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(2) Port mode register 5 (PM5)

This register sets the input/output of port 5 in 1-bit units.

To use the P51/TO2 pin for timer output, set the output latch of PM51 and P51 to 0.

PM5 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM5 to FFH.

Figure 6-3. Port Mode Register 5 Format

7

1

6

1

5

1

4

1

3

2

1

0

Symbol

PM5

Address After Reset R/W

FF25H FFH R/W

PM53

PM52

PM51

PM50

PM51

P51 Pin Input/Output Selection

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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6.4 16-Bit Timer Operation

6.4.1 Operation as timer interrupt

In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare

register 20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200.

To operate the 16-bit timer as a timer interrupt, the following settings are required.

• Set count values in CR20

• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 6-4.

Figure 6-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation

TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20

TMC20

-

0/1

0

0/1

Setting of Count Clock (see Table 6-2)

Caution If 0 is set both to CPT201 and CPT200 flags, capture edge becomes setting prohibited.

When the count value of 16-bit timer counter 20 (TM20) coincides with the value set to CR20, counting of TM20

continues and an interrupt request signal (INTTM2) is generated.

Table 6-2 shows interval time, and Figure 6-5 shows timing of timer interrupt operation.

Caution Perform the following processing when rewriting CR20 during count operation.

<1> Disable the interrupt (TMMK20 (bit 7 of interrupt mask flag register 0 (MK0)) = 1).

<2> Disable inversion control of timer output data (TOC20 = 0).

If CR20 is rewritten with the interrupt enabled, an interrupt request may be issued

immediately.

Table 6-2. Interval Time of 16-Bit Timer 20

TCL201

TCL200

Count Clock

Interval Time

2¹⁸/f^X(52.4 ms)

2²²/f^X(838.9 ms)

0

1

2²/f^X(0.8 µs)

0

2⁶/f^X(12.8 µs)

Other than above

Setting prohibited

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

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Figure 6-5. Timer Interrupt Operation Timing

t

Count Clock

TM20 Count Value

CR20

0000H

0001H

N

FFFFH 0000H 0001H

N

FFFFH

N

INTTM2

Interrupt Accepted

TO20

TOF20

Overflow Flag Set

Remark N = 0000H to FFFFH

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6.4.2 Operation as timer output

Timer outputs are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance

based on the intervals of the value set in TCL201 and TCL200.

To operate the 16-bit timer as a timer output, the following settings are required.

• Set P51 to output mode (PM51 = 0).

• Set 0 to the output latch of P51.

• Set the count value in CR20.

• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 6-6.

Figure 6-6. Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation

TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20

TMC20

-

0/1

1

0

0/1

1

TO20 Output Enable

Setting of Count Clock (see Table 6-2)

Inverse Enable of Timer Output Data

Caution If both CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation

prohibited.

When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of the

TO2/P51 pin is inverted. This enables timer output. At that time, TM20 count is continued and an interrupt request

signal (INTTM2) is generated.

Figure 6-7 shows the timing of timer output (see Table 6-2 for the interval time of the 16-bit timer).

Figure 6-7. Timer Output Timing

t

Count Clock

TM20 Count Value

CR20

0000H

0001H

N

FFFFH 0000H 0001H

N

FFFFH

N

INTTM2

Interrupt Accepted

TO20^Note

TOF20

Overflow Flag Set

Note The TO20 initial value becomes low level during output enable (TOE20 = 1).

Remark N = 0000H to FFFFH

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6.4.3 Capture operation

The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20)

synchronizing with a capture trigger.

Set as shown in Figure 6-8 to allow the 16-bit timer to start the capture operation.

Figure 6-8. Setting Contents of 16-Bit Timer Mode Control Register 20 during Capture Operation

TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20

TMC20

-

0/1

0

0/1

Count Clock Selection

Capture Edge Selection (see Table 6-3)

16-bit capture register 20 (TCP20) starts capture operation after being detected a CPT20 capture trigger edge,

and latches and retains the count value of 16-bit timer counter 20. TCP20 fetches count value within 2 clocks and

retains the count value until the next capture edge detection.

Table 6-3 and Figure 6-9 show the setting contents of capture edge and capture operation timing, respectively.

Table 6-3. Setting Contents of Capture Edge

CPT201

CPT200

Capture Edge Selection

0

1

0

1

0

1

Capture operation prohibited

CPT2 pin rising edge

CPT2 pin falling edge

CPT2 pin both edges

Caution Because TCP20 is rewritten when a capture trigger edge is detected during TCP20 read, disable

the capture trigger detection during TCP20 read.

Figure 6-9. Capture Operation Timing (Both Edges of CPT2 Pin are Specified)

Count Clock

TM20

Count Read Buffer

TCP20

0000H 0001H

N

M - 1

M

Undefined

N

M

Capture Start

CPT2

Capture Edge Detection

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6.4.4 16-bit timer counter 20 readout

The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction.

TM20 readout is performed through a counter read buffer. The counter read buffer latches the TM20 count

value. And buffer operation is pended at the CPU clock falling edge after the read signal of the TM20 lower byte

rises and the count value is retained. The counter read buffer value at the retention state can be read out as the

count value.

Cancellation of pending is performed at the CPU clock falling edge after the read signal of TM20 higher byte falls.

RESET input clears TM20 to 0000H and starts freerunning.

Figure 6-10 shows the timing of 16-bit timer counter 20 readout.

Cautions 1. The count value after releasing stop becomes undefined because the count operation is

executed during oscillation settling time.

2. Though TM20 is a dedicated register of a 16-bit transfer instruction, an 8-bit transfer

instruction can be used.

When using the 8-bit transfer instruction, execute by direct addressing.

3. When using the 8-bit transfer instruction, execute in the order from lower byte to higher

byte in pairs. If the only lower byte is read, the pending state of the counter read buffer is

not canceled, and if the only higher byte is read, an undefined count value is read.

Figure 6-10. 16-Bit Timer Counter 20 Readout Timing

CPU Clock

Count Clock

TM20

Count Read Buffer

TM20 Read Signal

0000H

0001H

N

N + 1

N

Read Signal Latch

Prohibited Period

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER

7.1 8-Bit Timer/Event Counter Functions

8-bit timer/event counter 00 (TM00) has the following functions:

• Interval timer

• External event counter

• Square wave output

(1) 8-bit interval timer

When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at any time

intervals set in advance.

Table 7-1. Interval Time of 8-Bit Timer/Event Counter 00

Minimum Interval Time

1/f^X(200 ns)

2⁵/f^X(6.4 µs)

Maximum Interval Time

2⁸/f^X(51.2 µs)

2¹³/f^X(1.64 ms)

Resolution

1/f^X(200 ns)

2⁵/f^X(6.4 µs)

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

(2) External event counter

The number of pulses of an externally input signal can be measured.

(3) Square wave output

A square wave of arbitrary frequency can be output.

Table 7-2. Square Wave Output Range of 8-Bit Timer/Event Counter 00

Minimum Pulse Width

Maximum Pulse Width

2⁸/f^X(51.2 µs)

2¹³/f^X(1.64 ms)

Resolution

1/f^X(200 ns)

2⁵/f^X(6.4 µs)

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

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7.2 8-Bit Timer/Event Counter Configuration

The 8-bit timer/event counter consists of the following hardware configuration.

Table 7-3. Configuration of 8-Bit Timer/Event Counter 00

Item

Timer counter

Register

Configuration

8 bits × 1 (TM00)

Compare register: 8 bits × 1 (CR00)

1 (TO0)

Timer output

Control register

8-bit timer mode control register 00 (TMC00)

Port mode register 5 (PM5)

Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 00

Internal Bus

8-Bit Compare Register 00

(CR00)

P50

Output Latch

PM50

Match

INTTM0

f

X

8-Bit Timer Counter 00

(TM00)

/2⁵

TO0/P50/TI0

f

X

F/F

Clear

Selector

TI0/P50/TO0

2

TCE00 TCL001 TCL000 TOE00

8-Bit Timer Mode Control Register 1

Internal Bus

(1) 8-bit compare register 00 (CR00)

This is an 8-bit register to compare the value set to CR00 with the 8-bit timer register 00 (TM00) count

value, and if they match, generates an interrupt request (INTTM0).

CR00 is set with an 8-bit memory manipulation instruction. The 00H to FFH values can be set.

RESET input makes CR00 undefined.

Caution Before rewriting CR00, stop the timer operation. If CR00 is rewritten while the timer

operation is enabled, the coincidence interrupt request signal may be generated

immediately.

(2) 8-bit timer counter 00 (TM00)

This is an 8-bit register to count pulses.

TM00 is read with an 8-bit memory manipulation instruction.

RESET input clears TM00 to 00H.

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7.3 8-Bit Timer/Event Counter Control Registers

The following two types of registers are used to control the 8-bit timer/event counter.

• 8-bit timer mode control register 00 (TMC00)

• Port mode register 5 (PM5)

(1) 8-bit timer mode control register 00 (TMC00)

TMC00 determines whether to enable or disable 8-bit timer counter 00 (TM00), specifies the count clock for

TM00, and controls the operation of the output control circuit of 8-bit timer/event counter 00.

TMC00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC00 to 00H.

Figure 7-2. 8-Bit Timer Mode Control Register 00 Format

Symbol <7>

6

0

5

0

4

0

3

0

2

1

<0>

Address

FF53H

After Reset

00H

R/W

TMC00 TCE00

TCL001 TCL000 TOE00

TCE00

8-Bit Timer Counter 00 Operation Control

0

1

Operation disabled (TM00 is cleared to 0.)

Operation enabled

TCL001 TCL000

8-Bit Timer Counter 00 Count Clock Selection

0

1

0

1

0

1

f

X

(5.0 MHz)

/2⁵(156 kHz)

Rising edge of TI0^Note

Falling edge of TI0^Note

TOE00

8-Bit Timer/Event Counter 00 Output Control

0

1

Output disabled (port mode)

Output enabled

Note When inputting a clock signal eternally, timer output cannot be used.

Caution Always stop the timer before setting TMC00.

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

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(2) Port mode register 5 (PM5)

This register sets port 5 input/output in 1-bit units.

When using the P50/TI0/TO0 pin for timer output, set PM50 and the output latch of P50 to 0.

PM5 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM5 to FFH.

Figure 7-3. Port Mode Register 5 Format

7

1

6

1

5

1

4

1

3

2

1

0

Symbol

PM5

Address After Reset

FF25H FFH

R/W

PM53

PM52

PM51

PM50

P50 Pin Input/Output Mode Selection

0

1

Output mode (output buffer ON)

Input mode (output buffer OFF)

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7.4 8-Bit Timer/Event Counter Operation

7.4.1 Operation as interval timer

Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare

register 00 (CR00) in advance.

To operate the 8-bit timer/event counter as an interval timer, the following settings are required.

<1> Disable the operation of 8-bit timer counter 00 (TM00) (TCE00 (bit 7 of 8-bit timer mode control register 00

(TMC00)) = 0).

<2> Set the count clock of the 8-bit timer/event counter (see Table 7-4).

<3> Set a count value in CR00.

<4> Enable the operation of TM00 (TCE00 = 1).

When the count value of the 8-bit timer counter 00 (TM00) coincides with the value set to CR00, the value of

TM00 is cleared to 0 and TM00 continues counting. At the same time, an interrupt request signal (INTTM0) is

generated.

Table 7-4 shows interval time, and Figure 7-4 shows the timing of interval timer operation.

Cautions 1. Before rewriting CR00, stop the timer operation. If CR00 is rewritten while the timer

operation is enabled, the coincidence interrupt request signal may be generated

immediately.

2. If setting the count clock in TMC00 and enabling the operation of TM00 are performed at the

same time with an 8-bit memory manipulation instruction, the error one cycle after the timer

has been started may exceed one clock. To use the 8-bit timer/event counter as an interval

timer, therefore, perform the setting in the above sequence.

Table 7-4. Interval Time of 8-Bit Timer/Event Counter 00

TCL001

TCL000

Minimum Interval Time

1/f^X(200 ns)

Maximum Interval Time

2⁸/f^X(51.2 µs)

Resolution

1/f^X(200 ns)

0

1

0

1

0

1

2⁵/f^X(6.4 µs)

2¹³/f^X(1.64 ms)

2⁵/f^X(6.4 µs)

TI0 input cycle

2⁸× TI0 input cycle

TI0 input edge cycle

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

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Figure 7-4. Interval Timer Operation Timing

t

Count Clock

TM00 Count Value

00

01

N

00

01

N

00

01

N

Clear

CR00

N

TCE00

Count Start

INTTM0

Interrupt Accepted

Interval Time

Interrupt Accepted

Interval Time

TO0

Interval Time

Remark Interval time = (N + 1) × t

where N = 00H to FFH

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7.4.2 Operation as external event counter

The external event counter counts the number of external clock pulses input to the TI0/P50/TO0 pin by using

timer counter 00 (TM00).

To operate the 8-bit timer/event counter as an external event counter, the following settings are required.

<1> Set P50 to input mode (PM50 = 1).

<2> Disable the operation of 8-bit timer counter 00 (TM00) (TCE00 (bit 7 of 8-bit timer mode control register 00

(TMC00)) = 0).

<3> Specify the rising or falling edge of TI0 (see Table 7-4).

<4> Set a count value in CR00.

<5> Enable the operation of TM00 (TCE00 = 1).

Each time the valid edge specified by the bit 1 or 2 (TCL001 or TCL000) of TMC00 is input, the value of 8-bit

timer counter 00 (TM00) is incremented.

When the count value of TM00 coincides with the value set to CR00, the value of TM00 is cleared to 0 and TM00

continues counting. At the same time, an interrupt request signal (INTTM0) is generated.

Figure 7-5 shows the timing of external event counter operation (with rising edge specified).

Cautions 1. Before rewriting CR00, stop the timer operation. If CR00 is rewritten while the timer

operation is enabled, the coincidence interrupt request signal may be generated

immediately.

2. If setting the count clock in TMC00 and enabling the operation of TM00 are performed at the

same time with an 8-bit memory manipulation instruction, the error one cycle after the timer

has been started may exceed one clock. To use the 8-bit timer/event counter as an external

event counter, therefore, perform the setting in the above sequence.

Figure 7-5. External Event Counter Operation Timing (with Rising Edge Specified)

TI0 Pin Input

TM00 Count Value

CR00

00

01

02

03

04

05

N

N - 1

N

00

01

02

03

TCE00

INTTM0

Remark N = 00H to FFH

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7.4.3 Operation as square wave output

The 8-bit timer/event counter can generate the output square waves of arbitrary frequency at intervals specified

by the count value set to 8-bit compare register 00 (CR00) in advance.

To operate 8-bit timer/event counter 00 as square wave output, the following settings are required.

<1> Set P50 to output mode (PM50 = 0).

<2> Set 0 for the output latch of P50.

<3> Disable the operation of 8-bit timer counter 00 (TM00) (TCE00 (bit 7 of 8-bit timer mode control register 00

(TMC00)) = 1).

<4> Set a count clock for 8-bit timer/event counter 00 and enable output of TO0 (TOE00 (bit 0 of TMC00) = 1).

<5> Set a count value in CR00.

<6> Enable the operation of TM00 (TCE00 = 1).

When the count value of 8-bit timer counter 00 (TM00) matches the value set in CR00, the TO0/P50/TI0 pin

output will be inverted, respectively. Through application of this mechanism, square waves of any frequency can be

output. As soon as a match occurred, the TM00 value will be cleared to 0 then resume to count, generating an

interrupt request signal (INTTM0).

Setting 0 to the bit 7 in TMC00, that is, TCE00 makes the square-wave output clear to 0.

Table 7-5 lists square wave output range, and Figure 7-6 shows timing of square wave output.

Cautions 1. Before rewriting CR00, stop the timer operation. If CR00 is rewritten while the timer

operation is enabled, the coincidence interrupt request signal may be generated

immediately.

2. If setting the count clock in TMC00 and enabling the operation of TM00 are performed at the

same time with an 8-bit memory manipulation instruction, the error one cycle after the timer

has been started may exceed one clock. To use the 8-bit timer/event counter as a square

wave output, therefore, perform the setting in the above sequence.

Table 7-5. Square Wave Output Range of 8-Bit Timer/Event Counter 00

TCL001

TCL000

Minimum Pulse Width

1/f^X(200 ns)

2⁵/f^X(6.4 µs)

Maximum Pulse Width

2⁸/f^X(51.2 µs)

2¹³/f^X(1.64 ms)

Resolution

1/f^X(200 ns)

2⁵/f^X(6.4 µs)

0

1

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

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Figure 7-6. Square Wave Output Timing

Count Clock

TM00 Count Value

00

01

N

00

01

N

00

01

N

Clear

CR00

N

TCE00

Count Start

INTTM0

Interrupt Accepted

TO0^Note

Note The initial value of TO0 at output enable (TOE00 = 1) becomes low-level.

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7.5 Notes on Using 8-Bit Timer/Event Counters

(1) Error on starting timer

An error of up to 1 clock occurs after the timer has been started until a coincidence signal is generated.

This is because 8-bit timer counter 00 (TM00) started asynchronously with the count pulse.

Figure 7-7. 8-Bit Timer Counter 00 Start Timing

Count Pulse

TM00 Count Value

00H

01H

02H

03H

04H

Timer starts

(2) Setting of 8-bit compare register

8-bit compare register 00 (CR00) can be set to 00H.

Therefore, one pulse can be counted when an 8-bit timer/event counter operates as an event counter.

Figure 7-8. External Event Counter Operation Timing

TI0 Input

CR00

TM00 Count Value

00H

Interrupt Request Flag

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CHAPTER 8 WATCHDOG TIMER

8.1 Watchdog Timer Functions

The watchdog timer has the following functions:

• Watchdog timer

• Interval timer

Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode

register (WDTM).

(1) Watchdog timer

The watchdog timer is used to detect inadvertent program loops. When an inadvertent loop is detected, a

non-maskable interrupt or the RESET signal can be generated.

Table 8-1. Inadvertent Loop Detection Time of Watchdog Timer

Inadvertent Loop

Detection Time

At f^X= 5.0 MHz

2

¹¹× 1/f^X

410 µs

¹³× 1/f^X

¹⁵× 1/f^X

¹⁷× 1/f^X

1.64 ms

6.55 ms

26.2 ms

f^X: System clock oscillation frequency

(2) Interval timer

The interval timer generates an interrupt at a given interval set in advance.

Table 8-2. Interval Time

Interval

At f^X= 5.0 MHz

410 µs

2

¹¹× 1/f^X

¹³× 1/f^X

¹⁵× 1/f^X

¹⁷× 1/f^X

1.64 ms

6.55 ms

26.2 ms

f^X: System clock oscillation frequency

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8.2 Watchdog Timer Configuration

The watchdog timer consists of the following hardware.

Table 8-3. Configuration of Watchdog Timer

Configuration

Item

Control register

Timer clock select register 2 (TCL2)

Watchdog timer mode register (WDTM)

Figure 8-1. Block Diagram of Watchdog Timer

Internal Bus

f

X

TMMK4

Prescaler

2⁴

f

X

f

X

f

X

2⁶

2⁸

2¹⁰

INTWDT

Maskable

TMIF4

Interrupt Request

Control

7-Bit Counter

RESET

Circuit

INTWDT

Clear

Non-Maskable

Interrupt Request

3

TCL22 TCL21 TCL20

RUN WDTM4 WDTM3

Timer Clock Select Register 2

(TCL2)

Watchdog Timer Mode Register

(WDTM)

Internal Bus

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8.3 Watchdog Timer Control Registers

The following two types of registers are used to control the watchdog timer.

•

Timer clock select register 2 (TCL2)

Watchdog timer mode register (WDTM)

(1) Timer clock select register 2 (TCL2)

This register sets the watchdog timer count clock.

TCL2 is set with an 8-bit memory manipulation instruction.

RESET input clears TCL2 to 00H.

Figure 8-2. Timer Clock Select Register 2 Format

Symbol

TCL2

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FF42H

After Reset

00H

R/W

TCL22

TCL21 TCL20

TCL22

TCL21 TCL20

Watchdog Timer Count Clock Selection

/2⁴(312.5 kHz)

Interval Time

2¹¹/f

2¹³/f

2¹⁵/f

2¹⁷/f

X

(410 s)

µ

f

X

0

1

0

1

0

1

0

/2⁶(78.1 kHz)

(1.64 ms)

(6.55 ms)

(26.2 ms)

/2⁸(19.5 kHz)

/2¹⁰(4.88 kHz)

Other than above

Setting prohibited

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

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(2) Watchdog timer mode register (WDTM)

This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog

timer.

WDTM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears WDTM to 00H.

Figure 8-3. Watchdog Timer Mode Register Format

<7>

6

0

5

0

4

3

2

0

1

0

Address

FFF9H

After Reset

00H

R/W

Symbol

WDTM

RUN

WDTM4 WDTM3

Selects Operation of Watchdog Timer^{Note 1}

RUN

0

1

Stops counting.

Clears counter and starts counting.

Selects Operation Mode of Watchdog Timer^{Note 2}

WDTM4 WDTM3

0

1

0

1

0

1

Operation stop

Interval timer mode (overflow and maskable interrupt occur)^{Note 3}

Watchdog timer mode 1 (overflow and non-maskable interrupt occur)

Watchdog timer mode 2 (overflow occurs and reset operation started)

Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is

started, it cannot be stopped by any means other than RESET input.

2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software.

3. The watchdog timer starts operations as an interval timer when RUN is set to 1.

Cautions 1. When the watchdog timer is cleared by setting 1 to RUN, the actual overflow time is up

to 0.8% shorter than the time set by timer clock select register 2 (TCL2).

2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of

interrupt request flag register 0 (IF0)) being set to 0. When watchdog timer mode 1 or 2

is selected under the condition where TMIF4 is 1, a non-maskable interrupt occurs at

the completion of rewriting.

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8.4 Operation of Watchdog Timer

8.4.1 Operation as watchdog timer

The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode

register (WDTM) is set to 1.

The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2

(TCL20 to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer

is started. Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has been

started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the

inadvertent loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the

value of bit 3 (WDTM3) of WDTM.

The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to

1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.

Caution The actual inadvertent loop detection time may be up to 0.8% shorter than the set time.

Table 8-4. Inadvertent Loop Detection Time of Watchdog Timer

TCL22

TCL21

TCL20

Inadvertent Loop Detection Time

At f^X= 5.0 MHz

410 µs

0

1

0

1

0

1

0

2

¹¹× 1/f^X

¹³× 1/f^X

¹⁵× 1/f^X

¹⁷× 1/f^X

2

1.64 ms

6.55 ms

26.2 ms

f^X: System clock oscillation frequency

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8.4.2 Operation as interval timer

When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1

respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time

intervals specified by a count value set in advance.

Select a count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2

(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.

In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be

generated. The priority of INTWDT is set as the highest of all the maskable interrupts.

The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1

before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the

interval timer mode is not set, unless the RESET signal is input.

2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the

set time.

Table 8-5. Interval Time of Interval Timer

TCL22

TCL21

TCL20

Interval Time

At f^X= 5.0 MHz

410 µs

0

1

0

1

0

1

0

2

¹¹× 1/f^X

¹³× 1/f^X

¹⁵× 1/f^X

¹⁷× 1/f^X

1.64 ms

6.55 ms

26.2 ms

f^X: System clock oscillation frequency

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CHAPTER 9 SERIAL INTERFACE 00

9.1 Serial Interface 00 Functions

Serial interface 00 employs the following three modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

• 3-wire serial I/O mode

(1) Operation stop mode

This mode is used when serial transfer is not carried out. It enables power consumption reduction.

(2) Asynchronous serial interface (UART) mode

In this mode, one byte of data following the start bit is transmitted/received, and full-duplex operation is

possible.

A UART-dedicated baud rate generator is incorporated, allowing communication over a wide range of baud

rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.

(3) 3-wire serial I/O mode (MSB/LSB start bit switchable)

In this mode, 8-bit data transfer is carried out with three lines, one for serial clock (SCK0) and two for serial

data (SI0, SO0).

The 3-wire serial I/O mode supports simultaneous transmit and receive operation, reducing data transfer

processing time.

It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus

allowing connection to devices with either start bit.

The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/Os such as the

75XL Series, 78K Series, and 17K Series, which have internal conventional synchronous serial interface.

9.2 Serial Interface 00 Configuration

Serial interface 00 has the following hardware configuration.

Table 9-1. Configuration of Serial Interface 00

Item

Configuration

Register

Transmission shift register 00 (TXS00)

Receive shift register 00 (RXS00)

Receive buffer register 00 (RXB00)

Control register

Serial operation mode register 00 (CSIM00)

Asynchronous serial interface mode register 00 (ASIM00)

Asynchronous serial interface status register 00 (ASIS00)

Baud rate generator control register 00 (BRGC00)

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S e l e c t o r

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(1) Transmit shift register 00 (TXS00)

This register is used to specify data to be transmitted. Data written to TXS00 is transmitted as serial data.

If the data length is specified as 7 bits, bits 0 to 6 of the data written to TXS00 are transferred as the

transmit data. The transmit operation is started by writing data to TXS00.

TXS00 is written to with an 8-bit memory manipulation instruction. It cannot be read.

RESET input sets TXS00 to FFH.

Caution Do not write to TXS00 during transmission.

TXS00 and receive buffer register 00 (RXB00) are allocated to the same address, and when

reading is performed, RXB00 values are read.

(2) Receive shift register 00 (RXS00)

This register is used to convert serial data input to the RxD pin into parallel data. Each time one byte of

data is received, it is transferred to receive buffer register 00 (RXB00).

RXS00 cannot be manipulated directly by program.

(3) Receive buffer register 00 (RXB00)

This register is used to hold received data. Each time one byte of data is received, a new byte of data is

transferred from receive shift register 00 (RXS00).

If the data length is specified as 7 bits, receive data is transferred to bits 0 to 6 of RXB00, and the MSB of

RXB00 always becomes 0.

RXB00 can be read with an 8-bit memory manipulation instruction. It cannot be written to.

RESET input makes RXB00 undefined.

Caution RXB00 and transmit shift register 00 (TXS00) are allocated to the same address, and when

writing is performed, the values are written to TXS00.

(4) Transmit control circuit

This circuit controls transmit operations by adding a start bit, parity bit, and stop bit to data written to

transmit shift register 00 (TXS00), according to the data set to asynchronous serial interface mode register

00 (ASIM00).

(5) Receive control circuit

This circuit controls receive operations according to the data set to asynchronous serial interface mode

register 00 (ASIM00). It performs also parity error check, etc., during receive operations, and when an error

is detected, it sets the value to asynchronous serial interface status register 00 (ASIS00) depending on the

nature of the error.

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9.3 Serial Interface 00 Control Register

The following four types of registers are used to control serial interface 00.

• Serial operation mode register 00 (CSIM00)

• Asynchronous serial interface mode register 00 (ASIM00)

• Asynchronous serial interface status register 00 (ASIS00)

• Baud rate generator control register 00 (BRGC00)

(1) Serial operation mode register 00 (CSIM00)

This register is set when using serial interface 00 in the 3-wire serial I/O mode.

CSIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSIM00 to 00H.

Figure 9-3. Serial Operation Mode Register 00 Format

<7>

6

0

5

0

4

0

3

0

2

1

0

Address

FF72H

After Reset

00H

R/W

Symbol

CSIM00 CSIE00

DIR00 CSCK00

CSIE00

Operation Control in 3-Wire Serial I/O Mode

0

1

Operation stop

Operation enable

DIR00

Start Bit Specification

MSB

LSB

0

1

CSCK00

Clock Selection in 3-Wire Serial I/O Mode

0

1

Input clock to SCK0 pin from external

Dedicated baud rate generator output

Cautions 1. Be sure to set bit 0 and bits 3 to 6 to 0.

2. Set 00H to CSIM00 at the UART mode.

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(2) Asynchronous serial interface mode register 00 (ASIM00)

This register is set when using serial interface 00 in the asynchronous serial interface mode.

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

Figure 9-4. Asynchronous Serial Interface Mode Register 00 Format

Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FF70H

After Reset

00H

R/W

TXE00 RXE00

PS001

PS000

CL00

SL00

TXE00

Transmit Operation Control

Receive Operation Control

Parity Bit Specification

0

1

Transmit operation stop

Transmit operation enable

RXE00

0

1

Receive operation stop

Receive operation enable

PS001 PS000

0

1

No parity

Always add 0 parity at transmission

Parity check is not performed at reception (No parity error is generated)

Odd parity

Even parity

1

0

1

CL00

Character Length Specification

0

1

7 bits

8 bits

SL00

Transmit Data Stop Bit Length Specification

0

1

1 bit

2 bits

Cautions 1. Be sure to set bits 0 and 1 to 0.

2. Set 00H to ASIM00 at the 3-wire serial I/O mode.

3. Switching operating modes must be performed after the halt of serial transmit/receive

operation.

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Table 9-2. Serial Interface 00 Operating Mode Settings

(1) Operation stop mode

ASIM00

CSIM00

PM22 P22 PM21 P21 PM20 P20 Start Shift P22/SI0/RxD P21/SO0/TxD P20/SCK0/ASCK

Bit Clock Pin Function Pin Function Pin Function

TXE00 RXE00 CSIE00 DIR00

CSCK00

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

0

×

−

P22

P21

P20

Other than above

Setting prohibited

(2) 3-wire serial I/O mode

ASIM00

CSIM00

PM22 P22 PM21 P21 PM20 P20 Start Shift P22/SI0/RxD P21/SO0/TxD P20/SCK0/ASCK

Bit Clock Pin Function Pin Function

Pin Function

TXE00 RXE00 CSIE00 DIR00

CSCK00

0

Note 2

×

0

1

0

1

1^{Note 2}

0

1

0

1

0

×

1

×

1

MSB

SI0^{Note 2}

SO0

SCK0 input

External

clock

(CMOS output)

1

0

1

SCK0 output

SCK0 input

SCK0 output

Internal

clock

LSB

External

clock

Internal

clock

Other than above

Setting prohibited

(3) Asynchronous serial interface mode

ASIM00

CSIM00

PM22 P22 PM21 P21 PM20 P20 Start Shift P22/SI0/RxD P21/SO0/TxD P20/SCK0/ASCK

Bit Clock Pin Function Pin Function

Pin Function

TXE00 RXE00 CSIE00 DIR00

CSCK00

0

Note 1

1

0

1

0

1

0

×

0

1

×

LSB

P22

TxD

ASCK input

External

clock

(CMOS output)

Note 1

×

P20

Internal

clock

Note 1

0

1

×

1

×

RxD

P21

ASCK input

P20

External

clock

Note 1

Internal

clock

0

1

×

TxD

ASCK input

P20

External

clock

(CMOS output)

Note 1

Internal

clock

Other than above

Setting prohibited

Notes 1. Can be used as port function.

2. If used only for transmission, can be used as P22 (CMOS input/output).

Remark ×: Don't care.

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(3) Asynchronous serial interface status register 00 (ASIS00)

This register indicates types of error when a reception error is generated in the asynchronous interface

mode.

ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction.

The contents of ASIS00 become undefined in the 3-wire serial I/O mode.

RESET input clears ASIS00 to 00H.

Figure 9-5. Asynchronous Serial Interface Status Register 00 Format

Symbol

ASIS00

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FF71H

After Reset

00H

R/W

R

PE00

FE00

OVE00

PE00

Parity Error Flag

0

1

Parity error not generated

Parity error generated (when the parity of transmit data does not coincide.)

Flaming Error Flag

FE00

0

1

Flaming error not generated

Flaming error generated (when stop bit is not detected.)^{Note 1}

OVE00

Overrun Error Flag

Overrun error not generated

0

1

Overrun error generated^{Note 2}

(when the next receive operation is completed before the data is read from the receive buffer register.)

Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial

interface mode register 00 (ASIM00), the stop bit detection in the case of reception is performed

with 1 bit.

2. When an overrun error occurs, be sure to read out receive buffer register 00 (RXB00). Unless

RXB00 is read out, overrun errors occur at each data reception.

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(4) Baud rate generator control register 00 (BRGC00)

This register is used to set the serial clock of serial interface 00.

BRGC00 is set with an 8-bit memory manipulation instruction.

RESET input clears BRGC00 to 00H.

Figure 9-6. Baud Rate Generator Control Register 00 Format

7

6

5

4

3

0

2

0

1

0

After Reset

00H

Address

FF73H

R/W

Symbol

BRGC00 TPS003 TPS002 TPS001 TPS000

n

1

2

3

4

5

6

7

8

–

TPS003 TPS002 TPS001 TPS000

3-Bit Counter Source Clock Selection

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

f

X

/2 (2.5 MHz)

/2²(1.25 MHz)

/2³(625 kHz)

/2⁴(313 kHz)

/2⁵(156 kHz)

/2⁶(78.1 kHz)

/2⁷(39.1 kHz)

/2⁸(19.5 kHz)

Input clock from external to ASCK pin^Note

Setting prohibited

Other than above

Note Only used in UART mode.

Cautions 1. When writing to BRGC00 is performed during a communication operation, the baud

rate generator output is disrupted and communications cannot be performed normally.

Be sure not to write to BRGC00 during communication operation.

2. Be sure not to select n = 1 during an operation at f^X= 5.0 MHz because n = 1 exceeds

the baud rate limit.

3. When selecting an input clock from an external source, set port mode register 2 (PM2)

to the input mode.

Remarks 1. f^X: System clock oscillation frequency

2. n : Value determined by setting TPS000 through TPS003 (1 ≤ n ≤ 8)

3. The parenthesized values apply to operation at f^X= 5.0 MHz.

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The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a

signal scaled from the clock input from the ASCK pin.

(a) Generation of baud rate transmit/receive clock by means of system clock

The transmit/receive clock is generated by scaling the system clock. The baud rate generated from the

system clock is found from the following expression.

f^X

[Baud rate] =

[Hz]

2

^{n + 1}× 8

f^X: System clock oscillation frequency

n : Value determined by values of TPS000 through TPS003 as shown in Figure 9-6 (2 ≤ n ≤ 8)

Table 9-3. Example of Relationship between System Clock and Baud Rate

Baud Rate (bps)

n

BRGC00 Set Value

Error (%)

f^X= 4.9152 MHz

f^X= 5.0 MHz

1.73

1,200

8

7

6

5

4

3

2

70H

60H

50H

40H

30H

20H

10H

0

2,400

4,800

9,600

19,200

38,400

76,800

Caution Be sure not to select n = 1 during an operation at f^X= 5.0 MHz because n = 1 exceeds

the baud rate limit.

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(b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin

The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate

generated from the clock input from the ASCK pin is found from the following expression.

f^ASCK

16

[Baud rate] =

[Hz]

f^ASCK: Frequency of clock input to the ASCK pin

Table 9-4. Relationship between ASCK Pin Input Frequency

and Baud Rate (When BRGC00 is Set to 80H)

Baud Rate (bps)

ASCK Pin Input Frequency (kHz)

75

1.2

2.4

150

300

4.8

600

9.6

1,200

2,400

4,800

9,600

19,200

31,250

38,400

19.2

38.4

76.8

153.6

307.2

500.0

614.4

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9.4 Serial Interface 00 Operation

Serial interface 00 provides the following three types of modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

• 3-wire serial I/O mode

9.4.1 Operation stop mode

In the operation stop mode, serial transfer is not executed, therefore, the power consumption can be reduced.

The P20/SCK0/ASCK, P21/SO0/TxD, and P22/SI0/RxD pins can be used as normal I/O ports.

(1) Register setting

Operation stop mode is set by serial operation mode register 00 (CSIM00) and asynchronous serial

interface mode register 00 (ASIM00).

(a) Serial operation mode register 00 (CSIM00)

CSIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSIM00 to 00H.

<7>

6

0

5

0

4

0

3

0

2

1

0

Address After Reset

FF72H 00H

R/W

Symbol

CSIM00 CSIE00

DIR00 CSCK00

CSIE00

Operation Control in 3-Wire Serial I/O Mode

0

1

Operation stop

Operation enable

Caution Be sure to set bit 0 and bits 3 to 6 to 0.

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(b) Asynchronous serial interface mode register 00 (ASIM00)

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FF70H

After Reset

00H

R/W

TXE00

RXE00 PS001

PS000

CL00

SL00

TXE00

Transmit Operation Control

Receive Operation Control

0

1

Transmit operation stop

Transmit operation enable

RXE00

0

1

Receive operation stop

Receive operation enable

Caution Be sure to set bits 0 and 1 to 0.

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9.4.2 Asynchronous serial interface (UART) mode

In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication

is possible.

This device incorporates a UART-dedicated baud rate generator that enables communications at a desired

transfer rate from many options. In addition, the baud rate can also be defined by dividing the input clock to the

ASCK pin.

The UART-dedicated baud rate generator also can output the 31.25-kbps baud rate that complies with the MIDI

standard.

(1) Register setting

The UART mode is set by serial operation mode register 00 (CSIM00), asynchronous serial interface mode

register 00 (ASIM00), asynchronous serial interface status register 00 (ASIS00), and baud rate generator

control register 00 (BRGC00).

(a) Serial operation mode register 00 (CSIM00)

CSIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSIM00 to 00H.

Set 00H to CSIM00 when UART mode is selected.

<7>

6

0

5

0

4

0

3

0

2

1

0

Address After Reset

FF72H 00H

R/W

Symbol

CSIM00 CSIE00

DIR00 CSCK00

CSIE00

Operation Control in 3-Wire Serial I/O Mode

0

1

Operation stop

Operation enable

DIR00

Start Bit Specification

MSB

LSB

0

1

CSCK00

Clock Selection in 3-Wire Serial I/O Mode

0

1

Input clock to SCK0 pin from external

Dedicated baud rate generator output

Caution Be sure to set bit 0 and bits 3 to 6 to 0.

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(b) Asynchronous serial interface mode register 00 (ASIM00)

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FF70H

After Reset

00H

R/W

TXE00

RXE00

PS001

PS000

CL00

SL00

TXE00

Transmit Operation Control

Receive Operation Control

Parity Bit Specification

0

1

Transmit operation stop

Transmit operation enable

RXE00

0

1

Receive operation stop

Receive operation enable

PS001 PS000

0

1

No parity

Always add 0 parity at transmission

Parity check is not performed at reception (No parity error is generated)

Odd parity

Even parity

1

0

1

CL00

Character Length Specification

0

1

7 bits

8 bits

SL00

Transmit Data Stop Bit Length Specification

0

1

1 bit

2 bits

Cautions 1. Be sure to set bits 0 and 1 to 0.

2. Switching operating modes must be performed after the halt of serial

transmit/receive operation.

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(c) Asynchronous serial interface status register 00 (ASIS00)

ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIS00 to 00H.

Symbol

ASIS00

7

0

6

0

5

0

4

0

3

0

1

0

Address

FF71H

After Reset

00H

R/W

R

2

FE00

OVE00

PE00

Parity Error Flag

0

1

Parity error not generated

Parity error generated (when the parity of transmit data does not coincide.)

Flaming Error Flag

FE00

0

1

Framing error not generated

Framing error generated (when stop bit is not detected.)^{Note 1}

OVE00

Overrun Error Flag

Overrun error not generated

0

1

Overrun error generated^{Note 2}

(when the next receive operation is completed before the data is read from the receive buffer register.)

Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial

interface mode register 00 (ASIM00), the stop bit detection in the case of reception is

performed with 1 bit.

2. Be sure to read reception buffer register 00 (RXB00) when an overrun error occurs. If not,

every time the data is received an overrun error is generated.

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(d) Baud rate generator control register 00 (BRGC00)

BRGC00 is set with an 8-bit memory manipulation instruction.

RESET input clears BRGC00 to 00H.

7

6

5

4

3

0

2

0

1

0

After Reset

00H

Address

FF73H

R/W

Symbol

BRGC00 TPS003 TPS002 TPS001 TPS000

n

1

2

3

4

5

6

7

8

-

TPS003 TPS002 TPS001 TPS000

3-Bit Counter Source Clock Selection

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

fX

/2 (2.5 MHz)

/2²(1.25 MHz)

/2³(625 kHz)

/2⁴(313 kHz)

/2⁵(156 kHz)

/2⁶(78.1 kHz)

/2⁷(39.1 kHz)

/2⁸(19.5 kHz)

Input clock from external to ASCK pin

Setting prohibited

Other than above

Cautions 1. When writing to BRGC00 is performed during a communication operation, the

output of baud rate generator is disrupted and communications cannot be

performed normally. Be sure not to write to BRGC00 during communication

operation.

2. Be sure not to select n = 1 during an operation at f^X= 5.0 MHz because n = 1

exceeds the baud rate limit.

3. When selecting an input clock from an external source, set port mode register 2

(PM2) to the input mode.

Remarks 1. f^X: System clock oscillation frequency

2. n : Value determined by setting TPS000 through TPS003 (1 ≤ n ≤ 8)

3. The parenthesized values apply to operation at f^X= 5.0 MHz.

The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or

a signal scaled from the clock input from the ASCK pin.

(i) Generation of baud rate transmit/receive clock by means of system clock

The transmit/receive clock is generated by scaling the system clock. The baud rate generated from

the system clock is estimated by using the following expression.

f^X

[Baud rate] =

[Hz]

2

^{n + 1}× 8

f^X: System clock oscillation frequency

n : Value determined by setting TPS000 through TPS003 as shown in the above table (2 ≤ n ≤ 8)

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Table 9-5. Example of Relationship between System Clock and Baud Rate

Baud Rate (bps)

n

BRGC00 Set Value

Error (%)

f^X= 4.9152 MHz

f^X= 5.0 MHz

1.73

1,200

2,400

8

7

6

5

4

3

2

70H

60H

50H

40H

30H

20H

10H

0

4,800

9,600

19,200

38,400

76,800

Caution Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds

the baud rate limit.

(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin

The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud

rate generated from the clock input from the ASCK pin is estimated by using the following

expression.

f^ASCK

16

[Baud rate] =

[Hz]

f^ASCK: Frequency of clock input to the ASCK pin

Table 9-6. Relationship between ASCK Pin Input Frequency

and Baud Rate (When BRGC00 is Set to 80H)

Baud Rate (bps)

75

ASCK Pin Input Frequency (kHz)

1.2

2.4

150

300

4.8

600

9.6

1,200

2,400

4,800

9,600

19,200

31,250

38,400

19.2

38.4

76.8

153.6

307.2

500.0

614.4

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(2) Communication operation

(a) Data format

The transmit/receive data format is as shown in Figure 9-7. One data frame consists of a start bit,

character bits, parity bit, and stop bit(s).

The specification of character bit length, parity selection, and specification of stop bit length for one

data frame is carried out with asynchronous serial interface mode register 00 (ASIM00).

Figure 9-7. Asynchronous Serial Interface Transmit/Receive Data Format

One Data Frame

Start

Bit

Parity

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Stop Bit

• Start bit......................1 bit

• Character bits............7 bits/8 bits

• Parity bit....................Even parity/odd parity/0 parity/no parity

• Stop bit(s)..................1 bit/2 bits

When 7 bits are selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are

valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit

(bit 7) is always "0".

The serial transfer rate is selected by means of ASIM00 and baud rate generator control register 00

(BRGC00).

If a serial data receive error is generated, the receive error contents can be determined by reading the

status of asynchronous serial interface status register 00 (ASIS00).

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(b) Parity types and operation

The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity

bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit

(odd number) error can be detected. With 0 parity and no parity, an error cannot be detected.

(i) Even parity

• At transmission

The parity bit is determined so that the number of bits with a value of "1" in the transmit data

including parity bit may be even. The parity bit value should be as follows.

The number of bits with a value of "1" is an odd number in transmit data : 1

The number of bits with a value of "1" is an even number in transmit data : 0

• At reception

The number of bits with a value of "1" in the receive data including parity bit is counted, and if the

number is odd, a parity error is generated.

(ii) Odd parity

• At transmission

Conversely to the even parity, the parity bit is determined so that the number of bits with a value

of "1" in the transmit data including parity bit may be odd. The parity bit value should be as

follows.

The number of bits with a value of "1" is an odd number in transmit data : 0

The number of bits with a value of "1" is an even number in transmit data : 1

• At reception

The number of bits with a value of "1" in the receive data including parity bit is counted, and if the

number is even, a parity error is generated.

(iii) 0 parity

When transmitting, the parity bit is set to "0" irrespective of the transmit data.

At reception, a parity bit check is not performed. Therefore, a parity error is not generated,

irrespective of whether the parity bit is set to "0" or "1".

(iv) No parity

A parity bit is not added to the transmit data. At reception, data is received assuming that there is

no parity bit. Since there is no parity bit, a parity error is not generated.

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(c) Transmission

A transmit operation is started by writing transmit data to transmit shift register 00 (TXS00). The start

bit, parity bit, and stop bit(s) are added automatically.

When the transmit operation starts, the data in TXS00 is shifted out, and when TXS00 is empty, a

transmission completion interrupt (INTST) is generated.

Figure 9-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing

(a) Stop bit length: 1

STOP

D0

D1

D2

D6

D7

Parity

TxD (Output)

INTST

START

(b) Stop bit length: 2

D0

D1

D2

D6

D7

Parity

TxD (Output)

INTST

STOP

START

Caution Do not rewrite to asynchronous serial interface mode register 00 (ASIM00) during a

transmit operation. If the ASIM00 register is rewritten to during transmission,

subsequent transmission may not be performed (the normal state is restored by

RESET input).

It is possible to determine whether transmission is in progress by software by using a

transmission completion interrupt (INTST) or the interrupt request flag (STIF00) set by

INTST.

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(d) Reception

When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is set to 1, a receive

operation is enabled and sampling of the RxD pin input is performed.

RxD pin input sampling is performed using the serial clock specified by ASIM00.

When the RxD pin input becomes low, the 3-bit counter starts counting, and at the time when half the

time determined by the specified baud rate has passed, the data sampling start timing signal is output.

If the RxD pin input sampled again as a result of this start timing signal is low, it is identified as a start

bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character

data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends.

When one frame of data has been received, the receive data in the shift register is transferred to

receive buffer register 00 (RXB00), and a reception completion interrupt (INTSR) is generated.

If an error is generated, the receive data in which the error was generated is still transferred to RXB00,

and INTSR is generated.

If the RXE00 bit is reset to 0 during the receive operation, the receive operation is stopped immediately.

In this case, the contents of RXB00 and asynchronous serial interface status register 00 (ASIS00) are

not changed, and INTSR is not generated.

Figure 9-9. Asynchronous Serial Interface Reception Completion Interrupt Timing

STOP

D0

D1

D2

D6

D7

Parity

RxD (Input)

INTSR

START

Caution Be sure to read receive buffer register 00 (RXB00) even if a receive error occurs. If

RXB00 is not read, an overrun error will be generated when the next data is received,

and the receive error state will continue indefinitely.

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(e) Receive errors

The following three errors may occur during a receive operation: a parity error, framing error, or

overrun error. Upon data reception, an error flag is set in asynchronous serial interface status register

00 (ASIS00). Receive error causes are shown in Table 9-7.

It is possible to determine what kind of error was generated during reception by reading the contents of

ASIS00 in the reception error interrupt servicing (see Figures 9-9 and 9-10).

The contents of ASIS00 are reset to 0 by reading receive buffer register 00 (RXB00) or receiving the

next data (if there is an error in the next data, the corresponding error flag is set).

Table 9-7. Receive Error Causes

Receive Error

Cause

Transmission-time parity specification and reception data parity do not match

Stop bit not detected

Parity error

Framing error

Overrun error

Reception of next data is completed before data is read from receive buffer register

Figure 9-10. Receive Error Timing

(a) Parity error generated

STOP

D0

D1

D2

D6

D7

Parity

RxD (Input)

START

INTSR

(b) Framing error or overrun error generated

STOP

D0

D1

D2

D6

D7

Parity

RxD (Input)

INTSR

START

Cautions 1. The contents of the ASIS00 register are reset to 0 by reading receive buffer register

00 (RXB00) or receiving the next data. To ascertain the error contents, read

ASIS00 before reading RXB00.

2. Be sure to read receive buffer register 00 (RXB00) even if a receive error is

generated. If RXB00 is not read, an overrun error will be generated when the next

data is received, and the receive error state will continue indefinitely.

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(3) Cautions related to UART mode

(a) When bit 7 (TXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during

transmission, be sure to set transmit shift register 00 (TXS00) to FFH, then set TXE00 to 1 before

executing the next transmission.

(b) When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during

reception, receive buffer register 00 (RXB00) and receive completion interrupt (INTSR) are as follows.

RxD Pin

RXB00

INTSR

Parity

<1>

<3>

<2>

When RXE00 is set to 0 at a time indicated by <1>, RXB00 holds the previous data and INTSR is not

generated.

When RXE00 is set to 0 at a time indicated by <2>, RXB00 renews the data and INTSR is not generated.

When RXE00 is set to 0 at a time indicated by <3>, RXB00 renews the data and INTSR is generated.

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9.4.3 3-wire serial I/O mode

The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which

incorporate a conventional synchronous serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc.

Communication is performed using three lines: the serial clock (SCK0), serial output (SO0), and serial input

(SI0).

(1) Register setting

3-wire serial I/O mode settings are performed using serial operation mode register 00 (CSIM00),

asynchronous serial interface mode register 00 (ASIM00), and baud rate generator control register 00

(BRGC00).

(a) Serial operation mode register 00 (CSIM00)

CSIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSIM00 to 00H.

<7>

6

0

5

0

4

0

3

0

2

1

0

Address

FF72H

After Reset

00H

R/W

Symbol

CSIM00 CSIE00

DIR00 CSCK00

CSIE00

Operation Control in 3-Wire Serial I/O Mode

0

1

Operation stop

Operation enable

DIR00

Start Bit Specification

MSB

LSB

0

1

CSCK00

Clock Selection in 3-Wire Serial I/O Mode

0

1

Input clock to SCK0 pin from external

Dedicated baud rate generator output

Caution Be sure to set bit 0 and bits 3 to 6 to 0.

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(b) Asynchronous serial interface mode register 00 (ASIM00)

ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ASIM00 to 00H.

When the 3-wire serial I/O mode is selected, 00H must be set to ASIM00.

Symbol

ASIM00

<7>

<6>

5

4

3

2

1

0

Address

FF70H

After Reset

00H

R/W

TXE00 RXE00

PS001

PS000

CL00

SL00

TXE00

Transmit Operation Control

Receive Operation Control

Parity Bit Specification

0

1

Transmit operation stop

Transmit operation enable

RXE00

0

1

Receive operation stop

Receive operation enable

PS001

PS000

0

1

No parity

Always add 0 parity at transmission

Parity check is not performed at reception (No parity error is generated)

Odd parity

Even parity

1

0

1

CL00

Character Length Specification

0

1

7 bits

8 bits

SL00

Transmit Data Stop Bit Length Specification

0

1

1 bit

2 bits

Cautions 1. Be sure to set bits 0 and 1 to 0.

2. Switching operating modes must be performed after serial transmit/receive

operation is halted.

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(c) Baud rate generator control register 00 (BRGC00)

BRGC00 is set with an 8-bit memory manipulation instruction.

RESET input clears BRGC00 to 00H.

7

6

5

4

3

0

2

0

1

0

After Reset

00H

Address

FF73H

R/W

Symbol

BRGC00 TPS003 TPS002 TPS001 TPS000

n

1

2

3

4

5

6

7

8

TPS003 TPS002 TPS001 TPS000

3-Bit Counter Source Clock Selection

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f

X

/2 (2.5 MHz)

/2²(1.25 MHz)

/2³(625 kHz)

/2⁴(313 kHz)

/2⁵(156 kHz)

/2⁶(78.1 kHz)

/2⁷(39.1 kHz)

/2⁸(19.5 kHz)

Other than above

Setting prohibited

Cautions 1. When writing to BRGC00 is performed during a communication operation, the

baud rate generator output is disrupted and communications cannot be performed

normally. Be sure not to write to BRGC00 during communication operation.

2. Be sure not to select n = 1 during an operation at f^X= 5.0 MHz because n = 1

exceeds the baud rate limit.

3. When selecting an input clock from an external source, set port mode register 2

(PM2) to the input mode.

Remarks 1. f^X: System clock oscillation frequency

2. n : Value determined by setting TPS000 through TPS003 (1 ≤ n ≤ 8)

3. The parenthesized values apply to operation at f^X= 5.0 MHz.

If the internal clock is used as the serial clock for 3-wire serial I/O mode, set the TPS000 to TPS003 bits

to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula.

When the serial clock is input from external, setting BRGC00 is not necessary.

f^X

Serial clock frequency =

[Hz]

2^{n + 1}

f^X: System clock oscillation frequency

n : Value determined by setting TPS000 through TPS003 as shown in the above table (1 ≤ n ≤ 8)

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(2) Communication operation

In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is

transmitted/received bit by bit in synchronization with the serial clock.

Transmit shift register 00 (TXS00/SIO00) and receive shift register 00 (RXS00) shift operations are

performed in synchronization with the fall of the serial clock (SCK0). Then transmit data is held in the SO0

latch and output from the SO0 pin. Also, receive data input to the SI0 pin is latched in receive buffer

register 00 (RXB00/SIO00) on the rise of SCK0.

At the end of an 8-bit transfer, the operations of TXS00/SIO00 and RXS00 stop automatically, and the

interrupt request signal (INTCSI0) is generated.

Figure 9-11. 3-Wire Serial I/O Mode Timing

SCK0

SI0

1

2

3

4

5

6

7

8

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

SO0

INTCSI0

End of Transfer

Transfer start at the falling edge of SCK0

(3) Transfer start

Serial transfer is started by setting transfer data to transmit shift register 00 (TXS00/SIO00) when the

following two conditions are satisfied.

• Serial operation mode register 00 (CSIM00) bit 7 (CSIE00) = 1

• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.

Caution If CSIE00 is set to "1" after data write to TXS00/SIO00, transfer does not start.

A termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request

signal (INTCSI0).

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CHAPTER 10 INTERRUPT FUNCTIONS

10.1 Interrupt Function Types

The following two types of interrupt functions are used.

(1) Non-maskable interrupt

This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top

priority over all other interrupt requests.

A standby release signal is generated.

The non-maskable interrupt has one source of interrupt from the watchdog timer.

(2) Maskable interrupt

These interrupts undergo mask control. If two or more interrupts are simultaneously generated, each

interrupt has a predetermined priority (priority) as shown in Table 10-1.

A standby release signal is generated.

The maskable interrupt has four sources of external interrupts and five sources of internal interrupts.

10.2 Interrupt Sources and Configuration

There are total of ten non-maskable and maskable interrupts in the interrupt sources (see Table 10-1).

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Table 10-1. Interrupt Source List

Interrupt Type

Priority^{Note 1}

Interrupt Source

Trigger

Internal/

External

Vector

Table

Basic

Configuration

Type^{Note 2}

Name

Address

Non-maskable

Maskable

−

INTWDT

Watchdog timer overflow (watchdog timer Internal

mode 1 selected)

0004H

(A)

(B)

(C)

0

INTWDT

Watchdog timer overflow (interval timer

mode selected)

1

2

3

4

INTP0

INTP1

INTP2

INTSR

INTCSI0

INTST

Pin input edge detection

External

0006H

0008H

000AH

000CH

End of serial interface 00 UART reception Internal

End of serial interface 00 3-wire transfer

(B)

5

6

7

8

End of serial interface 00 UART

transmission

000EH

0010H

0014H

002AH

INTTM0

INTTM2

INTKR

Generation of 8-bit timer/event counter 00

match signal

Generation of 16-bit timer 20 match

signal

Key return signal detection

External

(C)

Notes 1. Priorities are intended for the priority for two or more simultaneously generated maskable interrupts. 0

is the highest priority and 8 is the lowest priority.

2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 10-1.

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Figure 10-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Internal Bus

Vector Table

Address Generator

Interrupt Request

Standby Release Signal

(B) Internal maskable interrupt

Internal Bus

MK

IE

Vector Table

Address Generator

IF

Interrupt Request

Standby Release Signal

(C) External maskable interrupt

Internal Bus

INTM0, KRM00

MK

IE

Vector Table

Address Generator

Interrupt

Request

Edge

Detector

IF

Standby

Release Signal

INTM0 : External interrupt mode register 0

KRM00 : Key return mode register 00

IF

: Interrupt request flag

: Interrupt enable flag

: Interrupt mask flag

IE

MK

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10.3 Interrupt Function Control Registers

The following five registers are used to control the interrupt functions.

• Interrupt request flag registers (IF0 and IF1)

• Interrupt mask flag registers (MK0 and MK1)

• External interrupt mode register 0 (INTM0)

• Program status word (PSW)

• Key return mode register 00 (KRM00)

Table 10-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt

requests.

Table 10-2. Flags Corresponding to Interrupt Request Signal Name

Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag

INTWDT

INTP0

TMIF4

PIF0

TMMK4

PMK0

INTP1

PIF1

PMK1

INTP2

PIF2

PMK2

INTSR/INTCSI0

INTST

SRIF00

STIF00

TMIF00

TMIF20

KRIF00

SRMK00

STMK00

TMMK00

TMMK20

KRMK00

INTTM0

INTTM2

INTKR

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(1) Interrupt request flag registers (IF0 and IF1)

The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction

is executed. It is cleared to 0 upon acknowledgement of an interrupt request, upon RESET input, or when

an instruction is executed.

IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears IF0 and IF1 to 00H.

Figure 10-2. Interrupt Request Flag Register Format

7

0

<6>

<5>

<4>

<3>

<2>

<1>

<0>

Address

FFE0H

After Reset

00H

R/W

Symbol

IF0

TMIF00 STIF00

SRIF00

PIF2

PIF1

PIF0

TMIF4

<7>

6

0

5

0

4

0

3

0

2

0

1

0

<0>

IF1

TMIF20

KRIF00

FFE1H

00H

R/W

Interrupt Request Flag

××IF×

0

1

No interrupt request signal is generated

Interrupt request signal is generated; Interrupt request state

Cautions 1. Be sure to clear bit 7 of IF0 and bits 1 to 6 of IF1 to 0.

2. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If

the watchdog timer mode 1 or 2 is used, set TMIF4 flag to 0.

3. Because port 3 has an alternate function as the external interrupt input, when the

output level is changed by specifying the output mode of the port function, an

interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag

before using the output mode.

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(2) Interrupt mask flag registers (MK0 and MK1)

The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing.

MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets MK0 and MK1 to FFH.

Figure 10-3. Interrupt Mask Flag Register Format

7

1

<6>

<5>

<4>

<3>

<2>

<1>

<0>

Address

FFE4H

After Reset

FFH

R/W

Symbol

MK0

TMMK00 STMK00 SRMK00 PMK2

PMK1

PMK0 TMMK4

<7>

6

1

5

1

4

1

3

1

2

1

<0>

KRMK00 FFE5H

MK1

TMMK20

FFH

R/W

Interrupt Servicing Control

××MK×

0

1

Interrupt servicing enabled

Interrupt servicing disabled

Cautions 1. Be sure to set bit 7 of MK0 and bits 1 to 6 of MK1 to 1.

2. IF the TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1 or

2, its value becomes undefined.

3. Because port 3 has an alternate function as the external interrupt input, when the

output level is changed by specifying the output mode of the port function, an

interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag

before using the output mode.

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(3) External interrupt mode register 0 (INTM0)

This register is used to set the valid edge of INTP0 to INTP2.

INTM0 is set with an 8-bit memory manipulation instruction.

RESET input clears INTM0 to 00H.

Figure 10-4. External Interrupt Mode Register 0 Format

'

Address

FFECH

7

6

5

4

3

2

1

0

After Reset

00H

R/W

Symbol

INTM0

ES21

ES20

ES11

ES10

ES01

ES00

ES21

ES20

INTP2 Valid Edge Selection

INTP1 Valid Edge Selection

INTP0 Valid Edge Selection

Falling edge

0

1

0

1

0

1

Rising edge

Setting prohibited

Both rising and falling edges

ES11

ES10

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES00

ES01

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

Cautions 1. Be sure to set bits 0 and 1 to 0.

2. Before setting INTM0 register, be sure to set the corresponding interrupt mask flag

(××MK× = 1) to disable interrupts. After setting INTM0 register, clear the interrupt

request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0) to enable

interrupts.

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(4) Program status word (PSW)

The program status word is a register used to hold the instruction execution result and the current status of

the interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped.

Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and

dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, PSW is

automatically saved into a stack, and the IE flag is reset to 0. It is restored from the stack with the RETI and

POP PSW instructions.

RESET input sets PSW to 02H.

Figure 10-5. Program Status Word Configuration

After Reset

02H

7

6

Z

5

0

4

3

0

2

0

1

0

Symbol

PSW

IE

AC

CY

Used when normal instruction is executed

IE

Interrupt Acknowledge Enable/Disable

Disable

Enable

0

1

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(5) Key return mode register 00 (KRM00)

KRM00 is used to specify the pin at which a key return signal is detected.

KRM00 is set with a 1-bit or 8-bit memory manipulation instruction.

Bit 0 (KRM000) is set for the four pins from KR0/P40 to KR3/P43. Bits 4 to 7 (KRM004 to KRM007) are set

in 1-bit units for pins KR4/P44 to KR7/P47, respectively.

RESET input clears KRM00 to 00H.

Figure 10-6. Key Return Mode Register 00 Format

Symbol

7

6

5

4

3

0

2

0

1

0

Address

FFF5H

After Reset

00H

R/W

KRM00 KRM007 KRM006 KRM005 KRM004

KRM000

KRM00n

Key Return Signal Detection Selection

0

1

Undetected

Detected (at the falling edge of port 4)

Cautions 1. Be sure to set bits 1 to 3 to 0.

2. When KRM00 is set to 1, the corresponding pin is connected to a pull-up resistor

unless it is in output mode. In output mode, the pull-up resistor is not connected.

3. Before setting KRM00, set bit 0 of MK1 (KRMK00 = 1) to disable interrupts.

To enable interrupts, clear bit 0 of IF1 (KRIF00 = 0), then bit 0 of MK1 (KRMK00 = 0).

Remark n = 0, 4 to 7

Figure 10-7. Falling Edge Detection Circuit

Key Return Mode Register (KRM00)

Note

P40/KR0

P41/KR1

P42/KR2

P43/KR3

P44/KR4

Falling Edge

Detection Circuit

KRIF00 Set Signal

P45/KR5

P46/KR6

Standby Release Signal

KRMK00

P47/KR7

Note Selector used to select the pin to be used for falling edge input

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10.4 Interrupt Processing Operation

10.4.1 Non-maskable interrupt request acceptance operation

The non-maskable interrupt request is unconditionally accepted even when interrupts are disabled. It is not

subject to interrupt priority control and takes precedence over all other interrupts.

When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order,

the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.

Figure 10-8 shows the flowchart from non-maskable interrupt request generation to acceptance. Figure 10-9

shows the timing of non-maskable interrupt request acceptance. Figure 10-10 shows the acceptance operation if

multiple non-maskable interrupts are generated.

Caution During a non-maskable interrupt service program execution, do not input another non-

maskable interrupt request; if it is input, the service program will be interrupted and the new

interrupt request will be acknowledged.

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Figure 10-8. Flowchart from Non-Maskable Interrupt Request Generation to Acceptance

Start

WDTM4 = 1

No

(watchdog timer mode

is selected)

Interval Timer

Yes

No

WDT

overflows

Yes

WDTM3 = 0

(non-maskable interrupt

is selected)

Reset Processing

Yes

Interrupt request is generated

Interrupt processing is started

WDTM : Watchdog timer mode register

WDT : Watchdog timer

Figure 10-9. Non-Maskable Interrupt Request Acceptance Timing

Saving PSW and PC, and

jump to interrupt processing

CPU Processing

TMIF4

Instruction

Interrupt Processing Program

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Figure 10-10. Accepting Non-Maskable Interrupt Request

Main Routine

First Interrupt Processing

NMI Request

(second)

NMI Request

(first)

Second Interrupt Processing

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10.4.2 Maskable interrupt request acceptance operation

A maskable interrupt request can be accepted when the interrupt request flag is set to 1 and the corresponding

interrupt mask flag is cleared to 0. A vectored interrupt request is accepted in the interrupt enabled status (when the

IE flag is set to 1).

The time required to start the interrupt processing after a maskable interrupt request has been generated is

shown in Table 10-3.

See Figures 10-12 and 10-13 for the interrupt request acceptance timing.

Table 10-3. Time from Generation of Maskable Interrupt Request to Processing

Minimum Time

9 clocks

Maximum Time^Note

19 clocks

Note The wait time is maximum when an interrupt

request is generated immediately before BT and

BF instruction.

1

f^CPU

Remark 1 clock:

(f^CPU: CPU clock)

When two or more maskable interrupt requests are generated at the same time, they are accepted starting from

the interrupt request assigned the highest priority.

A pended interrupt is accepted when the status where it can be accepted is set.

Figure 10-11 shows the algorithm of accepting interrupt requests.

When a maskable interrupt request is accepted, the contents of PSW and PC are saved to the stack in that

order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the

PC, and execution branches.

To return from interrupt processing, use the RETI instruction.

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Figure 10-11. Interrupt Request Acceptance Program Algorithm

Start

No

××IF = 1 ?

Yes (Interrupt request generated)

No

××MK = 0 ?

Yes

Interrupt Request Pending

No

IE = 1 ?

Yes

Vectored Interrupt

Processing

××IF : Interrupt request flag

××MK : Interrupt mask flag

IE

: Flag to control maskable interrupt request acceptance (1 = enable, 0 = disable)

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Figure 10-12. Interrupt Request Acceptance Timing (Example of MOV A,r)

8 Clocks

Clock

Saving PSW and PC, jump

to interrupt processing

Interrupt Processing Program

CPU

MOV A,r

Interrupt

If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1,

the interrupt is accepted after the instruction under execution completes. Figure 10-12 shows an example of the

interrupt request acceptance timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is executed

for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acceptance processing is

performed after the MOV A,r instruction is completed.

Figure 10-13. Interrupt Request Acceptance Timing (When Interrupt Request Flag Generates at the Last

Clock during Instruction Execution)

8 Clocks

Clock

Interrupt

Processing

Program

Saving PSW and PC, jump

to interrupt processing

CPU

NOP

MOV A,r

Interrupt

If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acceptance processing

starts after the next instruction is executed. Figure 10-13 shows an example of the interrupt acceptance timing for

an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A,r

instruction after the NOP instruction is executed, and then the interrupt acceptance processing is performed.

Caution Interrupt requests are reserved while the interrupt request flag register (IF0 or IF1) or the

interrupt mask flag register (MK0 or MK1) is being accessed.

10.4.3 Nesting processing

Nesting processing in which another interrupt is accepted while an interrupt is processed can be processed by

priority. When two or more interrupts are generated at once, interrupt processing is performed according to the

priority assigned to each interrupt request in advance (see Table 10-1).

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Figure 10-14. Example of Nesting

Example 1. Nesting is accepted

INTxx Processing

INTyy Processing

Main Processing

IE = 0

EI

INTxx

INTyy

RETI

During interrupt INTxx servicing, interrupt request INTyy is accepted, and a nesting is generated. An EI

instruction is issued before each interrupt request acceptance, and the interrupt request acceptance enable state is

set.

Example 2. A nesting is not generated because interrupts are not enabled

INTxx Processing

INTyy Processing

Main Processing

EI

IE = 0

INTyy is kept pending

INTyy

RETI

INTxx

IE = 0

RETI

Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request

INTyy is not accepted, and a nesting is not generated. The INTyy request is reserved and accepted after the INTxx

processing is performed.

IE = 0: Interrupt request acceptance disabled

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10.4.4 Interrupt request reserve

Some instructions may reserve the acceptance of an interrupt request until the completion of the execution of the

next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is

generated during the execution. The following shows such instructions (interrupt request reserve instruction).

• Manipulation instruction for the interrupt request flag registers 0 and 1 (IF0 and IF1)

• Manipulation instruction for the interrupt mask flag registers 0 and 1 (MK0 and MK1)

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CHAPTER 11 STANDBY FUNCTION

11.1 Standby Function and Configuration

11.1.1 Standby function

The standby function is to reduce the power consumption of the system and can be effected in the following two

modes:

(1) HALT mode

This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the

CPU. The system clock oscillation circuit continues oscillating. This mode does not reduce the current

drain as much as the STOP mode, but is useful for resuming processing immediately when an interrupt

request is generated, or for intermittent operations.

(2) STOP mode

This mode is set when the STOP instruction is executed. The STOP mode stops the system clock

oscillation circuit and stops the entire system. The current drain of the CPU can be substantially reduced in

this mode.

Data memory can be retained at low voltages (V^DD= 1.8 V min.). Therefore, this mode is useful for

retaining the contents of the data memory at an extremely low current.

The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent

operation. However, some time is required until the system clock oscillation circuit settles after the STOP

mode has been released. If processing must be resumed immediately by using an interrupt request,

therefore, use the HALT mode.

In both modes, the previous contents of the registers, flags, and data memory before setting standby mode are

all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.

Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then

execute the STOP instruction.

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11.1.2 Standby function control register

The wait time after the STOP mode is released upon interrupt request until the oscillation settles is controlled

with the oscillation settling time select register (OSTS).

OSTS is set with an 8-bit memory manipulation instruction.

RESET input sets OSTS to 04H. However, the oscillation settling time after RESET input is 2¹⁵/f^X, instead of

2¹⁷/f^X.

Figure 11-1. Oscillation Settling Time Select Register Format

7

0

6

0

5

0

4

0

3

0

2

1

0

Symbol

OSTS

Address

FFFAH

R/W

After Reset

04H

OSTS2

OSTS1

OSTS0

OSTS2

OSTS1

OSTS0

Oscillation Settling Time Selection

2¹²/f

X

(819 s)

0

1

0

1

0

µ

2¹⁵/f

2¹⁷/f

(6.55 ms)

(26.2 ms)

Other than above

Setting prohibited

Caution The wait time after the STOP mode is released does not include the time from STOP mode

release to clock oscillation start ("a" in the figure below), regardless of release by RESET input

or by interrupt generation.

STOP Mode Release

X1 Pin Voltage

Waveform

a

VSS

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

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11.2 Operation of Standby Function

11.2.1 HALT mode

(1) HALT mode

HALT mode is set by executing the HALT instruction.

The operation status in the HALT mode is shown in the following table.

Table 11-1. HALT Mode Operating Status

Item

HALT Mode Operating Status

Clock generation circuit

System clock oscillation enabled

Clock supply to CPU stopped

CPU

Operation stopped

Port (Output latch)

16-bit timer

Retains the status before setting the HALT mode

Operation enabled

8-bit timer/event counter

Watchdog timer

Serial interface

External interrupt

Key return

Operation enabled

Only the pin set to key return mode is enabled

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(2) Releasing HALT mode

The HALT mode can be released by the following three types of sources:

(a) Releasing by unmasked interrupt request

The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is

enabled to be accepted, vectored interrupt processing is performed. If the interrupt is disabled, the

instruction at the next address is executed.

Figure 11-2. Releasing HALT Mode by Interrupt

HALT

Instruction

Wait

Standby

Release Signal

Operation

Mode

HALT Mode

Operation Mode

Oscillation

Clock

Remarks 1. The broken line indicates the case where the interrupt request that has released the

standby mode is accepted.

2. The wait time is as follows:

• When vectored interrupt processing is performed

: 9 to 10 clocks

• When vectored interrupt processing is not performed : 1 to 2 clocks

(b) Releasing by non-maskable interrupt request

The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored

interrupt processing is performed.

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(c) Releasing by RESET input

When the HALT mode is released by the RESET signal, execution branches to the reset vector address

in the same manner as the ordinary reset operation, and program execution is started.

Figure 11-3. Releasing HALT Mode by RESET Input

Wait

X

HALT

Instruction

(2¹⁵/f

: 6.55 ms)

RESET

Signal

Oscillation

Settling

Wait Status

Reset

Period

Operation

Mode

Operation

Mode

HALT Mode

Oscillation

Stop

Oscillation

Clock

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

Table 11-2. Operation after Release of HALT Mode

Releasing Source

MK××

IE

0

Operation

Executes next address instruction

Executes interrupt processing

Retains HALT mode

Maskable interrupt request

0

1

−

1

×

Non-maskable interrupt request

RESET input

×

Executes interrupt processing

Reset processing

−

×: Don't care

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11.2.2 STOP mode

(1) Setting and operation status of STOP mode

The STOP mode is set by executing the STOP instruction.

Caution Because the standby mode can be released by an interrupt request signal, the standby mode is

released as soon as it is set if there is an interrupt source whose interrupt request flag is set

and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode is set

immediately after the STOP instruction has been executed, the wait time set by the oscillation

settling time select register (OSTS) elapses, and then operation mode is set.

The operation status in the STOP mode is shown in the following table.

Table 11-3. STOP Mode Operating Status

Item

Clock generation circuit

CPU

STOP Mode Operation Status

Stops system clock oscillation

Stops operation

Port (Output latch)

16-bit timer

Retains the status before setting the STOP mode

Stops operation

8-bit timer/event counter

Watchdog timer

Serial interface

External interrupt

Key return

Operation is enabled only when TI0 is selected as the count clock

Stops operation

Enables operation only when input clock from external is selected as serial clock

Operation enabled

Only the pin set to key return mode is enabled

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(2) Releasing STOP mode

The STOP mode can be released by the following two types of sources:

(a) Releasing by unmasked interrupt request

The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is

enabled to be accepted, vectored interrupt processing is performed, after the oscillation settling time

has elapsed. If the interrupt acceptance is disabled, the instruction at the next address is executed.

Figure 11-4. Releasing STOP Mode by Interrupt

Wait

STOP

Instruction

( Set Time by OSTS)

Standby

Release Signal

Oscillation Settling

Operation

Mode

Operation

Mode

Wait Status

STOP Mode

Oscillation

Stop

Oscillation

Clock

Remark The broken line indicates the case where the interrupt request that has released the standby

mode is accepted.

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(b) Releasing by RESET input

When the STOP mode is released by the RESET signal, the reset operation is performed after the

oscillation settling time has elapsed.

Figure 11-5. Releasing STOP Mode by RESET Input

Wait

X

STOP

Instruction

(2¹⁵/f

: 6.55 ms)

RESET

Signal

Oscillation

Settling

Wait Status

Operation

Mode

Reset

Period

Operation

Mode

STOP Mode

Oscillation

Stop

Oscillation

Clock

Remarks 1. f^X: System clock oscillation frequency

2. The parenthesized values apply to operation at f^X= 5.0 MHz.

Table 11-4. Operation after Release of STOP Mode

Releasing Source

MK××

IE

0

Operation

Maskable interrupt request

0

1

−

Executes next address instruction

Executes interrupt processing

Retains STOP mode

1

×

RESET input

−

Reset processing

×: Don't care

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The following two operations are available to generate reset signals.

(1) External reset input with RESET pin

(2) Internal reset by program run-away time detected with watchdog timer

External and internal reset have no functional differences. In both cases, program execution starts at the

address at 0000H and 0001H by reset signal input.

When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each

hardware is set to the status shown in Table 12-1. Each pin has a high impedance during reset input or during

oscillation settling time just after reset clear.

When a high level is input to the RESET pin, the reset is cleared and program execution is started after the

oscillation settling time (2¹⁵/f^X) has elapsed. The reset applied by the watchdog timer overflow is automatically

cleared after reset, and program execution is started after the oscillation settling time (2¹⁵/f^X) has elapsed (see

Figures 12-2 through 12-4).

Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.

2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset

input. However, the port pins become high impedance.

Figure 12-1. Block Diagram of Reset Function

RESET

Reset Signal

Reset Control Circuit

Over-

flow

Interrupt Function

Count Clock

Watchdog Timer

Stop

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CHAPTER 12 RESET FUNCTION

Figure 12-2. Reset Timing by RESET Input

X1

Reset Period

(oscillation

stops)

Oscillation

Settling

Time Wait

Normal Operation

(reset processing)

Normal Operation

RESET

Internal

Reset Signal

Delay

Hi-Z

Port Pin

Figure 12-3. Reset Timing by Overflow in Watchdog Timer

X1

Reset Period

(oscillation

continues)

Oscillation

Settling

Time Wait

Normal Operation

(reset processing)

Normal Operation

Overflow in

Watchdog Timer

Internal

Reset Signal

Hi-Z

Port Pin

Figure 12-4. Reset Timing by RESET Input in STOP Mode

X1

STOP Instruction Execution

Stop Status

(oscillation

stops)

Reset Period

(oscillation

stops)

Oscillation

Settling

Time Wait

Normal Operation

(reset processing)

Normal Operation

RESET

Internal

Reset Signal

Delay

Hi-Z

Port Pin

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Table 12-1. Hardware Status after Reset

Hardware

State after Reset

Program counter (PC)^{Note 1}

The contents of reset vector

tables (0000H and 0001H)

are set.

Stack pointer (SP)

Program status word (PSW)

RAM

Undefined

02H

Data memory

General-purpose register

Undefined^{Note 2}

00H

Ports (P0 to P5) (Output latch)

Port mode registers (PM0 to PM5)

FFH

Pull-up resistor option register (PUO)

Processor clock control register (PCC)

Oscillation settling time select register (OSTS)

00H

02H

04H

16-bit timer

Timer counter (TM20)

0000H

FFFFH

00H

Compare register (CR20)

Mode control register (TMC20)

Capture register (TCP20)

Undefined

00H

8-bit timer/event counter

Timer counter (TM00)

Compare register (CR00)

00H

Mode control register (TMC00)

Timer clock select register (TCL2)

Mode register (WDTM)

00H

Watchdog timer

Serial interface

00H

Mode register (CSIM00)

00H

Asynchronous serial interface mode register (ASIM00)

Asynchronous serial interface status register (ASIS00)

Baud rate generator control register (BRGC00)

Transmit shift register (TXS00)

Receive buffer register (RXB00)

Request flag registers (IF0, IF1)

Mask flag registers (MK0, MK1)

External interrupt mode register (INTM0)

Key return mode register (KRM00)

00H

FFH

Undefined

00H

Interrupt

FFH

00H

Notes 1. During reset input and oscillation settling time wait, only the PC contents among the hardware

statuses become undefined.

All other hardware remains unchanged after reset.

2. In post-reset values are retained in the standby mode.

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CHAPTER 13 µPD78F9026A

The µPD78F9026A is a version with an internal ROM of the mask ROM models replaced with a flash memory.

The differences between the µPD78F9026A and the mask ROM models are shown in Table 13-1.

Table 13-1. Differences between µPD78F9026A and Mask ROM Models

Item

Flash Memory Model

Mask ROM Model

µPD78F9026A

µPD789022

µPD789024

8 Kbytes

µPD789025

µPD789026

Internal

memory

ROM

16 Kbytes

4 Kbytes

12 Kbytes

16 Kbytes

(flash memory)

Internal high-

speed RAM

512 bytes

256 bytes

512 bytes

IC pin

Not provided

Provided

V^PPpin

Provided

Not provided

Electric characteristics

Refer to Data Sheet.

Caution The flash memory and masked ROM products have different noise immunity and noise

radiation characteristics. Do not use ES products for evaluation when considering switching

from flash memory products to those using masked ROM upon the transition from

preproduction to mass-production. CS products (masked ROM products) should be used in

this case.

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13.1 Flash Memory Programming

The program memory provided to the µPD78F9026A is flash memory.

The flash memory can be written on-board, i.e., with the µPD78F9026A mounted on the target system.

To do so, connect a dedicated flash writer (Flashpro III (Part number: FL-PR3, PG-FP3)) to the host machine

and target system.

Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.

13.1.1 Selecting communication mode

The flash memory is written by using Flashpro III and by means of serial communication. Select a

communication mode from those listed in Table 13-2. To select a communication mode, the format shown in Figure

13-1 is used. Each communication mode is selected depending on the number of V^PPpulses shown in Table 13-2.

Table 13-2. Communication Modes

Communication Mode

3-wire serial I/O

Pins Used

SCK0/ASCK/P20

Number of V^PPPulses

0

SO0/TxD/P21

SI0/RxD/P22

UART

TxD/SO0/P21

RxD/SI0/P22

8

Pseudo 3-wire mode^Note

P00 (Serial clock input)

P01 (Serial data output)

P02 (Serial data input)

12

P40/KR0 (serial clock input)

P41/KR1 (serial data output)

P42/KR2 (serial data input)

13

Note Serial transfer is performed by controlling the port with software.

Caution Be sure to select a communication mode by the number of V^PPpulses shown in Table 13-2.

Figure 13-1. Communication Mode Selection Format

10 V

VPP

VDD

1

2

n

VSS

V

DD

SS

RESET

V

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CHAPTER 13 µPD78F9026A

13.1.2 Flash memory programming function

An operation such as writing the flash memory is performed when a command or data is transmitted/received in

the selected communication mode. The major flash memory programming functions are listed in Table 13-3.

Table 13-3. Major Flash Memory Programming Functions

Function

Batch erase

Description

Erases all memory contents.

Batch blank check

Data write

Checks erased status of entire memory.

Writes data to flash memory starting from write start address and based on number of data (bytes)

to be written.

Batch verify

Compares all contents of memory with input data

13.1.3 Connection Example of Flashpro III

Connection with Flashpro III differs depending on the communication mode (3-wire serial I/O, UART, or pseudo

3-wire mode). Figures 13-2 through 13-4 show the connection in the respective modes.

Figure 13-2. Connection Example of Flashpro III in 3-Wire Serial I/O Mode

PD78F9026A

µ

Flashpro III

V

PPn^Note

VPP

VDD

VDD0, VDD1

RESET

SCK

SO

RESET

SCK0

SI0

SI

SO0

GND

VSS0, VSS1

Note n = 1, 2

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Figure 13-3. Connection Example of Flashpro III in UART Mode

PD78F9026A

µ

Flashpro III

V

PPn^Note

VPP

VDD

V

DD0, VDD1

RESET

SO

RESET

RxD

SI

TxD

GND

VSS0, VSS1

Note n = 1, 2

Figure 13-4. Connection Example of Flashpro III in Pseudo 3-Wire Mode (When using P0)

µ

Flashpro III

PD78F9026A

V

PPn^Note

VPP

VDD

VDD0, VDD1

RESET

SCK

RESET

P00 (serial clock)

P02 (serial input)

SO

SI

P01 (serial output)

GND

VSS0, VSS1

Note n = 1, 2

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13.1.4 Setting example when using Flashpro III (PG-FP3)

When writing data to flash memory by using Flashpro III (PG-FP3), set as follows.

<1> Load the parameter file.

<2> Select a serial mode and serial clock by using the type command.

<3> An example of setting with PG-FP3 is shown below.

Table 13-4. Setting Example When Using PG-FP3

Communication Mode

3-wire serial I/O

Setting Example with PG-FP3

SIO-ch0

Number of V

0

^PPPulses^{Note 1}

COMM PORT

CPU CLK

On Target Board

In Flashpro

4.1943 MHz

1.0 MHz

On Target Board

SIO CLK

In Flashpro

SIO CLK

4.0 MHz

1.0 MHz

UART

COMM PORT

CPU CLK

UART-ch0

On Target Board

4.1943 MHz

9,600 bps^{Note 2}

Port A

8

On Target Board

UART BPS

COMM PORT

CPU CLK

Pseudo 3-wire mode

12

On Target Board

In Flashpro

4.1943 MHz

1.0 MHz

On Target Board

SIO CLK

In Flashpro

SIO CLK

4.0 MHz

1.0 MHz

COMM PORT

CPU CLK

Port B

13

On Target Board

In Flashpro

4.1943 MHz

1 kHz

On Target Board

SIO CLK

In Flashpro

SIO CLK

4.0 MHz

1 kHz

Notes 1. This is the number of V^PPpulses supplied from Flashpro III during initialization of serial

communication. The pin used for the communication is decided depending on this number.

2. Select from 9,600 bps, 19,200 bps, 38,400 bps, or 76,800 bps.

Remark COMM PORT : Selection of serial port.

SIO CLK

CPU CLK

:

Selection of serial clock frequency.

Selection of source of CPU clock to be input.

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CHAPTER 14 INSTRUCTION SET

This chapter lists the instruction set of the µPD789026 Subseries. For the details of the operation and machine

language (instruction code) of each instruction, refer to 78K/0S Series User's Manual

Instruction (U11047E).

14.1 Operation

14.1.1 Operand identifiers and writing methods

Operands are written in "Operand" column of each instruction in accordance with the writing method of the

instruction operand identifier (refer to the assembler specifications for detail). When there are two or more writing

methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are written

as they are. Each symbol has the following meaning.

• # : Immediate data specification

• ! : Absolute address specification

• $ : Relative address specification

• [ ] : Indirect address specification

In the case of immediate data, write an appropriate numeric value or a label. When using a label, be sure to

write the #, !, $ and [ ] symbols.

For operand register identifiers, r and rp, either functional names (X, A, C, etc.) or absolute names (names in

parentheses in the table below, R0, R1, R2, etc.) can be used.

Table 14-1. Operand Identifiers and Writing Methods

Identifier

Writing Method

r

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special-function register symbol

rp

sfr

saddr

FE20H to FF1FH Immediate data or labels

saddrp

FE20H to FF1FH Immediate data or labels (even addresses only)

addr16

addr5

0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)

0040H to 007FH Immediate data or labels (even addresses only)

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

Remark See Table 3-4 for symbols of special function registers.

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14.1.2 Description of "Operation" column

A

: A register; 8-bit accumulator

X

: X register

B

: B register

C

: C register

D

: D register

E

: E register

H

: H register

L

: L register

AX

BC

DE

HL

PC

SP

PSW

CY

AC

Z

: AX register pair; 16-bit accumulator

: BC register pair

: DE register pair

: HL register pair

: Program counter

: Stack pointer

: Program status word

: Carry flag

: Auxiliary carry flag

: Zero flag

IE

: Interrupt request enable flag

NMIS : Flag indicating non-maskable interrupt servicing in progress

( ) : Memory contents indicated by address or register contents in parentheses

×^H, ×^L: High-order 8 bits and low-order 8 bits of 16-bit register

: Logical product (AND)

: Logical sum (OR)

: Exclusive logical sum (exclusive OR)

: Inverted data

addr16 : 16-bit immediate data or label

jdisp8 : Signed 8-bit data (displacement value)

14.1.3 Description of "Flag" column

(Blank) : Unchanged

0

1

×

R

: Cleared to 0

: Set to 1

: Set/cleared according to the result

: Previously saved value is restored

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CHAPTER 14 INSTRUCTION SET

14.2 Operation List

Mnemonic

MOV

Operands

Byte

Clock

Operation

Flag

Z

AC CY

r,#byte

3

2

3

2

1

2

1

2

1

2

6

4

8

6

4

6

4

6

8

r ← byte

saddr,#byte

sfr,#byte

A,r ^{Note 1}

(saddr) ← byte

sfr ← byte

A ← r

r,A ^{Note 1}

r ← A

A,saddr

saddr,A

A,sfr

A ← (saddr)

(saddr) ← A

A ← sfr

sfr,A

sfr ← A

A,!addr16

!addr16,A

PSW,#byte

A,PSW

PSW,A

A,[DE]

A ← (addr16)

(addr16) ← A

PSW ← byte

A ← PSW

PSW ← A

A ← (DE)

(DE) ← A

A ← (HL)

×

[DE],A

A,[HL]

[HL],A

(HL) ← A

A,[HL+byte]

[HL+byte],A

A,X

A ← (HL+byte)

(HL+byte) ← A

A ↔ X

XCH

A,r^{Note 2}

A ↔ r

A,saddr

A,sfr

A ↔ (saddr)

A ↔ sfr

A,[DE]

A ↔ (DE)

A ↔ (HL)

A ↔ (HL+byte)

A,[HL]

A,[HL+byte]

Notes 1. Except r = A.

2. Except r = A, X.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by processor clock control register

(PCC).

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Mnemonic

MOVW

Operands

Byte

Clock

Operation

Flag

Z

AC CY

rp,#word

3

2

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

6

8

4

8

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

rp ← word

AX,saddrp

saddrp,AX

AX,rp^Note

rp,AX^Note

AX,rp^Note

A,#byte

saddr,#byte

A,r

AX ← (saddrp)

(saddrp) ← AX

AX ← rp

rp ← AX

XCHW

ADD

AX ↔ rp

A,CY ← A + byte

×

(saddr),CY ← (saddr) + byte

A,CY ← A + r

A,saddr

A,!addr16

A,[HL]

A,CY ← A + (saddr)

A,CY ← A + (addr16)

A,CY ← A + (HL)

A,[HL+byte]

A,#byte

saddr,#byte

A,r

A,CY ← A + (HL+byte)

A,CY ← A + byte + CY

(saddr),CY ← (saddr) + byte + CY

A,CY ← A + r + CY

ADDC

A,saddr

A,!addr16

A,[HL]

A,CY ← A + (saddr) + CY

A,CY ← A + (addr16) + CY

A,CY ← A + (HL) + CY

A,CY ← A + (HL+byte) + CY

A,CY ← A − byte

A,[HL+byte]

A,#byte

saddr,#byte

A,r

SUB

(saddr),CY ← (saddr) − byte

A,CY ← A − r

A,saddr

A,!addr16

A,[HL]

A,CY ← A − (saddr)

A,CY ← A − (addr16)

A,CY ← A − (HL)

A,[HL+byte]

A,CY ← A − (HL+byte)

Note Only when rp = BC, DE, or HL.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by processor clock control register

(PCC).

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Mnemonic

SUBC

Operands

Byte

Clock

Operation

Flag

Z

×

AC CY

A,#byte

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

A,CY ← A − byte − CY

×

saddr,#byte

A,r

(saddr),CY ← (saddr) − byte − CY

A,CY ← A − r − CY

A,saddr

A,!addr16

A,[HL]

A,CY ← A − (saddr) − CY

A,CY ← A − (addr16) − CY

A,CY ← A − (HL) − CY

A,CY ← A − (HL+byte) − CY

A ← A byte

A,[HL+byte]

A,#byte

saddr,#byte

A,r

AND

(saddr) ← (saddr) byte

A ← A

r

A,saddr

A,!addr16

A,[HL]

A ← A (saddr)

A ← A (addr16)

A ← A (HL)

A,[HL+byte]

A,#byte

saddr,#byte

A,r

A ← A (HL+byte)

A ← A byte

OR

(saddr) ← (saddr) byte

A ← A

r

A,saddr

A,!addr16

A,[HL]

A ← A (saddr)

A ← A (addr16)

A ← A (HL)

A,[HL+byte]

A,#byte

saddr,#byte

A,r

A ← A (HL+byte)

A ← A byte

XOR

(saddr) ← (saddr) byte

A ← A

r

A,saddr

A,!addr16

A,[HL]

A ← A (saddr)

A ← A (addr16)

A ← A (HL)

A,[HL+byte]

A ← A (HL+byte)

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by processor clock control register

(PCC).

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CHAPTER 14 INSTRUCTION SET

Mnemonic

CMP

Operands

Byte

Clock

Operation

Flag

Z

×

AC CY

A,#byte

2

3

2

3

1

2

3

2

1

3

2

3

2

3

2

3

2

1

4

6

4

8

6

4

2

6

4

6

10

6

4

6

10

2

A − byte

×

saddr,#byte

A,r

(saddr) − byte

A − r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

AX,#word

r

A − (saddr)

A − (addr16)

A − (HL)

A − (HL+byte)

ADDW

SUBW

CMPW

INC

AX,CY ← AX + word

AX,CY ← AX − word

AX − word

r ← r + 1

saddr

r

(saddr) ← (saddr) + 1

r ← r − 1

DEC

saddr

rp

(saddr) ← (saddr) − 1

rp ← rp + 1

INCW

DECW

ROR

rp

rp ← rp − 1

A,1

(CY,A⁷← A⁰,A^m⁻¹← A^m) × 1

(CY,A⁰← A⁷,A^m+1← A^m) × 1

(CY ← A⁰,A⁷← CY,A^m⁻¹← A^m) × 1

(CY ← A⁷,A⁰← CY,A^m+1← A^m) × 1

(saddr.bit) ← 1

sfr.bit ← 1

×

ROL

A,1

RORC

ROLC

SET1

A,1

saddr.bit

sfr.bit

A.bit

A.bit ← 1

PSW.bit

[HL].bit

saddr.bit

sfr.bit

A.bit

PSW.bit ← 1

×

(HL).bit ← 1

CLR1

(saddr.bit) ← 0

sfr.bit ← 0

A.bit ← 0

PSW.bit

[HL].bit

CY

PSW.bit ← 0

×

(HL).bit ← 0

SET1

CLR1

NOT1

CY ← 1

1

0

×

CY

CY ← 0

CY

CY ← CY

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by processor clock control register

(PCC).

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Mnemonic

Operands

Byte

Clock

Operation

Flag

Z

AC CY

CALL

!addr16

[addr5]

3

1

6

8

(SP−1) ← (PC+3)^H, (SP−2) ← (PC+3)^L,

PC ← addr16, SP ← SP − 2

CALLT

(SP−1) ← (PC+1)^H, (SP−2) ← (PC+1)^L,

PC^H← (00000000,addr5+1),

PC^L← (00000000,addr5), SP ← SP − 2

RET

1

6

8

PC^H← (SP+1), PC^L← (SP), SP ← SP + 2

RETI

PC^H← (SP+1), PC^L← (SP),

R

PSW ← (SP+2), SP ← SP + 3, NMIS ← 0

PUSH

POP

PSW

1

2

3

2

1

2

4

3

4

3

4

2

3

2

4

(SP−1) ← PSW, SP ← SP − 1

(SP−1) ← rp^H, (SP−2) ← rp^L, SP ← SP − 2

PSW ← (SP), SP ← SP + 1

rp

PSW

4

rp

6

rp^H← (SP+1), rp^L← (SP), SP ← SP + 2

SP ← AX

MOVW

BR

SP,AX

AX,SP

!addr16

$addr16

AX

8

6

AX ← SP

6

PC ← addr16

6

PC ← PC + 2 + jdisp8

6

PC^H← A, PC^L← X

BC

$saddr16

6

PC ← PC + 2 + jdisp8 if CY = 1

PC ← PC + 2 + jdisp8 if CY = 0

PC ← PC + 2 + jdisp8 if Z = 1

PC ← PC + 2 + jdisp8 if Z = 0

PC ← PC + 4 + jdisp8 if (saddr.bit) = 1

PC ← PC + 4 + jdisp8 if sfr.bit = 1

PC ← PC + 3 + jdisp8 if A.bit = 1

PC ← PC + 4 + jdisp8 if PSW.bit = 1

PC ← PC + 4 + jdisp8 if (saddr.bit) = 0

PC ← PC + 4 + jdisp8 if sfr.bit = 0

PC ← PC + 3 + jdisp8 if A.bit = 0

PC ← PC + 4 + jdisp8 if PSW.bit = 0

B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0

C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0

BNC

BZ

6

BNZ

BT

6

saddr.bit,$addr16

sfr.bit,$addr16

A.bit,$addr16

PSW.bit,$addr16

saddr.bit,$addr16

sfr.bit,$addr16

A.bit,$addr16

PSW.bit,$addr16

B,$addr16

10

8

10

8

BF

10

6

DBNZ

C,$addr16

6

saddr,$addr16

8

(saddr) ← (saddr) − 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

NOP

EI

1

3

1

2

6

2

No Operation

IE ← 1 (Enable Interrupt)

IE ← 0 (Disable Interrupt)

Set HALT Mode

DI

HALT

STOP

Set STOP Mode

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by processor clock control register

(PCC).

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14.3 Instructions Listed by Addressing Type

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,

POP, DBNZ

2nd Operand

1st Operand

#byte

A

r

sfr

saddr !addr16

PSW

[DE]

[HL]

$addr16

1

None

[HL+byte]

A

ADD

MOV^NoteMOV

XCH^NoteXCH

ADD

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

ROR

ADDC

SUB

SUBC

AND

OR

ROL

ADD

ADDC

SUB

SUBC

AND

OR

RORC

ROLC

ADDC

SUB

SUBC

XOR

CMP

AND

OR

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

r

MOV

INC

DEC

B, C

sfr

DBNZ

MOV

saddr

MOV

ADD

ADDC

SUB

SUBC

AND

OR

INC

DEC

XOR

CMP

!addr16

PSW

MOV

PUSH

POP

[DE]

MOV

[HL]

[HL+byte]

Note Except r = A.

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CHAPTER 14 INSTRUCTION SET

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand

1st Operand

#word

AX

rp^Note

saddrp

SP

None

AX

ADDW

MOVW

XCHW

MOVW

SUBW

CMPW

rp

MOVW

MOVW^Note

INCW

DECW

PUSH

POP

saddrp

SP

MOVW

Note Only when rp = BC, DE, or HL.

(3) Bit manipulation instructions

SET1, CLR1, NOT1, BT, BF

2nd Operand

1st Operand

$addr16

None

A.bit

BT

BF

SET1

CLR1

sfr.bit

BT

BF

SET1

CLR1

saddr.bit

PSW.bit

[HL].bit

CY

BT

BF

SET1

CLR1

BT

BF

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

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CHAPTER 14 INSTRUCTION SET

(4) Call instructions/branch instructions

CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ

2nd Operand

1st Operand

AX

!addr16

[addr5]

$addr16

Basic instructions

BR

CALL

BR

CALLT

BR

BC

BNC

BZ

BNZ

Compound instructions

DBNZ

(5) Other instructions

RET, RETI, NOP, EI, DI, HALT, STOP

194

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APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for development of systems using the µPD789026 Subseries.

Figure A-1 shows development tools.

• Compatibility with PC98-NX series

Unless stated otherwise, products which are supported for the IBM PC/AT^TMcompatibles can also be used with

the PC98-NX series. When using the PC98-NX series, therefore, refer to the explanations for the IBM PC/AT

compatibles.

• Windows

Unless stated otherwise, "Windows" refers to the following operating systems.

• Windows 3.1

• Windows 95

• Windows NT^TMVer. 4.0

195

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tools

Language Processing Software

Embedded Software

• Assembler package

• C compiler package

• System simulator

• Device file

• OS

• C compiler source file

• Integrated debugger

Host Machine

(PC or EWS)

Interface adapter

Flash Memory

Writing Environment

In-Circuit Emulator

Emulation board

Flash writer

Power-Supply Unit

Flash memory

writing adapter

Emulation Probe

Flash memory

Conversion socket

Target System

196

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APPENDIX A DEVELOPMENT TOOLS

A.1 Language Processing Software

RA78K0S

Program that converts program written in mnemonic into object code that can be executed by

microcontroller.

Assembler package

In addition, automatic functions to generate symbol table and optimize branch instructions are also

provided.

Used in combination with optional device file (DF789026).

The assembler package is a DOS-based application but may be used under the Windows

environment by using Project Manager of Windows (included in the assembler package).

Part number: µS××××RA78K0S

CC78K0S

Program that converts program written in C language into object codes that can be executed by

microcontroller.

C compiler package

Used in combination with optional assembler package (RA78K0S) and device file (DF789026).

The C compiler package is a DOS-based application but may be used under the Windows

environment by using Project Manager of Windows (included in the assembler package).

Part number: µS××××CC78K0S

DF789026^Note

Device file

File containing the information inherent to the device.

Used in combination with other optional tools (RA78K0S, CC78K0S, SM78K0S).

Part number: µS××××DF789026

CC78K0S-L

Source file of functions constituting object library included in C compiler package.

C compiler source file

Necessary for changing object library included in C compiler package according to customer's

specifications.

Since this is the source file, its working environment does not depend on any particular operating

system.

Part number: µS××××CC78K0S-L

Note DF789026 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S.

Remark ×××× in the part number differs depending on the host machines and operating systems to be used.

µS××××RA78K0S

µS××××CC78K0S

µS××××DF789026

µS××××CC78K0S-L

××××

AA13

Host Machine

PC-9800 series

OS

Supply Media

3.5" 2HD FD

Japanese Windows^Note

HP-UX^TM(Rel.10.10)

AB13

3P16

3K13

3K15

3R13

IBM PC/AT compatibles

HP9000 series 700^TM

SPARCstation^TM

3.5" 2HC FD

DAT (DDS)

3.5" 2HC FD

1/4" CGMT

3.5" 2HC FD

SunOS^TM(Rel.4.1.1),

Solaris^TM(Rel.2.5.1)

NEWS^TM(RISC)

NEWS-OS^TM(Rel.6.1)

Note Also operates under the DOS environment.

197

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APPENDIX A DEVELOPMENT TOOLS

A.2 Flash Memory Writing Tools

Flashpro III

Flash writer dedicated to microcontrollers with flash memory.

(part number: FL-PR3, PG-FP3)

Flash writer

FA-42CU

Flash memory writing adapter. Used in connection with Flashpro III.

• FA-42CU: For 42-pin plastic shrink DIP (CU type)

• FA-44GB: For 44-pin plastic QFP (GB-3BS type)

FA-44GB

FA-44GB-8ES

Flash memory writing adapter

• FA-44GB-8ES: For 44-pin plastic LQFP (GB-8ES type)

Remark FL-PR3, FA-42CU, FA-44GB, and FA-44GB-8ES are products of Naito Densei Machida Mfg. Co., Ltd.

For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (044-822-3813)

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APPENDIX A DEVELOPMENT TOOLS

A.3 Debugging Tools

A.3.1 Hardware

IE-78K0S-NS

In-circuit emulator for debugging hardware and software upon developing the application

system using 78K/0S series. Supports integrated debugger (ID78K0S-NS). Used in

combination with AC adapter, emulation probe, and interface adapter for connecting the host

machine.

In-circuit emulator

IE-70000-MC-PS-B

AC adapter

This is the adapter for supplying power from 100 to 240 VAC outlet.

IE-70000-98-IF-C

Interface adapter

This adapter is needed when PC-9800 series (excluding notebook models) is used as a host

machine of IE-78K0S-NS (C bus compatible).

IE-70000-CD-IF-A

PC card interface

This PC card and interface cable are needed when a notebook-type personal computer is

used as a host machine of IE-78K0S-NS (PCMCIA socket compatible).

IE-70000-PC-IF-C

Interface adapter

This adapter is needed when IBM PC/AT compatibles are used as a host machine of IE-

78K0S-NS (ISA bus compatible).

IE-70000-PCI-IF

Interface adapter

This adapter is needed when a personal computer incorporating the PCI bus is used as a host

machine of IE-78K0S-NS.

IE-789026-NS-EM1

Emulation board

Emulation board for emulating the peripheral hardware inherent to the device.

Used in combination with in-circuit emulator.

NP-44GB^Note

Emulation probe for connecting the in-circuit emulator and target system. This is for the

44-pin plastic QFP (GB-3BS type) and the 44-pin plastic LQFP (GB-8ES type).

Emulation probe

EV-9200G-44

This conversion adapter is used to connect a target system board designed to allow mounting

of the 44-pin plastic QFP (GB-3BS type) and the 44-pin plastic LQFP (GB-8ES type) and the

NP-44GB.

Conversion adapter

NP-44GB-TQ

Emulation probe for connecting the in-circuit emulator and target system. This is for the

44-pin plastic QFP (GB-3BS type) and the 44-pin plastic LQFP (GB-8ES type).

Emulation probe

TGB-044SAP

This conversion adapter is used to connect a target system board designed to allow mounting

of the 44-pin plastic QFP (GB-3BS type) and the 44-pin plastic LQFP (GB-8ES type) and the

NP-44GB-TQ.

Conversion adapter

Remarks 1. NP-44GB and NP-44GB-TQ are products of Naito Densei Machida Mfg. Co., Ltd.

For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (044-822-3813)

2. TGB-044SAP is a product of TOKYO ELETECH CORPORATION.

For further information, contact: Daimaru Kougyou, Ltd.

Tokyo Electronics Department (03-3820-7112)

Osaka Electronics Department (06-6244-6672)

199

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APPENDIX A DEVELOPMENT TOOLS

A.3.2 Software

ID78K0S-NS

Control program for debugging 78K/0S Series.

Integrated debugger

(Supports in-circuit emulator

IE78K0S-NS)

This program provides a graphical user interface. It runs on Windows for personal computer

users and on OSF/Motif^TMfor engineering work station users, and has visual designs and

operationability that comply with these operating systems. In addition, it has a powerful debug

function that supports C language. Therefore, trace results can be displayed at a C language

level by the window integration function that links source program, disassembled display, and

memory display, to the trace result. This software also allows users to add other function

extension modules such as task debugger and system performance analyzer to improve the

debug efficiency for programs using a real-time operating system.

Used in combination with optional device file (DF789026).

Part number: µS××××ID78K0S-NS

Remark ×××× in the part number differs depending on the host machines and operating system to be used.

µS××××ID78K0S-NS

××××

Host Machine

PC-9800 series

IBM PC/AT compatibles

OS

Supply Media

3.5" 2HD FD

3.5" 2HC FD

AA13

AB13

Japanese Windows^Note

Note Also operates under the DOS environment.

SM78K0S

Debugs program at C source level or assembler level while simulating operation of target

system on host machine.

System simulator

SM78K0S runs on Windows.

By using SM78K0S, the logic and performance of an application can be verified independently

of hardware development even when the in-circuit emulator is not used. This enhances

development efficiency and improves software quality.

Used in combination with optional device file (DF789026).

Part number: µS××××SM78K0S

DF789026^Note

Device file

File containing the information inherent to the device.

Used in combination with other optional tools (RA78K0S, CC78K0S, SM78K0S).

Part number: µS××××DF789026

Note DF789026 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S.

Remark ×××× in the part number differs depending on the host machines and operating system to be used.

µS××××SM78K0S

××××

Host Machine

PC-9800 series

IBM PC/AT compatibles

OS

Supply Media

3.5" 2HD FD

3.5" 2HC FD

AA13

AB13

Japanese Windows^Note

Note Also operates under the DOS environment.

200

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APPENDIX A DEVELOPMENT TOOLS

A.4 Conversion Socket (EV-9200G-44) Drawing and Recommended Footprint

Figure A-2. EV-9200G-44 Package Drawing (Reference)

Based on EV-9200G-44

(1) Package drawing (in mm)

A

B

M

N

E

O

F

EV-9200G-44

1

No.1 pin index

G

H

I

EV-9200G-44-G0

ITEM

A

MILLIMETERS

15.0

10.3

15.0

4-C 3.0

0.8

INCHES

0.591

0.406

0.591

4-C 0.118

0.031

0.197

0.472

0.579

0.197

0.472

0.579

0.315

0.307

0.079

B

C

D

E

F

G

H

I

5.0

12.0

14.7

5.0

J

K

12.0

14.7

8.0

L

M

O

N

P

7.8

2.0

1.35

0.053

+0.004

±

Q

R

0.35 0.1

0.014

–0.005

1.5

0.059

201

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APPENDIX A DEVELOPMENT TOOLS

Figure A-3. EV-9200G-44 Recommended Footprint (Reference)

Based on EV-9200G-44

(2) Pad drawing (in mm)

G

J

K

L

C

B

A

EV-9200G-44-P1E

ITEM

MILLIMETERS

15.7

INCHES

0.618

A

B

C

D

E

F

G

H

I

11.0

0.433

0.8 0.02 × 10=8.0 0.05 0.031^+0.002

+0.002

_–0.001× 0.394=0.315

–0.002

±

+0.002

_–0.001× 0.394=0.315

–0.002

0.8 0.02 × 10=8.0 0.05 0.031^+0.002

±

11.0

15.7

0.433

0.618

0.197

+0.003

–0.004

±

5.00 0.08

+0.003

–0.004

±

5.00 0.08

+0.001

±

0.5 0.02

0.02

–0.002

+0.001

±

J

1.57 0.03

0.062

–0.002

+0.004

–0.005

±

K

L

2.2 0.1

0.087

0.062

+0.001

–0.002

±

1.57 0.03

Dimensions of mount pad for EV-9200 and that for target

device (QFP) may be different in some parts. For the

recommended mount pad dimensions for QFP, refer to

"SEMICONDUCTOR DEVICE MOUNTING

Caution

TECHNOLOGY MANUAL" (C10535E).

202

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APPENDIX A DEVELOPMENT TOOLS

A.5 Conversion Adapter (TGB-044SAP) Drawing

Figure A-4. TGB-044SAP Package Drawing (Reference)

Reference diagram: TGB-044SAP (TQPACK044SA+TQSOCKET044SAP)

Package dimension (unit: mm)

A

H

B

C

P

D

E

F

G

N O

Protrusion height

Q

S

J

K

I

T

L

M

X

R

g

f

U

W

ITEM MILLIMETERS

INCHES

ITEM MILLIMETERS

INCHES

0.079

a

A

B

C

D

E

F

10.12

0.8x10=8.0

0.8

0.398

a

b

c

d

e

f

2.0

0.25

9.6

1.2

2.4

2.7

0.031x0.394=0.315

0.031

0.010

0.378

0.047

0.094

0.106

V

Z

0.656

16.65

8.4

0.331

10.8

13.2

C 2.0

9.35

1.325

12.0

16.65

8.5

0.425

Y

G

H

I

0.520

g

C 0.079

0.368

TGB-044SAP-G0E

b

d

e

c

J

0.052

K

L

0.052

0.472

M

N

O

P

Q

R

S

T

0.656

0.335

13.15

5.0

0.518

0.197

1.8

0.071

φ

3.55

0.9

φ

0.140

0.035

0.012

0.3

U

V

W

X

Y

Z

(16.95)

7.35

1.2

(0.667)

0.289

0.047

0.236

0.073

0.138

6.0

1.85

3.5

note: Product by TOKYO ELETECH CORPORATION.

203

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[MEMO]

204

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APPENDIX B EMBEDDED SOFTWARE

The following embedded software products are available for efficient program development and maintenance of

the µPD789026 Subseries.

MX78K0S

OS

MX78K0S is a subset OS that is based on the µITRON specification. Supplied with the

MX78K0S nucleus. The MX78K0S OS controls tasks, events, and time. In task control, the

MX78K0S OS controls task execution order, and performs the switching process to a task to

be executed.

The MX78K0S is a DOS-based application. Use this software in the DOS pane when running

it on Windows.

Remark ×××× in the part number differs depending on the host machines and operating system to be used.

µS××××MX78K0S

××××

AA13

Host Machine

PC-9800 series

IBM PC/AT compatibles

OS

Supply Media

3.5" 2HD FD

3.5" 2HC FD

Japanese Windows^Note

English Windows^Note

AB13

BB13

Note Also operates under the DOS environment.

205

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[MEMO]

206

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APPENDIX C REGISTER INDEX

C.1 Register Name Index

16-bit capture register 20 (TCP20).............................................................................................................................. 95

16-bit compare register 20 (CR20).............................................................................................................................. 95

16-bit timer counter 20 (TM20).................................................................................................................................... 95

16-bit timer mode control register 20 (TMC20) ........................................................................................................... 96

8-bit compare register 00 (CR00).............................................................................................................................. 106

8-bit timer counter 00 (TM00).................................................................................................................................... 106

8-bit timer mode control register 00 (TMC00) ........................................................................................................... 107

[A]

Asynchronous serial interface mode register 00 (ASIM00)............................................................... 126, 133, 135, 146

Asynchronous serial interface status register 00 (ASIS00)............................................................................... 128, 136

[B]

Baud rate generator control register 00 (BRGC00)................................................................................... 129, 137, 147

[E]

External interrupt mode register 0 (INTM0)............................................................................................................... 155

[I]

Interrupt mask flag register 0 (MK0).......................................................................................................................... 154

Interrupt mask flag register 1 (MK1).......................................................................................................................... 154

Interrupt request flag register 0 (IF0) ........................................................................................................................ 153

Interrupt request flag register 1 (IF1) ........................................................................................................................ 153

[K]

Key return mode register 00 (KRM00) ...................................................................................................................... 157

[O]

Oscillation settling time select register (OSTS)......................................................................................................... 168

[P]

Port 0 (P0)................................................................................................................................................................... 71

Port 1 (P1)................................................................................................................................................................... 72

Port 2 (P2)................................................................................................................................................................... 73

Port 3 (P3)................................................................................................................................................................... 76

Port 4 (P4)................................................................................................................................................................... 77

Port 5 (P5)................................................................................................................................................................... 78

Port mode register 0 (PM0)......................................................................................................................................... 81

Port mode register 1 (PM1)......................................................................................................................................... 81

Port mode register 2 (PM2)......................................................................................................................................... 81

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APPENDIX C REGISTER INDEX

Port mode register 3 (PM3)..........................................................................................................................................81

Port mode register 4 (PM4)..........................................................................................................................................81

Port mode register 5 (PM5)............................................................................................................................81, 98, 108

Processor clock control register (PCC)........................................................................................................................86

Pull-up resistor option register (PUO) ..........................................................................................................................82

[R]

Receive buffer register 00 (RXB00) ...........................................................................................................................124

Receive shift register 00 (RXS00)..............................................................................................................................124

[S]

Serial operation mode register 00 (CSIM00)......................................................................................125, 132, 134, 145

[T]

Timer clock select register 2 (TCL2)..........................................................................................................................117

Transmit shift register 00 (TXS00) .............................................................................................................................124

[W]

Watchdog timer mode register (WDTM) ....................................................................................................................118

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APPENDIX C REGISTER INDEX

C.2 Register Symbol Index

[A]

ASIM00 : Asynchronous serial interface mode register 00............................................................ 126, 133, 135, 146

ASIS00 : Asynchronous serial interface status register 00 ........................................................................... 128, 136

[B]

BRGC00 : Baud rate generator control register 00 ................................................................................. 129, 137, 147

[C]

CR00

CR20

: 8-bit compare register 00 ...................................................................................................................... 106

: 16-bit compare register 20 ...................................................................................................................... 95

CSIM00 : Serial operation mode register 00................................................................................. 125, 132, 134, 145

[I]

IF0

: Interrupt request flag register 0............................................................................................................. 153

: Interrupt request flag register 1............................................................................................................. 153

: External interrupt mode register 0......................................................................................................... 155

IF1

INTM0

[K]

KRM00 : Key return mode register 00.................................................................................................................. 157

[M]

MK0

MK1

: Interrupt mask flag register 0 ................................................................................................................ 154

: Interrupt mask flag register 1 ................................................................................................................ 154

[O]

OSTS

[P]

: Oscillation settling time select register.................................................................................................. 168

P0

: Port 0....................................................................................................................................................... 71

: Port 1....................................................................................................................................................... 72

: Port 2....................................................................................................................................................... 73

: Port 3....................................................................................................................................................... 76

: Port 4....................................................................................................................................................... 77

: Port 5....................................................................................................................................................... 78

: Processor clock control register.............................................................................................................. 86

: Port mode register 0................................................................................................................................ 81

: Port mode register 1................................................................................................................................ 81

: Port mode register 2................................................................................................................................ 81

: Port mode register 3................................................................................................................................ 81

: Port mode register 4................................................................................................................................ 81

: Port mode register 5.................................................................................................................. 81, 98, 108

: Pull-up resistor option register ............................................................................................................... 82

P1

P2

P3

P4

P5

PCC

PM0

PM1

PM2

PM3

PM4

PM5

PUO

[R]

RXB00

RXS00

: Receive buffer register 00..................................................................................................................... 124

: Receive shift register 00........................................................................................................................ 124

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APPENDIX C REGISTER INDEX

[T]

TCL2

TCP20

TM00

TM20

: Timer clock select register 2 ..................................................................................................................117

: 16-bit capture register 20 .........................................................................................................................95

: 8-bit timer counter 00 .............................................................................................................................106

: 16-bit timer counter 20 .............................................................................................................................95

TMC00 : 8-bit timer mode control register 00 .......................................................................................................107

TMC20 : 16-bit timer mode control register 20 .......................................................................................................96

TXS00

: Transmit shift register 00........................................................................................................................124

[W]

WDTM

: Watchdog timer mode register...............................................................................................................118

210

User's Manual U11919EJ3V0UM00

APPENDIX D REVISION HISTORY

Here is the revision history of this manual. "Chapter" indicates the chapter of the previous edition.

Edition

Revision from Previous Edition

Chapter

Second edition

Change of µPD789025 and µPD789026 from "under development" to

Throughout

"developed"

Change of symbols in Table 3-4

Chapter 3 CPU Architecture

Change of asynchronous serial interface status register 00 so that it can

be manipulated in 1-bit units

Change of block diagram of each port in Section 4.2

Chapter 4 Port Functions

Change of symbols and flag names of 16-bit timer mode control register

20

Chapter 6 16-Bit Timer

Counter

Change of symbols and flag names of 8-bit timer mode control register 00

Chapter 7 8-Bit Timer/Event

Counter

Change of symbols and flag names of serial operation mode register 00

Chapter 9 Serial Interface 00

Change of symbols and flag names of asynchronous serial interface

mode register 00

Change of symbols and flag names of asynchronous serial interface

status register 00

Change of asynchronous serial interface status register 00 so that 1-bit

memory manipulation instruction can be used

Change of symbols and flag names of baud rate generator control register

00

Change of flag names of interrupt request flag register

Change of flag names of interrupt mask flag register

Change of symbols and flag names of key return mode register 00

Addition of description on timing of maskable interrupt request acceptance

Addition of setting with Flashpro II

Chapter 10 Interrupt Functions

Chapter 13 µPD78F9026

Third edition

Completion of development of µPD789022 and µPD789024

Change of part number from µPD78F9026 to µPD78F9026A

Throughout

Deletion of following products:

µPD789022CU-×××, µPD789024CU-×××

Addition of GB-8ES type package to all models

Change of circuit type and recommended connection of unused pins in

processing of input/output circuit type of each pin and unused pins

CHAPTER 2 PIN FUNCTION

CHAPTER 6 16-BIT TIMER

Addition of cautions on rewriting CR20 to operation as timer interrupt

Addition of cautions on rewriting CR00 to 8-bit compare register 00

(CR00)

CHAPTER 7 8-BIT

TIMER/EVENT COUNTER

Addition of description of operation to operation as interval timer

Addition of description of operation to operation as external event counter

Addition of description of operation to operation as square wave output

Change of flash writer from Flashpro II to Flashpro III

CHAPTER 13 µPD78F9026A

Addition of part number of MX78K0S to embedded software

APPENDIX B EMBEDDED

SOFTWARE

211

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[MEMO]

212

User's Manual U11919EJ3V0UM00

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toensurethatthedocumentationsupplied

to our customers is complete, bug free

and up-to-date, we readily accept that

errorsmayoccur. Despiteallthecareand

precautions we've taken, you may

encounterproblemsinthedocumentation.

Please complete this form whenever

you'd like to report errors or suggest

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CS 00.6


型号：	UPD789026
厂家：	NEC
描述：	8-Bit Single-Chip Microcontrollers 8位单芯片微控制器微控制器
文件：	总213页 (文件大小：816K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD789026 [NEC]

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