UPD789046GB-XXX-8ES-A [NEC]
Microcontroller, 8-Bit, MROM, 5MHz, MOS, PQFP44, 10 X 10 MM, LEAD FREE, PLASTIC, LQFP-44;
| 型号： | UPD789046GB-XXX-8ES-A |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 8-Bit, MROM, 5MHz, MOS, PQFP44, 10 X 10 MM, LEAD FREE, PLASTIC, LQFP-44 微控制器 |
| 文件： | 总49页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD789046
8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD789046 is a µPD789046 Subseries (small-scale, general-purpose applications) product of the 78K/0S
Series.
A flash memory version (µPD78F9046) that can operate within the same power supply voltage range as the mask
ROM version, and various development tools are being developed.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD789046 Subseries User’s Manual:
U13600E
78K/0S Series Instructions User’s Manual: U11047E
FEATURES
•
•
•
Internal ROM: 16 Kbytes
Internal high-speed RAM: 512 bytes
Minimum instruction execution time can be changed from high-speed (0.4 µs: @ 5.0-MHz operation with main
system clock) to ultra-low-speed (122 µs: @ 32.768-kHz operation with subsystem clock)
•
•
I/O ports: 34
Serial interface: 1 channel
Switchable between 3-wire serial I/O and UART modes
Timer: 4 channels
•
•
•
•
•
16-bit timer counter: 1 channel
8-bit timer/event counter: 1 channel
Watch timer: 1 channel
Watchdog timer: 1 channel
•
•
•
Vectored interrupt source: 12
Power supply voltage: VDD = 1.8 to 5.5 V
Operating ambient temperature: T
A
= −40 to +85°C
APPLICATIONS
Cordless phones, etc.
ORDERING INFORMATION
Part Number
Package
µPD789046GB-×××-8ES
44-pin plastic LQFP (10 × 10)
µPD789046GB-×××-8ES-A 44-pin plastic LQFP (10 × 10)
Remark 1. ××× indicates ROM code suffix.
2. Products with -A at the end of the part number are lead-free products.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U13380EJ1V2DS00 (1st edition)
Date Published August 2005 N CP(K)
Printed in Japan
The mark
shows major revised points.
1998, 1999
µPD789046
78K/0S SERIES LINEUP
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
In mass-production
Under development
For small-scale, general-
purpose applications
µ
µ
PD789026 with internal subsystem clock
44-pin
µ
µ
µ
PD789046
PD789014 with enhanced timer and expanded ROM and RAM
42/44-pin
28-pin
PD789026
PD789014
On-chip UART and capable of low-voltage (1.8 V) operation
For small-scale, general-
purpose applications and A/D function
µ
µ
µ
µ
µ
µ
µ
PD789217AY
44/48-pin
44/48-pin
44-pin
RC oscillation version of the
µ
PD789197AY
PD789197AY
PD789177
PD789167
PD789156
PD789146
PD789134A
µ
µ
µ
µ
µ
µ
PD789177 with internal EEPROMTM and SMB
PD789167 with enhanced A/D converter
PD789104A with enhanced timer
44-pin
30-pin
30-pin
PD789146 with enhanced A/D converter
PD789104A with EEPROM
PD789124A with enhanced A/D converter
28/30-pin
28/30-pin
28/30-pin
28/30-pin
RC oscillation version of the
µ
PD789104A
PD789104A with enhanced A/D converter
PD789026 with A/D converter and multiplier
µPD789124A
PD789114A
µ
µ
µ
µ
PD789104A
For inverter control
PD789842
µ
44-pin
On-chip inverter control circuit and UART
78K/0S
Series
For LCD driving
µ
PD789830
On-chip UART and dot LCD
88-pin
80-pin
µ
PD789417A
µ
PD789407A
µ
PD789457
µ
PD789407A with enhanced A/D converter
µ
µ
PD789457 with enhanced I/O
PD789447 with enhanced A/D converter
80-pin
64-pin
64-pin
64-pin
64-pin
RC oscillation version of the
µ
PD789427
PD789427 with enhanced A/D converter
PD789306 with A/D converter
PD789306
µPD789447
µ
PD789437
µPD789427
µPD789316
µPD789306
µ
µ
RC oscillation version of the
µ
64-pin
64-pin
Basic subseries for LCD driving
For ASSP
For PC keyboard, on-chip USB function
For key pad, on-chip POC
RC oscillation version of the µPD789860
42/44-pin
44-pin
µ
µ
µ
µ
PD789800
PD789840
PD789861
PD789860
20-pin
20-pin
For keyless entry, on-chip POC and key return circuit
For IC card
PD789810
µ
5-pin
On-chip EEPROM and security circuit
2
Data Sheet U13380EJ1V2DS
µPD789046
The major functional differences among the subseries are listed below.
V
DD
Min.
Valu
e
Function
Timer
8-bit
A/D
10-bit
A/D
ROM
Serial Interface
I/O
34
Remarks
Subseries Name
8-bit
1 ch
16-bit Watch WDT
Capacity
µPD789046
µPD789026
−
−
−
Small-
16 K
1 ch
1 ch
1 ch
1 ch (UART: 1 ch)
1.8 V
scale,
−
4 K to 16
K
general-
purpose
applications
µPD789014
−
2 K to 4 K
2 ch
3 ch
22
31
µ
PD789217A
−
Small-
16 K to 24
K
1 ch
1 ch
1 ch
8 ch 2 ch UART: 1 ch
SMB: 1 ch
1.8 V RC oscillation
version, on-chip
EEPROM
scale,
Y
general-
purpose
application
s and A/D
function
µ
PD789197A
On-chip
Y
EEPROM
µPD789177
µPD789167
µPD789156
µPD789146
µPD789134A
µPD789124A
µPD789114A
µPD789104A
µPD789842
−
1 ch (UART: 1 ch)
−
4 ch
−
8 ch
−
−
8 K to 16
K
1 ch
20
On-chip
EEPROM
4 ch
−
2 K to 8 K
4 ch
−
RC oscillation
version
4 ch
−
−
4 ch
−
4 ch
−
−
−
Inverter
control
8 K to 16
K
3 ch
Note
1 ch
1 ch
1 ch
1 ch
8 ch
1 ch (UART: 1 ch)
1 ch (UART: 1 ch)
30
4.0 V
µPD789830
µPD789417A
µPD789407A
µPD789457
µPD789447
µPD789437
µPD789427
µPD789316
−
−
7 ch
−
LCD
24 K
1 ch
3 ch
1 ch
30
43
25
2.7 V
1.8 V
driving
12 K to 24 K
7 ch
−
16 K to 24 K
2 ch
4 ch 2 ch (UART: 1 ch)
RC oscillation
version
−
4 ch
−
4 ch
−
−
4 ch
−
8 K to 16
K
23
RC oscillation
version
µPD789306
µPD789800
µPD789840
µPD789861
−
−
−
−
−
4 ch
−
−
−
ASSP
8 K
4 K
2 ch
1 ch
1 ch
2 ch (USB: 1 ch)
31
29
14
4.0 V
2.8 V
1 ch
−
−
1.8 V RC oscillation
version
µPD789860
µPD789810
−
−
−
−
−
IC card
6 K
1 ch
1
2.7 V On-chip
EEPROM
Note 10-bit timer: 1 channel
3
Data Sheet U13380EJ1V2DS
µPD789046
OVERVIEW OF FUNCTIONS
Item
Function
Internal memory
ROM
16 Kbytes
512 bytes
High-speed RAM
Minimum instruction execution time
• 0.4/1.6 µs (@ 5.0-MHz operation with main system clock)
• 122 µs (@ 32.768-kHz operation with subsystem clock)
8 bits × 8 registers
General-purpose registers
Instruction set
• 16-bit operation
• Bit manipulation (set, reset, and test), etc.
CMOS input/output: 34
I/O ports
Switchable between 3-wire serial I/O and UART modes: 1 channel
Serial interface
Timers
• 16-bit timer counter:
1 channel
• 8-bit timer/event counter: 1 channel
• Watch timer:
1 channel
1 channel
• Watchdog timer:
Timer output
2
Vectored interrupt
sources
Maskable
Internal: 7, external: 4
Internal: 1
Non-maskable
Power supply voltage
VDD = 1.8 to 5.5 V
TA = −40 to +85°C
Operating ambient temperature
Package
44-pin plastic LQFP (10 × 10 mm)
4
Data Sheet U13380EJ1V2DS
µPD789046
CONTENTS
1. PIN CONFIGURATION (Top View) ................................................................................................... 6
2. BLOCK DIAGRAM .............................................................................................................................. 7
3. PIN FUNCTIONS ................................................................................................................................. 8
3.1 Port Pins .....................................................................................................................................................
3.2 Non-Port Pins .............................................................................................................................................
8
9
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.......................................................... 10
4. MEMORY SPACE................................................................................................................................ 12
5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 13
5.1 Ports............................................................................................................................................................ 13
5.2 Clock Generator ......................................................................................................................................... 13
5.3 Timers ......................................................................................................................................................... 14
5.4 Serial Interface ........................................................................................................................................... 16
6. INTERRUPT FUNCTIONS................................................................................................................... 17
7. STANDBY FUNCTIONS...................................................................................................................... 19
8. RESET FUNCTIONS ........................................................................................................................... 19
9. INSTRUCTION SET OVERVIEW ....................................................................................................... 20
9.1 Legend ........................................................................................................................................................ 20
9.2 Operations .................................................................................................................................................. 22
10. ELECTRICAL SPECIFICATIONS....................................................................................................... 27
11. CHARACTERISTICS CURVES........................................................................................................... 38
12. PACKAGE DRAWING......................................................................................................................... 40
13. RECOMMENDED SOLDERING CONDITIONS................................................................................. 41
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 42
APPENDIX B. RELATED DOCUMENTS............................................................................................... 44
5
Data Sheet U13380EJ1V2DS
µPD789046
1. PIN CONFIGURATION (Top View)
•
44-pin plastic LQFP (10 × 10)
44 43 42 41 40 39 38 37 36 35 34
33
1
P04
P12
P11
2
32
31
30
29
28
27
26
25
24
23
P05
3
P06
P10
4
P07
P47/KR07
P46/KR06
P45/KR05
P44/KR04
P43/KR03
P42/KR02
P41/KR01
P40/KR00
5
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/SS20
P24/INTP0
P25/INTP1
P26/INTP2/CPT90
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
Caution Connect the IC0 (Internally Connected) pin directly to VSS0 or VSS1 pin.
ASCK20:
BZO90:
CPT90:
IC0:
Asynchronous Serial Input
Buzzer Output
RxD20:
SCK20:
SI20:
Receive Data
Serial Clock
Serial Input
Capture Trigger Input
Internally Connected
SO20:
SS20:
TI80:
Serial Output
Chip Select Input
Timer Input
INTP0 to INTP2: Interrupt from Peripherals
KR00 to KR07: Key Return
P00 to P07:
P10 to P17:
P20 to P27:
P30, P31:
P40 to P47:
RESET:
Port 0
Port 1
Port 2
Port 3
Port 4
Reset
TO80, TO90: Timer Output
TxD20:
Transmit Data
VDD0, VDD1:
VSS0, VSS1:
X1, X2:
Power Supply
Ground
Crystal (Main System Clock)
Crystal (Subsystem Clock)
XT1, XT2:
6
Data Sheet U13380EJ1V2DS
µPD789046
2. BLOCK DIAGRAM
8-bit timer/event
counter 80
Port 0
Port 1
Port 2
Port 3
Port 4
TI80/TO80/P27
P00 to P07
CPT90/INTP2/P26
TO90/P30
16-bit timer
counter 90
P10 to P17
P20 to P27
BZO90/P31
78K/0S
CPU core
Watch timer
ROM
P30, P31
Watchdog timer
SCK20/ASCK20/P20
SO20/TxD20/P21
Sl20/RxD20/P22
SS20/P23
P40 to P47
SIO20
RAM
RESET
X1
System control
X2
INTP0/P24
INTP1/P25
XT1
XT2
Interrupt control
INTP2/CPT90/P26
KR00/P40 to KR07/P47
V
V
DD0
DD1
V
V
SS0
SS1
IC0
7
Data Sheet U13380EJ1V2DS
µPD789046
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name
I/O
Function
After Reset
Input
Alternate Function
−
P00 to P07 I/O
Port 0
8-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
−
P10 to P17 I/O
Port 1
Input
Input
8-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
P20
P21
P22
P23
P24
P25
P26
P27
P30
I/O
Port 2
SCK20/ASCK20
SO20/TxD20
SI20/RxD20
SS20
8-bit input/output port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
INTP0
INTP1
INTP2/CPT90
TI80/TO80
TO90
I/O
Port 3
Input
Input
2-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
P31
BZO90
P40 to P47 I/O
Port 4
KR00 to KR07
8-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
8
Data Sheet U13380EJ1V2DS
µPD789046
3.2 Non-Port Pins
Pin Name
INTP0
I/O
Function
After Reset
Input
Alternate Function
Input
External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
P24
INTP1
INTP2
P25
P26/CPT90
P40 to P47
KR00 to
KR07
Input
Detection of key return signal
Input
SI20
Input
Output
I/O
Serial interface serial data input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
P22/RxD20
SO20
SCK20
SS20
ASCK20
RxD20
TxD20
TI80
Serial interface serial data output
P21/TxD20
Serial interface serial clock input/output
Serial interface chip select input
P20/ASCK20
Input
Input
Input
Output
Input
Output
Output
Output
Input
Input
−
P23
Asynchronous serial interface serial clock input
Asynchronous serial interface serial data input
Asynchronous serial interface serial data output
External count clock input to 8-bit timer (TM80)
8-bit timer (TM80) output
P20/SCK20
P22/SI20
P21/SO20
P27/TO80
TO80
TO90
BZO90
CPT90
X1
P27/TI80
16-bit timer (TM90) output
P30
16-bit timer (TM90) buzzer output
P31
Capture edge input
P26/INTP2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Connecting crystal resonator for main system clock oscillation
X2
XT1
Input
−
Connecting crystal resonator for subsystem clock oscillation
XT2
−
VDD0
Positive power supply for ports
Positive power supply except ports
Ground potential for ports
−
VDD1
−
VSS0
−
VSS1
Ground potential except ports
System reset input
RESET
IC0
Input
−
Input
−
Internally connected. Connect directly to VSS0 or VSS1.
9
Data Sheet U13380EJ1V2DS
µPD789046
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins
Pin Name
P00 to P07
I/O Circuit Type
5-H
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor.
Output: Leave open.
P10 to P17
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/SS20
8-C
P24/INTP0
P25/INTP1
P26/INTP2/CPT90
P27/TI80/TO80
P30/TO90
5-H
P31/BZO90
P40/KR00 to P47/KR07
XT1
8-C
−
Input
−
Connect to VSS0 or VSS1.
XT2
Leave open.
−
RESET
2
Input
−
−
IC
Connect directly to VSS0 or VSS1.
10
Data Sheet U13380EJ1V2DS
µPD789046
Figure 3-1. Pin Input/Output Circuits
Type 2
Type 8-C
V
DD0
Pull-up
enable
P-ch
IN
V
DD0
Data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristics
Output
disable
N-ch
V
SS0
Type 5-H
VDD0
Pull-up
enable
P-ch
V
DD0
Data
P-ch
IN/OUT
Output
disable
N-ch
V
SS0
Input
enable
11
Data Sheet U13380EJ1V2DS
µPD789046
4. MEMORY SPACE
The µPD789046 can access 64 Kbytes of memory space. Figure 4-1 shows the memory map.
Figure 4-1. Memory Map
F F F F H
Special function register
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
512 × 8 bits
F D 0 0 H
F C F F H
Data memory space
3 F F F H
Reserved
4 0 0 0 H
3 F F F H
Program area
0 0 8 0 H
0 0 7 F H
Program memory
space
Internal ROM
CALLT table area
16,384 × 8 bits
0 0 4 0 H
0 0 3 F H
Program area
0 0 1 A H
0 0 1 9 H
Vector table area
0 0 0 0 H
0 0 0 0 H
12
Data Sheet U13380EJ1V2DS
µPD789046
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 Ports
The µPD789046 is provided with the following I/O ports and various controls are available.
Table 5-1. Port Functions
Port Name
Port 0
Pin Name
Function
P00 to P07
Input/output port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 1
Port 2
Port 3
Port 4
P10 to P17
P20 to P27
P30, P31
Input/output port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Input/output port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Input/output port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
P40 to P47
Input/output port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
5.2 Clock Generator
A system clock generator is incorporated.
The minimum instruction execution time can be changed.
•
•
0.4 µs/1.6 µs (@ 5.0-MHz operation with main system clock)
122 µs (@ 32.768-kHz operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1
XT2
Watch timer
16-bit timer counter 90
fXT
Subsystem
clock oscillator
Prescaler
Clock to peripheral
hardware
X1
X2
Main system
clock oscillator
1/2
Prescaler
fX
f
X
22
Standby
control circuit
Wait control
circuit
CPU clock
(fCPU
)
STOP
13
Data Sheet U13380EJ1V2DS
µPD789046
5.3 Timers
Four timer channels are incorporated.
•
•
•
•
16-bit timer counter 90 (TM90):
1 channel
8-bit timer/event counter 80 (TM80): 1 channel
Watch timer (WT):
1 channel
1 channel
Watchdog timer (WDT):
Table 5-2. Operations of Timers
TM90
TM80
WT
WDT
−
Operation mode
Function
Interval timer
1 channel
1 channel
1 output
1 output
1 output
−
1 channel
1 channel
−
−
−
−
−
−
−
1
−
−
−
−
−
−
1
External event counter
Timer output
1 output
−
−
Square wave output
PWM output
Buzzer output
Capture
1 output
1 input
1
−
Interrupt request
1
Figure 5-2. Block Diagram of 16-Bit Timer Counter 90
Internal bus
Output
16-bit compare
control
TO90/P30
register 90 (CR90)
circuit
Match
INTTM90
f
X
/22
/24
fX
Output
16-bit timer
register 90 (TM90)
f
/26
X
control
circuit
BZO90/P31
OVF
fXT
CPT90/P26
/INTP2
Edge detection
circuit
16-bit counter
read buffer
16-bit capture
register 90 (TCP90)
Internal bus
14
Data Sheet U13380EJ1V2DS
µPD789046
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter 80
Internal bus
8-bit compare
register 80 (CR80)
Match
INTTM80
fX
Output control
circuit
TO80/P27/
TI80
OVF
Clear
8-bit timer
register 80 (TM80)
f
/28
X
TI80/P27/
TO80
Internal bus
Figure 5-4. Watch Timer Block Diagram
Clear
f
/27
X
5-bit counter
Clear
INTWT
INTWTI
9-bit prescaler
fW
fW
fW
fW
fW
f
W
f
W
29
24 25 26 27 28
fXT
WTM0Note
Note Bit 0 of watch timer mode control register (WTM)
Figure 5-5. Watchdog Timer Block Diagram
f
X
24
Prescaler
f
X
26
f
X
28
f
X
210
RUNNote
Clear
7-bit counter
INTWDT maskable
interrupt request
Control
circuit
RESET
INTWDT non-maskable
interrupt request
Note Bit 7 of watchdog timer mode register (WDTM)
15
Data Sheet U13380EJ1V2DS
µPD789046
5.4 Serial Interface
One serial interface channel is incorporated.
Serial interface 20 has the following three types of modes.
•
•
•
Operation stop mode:
3-wire serial I/O mode:
Can reduce power consumption
Switchable between MSB-first and LSB-first transmission
Asynchronous serial interface (UART) mode: On-chip dedicated baud rate generator
Figure 5-6. Serial Interface Block Diagram
Internal bus
Transmit shift
register 20
(TXS20/SIO20)
Receive buffer
register 20
(RXB20/SIO20)
Receive shift register 20
(RXS20)
SI20/P22/R
XD20
Selector
Data phase
control
SO20/P21/T
X
D20
Transmit data
counter
INTST20
Transmit data
counter
INTSR20/INTCSI20
SS20/P23
Baud rate generator
ASCK20/P20
/SCK20
Clock phase
control
f
X
/2 to f
/28
X
16
Data Sheet U13380EJ1V2DS
µPD789046
6. INTERRUPT FUNCTIONS
A total of 12 interrupt sources are provided, divided into the following two types.
•
•
Non-maskable:
Maskable:
1
11
Table 6-1. Interrupt Sources
Interrupt Source
Basic Configuration
TypeNote 2
Vector Table
Address
PriorityNote 1
Interrupt Type
Internal/External
Name
Trigger
−
Non-
INTWDT
Watchdog timer overflow
(with watchdog timer mode 1
selected)
Internal
0004H
(A)
(B)
(C)
maskable
Maskable
0
INTWDT
Watchdog timer overflow
(with interval timer mode
selected)
1
2
3
4
INTP0
Pin input edge detection
External
Internal
0006H
0008H
000AH
000CH
INTP1
INTP2
INTSR20
End of serial interface 20 UART
reception
(B)
INTCSI20
INTST20
End of serial interface 20 3-wire
SIO transfer reception
5
End of serial interface 20 UART
transmission
000EH
6
7
8
INTWT
Watch timer interrupt
Interval timer interrupt
0010H
0012H
0014H
INTWTI
INTTM80
Generation of matching signal of
8-bit timer/event counter 80
9
INTTM90
INTKR00
Generation of matching signal of
16-bit timer counter 90
0016H
0018H
10
Detection of key return signal
External
(C)
Notes 1. Priority is the priority order when several maskable interrupts are generated at the same time. 0 is the
highest order and 10 is the lowest order.
2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 6-1.
17
Data Sheet U13380EJ1V2DS
µPD789046
Figure 6-1. Basic Configuration of Interrupt Functions
(A) Internal non-maskable interrupt
Internal bus
Vector table address
generator
Interrupt request
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
Vector table address
generator
IF
Interrupt request
Standby release signal
(C) External maskable interrupt
Internal bus
INTM0, KRM00
MK
IE
Vector table address
generator
Interrupt
request
Edge detection
circuit
IF
Standby release
signal
INTM0: External interrupt mode register 0
KRM00: Key return mode register 00
IF:
Interrupt request flag
Interrupt enable flag
Interrupt mask flag
IE:
MK:
18
Data Sheet U13380EJ1V2DS
µPD789046
7. STANDBY FUNCTIONS
The following two standby functions are available for further reduction of system current consumption.
•
•
HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be
reduced by intermittent operation by combining this mode with the normal operation mode.
STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on the
main system clock are suspended, resulting in extremely small current consumption.
Figure 7-1. Standby Functions
CSS0Note 1 = 1
Subsystem clock operationNote 2
Main system clock operation
CSS0Note 1 = 0
HALT instruction
HALT instruction
Interrupt
request
STOP
instruction
Interrupt
request
Interrupt
request
HALT mode
(Clock supply to CPU halted,
oscillation maintained)
HALT mode
(Clock supply to CPU halted,
oscillation maintained)
STOP mode
(Main system clock
oscillation stopped)
Notes 1. Bit 4 of subclock control register (CSS)
2. The current consumption can be reduced by stopping the main system clock. When the CPU is
operating on the subsystem clock, set the bit 7 (MCC) of processor clock control register (PCC) to stop
the main system clock. The STOP instruction cannot be used.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back to
the main system clock.
8. RESET FUNCTIONS
The following two reset methods are available.
•
•
External reset by RESET signal input
Internal reset by watchdog timer runaway time detection
19
Data Sheet U13380EJ1V2DS
µPD789046
9. INSTRUCTION SET OVERVIEW
The instruction set for the µPD789046 is listed later.
9.1 Legend
9.1.1 Operand formats and descriptions
The description made in the operand field of each instruction conforms to the operand format for the instructions
listed below (the details conform with the assembler specification). If more than one operand format is listed for an
instruction, one is selected. Uppercase letters, #, !, $, and a pair of [ and ] are used to specify keywords, which must
be written exactly as they appear. The meanings of these special characters are as follows:
• #: Immediate data specification
• $: Relative address specification
• !: Absolute address specification
• [ and ]: Indirect address specification
Immediate data should be described using appropriate values or labels. The specification of values and labels
must be accompanied by #, !, $, or a pair of [ and ].
Operand registers, expressed as r or rp in the formats, can be described using both functional names (X, A, C, etc.)
and absolute names (R0, R1, R2, and other names listed in Table 9-1).
Table 9-1. Operand Formats and Descriptions
Format
Description
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
rp
sfr
saddr
FE20H to FF1FH: Immediate data or label
saddrp
FE20H to FF1FH: Immediate data or label (even addresses only)
addr16
addr5
0000H to FFFFH: Immediate data or label
(only even addresses for 16-bit data transfer instructions)
0040H to 007FH: Immediate data or label (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
20
Data Sheet U13380EJ1V2DS
µPD789046
9.1.2 Descriptions of operation field
A
: A register; 8-bit accumulator
: X register
X
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
AX
BC
DE
HL
PC
SP
: AX register pair; 16-bit accumulator
: BC register pair
: DE register pair
: HL register pair
: Program counter
: Stack pointer
PSW : Program status word
CY
AC
Z
: Carry flag
: Auxiliary carry flag
: Zero flag
IE
: Interrupt request enable flag
NMIS : Flag to indicate that a non-maskable interrupt is being handled
: Contents of a memory location indicated by a parenthesized address or register
XH, XL : Higher and lower 8 bits of a 16-bit register
(
)
^
: Logical product (AND)
: Logical sum (OR)
: Exclusive OR
∨
∨
: Inverted data
addr16 : 16-bit immediate data or label
jdisp8 : Signed 8-bit data (displacement value)
9.1.3 Descriptions of flag operation field
(blank) : No change
0
1
×
R
: To be cleared to 0
: To be set to 1
: To be set or cleared according to the result
: To be restored to the previous value
21
Data Sheet U13380EJ1V2DS
µPD789046
9.2 Operations
Flag
Mnemonic
Operand
Byte
Clock
Operation
Z
AC CY
r ← byte
MOV
r, #byte
saddr, #byte
3
3
3
2
6
6
6
4
(saddr) ← byte
sfr ← byte
A ← r
sfr, #byte
A, r
Note 1
Note 1
r ← A
2
4
r, A
A ← (saddr)
(saddr) ← A
A ← sfr
A, saddr
saddr, A
A, sfr
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
sfr ← A
sfr, A
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
×
×
×
×
×
×
(DE) ← A
[DE], A
A ← (HL)
A, [HL]
(HL) ← A
[HL], A
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
A, [HL + byte]
[HL + byte], A
A, X
XCH
Note 2
A ↔ r
A, r
A ↔ (saddr)
A ↔ (sfr)
A, saddr
A, sfr
2
2
1
1
2
3
2
2
1
6
6
8
8
8
6
6
8
4
A ↔ (DE)
A, [DE]
A ↔ (HL)
A, [HL]
A ↔ (HL + byte)
rp ← word
A, [HL + byte]
rp, #word
AX, saddrp
saddrp, AX
MOVW
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
Note 3
Note 3
AX, rp
rp, AX
rp ← AX
1
4
Notes 1. Except when r = A.
2. Except when r = A or X.
3. Only when rp = BC, DE, or HL.
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control
register (PCC).
22
Data Sheet U13380EJ1V2DS
µPD789046
Flag
Mnemonic
Operand
Byte
1
Clock
8
Operation
Z
AC CY
Note
AX ↔ rp
XCHW
ADD
AX, rp
A, CY ← A + byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
(saddr), CY ← (saddr) + byte
A, CY ← A + r
saddr, #byte
A, r
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
A, [HL + byte]
A, #byte
ADDC
saddr, #byte
A, r
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
SUB
(saddr), CY ← (saddr) − byte
A, CY ← A − r
saddr, #byte
A, r
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (HL + byte)
A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, [HL + byte]
A, #byte
SUBC
saddr, #byte
A, r
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A ← A ∧ byte
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
AND
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
saddr, #byte
A, r
A ← A ∧ (saddr)
A, saddr
A, !addr16
A, [HL]
A ← A ∧ (addr16)
A ← A ∧ (HL)
A ← A ∧ (HL + byte)
A, [HL + byte]
Note Only when rp = BC, DE, or HL.
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control
register (PCC).
23
Data Sheet U13380EJ1V2DS
µPD789046
Flag
Mnemonic
Operand
Byte
Clock
Operation
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
A ← A ∨ byte
OR
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
saddr, #byte
A, r
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A ∨ (HL + byte)
A ← A ∨ byte
XOR
(saddr) ← (saddr) byte
∨
A ← A
r
∨
A ← A (saddr)
∨
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A (addr16)
∨
A ← A (HL)
∨
A ← A (HL + byte)
∨
A − byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
CMP
(saddr) − byte
A − r
A − (saddr)
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
A − (addr16)
A − (HL)
A − (HL + byte)
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
ADDW
SUBW
CMPW
INC
r ← r + 1
(saddr) ← (saddr) + 1
r ← r − 1
saddr
DEC
r
(saddr) ← (saddr) − 1
rp ← rp + 1
saddr
INCW
DECW
ROR
rp
rp ← rp − 1
rp
(CY, A7 ← A0, Am−1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
×
×
×
×
A, 1
ROL
A, 1
RORC
ROLC
A, 1
A, 1
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control
register (PCC).
24
Data Sheet U13380EJ1V2DS
µPD789046
Flag
Mnemonic
SET1
Operand
Byte
Clock
Operation
Z
AC CY
(saddr. bit) ← 1
sfr. bit ← 1
A. bit ← 1
saddr. bit
sfr. bit
A. bit
3
3
2
3
2
3
3
2
3
2
1
1
1
3
6
6
4
PSW. bit ← 1
(HL). bit ← 1
(saddr. bit) ← 0
sfr. bit ← 0
A. bit ← 0
×
×
×
×
PSW. bit
[HL]. bit
saddr. bit
sfr. bit
A. bit
6
10
6
CLR1
6
4
PSW. bit ← 0
(HL). bit ← 0
CY ← 1
×
×
PSW. bit
[HL]. bit
CY
6
10
2
SET1
CLR1
NOT1
CALL
1
0
×
CY ← 0
CY
2
CY ← CY
CY
2
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
!addr16
6
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP − 2
CALLT
[addr5]
1
8
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
RETI
R
R
R
(SP − 1) ← PSW, SP ← SP − 1
PUSH
POP
PSW
rp
1
1
2
4
(SP − 1) ← rpH, (SP − 2) ← rpL,
SP ← SP − 2
PSW ← (SP), SP ← SP + 1
PSW
rp
1
1
4
6
R
R
R
rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
SP ← AX
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
2
2
3
2
1
8
6
6
6
6
AX ← SP
PC ← addr16
PC ← PC + 2 + jdisp8
PCH ← A, PCL ← X
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control
register (PCC).
25
Data Sheet U13380EJ1V2DS
µPD789046
Flag
Mnemonic
Operand
Byte
Clock
Operation
Z
AC CY
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
BC
$addr16
$addr16
$addr16
$addr16
2
2
2
2
4
6
6
BNC
BZ
6
BNZ
BT
6
PC ← PC + 4 + jdisp8
saddr. bit, $addr16
10
if (saddr. bit) = 1
PC ← PC + 4 + jdisp8 if sfr. bit = 1
PC ← PC + 3 + jdisp8 if A. bit = 1
PC ← PC + 4 + jdisp8 if PSW. bit = 1
sfr. bit, $addr16
A. bit, $addr16
4
3
4
4
10
8
PSW. bit, $addr16
saddr. bit, $addr16
10
10
PC ← PC + 4 + jdisp8
BF
if (saddr. bit) = 0
PC ← PC + 4 + jdisp8 if sfr. bit = 0
PC ← PC + 3 + jdisp8 if A. bit = 0
PC ← PC + 4 + jdisp8 if PSW. bit = 0
sfr. bit, $addr16
A. bit, $addr16
PSW. bit, $addr16
B, $addr16
4
3
4
2
10
8
10
6
B ← B − 1, then
DBNZ
PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C − 1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
C, $addr16
2
3
6
8
(saddr) ← (saddr) − 1, then
saddr, $addr16
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
Set HALT Mode
DI
HALT
STOP
Set STOP Mode
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock control
register (PCC).
26
Data Sheet U13380EJ1V2DS
µPD789046
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
VI
Conditions
Ratings
Unit
−0.3 to +6.5
−0.3 to VDD + 0.3
−0.3 to VDD + 0.3
−10
V
V
Input voltage
Output voltage
Output current, high
VO
V
IOH
Per pin
mA
mA
mA
mA
°C
°C
−30
Total for all pins
Per pin
Output current, low
IOL
30
Total for all pins
160
−40 to +85
−65 to +150
Operating ambient temperature
Storage temperature
TA
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
27
Data Sheet U13380EJ1V2DS
µPD789046
Main System Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit
Parameter
Conditions
MIN. TYP. MAX. Unit
IC0 X1
X2
X2
X2
Ceramic
Oscillation frequency
(fX)Note 1
VDD = oscillation voltage
range
1.0
5.0
MHz
resonator
C1
C2
C2
Oscillation stabilization
timeNote 2
After VDD reaches oscillation
voltage range MIN.
4
ms
Crystal
Oscillation frequency
(fX)Note 1
1.0
5.0
MHz
IC0 X1
C1
resonator
Oscillation stabilization
timeNote 2
VDD = 4.5 to 5.5 V
10
30
ms
Note 1
X1
X1 input frequency (f )
X
External
clock
1.0
85
5.0
MHz
ns
X1 input high-/low-level width
(tXH, tXL)
500
X1 input frequency (fX)Note 1
X1
X2
VDD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
X1 input high-/low-level width
V
DD = 2.7 to 5.5 V
500
OPEN
(tXH, tXL
)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator that
stabilizes oscillation within the oscillation wait time.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS0.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
28
Data Sheet U13380EJ1V2DS
µPD789046
Subsystem Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit
Parameter
Conditions
MIN. TYP. MAX. Unit
Note 1
Oscillation frequency (fXT
)
Crystal
32
32.768
35
kHz
IC0XT1 XT2
R
resonator
C4
C3
Oscillation stabilization
timeNote 2
VDD = 4.5 to 5.5 V
1.2
2
s
10
35
XT1 input frequency (fXT)Note 1
XT2
XT1
External
clock
32
kHz
µs
XT1 input high-/low-level
width (tXTH, tXTL)
14.3
15.6
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator that
stabilizes oscillation within the oscillation wait time.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS0.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
29
Data Sheet U13380EJ1V2DS
µPD789046
DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
−1
Unit
Output current,
high
IOH
Per pin
mA
mA
mA
mA
V
−15
10
Total for all pins
Per pin
Output current, low
IOL
Total for all pins
80
Input voltage, high
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
VOH
VOL
ILIH1
P00 to P07, P10 to P17,
P30, P31
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
0.7VDD
0.9VDD
VDD
VDD
V
RESET,
0.8VDD
VDD
V
P20 to P27, P40 to P47
X1, X2
0.9VDD
VDD
V
VDD − 0.5
VDD − 0.1
VDD − 0.5
VDD − 0.1
VDD
V
VDD
V
XT1, XT2
VDD
V
VDD
V
Input voltage, low
P00 to P07, P10 to P17,
P30, P31
0
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.4
V
0
V
RESET,
0
V
P20 to P27, P40 to P47
X1, X2
0
V
0
V
0
0.1
V
XT1, XT2
0
0.4
V
0
0.1
V
VDD = 4.5 to 5.5 V, IOH = −1 mA
IOH = −100 µA
VDD − 1.0
VDD − 0.5
Output voltage,
high
V
V
Output voltage, low
VDD = 4.5 to 5.5 V, IOL = 10 mA
IOL = 400 µA
1.0
0.5
3
V
V
µA
Input leakage
current, high
VIN = VDD
Pins other than X1,
X2, XT1, XT2
µA
µA
ILIH2
X1, X2, XT1, XT2
20
−3
Input leakage
current, low
ILIL1
VIN = 0 V
Pins other than X1,
X2, XT1, XT2
−20
µA
µA
ILIL2
X1, X2, XT1, XT2
Output leakage
current, high
ILOH
VOUT = VDD
VOUT = 0 V
VIN = 0 V
3
−3
µA
kΩ
Output leakage
current, low
ILOL
Software pull-up
resistor
R
50
100
200
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
30
Data Sheet U13380EJ1V2DS
µPD789046
DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
1.8
MAX.
3.2
Unit
mA
VDD = 5.0 V 10%Note
Power supply
currentNote 1
IDD1
5.0-MHz crystal oscillation
3
operating mode
(C1 = C2 = 22 pF)
VDD = 3.0 V 10%Note
0.45
0.25
0.8
0.9
0.45
1.6
mA
mA
mA
mA
mA
4
VDD = 2.0 V 10%Note
4
VDD = 5.0 V 10%Note
IDD2
5.0-MHz crystal oscillation
HALT mode
3
(C1 = C2 = 22 pF)
VDD = 3.0 V 10%Note
0.3
0.6
4
VDD = 2.0 V 10%Note
0.15
0.3
4
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
TA = 25°C
IDD3
IDD4
IDD5
32.768-kHz crystal oscillation
operating modeNote 2
70
40
160
90
(C3 = C4 = 22 pF, R = 220 k
Ω
)
)
25
60
32.768-kHz crystal oscillation
HALT modeNote 2
20
55
5
25
(C3 = C4 = 22 pF, R = 220 k
Ω
2.5
0.1
0.05
0.05
0.05
12.5
10
STOP mode
5.0
3.0
3.0
VDD = 2.0 V 10%
Notes 1. The port current (including the current flowing through the on-chip pull-up resistor) is not included.
2. When the main system clock is stopped
3. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
4. Low-speed mode operation (when PCC is set to 02H)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
31
Data Sheet U13380EJ1V2DS
µPD789046
AC Characteristics
(1) Basic operation (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.4
1.6
114
0
TYP.
122
MAX.
8
Unit
µs
TCY
Operating with main system VDD = 2.7 to 5.5 V
clock
(Minimum instruction
execution time)
µs
8
µs
Operating with subsystem clock
VDD = 2.7 to 5.5 V
125
4
MHz
kHz
µs
TI80 input
frequency
fTI
0
275
TI80 input high-
/low-level width
tTIH, tTIL
VDD = 2.7 to 5.5 V
0.1
1.8
10
µs
µs
Interrupt input high- tINTH, tINTL INTP0 to INTP2
/low-level width
µs
RESET input
tRSL
10
low-level width
TCY vs VDD (main system clock)
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
32
Data Sheet U13380EJ1V2DS
µPD789046
(2) Serial interface
(a) 3-wire serial I/O mode (SCK20...Internal clock)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK20 cycle time
tKCY1
VDD = 2.7 to 5.5 V
800
3,200
tKCY1/2−50
tKCY1/2−150
150
ns
ns
ns
ns
ns
ns
SCK20 high-/low-
level width
tKH1, tKL1 VDD = 2.7 to 5.5 V
SI20 setup time
tSIK1
tKSI1
tKSO1
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
(to SCK20 ↑)
500
SI20 hold time
400
ns
ns
ns
ns
(from SCK20 ↑)
600
R = 1 kΩ,
SO20 output delay
VDD = 2.7 to 5.5 V
0
250
C = 100 pFNote
time from SCK20 ↓
0
1,000
Note R and C are the load resistance and load capacitance of the SO20 output line.
(b) 3-wire serial I/O mode (SCK20...External clock)
Parameter
Symbol
Conditions
MIN.
900
3,500
400
1,600
100
150
400
600
0
TYP.
MAX.
Unit
SCK20 cycle time
tKCY2
VDD = 2.7 to 5.5 V
ns
ns
ns
ns
ns
ns
SCK20 high-/low-
level width
tKH2, tKL2 VDD = 2.7 to 5.5 V
SI20 setup time
tSIK2
tKSI2
tKSO2
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
(to SCK20 ↑)
SI20 hold time
ns
ns
ns
ns
(from SCK20 ↑)
R = 1 kΩ,
SO20 output delay
VDD = 2.7 to 5.5 V
300
C = 100 pFNote
time from SCK20 ↓
0
1,000
Note R and C are the load resistance and load capacitance of the SO20 output line.
(c) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
78,125
19,531
Unit
bps
bps
Transfer rate
VDD = 2.7 to 5.5 V
33
Data Sheet U13380EJ1V2DS
µPD789046
(d) UART mode (External clock input)
Parameter
Symbol
Conditions
MIN.
900
TYP.
MAX.
Unit
ASCK20 cycle time
tKCY3
VDD = 2.7 to 5.5 V
ns
ns
3,500
400
ASCK20 high-/low- tKH3, tKL3 VDD = 2.7 to 5.5 V
level width
ns
1,600
ns
bps
bps
Transfer rate
VDD = 2.7 to 5.5 V
39,063
9,766
1
µs
ASCK20 rise/fall
time
tR, tF
34
Data Sheet U13380EJ1V2DS
µPD789046
AC Timing Test Points (excluding X1 and XT1 inputs)
0.8VDD
0.8VDD
0.2VDD
Test points
0.2VDD
Clock Timing
1/fX
t
XL
tXH
V
IH3 (MIN.)
X1 input
V
IL3 (MAX.)
1/fXT
t
XTL
t
XTH
V
IH4 (MIN.)
IL4 (MAX.)
XT1 input
V
TI Timing
1/fTI
tTIL
tTIH
TI80
Interrupt Input Timing
t
INTL
tINTH
INTP0 to INTP2
RESET Input Timing
tRSL
RESET
35
Data Sheet U13380EJ1V2DS
µPD789046
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
Remark m = 1, 2
UART mode (external clock input):
tKCY3
tKL3
tKH3
t
R
tF
ASCK20
36
Data Sheet U13380EJ1V2DS
µPD789046
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T = −40 to +85°C)
A
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention power
supply voltage
VDDDR
µs
ms
ms
Release signal set time
tSREL
0
Oscillation stabilization
wait timeNote 1
tWAIT
Release by RESET
Release by interrupt request
215/fX
Note 2
Notes 1. Oscillation stabilization wait time is a time for stopping the CPU operation to prevent the unstable
operation when the oscillation is started.
2. Selection of 212/fX, 215/fX, and 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark fX: Main system clock oscillation frequency
Data Retention Timing (STOP mode release by RESET)
Internal reset operation
HALT mode
STOP mode
Operation mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT mode
STOP mode
Operation mode
Data retention mode
VDD
V
DDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
37
Data Sheet U13380EJ1V2DS
µPD789046
11. CHARACTERISTICS CURVES
IDD vs VDD (fX = 5.0 MHz, fXT = 32.768 kHz)
(TA = 25°C)
10.0
PCC = 00H
PCC = 02H
1.0
0.5
PCC = 00H
(HALT mode)
PCC = 02H
(HALT mode)
Subsystem clock
operation mode (CSS0 = 1)
0.1
0.05
Subsystem clock operation
HALT mode (CSS0 = 1)
0.01
XT1
X1
X2
XT2
0.005
Crystal
resonator
5.0 MHz
Crystal
resonator
220 kΩ
32.768 kHz
22 pF
22 pF
33 pF
33 pF
VSS
V
SS
0.001
0
1
2
3
4
5
6
7
8
Supply voltage
VDD (V)
38
Data Sheet U13380EJ1V2DS
µPD789046
–
IOH vs VDD VOH
IOL vs VOL
(TA
= 25°C)
(TA = 25°C)
V
DD = 5.5 V
V
DD = 5.5 V
30
20
10
0
VDD = 3.5 V
20
10
0
V
DD = 3.5 V
V
DD = 3.0 V
V
DD = 3.0 V
DD = 4.0 V
DD = 4.5 V
VDD = 5.0 V
VDD = 4.0 V
V
VDD = 4.5 V
V
VDD = 5.0 V
V
DD = 2.5 V
VDD = 2.5 V
V
DD = 2.0 V
DD = 1.8 V
V
DD = 2.0 V
DD = 1.8 V
V
V
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–
VDD
VOH (V)
Low-level output voltage VOL (V)
39
Data Sheet U13380EJ1V2DS
µPD789046
12. PACKAGE DRAWING
44 PIN PLASTIC QFP (10x10)
A
B
detail of lead end
23
22
33
34
S
P
T
C
D
R
L
12
11
44
1
U
Q
F
J
M
G
H
I
K
M
N
S
S
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.16 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
12.0 0.2
10.0 0.2
10.0 0.2
12.0 0.2
1.0
G
1.0
+0.08
H
0.37
−0.07
I
0.2
J
K
L
0.8 (T.P.)
1.0 0.2
0.5
+0.03
0.17
M
−0.06
N
P
Q
0.10
1.4 0.05
0.1 0.05
+4°
3°
R
−3°
S
U
1.6 MAX.
0.6 0.15
S44GB-80-8ES-1
40
Data Sheet U13380EJ1V2DS
µPD789046
13. RECOMMENDED SOLDERING CONDITIONS
The µPD789046 should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 13-1. Surface Mounting Type Soldering Conditions
(1) µPD789046GB-xxx-8ES: 44-pin plastic LQFP (10 × 10)
Recommended Condition
Soldering Method
Infrared reflow
Soldering Conditions
Symbol
Package peak temperature: 235°C, Time: 30 sec. Max.
(at 210°C or higher), Count: two times or less
IR35-00-2
Package peak temperature: 215°C, Time: 40 sec. Max.
(at 200°C or higher), Count: two times or less
VPS
VP15-00-2
Solder bath temperature: 260°C Max., Time: 10 sec. Max., Count: once,
Preheating temperature: 120°C Max. (package surface temperature)
Wave soldering
Partial heating
WS60-00-1
Pin temperature: 350°C Max., Time: 3 sec. Max. (per pin row)
−
Caution Do not use different soldering methods together (except for partial heating).
(2) µPD789046GB-xxx-8ES-A: 44-pin plastic LQFP (10 × 10)
Recommended Condition
Symbol
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or
higher), Count: Three times or less, Exposure limit: 7 daysNote (after that,
prebake at 125°C for 20 to 72 hours)
IR60-207-3
−
−
Wave soldering
Partial heating
For details, contact an NEC Electronics sales representative.
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products that have the part numbers suffixed by "-A" are lead-free products.
41
Data Sheet U13380EJ1V2DS
µPD789046
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD789046.
Language Processing Software
RA78K0SNotes 1, 2, 3
CC78K0SNotes 1, 2, 3
DF789046Notes 1, 2, 3
CC78K0S-LNotes 1, 2, 3
Assembler package common to 78K/0S Series
C compiler package common to 78K/0S Series
Device file for µPD789046 Subseries
C compiler library source file common to 78K/0S Series
Flash Memory Writing Tools
Flashpro lIl
Flash programmer dedicated to on-chip flash memory microcontroller
Flash memory writing adapter for 44-pin plastic LQFP (GB-8ES type)
(Part No. FL-PR3Note 4, PG-FP3)
FA-44GB-8ESNote 4
Notes 1. Based on the PC-9800 series (MS-DOS + Windows)
2. Based on the IBM PC/AT and compatibles (Japanese/English Windows)
3. Based on the HP9000 series 700 (HP-UX ), SPARCstation (SunOS , SolarisTM), and NEWS
(NEWS-OS
)
4. Products made by NAITO DENSEI MACHIDA MFG. CO., LTD. (+81-44-822-3813). Contact an NEC
distributor regarding the purchase of these products.
Remark The RA78K0S and CC78K0S are used in combination with the DF789046.
42
Data Sheet U13380EJ1V2DS
µPD789046
Debugging Tools
IE-78K0S-NS
This in-circuit emulator is used to debug hardware or software when application systems
which use the 78K/0S Series are developed. The IE-78K0S-NS supports the integrated
debugger (ID78K0S-NS). The IE-78K0S-NS is used in combination with an interface
adapter for connection to an AC adapter, emulation probe, or host machine.
In-circuit emulator
IE-70000-MC-PS-B
AC adapter
This adapter is used to supply power from a 100 to 240 V AC outlet.
IE-70000-98-IF-C
Interface adapter
This adapter is required when a PC-9800 series PC (except notebook type) is used as
the host machine for the IE-78K0S-NS (C bus supported).
IE-70000-CD-IF-A
PC card/interface
These PC card and interface cable are required when a notebook PC is used as the
host machine for the IE-78K0S-NS (PCMCIA socket supported).
IE-70000-PC-IF-C
Interface adapter
This adapter is required when an IBM PC/ATTM or compatible is used as the host
machine for the IE-78K0S-NS (ISA bus supported).
IE-70000-PCI-IF
Interface adapter
This adapter is required when a PCI bus incorporated personal computer is used as the
host machine for the IE-78K0S-NS.
IE-789046-NS-EM1
Emulation board
This board is used to emulate the peripheral hardware specific to the device. The
IE-789046-NS-EM1 is used in combination with the in-circuit emulator.
NP-44GBNote 3
NP-44GB-TQNote 3
This board is used to connect an in-circuit emulator to the target system. The board is
dedicated to the 44-pin plastic LQFP (GB-8ES type).
SM78K0SNotes 1, 2
ID78K0S-NSNotes 1, 2
DF789046Notes 1, 2
System simulator common to 78K/0S Series
Integrated debugger common to 78K/0S Series
Device file for µPD789046 Subseries
Real-time OS
MX78K0SNotes 1, 2
OS for 78K/0S Series
Notes 1. Based on the PC-9800 series (MS-DOS + Windows)
2. Based on the IBM PC/AT and compatibles (Japanese/English Windows)
3. Products made by NAITO DENSEI MACHIDA MFG. CO., LTD. (+81-44-822-3813). Contact an NEC
distributor regarding the purchase of these products.
Remark The SM78K0S is used in combination with the DF789046.
43
Data Sheet U13380EJ1V2DS
µPD789046
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document No.
Document Name
Japanese
U13380J
English
This manual
U13546E
µPD789046 Data Sheet
µPD78F9046 Preliminary Product Information
µPD789046 Subseries User’s Manual
78K/0S Series Instructions User’s Manual
U13546J
U13600J
U11047J
U13600E
U11047E
Documents Related to Development Tools (User’s Manuals)
Document No.
Japanese English
Document Name
RA78K0S Assembler Package
Operation
U11622J
U11599J
U11623J
U11622E
Assembly Language
U11599E
U11623E
Structured Assembly
Language
CC78K0S C Compiler
Operation
Language
Reference
U11816J
U11817J
U11489J
U10092J
U11816E
U11817E
U11489E
U10092E
SM78K0S System Simulator Windows Based
SM78K Series System Simulator
External Part User Open
Interface Specifications
ID78K0S-NS Integrated Debugger Windows Based
IE-78K0S-NS In-circuit Emulator
Reference
U12901J
U12901E
U13549J
U13549E
IE-789046-NS-EM1 Emulation Board
To be prepared
To be prepared
Documents Related to Embedded Software (User’s Manuals)
Document No.
Document Name
Japanese
U12938J
English
78K/0S Series OS MX78K0S
Fundamental
U12938E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
44
Data Sheet U13380EJ1V2DS
µPD789046
Other Related Documents
Document No.
Japanese English
Document Name
SEMICONDUCTORS SELECTION GUIDE Products & Packages
Semiconductor Device Mounting Technology Manual
X13769X
Note
Quality Grades on NEC Semiconductor Devices
C11531J
C10983J
C11892J
U11416J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Guide to Microcomputer-Related Products by Third Party
C10983E
C11892E
−
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
45
Data Sheet U13380EJ1V2DS
µPD789046
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
46
Data Sheet U13380EJ1V2DS
µPD789046
EEPROM is a trademark of NEC Electronics Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
47
Data Sheet U13380EJ1V2DS
µPD789046
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
•
•
•
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Tel: 02-558-3737
Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
•
Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-2654010
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
•
•
Tyskland Filial
Taeby, Sweden
Tel: 08-63 87 200
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J05.6
48
Data Sheet U13380EJ1V2DS
µPD789046
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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